A rack-mounted dual-path server mainboard

Abstract

The utility model discloses a rack type two -way server mainboard, and server mainboard includes: first treater and second treater, and first treater and second treater are all loongson 3D5000 treater, and are interconnected through four groups 16's HT bus, and first treater and second treater are all loongson 3D5000 treater and have four memory controllers, first bridge piece and second bridge piece, and first bridge piece and second bridge piece are all 7A2000, and first bridge piece is as main bridge piece and is connected with first treater electricity through a group 16's HT bus, and second bridge piece is as vice bridge piece and is connected with second treater electricity through a group 16's HT bus, BMS chip, BMS chip is connected with first bridge piece electricity respectively and is connected with first treater electricity, is used for the remote management and monitoring function of server, and expands multiple interfaces, CPLD chip, CPLD chip is connected with BMS chip, first treater and first bridge piece electricity respectively, is used for control signal management and debugging support.

Description

Technical Field

[0001] This utility model relates to the field of server technology, and more specifically, to a rack-mounted dual-socket server motherboard. Background Technology

[0002] In the server field, with the rapid development of information technology, the localization process has always been an important development direction. In recent years, domestic server technology has made significant progress. This is mainly reflected in the localization of some basic hardware and software, such as operating systems and some peripheral devices, which have gradually achieved independent control. At the same time, technological breakthroughs have also provided impetus for the development of domestic servers. For example, continuous progress has been made in chip manufacturing processes and system architecture design, resulting in certain improvements in the performance and stability of domestic servers.

[0003] Existing server core components suffer from deficiencies such as insufficient self-sufficiency, poor system ecosystem compatibility, and insufficient performance of domestically produced bridge chips. In particular, the use of high-performance server processors significantly increases energy consumption. Precise heat dissipation and power consumption control are required when the CPU is under high load, and the stability and reliability of the server also need to be further improved.

[0004] Therefore, it is necessary to provide a rack-mount dual-socket server motherboard to solve the above problems. Utility Model Content

[0005] The purpose of this invention is to provide a rack-mounted dual-socket server motherboard that overcomes the aforementioned defects in the prior art.

[0006] The technical solution to achieve the purpose of this utility model is: a rack-mounted dual-socket server motherboard, the server motherboard comprising:

[0007] The first processor and the second processor are both Loongson 3D5000 processors and are interconnected through four 16-bit HT buses; both the first processor and the second processor are Loongson 3D5000 processors and each integrates four memory controllers, each of which is connected to and manages two DIMM slots.

[0008] The first bridge chip and the second bridge chip are both 7A2000. The first bridge chip, as the main bridge chip, is electrically connected to the first processor through a 16-bit HT bus, and the second bridge chip, as the secondary bridge chip, is electrically connected to the second processor through a 16-bit HT bus. The first bridge chip has multiple external interfaces for the server, and the second bridge chip has multiple expansion interfaces.

[0009] The BMS chip is electrically connected to the first bridge chip and the first processor, respectively, and is used for remote management and monitoring functions of the server, and has expanded multiple interfaces.

[0010] The CPLD chip is electrically connected to the BMS chip, the first processor, and the first bridge chip, respectively, and is used for control signal management and debugging support.

[0011] Furthermore, it also includes a ROM read-only memory, which is electrically connected to the first processor via an SPI interface and is used to store firmware or boot program, which runs when the system starts up, initializes the hardware and loads the operating system.

[0012] Furthermore, the BMS chip is an AST2500 chip, which is electrically connected to the first bridge chip via a PCIE x1, LPC, I2C, and USB interface, and is electrically connected to the first processor via a JTAG interface.

[0013] Furthermore, the CPLD chip is model EF3L90CG400B, and the CPLD chip is electrically connected to the first processor, the BMS chip, and the first bridge chip via a UART interface.

[0014] Furthermore, the first bridge chip's external interfaces include a PCIE interface, a USB interface, an RJ-45 management interface, a VGA interface, a DB9 serial port, a CON console interface, a miniSAS interface, and an M.2 SSD interface; the second bridge chip's expansion interfaces include a PCIE interface, a Slimline interface, and a miniSAS interface.

[0015] Furthermore, the DB9 serial port is electrically connected to the CPLD chip via a UART interface.

[0016] Furthermore, the BMS chip is electrically connected to the RTL8211FD Ethernet physical layer transceiver via the GMII interface, and the RTL8211FD Ethernet physical layer transceiver is electrically connected to the RJ-45 management interface via the MGT management interface; the BMS chip is electrically connected to two VGA interfaces, and controls the two VGA interfaces via a switch.

[0017] Furthermore, the first bridge chip has two RJ-45 management interfaces; the first bridge chip is electrically connected to two RTL8111H Ethernet controllers via a PCIeX1 interface, and the two RTL8111H Ethernet controllers are electrically connected to the two RJ-45 management interfaces via GE network interfaces respectively; the first bridge chip has four USB 3.0 interfaces, of which two USB 3.0 interfaces are led to the front panel of the server and the other two USB 3.0 interfaces are led to the rear panel of the server.

[0018] Furthermore, both the first and second processor power supply systems adopt a 9+1 phase power supply design; the power supply system adopts a RAA228236 digital multiphase controller.

[0019] Furthermore, the server motherboard is also equipped with four hot-swappable fan modules. The CPLD chip is electrically connected to the four hot-swappable fan modules through the PWR interface, RST / GPIO interface and I2C interface, respectively, to monitor and adjust the status of the four hot-swappable fan modules.

[0020] By adopting the above technical solution, this utility model has the following beneficial effects:

[0021] (1) This utility model provides powerful parallel processing capabilities and high-speed data transmission speed through four sets of 16-bit HT bus interconnection. Each processor integrates four memory controllers and supports eight DIMM slots, which greatly improves the memory bandwidth and capacity of the system; through the four-way direct connection of 3D5000, a single system can be expanded to 64 cores, which is more suitable for enterprise-level servers, cloud computing centers, distributed storage and other scenarios that require high scalability.

[0022] (2) This utility model achieves real-time monitoring and rapid response through the design of direct connection between the BMC chip and the first processor, reducing the intermediate links in data transmission, enabling the BMC to obtain key indicators such as CPU temperature, voltage, and power consumption in real time, and quickly respond to anomalies (such as overheating or overload) to prevent hardware damage; direct access to the CPU status allows the BMC to dynamically adjust the heat dissipation strategy (such as fan speed) or power configuration to improve system stability.

[0023] It achieves high reliability and out-of-band management. Even if the operating system or main processor fails, the BMC can still remotely manage the server through an independent channel (such as forced restart and log capture) to ensure uninterrupted operation and maintenance. It does not rely on the main system network and achieves management through a dedicated interface (such as IPMI), avoiding network congestion or system paralysis from affecting operation and maintenance.

[0024] It also has efficient fault diagnosis and recovery capabilities, and can bypass the operating system to directly read CPU registers and sensor data to quickly locate hardware problems (such as cache errors and power fluctuations); it supports updating CPU microcode or firmware through BMC without physical contact with the server, thus shortening fault recovery time.

[0025] To improve security, the direct connection channel is independent of the operating system, reducing the risk of malware infiltrating the BMC through the main system and enhancing hardware-level security protection. It directly records CPU-related events (such as abnormal instructions) to provide lower-level data support for security analysis.

[0026] (3) This utility model realizes real-time monitoring and adjustment of the fan status through the PWR interface, RST / GPIO interface and I2C interface of the CPLD chip, ensuring that the heat dissipation effect can be maintained even under high load and extending the hardware life.

[0027] (4) This utility model connects to its respective processors via the HT bus, providing a variety of external interfaces and expansion interfaces, including PCIE, USB, VGA, etc., which enhances the system's compatibility and expansion capabilities.

[0028] (5) This utility model is connected to the first processor through the SPI interface to store firmware or boot program, initialize hardware and load operating system when the system starts, thereby increasing the system's startup stability and data integrity.

[0029] (6) This utility model provides redundant network connection through the GE network interface and two RJ-45 management interfaces, which improves network availability and fault tolerance; it is connected to the RTL8211FD Ethernet physical layer transceiver through the GMII interface, which further enhances network performance and stability, and is suitable for network applications that require high bandwidth and low latency.

[0030] (7) The CPLD chip (EF3L90CG400B) of this utility model is connected to multiple key components through the UART interface, which facilitates signal management and debugging support, simplifies the troubleshooting process, and improves maintenance efficiency.

[0031] (8) The CON console interface of this utility model provides system administrators with the ability to directly access the underlying settings of the server, which facilitates in-depth configuration and problem solving.

[0032] (9) This utility model adopts the RAA228236 digital multiphase controller, which ensures the stability and efficiency of power supply to the CPU, while reducing power consumption and heat generation, and improving system reliability and energy efficiency ratio. Attached Figure Description

[0033] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein...

[0034] Figure 1 This is a schematic diagram of the structure of this utility model. Detailed Implementation

[0035] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0038] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0039] In the description of the embodiments of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly used when the utility model product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0040] In the description of the embodiments of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances. The utility model will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of this utility model and should not be used to limit the scope of protection of this utility model.

[0041] (Example 1)

[0042] The Loongson 3D5000 is a high-performance server processor. By integrating two Loongson 3C5000 chips into one package, it forms a powerful processor with 32 cores. The 3D5000 uses efficient interconnect technology, enabling fast communication between the two dies (i.e., the two 3C5000 chips).

[0043] See Figure 1 A rack-mount dual-socket server motherboard, the server motherboard comprising:

[0044] The first processor and the second processor are both Loongson 3D5000 processors and are interconnected through four 16-bit HT buses. The first processor and the second processor are internally interconnected and integrated with DIE0 and DIE1 through a 16-bit HT bus. DIE0 and DIE1 are equivalent to 3C5000 chips.

[0045] Both the first and second processors are Loongson 3D5000 processors, each integrating four memory controllers. Each memory controller connects to and manages two DIMM slots, ensuring that each processor has an independent memory channel, enabling high-speed parallel data transfer and greatly improving memory bandwidth.

[0046] The first bridge chip and the second bridge chip are both 7A2000. The first bridge chip, as the main bridge chip, is electrically connected to the first processor through a 16-bit HT bus, and the second bridge chip, as the secondary bridge chip, is electrically connected to the second processor through a 16-bit HT bus. The first bridge chip has multiple external interfaces for the server, and the second bridge chip has multiple expansion interfaces.

[0047] The BMS chip is electrically connected to both the first bridge chip and the first processor, and is used for remote management and monitoring of the server, and also extends multiple interfaces.

[0048] The CPLD chip is electrically connected to the BMS chip, the first processor, and the first bridge chip, respectively, and is used for control signal management and debugging support.

[0049] The ROM (Read-Only Memory) is electrically connected to the primary processor via an SPI interface. It stores firmware or a bootloader, runs during system startup, initializes the hardware, and loads the operating system. The firmware in the ROM typically includes BIOS or UEFI, and it is responsible for the basic configuration and initialization of the processor and other system components. Initializing the hardware and loading the operating system during system startup increases system startup stability and data integrity.

[0050] Furthermore, the BMS chip is an AST2500 chip, which is electrically connected to the first bridge chip via PCIe x1, LPC, I2C, and USB interfaces, and electrically connected to the first processor via a JTAG interface. The CPLD chip is an EF3L90CG400B, which is electrically connected to the first processor, BMS chip, and first bridge chip via a UART interface. Connecting to multiple key components via the UART interface facilitates signal management and debugging support, simplifies troubleshooting, and improves maintenance efficiency.

[0051] Furthermore, the first bridge chip's external interfaces include a PCIE interface, a USB interface, an RJ-45 management interface, a VGA interface, a DB9 serial port, a CON console interface, a miniSAS interface, and an M.2 SSD interface; the second bridge chip's expansion interfaces include a PCIE interface, a Slimline interface, and a miniSAS interface.

[0052] The DB9 serial port is electrically connected to the CPLD chip via the UART interface; the BMS chip is electrically connected to the RTL8211FD Ethernet physical layer transceiver via the GMII interface, and the RTL8211FD Ethernet physical layer transceiver is electrically connected to the RJ-45 management interface via the MGT management interface; the BMS chip is electrically connected to two VGA interfaces and controls the two VGA interfaces via a switch.

[0053] The first bridge chip has two RJ-45 management interfaces. It is electrically connected to two RTL8111H Ethernet controllers via a PCIe x1 interface. The two RTL8111H Ethernet controllers are each electrically connected to the two RJ-45 management interfaces via a GE network interface. The first bridge chip also has four USB 3.0 ports: two are routed to the front panel of the server, and the other two to the rear panel. The connection to the two RJ-45 management interfaces via the GE network interface provides redundant network connectivity, improving network availability and fault tolerance. The connection to the RTL8211FD Ethernet physical layer transceiver via the GMII interface further enhances network performance and stability, making it suitable for network applications requiring high bandwidth and low latency.

[0054] Furthermore, both the first and second processor power supply systems employ a 9+1 phase power design; the power supply system utilizes a RAA228236 digital multiphase controller. The server motherboard also features four hot-swappable fan modules. A CPLD chip is electrically connected to each of the four hot-swappable fan modules via PWR, RST / GPIO, and I2C interfaces to monitor and adjust their status. The use of the RAA228236 digital multiphase controller ensures stable and efficient power supply to the CPU, while reducing power consumption and heat generation, thus improving system reliability and energy efficiency.

[0055] In this implementation, the design of directly connecting the BMC chip to the first processor enables real-time monitoring and rapid response, reducing intermediate links in data transmission. This allows the BMC to obtain key indicators such as CPU temperature, voltage, and power consumption in real time, quickly respond to anomalies (such as overheating or overload), and prevent hardware damage. Direct access to the CPU status allows the BMC to dynamically adjust cooling strategies (such as fan speed) or power configuration, improving system stability.

[0056] It achieves high reliability and out-of-band management. Even if the operating system or main processor fails, the BMC can still remotely manage the server through an independent channel (such as forced restart and log capture) to ensure uninterrupted operation and maintenance. It does not rely on the main system network and achieves management through a dedicated interface (such as IPMI), avoiding network congestion or system paralysis from affecting operation and maintenance.

[0057] It also has efficient fault diagnosis and recovery capabilities, and can bypass the operating system to directly read CPU registers and sensor data to quickly locate hardware problems (such as cache errors and power fluctuations); it supports updating CPU microcode or firmware through BMC without physical contact with the server, thus shortening fault recovery time.

[0058] To improve security, the direct connection channel is independent of the operating system, reducing the risk of malware infiltrating the BMC through the main system and enhancing hardware-level security protection. It directly records CPU-related events (such as abnormal instructions) to provide lower-level data support for security analysis.

[0059] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above descriptions are merely specific embodiments of this utility model and are not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A rack-mount dual-socket server motherboard, characterized in that: Server motherboards include: The first processor and the second processor are both Loongson 3D5000 processors and are interconnected through four 16-bit HT buses; both the first processor and the second processor are Loongson 3D5000 processors and each integrates four memory controllers, each of which is connected to and manages two DIMM slots. The first bridge chip and the second bridge chip are both 7A2000. The first bridge chip, as the main bridge chip, is electrically connected to the first processor through a 16-bit HT bus, and the second bridge chip, as the secondary bridge chip, is electrically connected to the second processor through a 16-bit HT bus. The first bridge chip has multiple external interfaces for the server, and the second bridge chip has multiple expansion interfaces. The BMS chip is electrically connected to the first bridge chip and the first processor, respectively, and is used for remote management and monitoring functions of the server, and has expanded multiple interfaces. The CPLD chip is electrically connected to the BMS chip, the first processor, and the first bridge chip, respectively, and is used for control signal management and debugging support.

2. The rack-mount dual-socket server motherboard according to claim 1, characterized in that: It also includes a ROM read-only memory, which is electrically connected to the first processor via an SPI interface and is used to store firmware or boot program, which runs when the system starts up, initializes the hardware and loads the operating system.

3. The rack-mount dual-socket server motherboard according to claim 1, characterized in that: The BMS chip is an AST2500 chip. The AST2500 chip is electrically connected to the first bridge chip through a PCIE x1, LPC, I2C, and USB interface. The AST2500 chip is electrically connected to the first processor through a JTAG interface.

4. A rack-mount dual-socket server motherboard according to claim 3, characterized in that: The CPLD chip is model EF3L90CG400B, and the CPLD chip is electrically connected to the first processor, the BMS chip and the first bridge chip through the UART interface.

5. A rack-mount dual-socket server motherboard according to claim 4, characterized in that: The first bridge chip's external interfaces include a PCIE interface, a USB interface, an RJ-45 management interface, a VGA interface, a DB9 serial port, a CON console interface, a miniSAS interface, and an M.2 SSD interface; the second bridge chip's expansion interfaces include a PCIE interface, a Slimline interface, and a miniSAS interface.

6. A rack-mount dual-socket server motherboard according to claim 5, characterized in that: The DB9 serial port is electrically connected to the CPLD chip via a UART interface.

7. A rack-mount dual-socket server motherboard according to claim 5, characterized in that: The BMS chip is electrically connected to the RTL8211FD Ethernet physical layer transceiver via the GMII interface, and the RTL8211FD Ethernet physical layer transceiver is electrically connected to the RJ-45 management interface via the MGT management interface. The BMS chip is electrically connected to two VGA interfaces and controls the two VGA interfaces via a switch.

8. A rack-mount dual-socket server motherboard according to claim 5, characterized in that: The first bridge chip has two RJ-45 management interfaces; the first bridge chip is electrically connected to two RTL8111H Ethernet controllers via a PCIE x1 interface, and the two RTL8111H Ethernet controllers are electrically connected to the two RJ-45 management interfaces via GE network interfaces respectively; the first bridge chip has four USB 3.0 interfaces, of which two USB 3.0 interfaces are led to the front panel of the server and the other two USB 3.0 interfaces are led to the rear panel of the server.

9. A rack-mount dual-socket server motherboard according to claim 1, characterized in that: Both the first and second processor power supply systems adopt a 9+1 phase power supply design; the power supply system adopts a RAA228236 digital multiphase controller.

10. A rack-mount dual-socket server motherboard according to claim 1, characterized in that: The server motherboard is also equipped with four hot-swappable fan modules. The CPLD chip is electrically connected to the four hot-swappable fan modules through the PWR interface, RST / GPIO interface and I2C interface, respectively, to monitor and adjust the status of the four hot-swappable fan modules.

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