Array substrate and display panel
By designing the main body and connection structure of the pixel electrode on the array substrate, or by setting a barrier layer on the main body, the problem of damage to the upper surface of the pixel electrode by dry etching is solved, thereby improving etching accuracy and display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2025-08-18
- Publication Date
- 2026-07-24
AI Technical Summary
In existing technologies, dry etching of the source and drain electrodes can cause excessive damage to the upper surface of the pixel electrodes, affecting the display effect.
Design an array substrate structure in which the pixel electrode includes a main body and a connecting part. The ratio of the thickness of the main body to the thickness of the connecting part is in the range of 0.7 to 1. The connecting part is protected from the substrate by dry etching, or a barrier layer is provided on the main body to avoid etching damage.
This reduces damage to the surface of the pixel electrodes, minimizes the impact on display quality, and improves the precision and reliability of the etching process.
Smart Images
Figure CN224556144U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology
[0002] In related technologies, pixel electrodes and interlayer dielectric layers are fabricated using a half-tone process to save on a photomask layer. However, during the subsequent etching of the metal layers containing the source and drain electrodes, there will be a variation between the preset pattern size of the source and drain electrodes on the photomask and the actual pattern size formed by etching. This variation is called the source and drain sizing (SD sizing). Since wet etching can cause a large sizing, dry etching is typically used to fabricate the source and drain electrodes to achieve the product requirement of a smaller sizing.
[0003] However, while dry etching the source and drain electrodes, the upper surface of the pixel electrode is also etched, causing excessive damage to the upper surface of the pixel electrode and affecting the display effect.
[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Utility Model Content
[0005] The purpose of this application is to provide an array substrate and a display panel that can reduce damage to the upper surface of the pixel electrodes or make the upper surface of the pixel electrodes undamaged, thereby reducing the impact on the display effect.
[0006] To solve the above problems, the technical solution of this application is as follows:
[0007] In a first aspect, this application proposes an array substrate, comprising:
[0008] Substrate;
[0009] A semiconductor layer is disposed on one side of the substrate;
[0010] An interlayer dielectric layer is disposed on the side of the semiconductor layer away from the substrate, and the interlayer dielectric layer is provided with a first via.
[0011] A pixel electrode, disposed on the side of the interlayer dielectric layer away from the substrate, includes a main body portion and a connecting portion connected together, wherein the orthographic projection of the connecting portion on the substrate lies between the orthographic projection of the first via on the substrate and the orthographic projection of the main body portion on the substrate; and
[0012] A first electrode is electrically connected to the pixel electrode. A portion of the first electrode passes through the first via and is electrically connected to the semiconductor layer. Another portion of the first electrode overlaps with the connection portion in the thickness direction of the array substrate and is located on the side of the connection portion away from the substrate.
[0013] The ratio of the thickness of the main body to the thickness of the connecting part is in the range of 0.7 to 1.
[0014] In one embodiment of this application, the array substrate further includes a barrier layer, which is disposed at least on the side of the main body away from the substrate.
[0015] In one embodiment of this application, the barrier layer is disposed only on the side of the main body away from the substrate, and another part of the first electrode is in direct contact with the side of the connection portion away from the substrate.
[0016] In one embodiment of this application, the barrier layer is disposed on the side of the main body away from the substrate and extends to the side of the connection portion away from the substrate, and another portion of the first electrode is in direct contact with the portion of the barrier layer located on the connection portion.
[0017] In one embodiment of this application, the thickness of the main body is equal to the thickness of the connecting portion; the ratio of the thickness of the barrier layer to the thickness of the pixel electrode is in the range of 0.5 to 2.
[0018] In one embodiment of this application, the material of the barrier layer includes at least one of silicon nitride and silicon oxide.
[0019] In one embodiment of this application, the thickness of the main body is less than the thickness of the connecting portion;
[0020] Another portion of the first electrode is in direct contact with the side of the connection portion away from the substrate.
[0021] In one embodiment of this application, the material of the first electrode is different from the material of the pixel electrode;
[0022] The etching selectivity ratio between the first electrode and the pixel electrode is greater than or equal to 5.
[0023] In one embodiment of this application, a second via is further provided in the interlayer dielectric layer;
[0024] The array substrate further includes:
[0025] A buffer layer is disposed on one side of the substrate, and the semiconductor layer is disposed on the side of the buffer layer away from the substrate;
[0026] A gate insulating layer is disposed on the side of the buffer layer away from the substrate and covers the semiconductor layer. The gate insulating layer has a third via and a fourth via. The third via communicates with the first via and the fourth via communicates with the second via. A portion of the first electrode passes through the first via and the third via in sequence and is connected to the semiconductor layer.
[0027] A gate is disposed on the side of the gate insulating layer away from the semiconductor layer and is disposed corresponding to the channel of the semiconductor layer. The interlayer dielectric layer is disposed on the side of the gate insulating layer away from the buffer layer and covers the gate.
[0028] The second electrode has a portion that passes sequentially through the second via and the fourth via and is connected to the semiconductor layer, and the other portion of the second electrode is disposed on the side of the interlayer dielectric layer away from the substrate;
[0029] A passivation layer is disposed on the side of the interlayer dielectric layer away from the gate insulating layer, and covers the first electrode, the second electrode, and the pixel electrode; and
[0030] A common electrode is disposed on the side of the passivation layer away from the interlayer dielectric layer and is disposed corresponding to the pixel electrode.
[0031] Secondly, this application proposes a display panel including an array substrate. The array substrate includes a substrate, a semiconductor layer, an interlayer dielectric layer, a pixel electrode, and a first electrode. The semiconductor layer is disposed on one side of the substrate. The interlayer dielectric layer is disposed on the side of the semiconductor layer away from the substrate, and the interlayer dielectric layer has a first via. The pixel electrode is disposed on the side of the interlayer dielectric layer away from the substrate and includes a connected main body portion and a connecting portion. The orthographic projection of the connecting portion on the substrate is located between the orthographic projection of the first via on the substrate and the orthographic projection of the main body portion on the substrate. The first electrode is electrically connected to the pixel electrode. A portion of the first electrode passes through the first via and is electrically connected to the semiconductor layer. Another portion of the first electrode overlaps with the connecting portion in the thickness direction of the array substrate and is located on the side of the connecting portion away from the substrate. The ratio of the thickness of the main body portion to the thickness of the connecting portion is in the range of 0.7 to 1.
[0032] The pixel electrode of this application includes a main body and a connecting portion. During the dry etching process of the first electrode, since a portion of the first electrode overlaps with the connecting portion in the thickness direction of the array substrate, this portion of the first electrode can protect the surface of the connecting portion away from the substrate from damage caused by dry etching. Before dry etching, the thickness ratio of the main body to the connecting portion is 1. After etching, the thickness ratio of the main body to the connecting portion is greater than or equal to 0.7, meaning that the thickness loss of the side of the main body away from the substrate during dry etching is less than or equal to 30%. The main body is the portion that does not overlap with the first electrode in the thickness direction of the array substrate and plays a role in controlling the light emission of the sub-pixel. In this application, since the thickness loss of the main body is small or non-existent, the problem of excessive damage to the upper surface of the pixel electrode can be solved, reducing damage to the upper surface of the pixel electrode and thus reducing the impact on the display effect. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0035] Figure 1 This is a schematic diagram of one embodiment of the array substrate of this application;
[0036] Figure 2 This is a schematic diagram of another embodiment of the array substrate of this application;
[0037] Figure 3 This is a schematic diagram of an array substrate according to the first embodiment of this application;
[0038] Figure 4 This is a schematic diagram of step S11 in the first method of fabricating the array substrate of this application;
[0039] Figure 5 This is a schematic diagram of step S21 in the first method of fabricating the array substrate of this application;
[0040] Figure 6 This is a schematic diagram of step S31 in the first method of fabricating the array substrate of this application;
[0041] Figure 7 This is a schematic diagram of step S41 in the first method of fabricating the array substrate of this application;
[0042] Figure 8 This is a schematic diagram of step S51 in the first method of fabricating the array substrate of this application;
[0043] Figure 9 This is a schematic diagram of step S61 in the first method of fabricating the array substrate of this application;
[0044] Figure 10 This is a schematic diagram of step S71 in the first method of fabricating the array substrate of this application;
[0045] Figure 11 This is a schematic diagram of step S81 in the first method of fabricating the array substrate of this application;
[0046] Figure 12 This is a schematic diagram of an array substrate according to a second embodiment of this application;
[0047] Figure 13 This is a schematic diagram of step S12 in the first method of fabricating the array substrate of this application;
[0048] Figure 14 This is a schematic diagram of step S22 in the first method of fabricating the array substrate of this application;
[0049] Figure 15 This is a schematic diagram of step S32 in the first method of fabricating the array substrate of this application;
[0050] Figure 16 This is a schematic diagram of step S42 in the first method of fabricating the array substrate of this application;
[0051] Figure 17 This is a schematic diagram of step S52 in the first method of fabricating the array substrate of this application;
[0052] Figure 18 This is a schematic diagram of step S62 in the first method of fabricating the array substrate of this application;
[0053] Figure 19 This is a schematic diagram of step S72 in the first method of fabricating the array substrate of this application;
[0054] Figure 20 This is a schematic diagram of step S82 in the first method of fabricating the array substrate of this application;
[0055] Figure 21 This is a schematic diagram of an array substrate according to the third embodiment of this application.
[0056] Explanation of reference numerals in the attached figures:
[0057] 100, Array substrate; Z, Thickness direction;
[0058] 10. Substrate;
[0059] 20. Semiconductor layer;
[0060] 30. Interlayer dielectric layer; First via 31; Second via 32;
[0061] 40. Pixel electrode; 41. Main body; 42. Connecting part;
[0062] 50. First electrode;
[0063] 60. Barrier layer;
[0064] 71. Buffer layer; 72. Gate insulating layer; 721. Third via; 722. Fourth via; 73. Gate; 74. Second electrode; 75. Passivation layer; 76. Common electrode;
[0065] 81. First transparent conductive layer; 82. Barrier material layer; 83. Two-stage photoresist; 831. Hollowed-out portion; 832. First photoresist portion; 833. Second photoresist portion; 841. First sub-hole; 842. Second sub-hole; 843. Third sub-hole; 844. Fourth sub-hole; 85. First metal layer. Detailed Implementation
[0066] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0067] This application discloses a display panel that can be applied to display devices, such as electronic paper, tablet computers, e-readers, electronic display screens, laptops, mobile phones, augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, and car navigation systems. The display panel can be a liquid crystal display panel. The display panel includes an array substrate 100.
[0068] This application proposes an array substrate 100, including a substrate 10, a semiconductor layer 20, an interlayer dielectric layer 30, a pixel electrode 40, and a first electrode 50.
[0069] The semiconductor layer 20 is disposed on one side of the substrate 10.
[0070] An interlayer dielectric layer 30 is disposed on the side of the semiconductor layer 20 away from the substrate 10. The interlayer dielectric layer 30 is provided with a first via 31.
[0071] The pixel electrode 40 is disposed on the side of the interlayer dielectric layer 30 away from the substrate 10, and includes a main body portion 41 and a connecting portion 42 connected to each other. The orthographic projection of the connecting portion 42 on the substrate 10 is located between the orthographic projection of the first via 31 on the substrate 10 and the orthographic projection of the main body portion 41 on the substrate 10.
[0072] The first electrode 50 is electrically connected to the pixel electrode 40. A portion of the first electrode 50 passes through the first via 31 and is electrically connected to the semiconductor layer 20. Another portion of the first electrode 50 overlaps with the connection portion 42 in the thickness direction Z of the array substrate 100 and is located on the side of the connection portion 42 away from the substrate 10.
[0073] The ratio of the thickness h1 of the main body 41 to the thickness h2 of the connecting part 42 is in the range of 0.7 to 1.
[0074] The pixel electrode of this application includes a main body and a connecting portion. During the dry etching process of the first electrode, since a portion of the first electrode overlaps with the connecting portion in the thickness direction of the array substrate, this portion of the first electrode can protect the surface of the connecting portion away from the substrate from damage caused by dry etching. Before dry etching, the thickness ratio of the main body to the connecting portion is 1. After etching, the thickness ratio of the main body to the connecting portion is greater than or equal to 0.7, meaning that the thickness loss of the side of the main body away from the substrate during dry etching is less than or equal to 30%. The main body is the portion that does not overlap with the first electrode in the thickness direction of the array substrate and plays a role in controlling the light emission of the sub-pixel. In this application, since the thickness loss of the main body is small or non-existent, the problem of excessive damage to the upper surface of the pixel electrode can be solved, reducing damage to the upper surface of the pixel electrode and thus reducing the impact on the display effect.
[0075] In this application, at least two methods can be used to reduce damage to the upper surface of the pixel electrode or to make the upper surface of the pixel electrode undamaged.
[0076] Please see Figure 1On the one hand, during the dry etching process of the first electrode 50, a first etchant can be used for etching. The etching selectivity ratio of the first electrode 50 to the pixel electrode 40 using the first etchant is greater than 5. The pixel electrode 40 includes a main body portion 41 and a connecting portion 42. The connecting portion 42 overlaps with the first electrode 50 in the thickness direction Z of the array substrate 100. The first electrode 50 can shield the connecting portion 42, preventing it from being etched by the first etchant. The main body portion 41 is exposed outside the first electrode 50 and will be etched by the first etchant. However, since the etching rate of the first electrode 50 in the first etchant is relatively fast, while the etching rate of the main body portion 41 is relatively slow, after the first electrode 50 is etched, the thickness of the portion of the main body portion 41 lost due to etching is less than or equal to 30% of the thickness of the un-etched connecting portion 42 of the pixel electrode 40. At this time, the ratio of the thickness h1 of the main body portion 41 to the thickness h2 of the connecting portion 42 is still greater than or equal to 0.7. It can reduce damage to the surface of the pixel electrode.
[0077] Please see Figure 2 On the other hand, a barrier layer 60 can also be provided on the pixel electrode 40, covering the main body portion 41 exposed outside the first electrode 50. During dry etching, since the barrier layer 60 shields the main body portion 41, it can prevent the main body portion 41 from being etched by the first etchant. After dry etching, the ratio of the thickness of the main body portion 41 to the thickness of the connecting portion 42 is equal to 1, which can prevent damage to the upper surface of the pixel electrode. Both of these approaches can reduce the impact on the display effect.
[0078] In this embodiment, the ratio of the thickness h1 of the main body 41 to the thickness h2 of the connecting part 42 can be 0.70, 0.71, 0.72, 0.73, 0.74, 0.75, 0.76, 0.77, 0.78, 0.79, 0.80, 0.81, 0.82, 0.83, 0.84, 0.85, 0.86, 0.87, 0.88, 0.89, 0.90, 0.91, 0.92, 0.93, 0.94, 0.95, 0.96, 0.97, 0.98, 0.99, or 1.00.
[0079] It should be understood that the thin-film transistor in this application is a low-temperature polycrystalline silicon thin-film transistor (LTPS). The first electrode 50 can be either the input electrode (source) or the output electrode (drain). The first electrode 50 can be a single layer of metal or a multilayer metal stacked structure. For example, the first electrode 50 can be a three-layer metal stack, with the three metal layers being made of molybdenum / aluminum / molybdenum, respectively.
[0080] Optionally, a second via 32 is also provided in the interlayer dielectric layer 30.
[0081] Optionally, the array substrate 100 further includes a buffer layer 71, a gate insulating layer 72, a gate 73, a second electrode 74, a passivation layer 75, and a common electrode 76.
[0082] A buffer layer 71 is disposed on one side of the substrate 10. A semiconductor layer 20 is disposed on the side of the buffer layer 71 away from the substrate 10.
[0083] A gate insulating layer 72 is disposed on the side of the buffer layer 71 away from the substrate 10 and covers the semiconductor layer 20. A third via 721 and a fourth via 722 are provided in the gate insulating layer 72. The third via 721 communicates with the first via 31. The fourth via 722 communicates with the second via 32. A portion of the first electrode 50 passes sequentially through the first via 31 and the third via 721 and is connected to the semiconductor layer 20.
[0084] The gate 73 is disposed on the side of the gate insulating layer 72 away from the semiconductor layer 20 and is disposed corresponding to the channel of the semiconductor layer 20. The interlayer dielectric layer 30 is disposed on the side of the gate insulating layer 72 away from the buffer layer 71 and covers the gate 73.
[0085] A portion of the second electrode 74 passes sequentially through the second via 32 and the fourth via 722, and is connected to the semiconductor layer 20. Another portion of the second electrode 74 is disposed on the side of the interlayer dielectric layer 30 away from the substrate 10.
[0086] The passivation layer 75 is disposed on the side of the interlayer dielectric layer 30 away from the gate insulating layer 72, and covers the first electrode 50, the second electrode 74 and the pixel electrode 40.
[0087] The common electrode 76 is located on the side of the passivation layer 75 away from the interlayer dielectric layer 30, and is correspondingly disposed to the pixel electrode 40.
[0088] In the first embodiment of this application:
[0089] Please see Figure 3 Optionally, the thickness h1 of the main body 41 is less than the thickness h2 of the connecting part 42.
[0090] In this embodiment, since the first electrode 50 only blocks the connecting portion 42 and not the main body portion 41 during the etching process, the thickness h1 of the main body portion 41 is less than the thickness h2 of the connecting portion 42 after the first electrode 50 is etched.
[0091] Alternatively, another portion of the first electrode 50 may be in direct contact with the side of the connection portion 42 away from the substrate 10.
[0092] In this embodiment, during the etching process of the first electrode 50, the un-etched portion of the first electrode 50 is directly disposed on the connection portion 42, thereby shielding the connection portion 42 and preventing it from being etched. Therefore, this portion is in direct contact with the side of the connection portion 42 away from the substrate 10.
[0093] Optionally, the material of the first electrode 50 is different from the material of the pixel electrode 40.
[0094] In this embodiment, the pixel electrode 40 is made of indium tin oxide (ITO). The first electrode 50 can be a single layer of metal or a multilayer metal stack. For example, the first electrode 50 can be a three-layer metal stack, with the three metal layers being made of molybdenum / aluminum / molybdenum, respectively.
[0095] Optionally, the etching selectivity ratio of the first electrode to the pixel electrode is greater than or equal to 5.
[0096] In this embodiment, a first etchant is used to form the first electrode 50, and the etching selectivity ratio of the first electrode 50 to the pixel electrode 40 in the first etchant is greater than or equal to 5.
[0097] In this embodiment, the first electrode 50 can be formed by dry etching. In this dry etching, the first electrode 50 can be etched using a first etchant. The first etchant can be sulfur hexafluoride. The etching selectivity ratio of the first electrode 50 to the pixel electrode 40 in sulfur hexafluoride is greater than or equal to 5.
[0098] The etching selectivity ratio of the first electrode 50 to the pixel electrode 40 in the first etchant can be 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 8.5, 9.0, 9.5, 10.0, etc.
[0099] In the first embodiment, the array substrate 100 is fabricated using a first fabrication method for the array substrate 100.
[0100] The first method for manufacturing the array substrate 100 includes the following steps:
[0101] Step S11: Please refer to Figure 4 A semiconductor layer 20, a gate insulating layer 72, a gate 73, an interlayer dielectric layer 30, and a first transparent conductive layer 81 are sequentially formed on a substrate 10. The semiconductor layer 20 includes a channel and doped portions connected to both sides of the channel.
[0102] Step S21: Please refer to Figure 5A two-segment photoresist 83 of different thicknesses is formed on the first transparent conductive layer 81, and the first transparent conductive layer 81 is patterned using the two-segment photoresist 83 as a mask. The two-segment photoresist 83 includes two cutout portions 831, a first photoresist portion 832, and two second photoresist portions 833. The thickness of the first photoresist portion 832 is greater than the thickness of the second photoresist portion 833. The cutout portions 831 expose a portion of the first transparent conductive layer 81. The two cutout portions 831 are located on opposite sides of the first photoresist portion 832, and the two second photoresist portions 833 are located on the side of the cutout portion 831 away from the first photoresist portion 832. Wet etching is performed on the portion of the first transparent conductive layer 81 exposed to the two cutout portions 831 to form a first sub-hole 841 and a second sub-hole 842 in the first transparent conductive layer 81. The portion of the first transparent conductive layer 81 located between the first sub-hole 841 and the second sub-hole 842 forms a pixel electrode 40.
[0103] The method for forming the two-stage photoresist 83 is as follows: first, a photoresist of uniform thickness is formed on the first transparent conductive layer 81, and then a halftone mask is used to pattern the photoresist to form the two-stage photoresist 83.
[0104] Step S31: Please refer to Figure 6 Dry etching is performed on the portions of the interlayer dielectric layer 30 and the gate insulating layer 72 exposed to the two cutouts 831, forming a first via 31 and a second via 32 in the interlayer dielectric layer 30. A third via 721 and a fourth via 722 are formed in the gate insulating layer 72. The first via 31 and the third via 721 are connected. The second via 32 and the fourth via 722 are connected. The third via 721 exposes a doped portion located on one side of the channel. The fourth via 722 exposes another doped portion located on the other side of the channel.
[0105] Step S41: Please refer to Figure 7 The two-stage photoresist 83 is aerated to remove the thinner second photoresist portion 833.
[0106] Step S51: Please refer to Figure 8 Wet etching is performed on the first transparent conductive layer 81 exposed outside the first photoresist portion 832 to remove the first transparent conductive layer 81 exposed outside the first photoresist portion 832.
[0107] Step S61: Please refer to Figure 9 Continue to perform ashing treatment on the two-stage photoresist 83 to remove the first photoresist part 832.
[0108] Step S71: Please refer to Figure 10A first metal layer 85 is formed on the array substrate 100. The first metal layer 85 covers the pixel electrode 40, the interlayer dielectric layer 30, the first via 31, the second via 32, the third via 721, and the fourth via 722.
[0109] Step S81: Please refer to Figure 11 The pixel electrode 40 includes a main body portion 41 and a connecting portion 42. A first etchant is used to dry etch a first metal layer 85. Specifically, the first metal layer 85 located on the main body portion 41 is etched away, while the first metal layers 85 located on the connecting portion 42 and within the first via 31, second via 32, third via 721, and fourth via 722 are retained. Specifically, the first metal layers 85 located on the connecting portion 42, within the first via 31, and within the third via 721 form the first electrode 50. The first metal layers 85 located within the second via 32 and the fourth via 722 form the second electrode 74. Since the etching selectivity ratio of the first electrode 50 to the pixel electrode 40 in the first etchant is greater than or equal to 5, the portion of the main body portion 41 lost due to the first etchant is relatively small. After etching, the ratio of the thickness of the main body portion 41 to the thickness of the connecting portion 42 is in the range of 0.7 to 1.
[0110] In the first fabrication method of the array substrate 100 of this application, the thickness of the main body 41 is less than the thickness of the connecting portion 42. Another portion of the first electrode 50 is in direct contact with the side of the connecting portion 42 away from the substrate 10. By using the first fabrication method, the number of photomasks required to fabricate the array substrate 100 can be reduced, thereby reducing production costs.
[0111] In the second embodiment of this application:
[0112] Please see Figure 12 Optionally, the thickness of the main body 41 is equal to the thickness of the connecting part 42.
[0113] Optionally, the array substrate 100 further includes a barrier layer 60. The barrier layer 60 is disposed at least on the side of the main body 41 away from the substrate 10.
[0114] In this embodiment, since a barrier layer 60 is provided on the main body 41 of the pixel electrode 40, the barrier layer 60 can prevent the main body 41 from being damaged by etching during the etching process of the first electrode 50. Therefore, the thickness of the main body 41 is equal to the thickness of the connecting part 42.
[0115] Optionally, the barrier layer 60 is disposed on the side of the main body 41 away from the substrate 10 and extends to the side of the connector 42 away from the substrate 10. Another portion of the first electrode 50 is in direct contact with the portion of the barrier layer 60 located on the connector 42.
[0116] In this embodiment, the barrier layer 60 is disposed not only on the main body 41 but also on the connecting portion 42. The first electrode 50 achieves electrical connection by directly contacting the side of the connecting portion 42 away from the main body 41.
[0117] Optionally, the ratio of the thickness of the barrier layer 60 to the thickness of the pixel electrode 40 is in the range of 0.5 to 2.
[0118] In this embodiment, in order to achieve a better blocking effect without affecting the display effect, the ratio of the thickness of the blocking layer 60 to the thickness of the pixel electrode 40 is in the range of 0.5 to 2. The value of the ratio of the thickness of the blocking layer 60 to the thickness of the pixel electrode 40 can be 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, etc.
[0119] Optionally, the material of the barrier layer 60 includes at least one of silicon nitride and silicon oxide.
[0120] In this embodiment, the material of the barrier layer 60 may be silicon nitride (SiN). x ) and silicon dioxide (SiO) x At least one of the following.
[0121] In this embodiment, due to the different packing density and surface roughness of the barrier layer 60 and the passivation layer 75, there will be an interface between the barrier layer 60 and the passivation layer 75.
[0122] On the one hand, during the process of dry etching the source and drain, the dry etchant will also etch the side of the barrier layer 60 away from the substrate 10, resulting in a difference in surface roughness between the side of the barrier layer 60 away from the substrate 10 and the side of the passivation layer 75 close to the substrate 10, thus forming the aforementioned interface.
[0123] On the other hand, since the barrier layer 60 is meant to prevent dry etchant from etching the surface of the pixel electrode 40, the density of the barrier layer 60, i.e., the packing density of the barrier layer, will be relatively high. After the barrier layer 60 is formed, the density (packing density) of the barrier layer 60 is greater than that of the passivation layer 75.
[0124] When a cross-sectional view of the array substrate 100 is obtained using a scanning electron microscope (SEM), since the density (packing density) of the barrier layer 60 is greater than that of the passivation layer 75, the delamination effect between the passivation layer 60 and the barrier layer 75 can be clearly seen in the cross-sectional view of the scanning electron microscope, that is, the interface mentioned above exists between the two.
[0125] In the second embodiment, the array substrate 100 is fabricated using a second fabrication method.
[0126] The second method for manufacturing the array substrate 100 includes the following steps:
[0127] Step S12: Please refer to Figure 13 A semiconductor layer 20, a gate insulating layer 72, a gate 73, an interlayer dielectric layer 30, a first transparent conductive layer 81, and a barrier material layer 82 are sequentially formed on a substrate 10. The semiconductor layer 20 includes a channel and doped portions connected to both sides of the channel.
[0128] Step S22: Please refer to Figure 14 A two-stage photoresist 83 of different thicknesses is formed on the barrier material layer 82, and the barrier material layer 82 and the first transparent conductive layer 81 are patterned using the two-stage photoresist 83 as a mask. The two-stage photoresist 83 includes two cutout portions 831, a first photoresist portion 832, and two second photoresist portions 833. The thickness of the first photoresist portion 832 is greater than the thickness of the second photoresist portion 833. The cutout portions 831 expose a portion of the barrier material layer 82. The two cutout portions 831 are located on opposite sides of the first photoresist portion 832, and the two second photoresist portions 833 are located on the side of the cutout portion 831 away from the first photoresist portion 832. Dry etching is performed on the portion of the barrier material layer 82 exposed to the two cutout portions 831 to form a third sub-hole 843 and a fourth sub-hole 844 in the barrier material layer 82. The portion of the barrier material layer 82 located between the third sub-hole 843 and the fourth sub-hole 844 is the barrier layer 60. Wet etching is performed on the portion of the first transparent conductive layer 81 exposed to the two cutouts 831 to form a first sub-hole 841 and a second sub-hole 842 in the first transparent conductive layer 81. A pixel electrode 40 is formed in the portion of the first transparent conductive layer 81 located between the first sub-hole 841 and the second sub-hole 842. The first sub-hole 841 communicates with a third sub-hole 843. The second sub-hole 842 communicates with a fourth sub-hole 844.
[0129] The method for forming the two-stage photoresist 83 is as follows: first, a photoresist of uniform thickness is formed on the barrier material layer 82, and then a halftone mask is used to pattern the photoresist to form the two-stage photoresist 83.
[0130] Step S32: Please refer to Figure 15Dry etching is performed on the portions of the interlayer dielectric layer 30 and the gate insulating layer 72 exposed to the two cutouts 831, forming a first via 31 and a second via 32 in the interlayer dielectric layer 30. A third via 721 and a fourth via 722 are formed in the gate insulating layer 72. The first via 31 and the third via 721 are connected. The second via 32 and the fourth via 722 are connected. The third via 721 exposes a doped portion located on one side of the channel. The fourth via 722 exposes another doped portion located on the other side of the channel.
[0131] Step S42: Please refer to Figure 16 The two-stage photoresist 83 is aerated to remove the thinner second photoresist portion 833.
[0132] Step S52: Please refer to Figure 17 Wet etching is performed on the first transparent conductive layer 81 exposed outside the first photoresist portion 832 to remove the barrier material layer 82 and the first transparent conductive layer 81 exposed outside the first photoresist portion 832.
[0133] Step S62: Please refer to Figure 18 Continue to perform ashing treatment on the two-stage photoresist 83 to remove the first photoresist part 832.
[0134] Step S72: Please refer to Figure 19 A first metal layer 85 is formed on the array substrate 100. The first metal layer 85 covers the barrier layer 60, the interlayer dielectric layer 30, the first via 31, the second via 32, the third via 721, and the fourth via 722.
[0135] Step S82: Please refer to Figure 20 The pixel electrode 40 includes a main body portion 41 and a connecting portion 42. A first etchant is used to dry etch the first metal layer 85. Specifically, the first metal layer 85 on the main body portion 41 is etched away, while the first metal layers 85 on the connecting portion 42 and within the first via 31, second via 32, third via 721, and fourth via 722 are retained. Specifically, the first metal layers 85 on the connecting portion 42, within the first via 31, and within the third via 721 form the first electrode 50. The first metal layers 85 within the second via 32 and fourth via 722 form the second electrode 74. Since both the main body portion 41 and the connecting portion 42 are covered by a barrier layer 60, after etching, the thickness of the main body portion 41 is equal to the thickness of the connecting portion 42.
[0136] Compared to the first embodiment, the second embodiment can better protect the pixel electrode 40 from etching damage, but it requires an additional process to form the barrier layer 60, and the process steps and material costs will be slightly higher than those of the first embodiment.
[0137] In the third embodiment of this application:
[0138] To avoid redundancy, the third embodiment of this application only describes the differences from the second embodiment of this application.
[0139] The third embodiment of this application differs from the second embodiment in that:
[0140] Please see Figure 21 Optionally, the barrier layer 60 is disposed only on the side of the main body 41 away from the substrate 10. The other part of the first electrode 50 is in direct contact with the side of the connecting portion 42 away from the substrate 10.
[0141] In this embodiment, since the first electrode 50 can also shield the connection portion 42, preventing the connection portion 42 from being etched, the barrier layer 60 can be disposed only on the side of the main body portion 41 away from the substrate 10. At this time, the first electrode 50 is in direct contact not only with the side of the connection portion 42 away from the main body portion 41, but also with the side of the connection portion 42 away from the substrate 10. This embodiment increases the contact area between the first electrode 50 and the pixel electrode 40, thereby reducing their contact resistance, improving the stability of their connection, and reducing the power consumption of the array substrate 100.
[0142] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0143] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0144] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0145] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. An array substrate, characterized in that, include: Substrate; A semiconductor layer is disposed on one side of the substrate; An interlayer dielectric layer is disposed on the side of the semiconductor layer away from the substrate, and the interlayer dielectric layer is provided with a first via. A pixel electrode is disposed on the side of the interlayer dielectric layer away from the substrate, and includes a main body portion and a connecting portion connected to each other. The orthographic projection of the connecting portion on the substrate is located between the orthographic projection of the first via on the substrate and the orthographic projection of the main body portion on the substrate. as well as A first electrode is electrically connected to the pixel electrode. A portion of the first electrode passes through the first via and is electrically connected to the semiconductor layer. Another portion of the first electrode overlaps with the connection portion in the thickness direction of the array substrate and is located on the side of the connection portion away from the substrate. The ratio of the thickness of the main body to the thickness of the connecting part is in the range of 0.7 to 1.
2. The array substrate as described in claim 1, characterized in that, The array substrate further includes a barrier layer, which is disposed at least on the side of the main body away from the substrate.
3. The array substrate as described in claim 2, characterized in that, The barrier layer is disposed only on the side of the main body away from the substrate, and the other part of the first electrode is in direct contact with the side of the connection portion away from the substrate.
4. The array substrate as described in claim 2, characterized in that, The barrier layer is disposed on the side of the main body away from the substrate and extends to the side of the connection portion away from the substrate. Another portion of the first electrode is in direct contact with the portion of the barrier layer located on the connection portion.
5. The array substrate as described in claim 2, characterized in that, The thickness of the main body is equal to the thickness of the connecting part; the ratio of the thickness of the barrier layer to the thickness of the pixel electrode is in the range of 0.5 to 2.
6. The array substrate as described in claim 2, characterized in that, The material of the barrier layer includes at least one of silicon nitride and silicon oxide.
7. The array substrate as claimed in claim 1, characterized in that, The thickness of the main body is less than the thickness of the connecting part; Another portion of the first electrode is in direct contact with the side of the connection portion away from the substrate.
8. The array substrate as claimed in claim 7, characterized in that, The material of the first electrode is different from the material of the pixel electrode; The etching selectivity ratio between the first electrode and the pixel electrode is greater than or equal to 5.
9. The array substrate as described in any one of claims 1-8, characterized in that, The interlayer dielectric layer is also provided with a second via; The array substrate further includes: A buffer layer is disposed on one side of the substrate, and the semiconductor layer is disposed on the side of the buffer layer away from the substrate; A gate insulating layer is disposed on the side of the buffer layer away from the substrate and covers the semiconductor layer. The gate insulating layer has a third via and a fourth via. The third via communicates with the first via and the fourth via communicates with the second via. A portion of the first electrode passes through the first via and the third via in sequence and is connected to the semiconductor layer. A gate is disposed on the side of the gate insulating layer away from the semiconductor layer and is disposed corresponding to the channel of the semiconductor layer. The interlayer dielectric layer is disposed on the side of the gate insulating layer away from the buffer layer and covers the gate. The second electrode has a portion that passes sequentially through the second via and the fourth via and is connected to the semiconductor layer, and the other portion of the second electrode is disposed on the side of the interlayer dielectric layer away from the substrate; A passivation layer is disposed on the side of the interlayer dielectric layer away from the gate insulating layer, and covers the first electrode, the second electrode, and the pixel electrode; and A common electrode is disposed on the side of the passivation layer away from the interlayer dielectric layer and is disposed corresponding to the pixel electrode.
10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.