Chip package structure with shielding performance

Abstract

The utility model discloses a chip packaging structure with shielding performance, including the chip unit and circuit layer in the plastic package body, the circuit layer is located the back of plastic package body and with the electrode electric connection in the chip unit chip, the plastic package body still has and the side shield frame of interval arrangement with the chip, the side shield frame includes setting N 1 intermediate metal shielding layer between the front and back of plastic package body, and N side metal shielding parts are separated by intermediate metal shielding layer from the front of plastic package body to the back of plastic package body, the intermediate metal shielding layer has the through -hole for the chip passes through in the middle, to make the side metal shielding part annular and surround the installation area setting of chip, N is equal to or greater than 2. The utility model discloses the annular frame of intermediate metal shielding layer for the side shield frame, can be used in the packaging structure of high height, and the shielding effect is good.

Description

Technical Field

[0001] This utility model relates to semiconductor packaging, and more particularly to a chip packaging structure with shielding properties. Background Technology

[0002] To prevent electromagnetic interference (EMI) between chips, current technology typically incorporates electromagnetic shielding structures within the chips. The core principle of electromagnetic shielding is based on Maxwell's electromagnetic theory, using a metallic shield to reflect or absorb interfering signals, thereby suppressing EMI. Specifically, this includes:

[0003] Electric field shielding: Utilizing the Faraday cage effect, when an electric field irradiates a metal surface, induced charges are generated. These charges are conducted to the grounding terminal to form a skin current, which consumes energy and thus shields the internal electric field.

[0004] Magnetic field shielding: For low-frequency magnetic fields, a low magnetic reluctance path is constructed using high-permeability materials to concentrate the magnetic field; for high-frequency magnetic fields, the interference magnetic field is canceled out by the eddy current reverse magnetic field generated by high-conductivity materials.

[0005] Therefore, electromagnetic shielding structures are typically incorporated into chips. Referring to Chinese Patent CN105074918 A, a metal casing is placed outside the chip to suppress the impact of external electromagnetic interference on chip performance. However, this design increases the chip's size due to the thick metal casing.

[0006] To address this, Chinese patent CN 203787410 U describes placing the shielding copper pillars within the insulating material used for packaging. However, this packaging structure can only be used for single-layer chip packaging; if used in taller packaging structures (such as chip stacking structures), the shielding effect will be weakened.

[0007] Therefore, there is an urgent need for a chip packaging method and chip packaging structure that can solve the above problems. Utility Model Content

[0008] The purpose of this invention is to provide a chip packaging structure with shielding performance, which can be used in packaging structures with high height and has a good shielding effect.

[0009] To achieve the above objectives, this utility model provides a chip packaging structure with shielding performance, including a chip unit and a circuit layer encapsulated in a plastic package. The circuit layer is located on the back side of the plastic package and is electrically connected to the electrodes of the chip in the chip unit. The plastic package also encapsulates a side shielding frame, which surrounds the mounting area of ​​the chip and is insulated from the chip at intervals. The side shielding frame includes N-1 intermediate metal shielding layers disposed between the front and back sides of the plastic package, and N side metal shielding portions separated by the intermediate metal shielding layers from the front to the back side of the plastic package. The intermediate metal shielding layers have a through hole in the middle for the chip to pass through, so that the intermediate metal shielding layers are annular and surround the mounting area of ​​the chip, where N is greater than or equal to 2.

[0010] Preferably, each of the side metal shielding portions is formed by a plurality of metal pillars surrounding the mounting area of ​​the chip.

[0011] Preferably, the intermediate metal shielding layer is in the form of a sheet parallel to the front side of the molding compound, and the thickness of the intermediate metal shielding layer is 1KA.

[0012] Preferably, the diameter of the metal pillar is 25-27 μm, and the width of the intermediate metal shielding layer is greater than or equal to 28 μm.

[0013] Preferably, the width of the intermediate metal shielding layer is greater than the width of the side metal shielding portion, and the projection of the intermediate metal shielding layer on the front side of the molding compound covers the projection of the side metal shielding portion.

[0014] Preferably, the chip packaging structure further includes an all-metal shielding layer formed on the front side of the molding compound. The projection of the all-metal shielding layer on the front side of the molding compound fully covers the projection of the chip unit and extends to the side metal shielding portion, thereby making contact between the side metal shielding portion and the all-metal shielding layer for electrical connection.

[0015] Preferably, the circuit layer has a first circuit electrically connected to the electrodes of the chip in the chip unit, and a second circuit electrically connected to the side shield. The circuit layer has a chip conductive connection portion electrically connected to the first circuit and a ground conductive connection portion electrically connected to the second circuit on the back side away from the molding compound.

[0016] More preferably, a grounded metal shielding layer is formed on the back side of the circuit layer, which is insulated from the distance between the conductive connection portion of the chip. The grounded metal shielding layer is electrically connected to the grounded conductive connection portion. The grounded metal shielding layer is formed on the side of the chip package structure connected to the solder balls, and does not increase the thickness of the chip package structure.

[0017] Specifically, the grounding metal shielding layer is sheet-shaped and has a plurality of isolation holes for accommodating the conductive connection portion of the chip and clearance holes for accommodating the conductive connection portion of the ground. The area of ​​the conductive connection portion of the chip is smaller than that of the isolation hole, and the conductive connection portion of the chip is spaced apart from the hole wall of the isolation hole. The size of the conductive connection portion of the ground is matched with that of the clearance hole, so that the conductive connection portion of the ground is in contact with the hole wall of the clearance hole for electrical connection.

[0018] Specifically, each of the side metal shielding portions is surrounded by a plurality of metal pillars around the mounting area of ​​the chip, and the second circuit includes a conductive ring formed on the front side of the circuit layer adjacent to the molded body, and a connection line disposed between the conductive ring and the ground conductive connection portion, wherein the conductive ring contacts and is electrically connected to each of the metal pillars exposed on the back side of the molded body.

[0019] Compared with the prior art, in the chip packaging structure of this utility model, the side shield frame encapsulated in the molding compound is an annular frame with an intermediate metal shield layer in the middle, and it surrounds the chip mounting area. The side shield frame includes multiple side metal shielding parts, and there is an annular intermediate metal shield layer between adjacent side metal shielding parts. The intermediate metal shield layer can combine with the side metal shielding parts to form multiple shielding spaces, so that the shielding effect of the side shield frame in the molding compound is better, and it can be used for chip stacking structures with a high height. Moreover, the intermediate metal shield layer of this utility model is not only thin, but also has a through hole in the middle for the chip to pass through, so that there is a distance between the intermediate metal shield layer and the chip for insulation, which can be used for various chip stacking structures, such as fan-shaped stacked chip structures. Attached Figure Description

[0020] Figure 1 This is a side cross-sectional view of the chip packaging structure in Example 1.

[0021] Figure 2 for Figure 1 A magnified view of a portion of the image.

[0022] Figure 3 This is a top view of the grounded metal shielding layer.

[0023] Figure 4 This is a perspective view of the chip packaging structure in Example 1.

[0024] Figure 5 This is a perspective view of the chip packaging structure after the plastic encapsulation has been removed in Example 1.

[0025] Figure 6 This is a side cross-sectional view of the chip packaging structure in Example 2.

[0026] Figure 7 This is a side cross-sectional view of the chip packaging structure in Example 3. Detailed Implementation

[0027] To explain in detail the technical content, structural features, objectives and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0028] Example 1:

[0029] refer to Figure 1 and Figure 4 This invention provides a chip packaging structure with shielding properties, including a chip unit 30 and a circuit layer 40 encapsulated within a molding compound 10. The molding compound 10 has a front and a back side with opposite positions. The circuit layer 40 is located on the back side of the molding compound 10 and is electrically connected to the electrodes of the chip in the chip unit 30. A side shielding frame 22 is also encapsulated within the molding compound 10. The side shielding frame 22 surrounds the mounting area of ​​the chip and is insulated from the chip at intervals. The circuit layer 40 may be a redistribution layer or a circuit board, etc.

[0030] refer to Figure 2 and Figure 5 The side shielding frame 22 includes N-1 intermediate metal shielding layers 220 disposed between the front and back sides of the molding compound 10, and N side metal shielding portions 221, 222 separated from the front to the back sides of the molding compound 10 by the intermediate metal shielding layers 220. The intermediate metal shielding layer 220 has a through hole in the middle for the chip to pass through, so that the intermediate metal shielding layer 220 is annular. The side metal shielding portions 221, 222 are annular and surround the mounting area of ​​the chip. The width of the intermediate metal shielding layer 220 is greater than the width of the side metal shielding portions 221, 222, so that the projection of the intermediate metal shielding layer 220 on the front side of the molding compound 10 covers the projection of the side shielding frame 22, and N is greater than or equal to 2.

[0031] The intermediate metal shielding layer 220 is a sheet-like structure arranged parallel to the front side of the molding compound 10, and a shielding space can be formed between the intermediate metal shielding layer 220 and the side metal shielding portions 221 and 222. Moreover, when there are multiple intermediate metal shielding layers 220, a shielding space can also be formed between the multiple intermediate metal shielding layers 220, thereby increasing the shielding effect.

[0032] Each of the side metal shielding portions 221 and 222 is formed by a plurality of metal pillars surrounding the mounting area of ​​the chip. All the metal pillars of each of the side metal shielding portions 221 and 222 are in contact with an intermediate metal shielding layer 220.

[0033] refer to Figure 1 and Figure 2The circuit layer 40 has a first circuit 41 electrically connected to the electrodes of the chip in the chip unit 30, and a second circuit 42 electrically connected to the side shield 22. The back side of the circuit layer 40 away from the molding compound 10 has a chip conductive connection portion 51 electrically connected to the first circuit 41, and a ground conductive connection portion 53 electrically connected to the second circuit 422. A ground metal shielding layer 52, insulated from the chip conductive connection portion 51, is formed on the back side of the circuit layer 40 away from the molding compound 10. The ground conductive connection portion 53 is electrically connected to the ground metal shielding layer 52. Chip pins 62 are formed on the chip conductive connection portion 51, and ground pins 61 are formed on the ground conductive connection portion 53. The chip pins 62 and ground pins 61 are soldered to the outside using solder balls or similar structures. The ground metal shielding layer 52 and the side shield 22 form a mesh-like Faraday cage, and the opposing arrangement of the ground metal shielding layer 52 and the middle metal shielding layer 220 further enhances the shielding effect of the Faraday cage.

[0034] To increase the stability of the shielding structure, the second line 42 includes a conductive ring 223 formed on the back side of the encapsulation 10, and a connection line disposed between the conductive ring 223 and the grounding conductive connection portion 53. The conductive ring 223 contacts and is electrically connected to each of the metal pillars exposed on the back side of the encapsulation 10.

[0035] refer to Figure 3 The grounding metal shielding layer 52 is sheet-shaped and has a plurality of isolation holes for accommodating chip conductive connection portions 51. The area of ​​the chip conductive connection portion 51 is smaller than the isolation holes, and the chip conductive connection portion 51 is spaced apart from the hole wall of the isolation hole. The grounding metal shielding layer 52 also has clearance holes for accommodating grounding conductive connection portions 53. The clearance holes are sized to match the grounding conductive connection portions 53 so that the grounding conductive connection portions 53 contact the hole wall for electrical connection.

[0036] refer to Figure 2 and Figure 5In this embodiment, N equals 2. There are two side metal shielding portions, namely side metal shielding portion 221 and side metal shielding portion 222. One end of side metal shielding portion 221 extends to the front side of the molding compound 10, and the other opposite end extends to the front side of the intermediate metal shielding layer 220 and contacts and connects with the intermediate metal shielding layer 220. One end of side metal shielding portion 222 extends to the back side of the intermediate metal shielding portion and contacts and connects with the intermediate metal shielding layer 220, and the other opposite end extends to the back side of the molding compound 10. Of course, N can also be equal to 3, 4, or other numbers greater than 2. In this case, there are multiple intermediate metal shielding layers 220, and side metal shielding portions are sandwiched between the multiple intermediate metal shielding layers 220. The two ends of the side metal shielding portions extend to two adjacent intermediate metal shielding layers 220 and contact and connect with them.

[0037] The diameter of the metal pillar is 25-27 μm, and the width of the intermediate metal shielding layer 220 is greater than or equal to 28 μm. In this embodiment, the diameter of the metal pillar is 25 μm, and the width of the intermediate metal shielding layer 220 is greater than or equal to 28 μm. The thickness of the intermediate metal shielding layer 220 is 1 kA. The central through-hole of the intermediate metal shielding layer 220 is square. The central through-hole of the intermediate metal shielding layer 220 is at least larger than the size of the chip mounting area at the corresponding height in the chip unit 30.

[0038] refer to Figure 1 and Figure 4 The molding compound 10 has a full-metal shielding layer 21 on its front side. The projection of the full-metal shielding layer 21 on the front side of the molding compound 10 completely covers the projection of the chip unit 30 and extends to the side shielding frame 22, making contact between the side shielding frame 22 and the full-metal shielding layer 21 for electrical connection. The full-metal shielding layer 21 has a thickness of 1KA, which is thin. The full-metal shielding layer 21 is fixed to the surface of the chip unit 30 away from the circuit layer 40, making the fixation of the chip unit 30 more stable. The full-metal shielding layer 21 is either soldered to the chip unit 30 or fixed to it with metal adhesive.

[0039] In this embodiment, the all-metal shielding layer 21, the grounded metal shielding layer 52, and the side shielding frame 22 together form a complete Faraday cage, providing good shielding effect. Furthermore, the grounded metal shielding layer 52 does not affect the signal output of the chip pins and has safe insulation isolation from the chip pins. The inclusion of the intermediate metal shielding layer 220 further enhances its effectiveness in conjunction with the all-metal shielding layer 21 and the grounded metal shielding layer 52 to achieve a superior shielding effect.

[0040] In this embodiment, the chip unit 30 is composed of multiple chips stacked in a fan-shaped pattern (zig zag structure). Of course, the structure of the chip unit 30 is not limited to a fan-shaped stack; other stacking methods are also possible. The electrodes of the multiple chips extend to the back side of the molding compound 10 via metal pillars. Alternatively, the multiple chips can be electrically connected via gold wires, with the topmost chip closest to the circuit layer 40 extending to the back side of the molding compound 10 via metal pillars.

[0041] The all-metal shielding layer 21, the grounded metal shielding layer 52, and the side shielding frame 22 constitute a complete shielding structure. This structure houses the circuit layer 40 and the encapsulated body 10 containing the chip unit 30, forming a sandwich structure that creates a sealed, box-like Faraday cage. The side shielding frame 22 consists of a shielding ring formed by one or more metal pillars. The metal pillars are electrically connected through the intermediate metal shielding layer 220b, the all-metal shielding layer 21, and the conductive ring 223, forming a metal cage with a uniform grid distribution as the shielding structure. Conductivity is achieved through the metal grid. The grounding pins 61 connected to the grounding conductive connection part 53 can be used for electrical connection to the outside, allowing the generated induced current to flow out. There are four grounding pins 61 located at the four corners of the GBA surface of the chip package structure, ensuring that the induced current can be discharged outside the chip package structure, achieving shielding of most wavelengths of electromagnetic signals and providing more reliable shielding.

[0042] To protect the chip package structure, the side of the all-metal shielding layer 21 away from the molding compound 10 is coated with a PI layer or a green oil layer to form a first insulating protective layer covering the all-metal shielding layer 21, and the side of the grounded metal shielding layer 52 away from the molding compound 10 is coated with a PI layer or a green oil layer to form a second insulating protective layer covering the grounded metal shielding layer 52.

[0043] The side shielding frame 22 is a copper shielding frame, Ti shielding frame, TiW shielding frame, Al shielding section, or W shielding frame, etc. The all-metal shielding layer 21 and the grounded metal shielding layer 52 are copper shielding layers, Ti shielding layers, TiW shielding layers, Al shielding layers, or W shielding layers, etc.

[0044] Example 2:

[0045] In Example 1, the intermediate metal shielding layer 220 is an annular band with a width slightly wider than the width of the side metal shielding portions. (Reference) Figure 6 In contrast, in embodiment 2, the intermediate metal shielding layer 220a has a through hole that matches the shape and size of the chip mounting area of ​​the entire chip unit, and is slightly larger than the chip mounting area, so that the width of the intermediate metal shielding layer 220a becomes a clearly visible sheet structure with through holes.

[0046] Example 3:

[0047] refer to Figure 7 In contrast, in embodiment 3, the chip unit 30 is a staggered fan-shaped stacked structure. The through-hole of the intermediate metal shielding layer 220b matches the shape and size of the mounting area of ​​the chip at the same height, and is slightly larger than the shape of the mounting area of ​​the chip at the same height. A portion of the intermediate metal shielding layer 220b extends to the relative position of some chips in the chip unit 30, that is, at least a portion of the intermediate metal shielding layer 220a will be opposite to some chips, so as to form a shielding structure in the chip unit 30 and increase the shielding effect of the chip packaging structure.

[0048] In Examples 1 to 3, the intermediate metal shielding layers 220, 220a, and 220b are all sheet-like structures with a width greater than their height. In contrast, the intermediate metal shielding layers 220, 220a, and 220b can also be annular block-like structures with a width equal to or less than their height.

[0049] In this invention, the chip packaging structure has pins on the back side to form a pin surface (e.g., a GBA surface), and the side opposite to the back side of the chip packaging structure is called the front side (e.g., a MARK surface). In this invention's chip packaging structure, the front side of each part (including the molding compound 10, the circuit layer 40, and the intermediate metal shielding layer) faces the front side of the entire chip packaging structure, and the back side faces the back side of the entire chip packaging structure.

[0050] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A chip packaging structure with shielding performance, comprising a chip unit and a circuit layer encapsulated within a molding compound, wherein the circuit layer is located on the back side of the molding compound and electrically connected to the electrodes of the chip in the chip unit, characterized in that: The molding compound also encapsulates a side shielding frame, which surrounds the mounting area of ​​the chip and is insulated from the chip at intervals. The side shielding frame includes N-1 intermediate metal shielding layers disposed between the front and back sides of the molding compound, and N side metal shielding portions separated by the intermediate metal shielding layers from the front to the back sides of the molding compound. The intermediate metal shielding layers have through holes in the middle for the chip to pass through, so that the intermediate metal shielding layers are annular and surround the mounting area of ​​the chip, where N is greater than or equal to 2.

2. The chip packaging structure with shielding performance as described in claim 1, characterized in that: Each of the aforementioned side metal shielding portions is formed by a plurality of metal pillars surrounding the mounting area of ​​the chip.

3. The chip packaging structure with shielding performance as described in claim 2, characterized in that: The diameter of the metal pillar is 25-27 μm, and the width of the intermediate metal shielding layer is greater than or equal to 28 μm.

4. The chip packaging structure with shielding performance as described in claim 1, characterized in that: The intermediate metal shielding layer is in the form of a sheet parallel to the front side of the encapsulated body, and the thickness of the intermediate metal shielding layer is 1KA.

5. The chip packaging structure with shielding performance as described in claim 1, characterized in that: The width of the intermediate metal shielding layer is greater than the width of the side metal shielding portion, and the projection of the intermediate metal shielding layer on the front of the molding compound covers the projection of the side metal shielding portion.

6. The chip packaging structure with shielding performance as described in claim 1, characterized in that: It also includes an all-metal shielding layer, which is formed on the front side of the molding compound, and the projection of the all-metal shielding layer on the front side of the molding compound fully covers the projection of the chip unit and extends to the side metal shielding portion, and the side metal shielding portion contacts the all-metal shielding layer for electrical connection.

7. The chip packaging structure with shielding performance as described in claim 1 or 6, characterized in that: The circuit layer has a first line electrically connected to the electrode of the chip in the chip unit, and a second line electrically connected to the side shield. The circuit layer has a chip conductive connection portion electrically connected to the first line and a ground conductive connection portion electrically connected to the second line on the back side away from the molding compound.

8. The chip packaging structure with shielding performance as described in claim 7, characterized in that: A grounded metal shielding layer is formed on the back side of the circuit layer, which is insulated from the conductive connection portion of the chip. The grounded metal shielding layer is electrically connected to the grounded conductive connection portion.

9. The chip packaging structure with shielding performance as described in claim 8, characterized in that: The grounding metal shielding layer is sheet-shaped and has a plurality of isolation holes for accommodating the conductive connection portion of the chip and clearance holes for accommodating the conductive connection portion of the ground. The area of ​​the conductive connection portion of the chip is smaller than that of the isolation hole, and the conductive connection portion of the chip is spaced apart from the hole wall of the isolation hole. The size of the conductive connection portion of the ground is matched with that of the clearance hole, so that the conductive connection portion of the ground is in contact with the hole wall of the clearance hole for electrical connection.

10. The chip packaging structure with shielding performance as described in claim 7, characterized in that: Each of the side metal shielding portions is surrounded by a plurality of metal pillars around the mounting area of ​​the chip. The second circuit includes a conductive ring formed on the front side of the circuit layer adjacent to the molded body, and a connection line disposed between the conductive ring and the ground conductive connection portion. The conductive ring contacts and is electrically connected to each of the metal pillars exposed on the back side of the molded body.

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