Chip package structure supported by silicon plate

Abstract

The utility model discloses a kind of chip packaging structures of silicon plate support, including support plate, chip unit, electrical connection component, plastic package, first rewiring layer and second rewiring layer, the first rewiring layer is supported on the support plate, the support plate is silicon plate, the chip unit includes one or more bare chip stacked on the first rewiring layer, the plastic package is molded on the first rewiring layer with the chip unit, the second rewiring layer is located at the side of the plastic package away from the support plate, the electrical connection component is together with the bare chip of the chip unit, the first rewiring layer and second rewiring layer electrically connected.Compared with prior art, the utility model leaves silicon plate on chip packaging structure after packaging, without key unbinding to remove carrier plate, save process, also make the structural stability of chip packaging structure strong.

Description

Technical Field

[0001] This utility model relates to semiconductor packaging, and more particularly to a chip packaging structure supported by a silicon substrate. Background Technology

[0002] With the rapid pace of technological advancements in smart terminal devices, from large industrial equipment to consumer mobile terminals, integrated circuit memory chips—their core component—remain at the heart of technological evolution. In the 3D packaging process, traditional methods primarily employ wire bonding (WB) technology, using gold or silver wires to achieve vertical interconnection of multiple chip layers. This approach still dominates the stacked packaging of LPDDR memory and flash memory chips. It's worth noting that as mobile smart terminals evolve towards ultra-thinness and integration, this technological innovation trend and the evolution of consumer electronics form a two-way driving force: on the one hand, the demand for device miniaturization drives continuous breakthroughs in packaging technology; on the other hand, breakthroughs in advanced packaging technology provide more possibilities for terminal product design. This synergistic evolution of technology and market demand is reshaping the entire electronics manufacturing industry.

[0003] During the packaging process, the chip is typically mounted on a temporary carrier board. After packaging, the temporary carrier board is removed from the chip packaging structure by debonding. This process is complex, and the packaging structure is easily damaged after debonding and removing the temporary carrier board, which affects the transportation and storage safety of the packaging structure.

[0004] Therefore, there is an urgent need for a silicon-supported chip packaging structure that can solve the above problems. Utility Model Content

[0005] The purpose of this invention is to provide a silicon substrate-supported chip packaging structure that leaves the silicon substrate on the chip packaging structure after packaging, eliminating the need for debonding and removing the carrier board, saving process time, and also making the chip packaging structure more stable.

[0006] To achieve the above objectives, this utility model provides a silicon substrate-supported chip packaging structure, including a support plate, a chip unit, an electrical connection component, a molding compound, a first rewiring layer, and a second rewiring layer. The first rewiring layer is supported on the support plate, which is a silicon substrate. The chip unit includes one or more bare dies stacked sequentially on the first rewiring layer. The molding compound encapsulates the chip unit on the first rewiring layer. The second rewiring layer is located on the side of the molding compound away from the support plate. The electrical connection component electrically connects the bare dies of the chip unit, the first rewiring layer, and the second rewiring layer together.

[0007] Preferably, the silicon substrate is a silicon substrate without conductive vias.

[0008] Preferably, the thickness of the silicon substrate is greater than 40 μm.

[0009] Preferably, the bare dies are multiple and staggered on the first wiring layer, so that the chip cells are in a fan-shaped stacked structure.

[0010] Preferably, the electrical connection component includes leads electrically connected between the bare die and the first redistribution layer, and conductive posts formed between the first redistribution layer and the second redistribution layer.

[0011] Specifically, the lead is electrically connected to the non-top-layer bare die, and the electrical connection assembly further includes a metal protrusion protruding on the top-layer bare die in the chip unit. The metal protrusion is exposed on the top surface of the molding compound away from the support plate, and the second redistribution layer is electrically connected to the metal protrusion.

[0012] Preferably, the silicon substrate-supported chip packaging structure further includes a functional chip, which is fixed on the first multiple wiring layer. The molding compound further encapsulates the functional chip, and the electrical connection component electrically connects the functional chip to the first multiple wiring layer and / or the second multiple wiring layer and / or the bare die. This solution fixes the functional chip on the first multiple wiring layer in a single step with the fixing of the bare die, simplifying the packaging process, reducing costs, and facilitating electrical connections between the functional chip and the bare die, the first multiple wiring layer, and the second multiple wiring layer.

[0013] Specifically, the functional chip is a logic control chip, a sensor chip, or a SOC chip, etc.

[0014] Specifically, the functional chip is electrically connected to the non-top-layer bare die in the chip unit via leads; and / or, the functional chip is electrically connected to the second wiring layer via conductive pillars. The functional chip of this invention can be electrically connected to the second wiring layer in various ways, offering diverse assembly methods and high flexibility.

[0015] Preferably, the conductive pillars include electroplated metal pillars. Compared with traditional vertical wire bonding technology, which reduces the yield due to mechanical offset during vertical wire bonding, the chip packaging structure of this invention has good electrical connection stability and high yield.

[0016] Specifically, the metal pillar has a metal protective layer near the top of the second redistribution layer. This metal protective layer is a nickel layer or a nickel-gold composite layer, so that the conductive pillar has a copper-nickel composite structure or a copper-nickel-gold composite structure, thereby enhancing the oxidation resistance and welding performance of the conductive pillar.

[0017] Preferably, the second redistribution layer has a conductive connection portion on the side away from the support plate, and the conductive connection portion has solder balls.

[0018] Compared with the prior art, this utility model uses a silicon plate as a support plate during packaging, and leaves the silicon plate in the packaging structure as a support layer after packaging. This not only eliminates the need to remove the support plate after packaging, saving processes, but also makes the chip packaging structure more stable as a support layer, ensuring and not affecting the heat dissipation of the chip packaging structure. Furthermore, the first wiring layer at the bottom of the chip packaging structure can be made very thin. Attached Figure Description

[0019] Figure 1 This is a structural diagram of the silicon plate-supported chip packaging structure in Embodiment 1 of this utility model.

[0020] Figure 2 This is a structural diagram of the silicon plate-supported chip packaging structure in Embodiment 2 of this utility model. Detailed Implementation

[0021] To explain in detail the technical content, structural features, objectives and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0022] Example 1: refer to Figure 1 This utility model discloses a silicon substrate-supported chip packaging structure, including a support plate 10, a chip unit 20, an electrical connection component, a molding compound 40, a first redistribution layer 51, and a second redistribution layer 52. The first redistribution layer 51 is supported on the support plate 10, which is a silicon substrate. The chip unit 20 includes one or more bare dies 21 stacked sequentially on the first redistribution layer 51. The molding compound 40 encapsulates the chip unit 20 on the first redistribution layer 51. The second redistribution layer 52 is located on the side of the molding compound 40 away from the support plate 10. The electrical connection component electrically connects the bare dies 21 of the chip unit 20, the first redistribution layer 51, and the second redistribution layer 52 together.

[0023] refer to Figure 1 The second redistribution layer 52 has a conductive connection portion 61 on the side away from the support plate 10, and the conductive connection portion 61 has solder balls 62. The conductive connection portion 61 is a pad formed by metal bumps or metal dots, and the solder balls 62 are implanted solder balls, gold balls, etc.

[0024] The silicon substrate is a silicon substrate without conductive vias. The thickness of the silicon substrate is 20~200μm.

[0025] refer to Figure 1Multiple bare dies 21 are stacked in a staggered manner on the first multiple wiring layer 51 to form a fan-shaped stacked structure for the chip unit 20. In this embodiment, four layers of bare dies 21 are stacked. However, the bare dies 21 can also be stacked with 2, 3, 5, or even 8 layers, and are not limited to 4 layers. The bare dies 21 are memory chips. The bare dies 21 are attached to the first multiple wiring layer 51 via a DAF film, and multiple bare dies 21 are sequentially attached and fixed together via the DAF film. The multiple bare dies 21 can be stacked in a staggered manner in one direction or in different directions.

[0026] In this embodiment, when adjacent bare dies 21 are stacked, the misalignment length is one-quarter of the length of the bare die 21.

[0027] refer to Figure 1 The electrical connection assembly includes a first lead 31 electrically connected between the bare die 21 and the first redistribution layer 51, and a first conductive post 32 formed between the first redistribution layer 51 and the second redistribution layer 52.

[0028] refer to Figure 1 The first lead 31 is electrically connected to the non-top-layer bare die 21. The electrical connection assembly also includes a metal bump 33 on the electrode of the top-layer bare die 21 in the chip unit 20. The metal bump 33 is exposed on the top surface of the molding compound 40 away from the support plate 10, and the second redistribution layer 52 is electrically connected to the metal bump 33. The metal bump 33 can be a bump made using bump fabrication technology, or it can be an implanted gold ball, etc. The first lead 31 is a conductive metal wire such as gold, silver, or copper. The arc height of the first lead 31 needs to be greater than or equal to the stacking spacing between the bare dies 21 to avoid the lower-layer bare die 21 during wire bonding of the stacked bare dies. Typically, the arc height of the first lead 31 is greater than or equal to 100 μm.

[0029] The top surface of the first wiring layer 51 has a first line electrically connected to the first lead 31 and the first conductive post 32, and the bottom surface of the second wiring layer 52 has a second line electrically connected to the first conductive post 32 and the metal protrusion 33. The conductive connection part 61 on the top surface of the second wiring layer 52 is electrically connected to the second line through the line in the second wiring layer 52.

[0030] Of course, in a different way, the bare dies 21 can also be electrically connected together by making leads between them.

[0031] In this embodiment, the non-top-layer bare die 21 leads the electrical signal to the first rewiring layer 51 through the first lead 31. After being connected in series and parallel in the first rewiring layer 51, the signal is led to the second rewiring layer 52 through the first conductive post 32. The top-layer bare die 21 guides the electrical signal to the second rewiring layer 52 through the metal bump 33. The second rewiring layer connects the electrical signal of the bare die 21 in series and parallel and leads it to the conductive connection portion 61, and then leads it out through the solder balls 62 on the conductive connection portion 61.

[0032] The first conductive post 32 includes an electroplated metal post 320. Compared to traditional vertical wire bonding technology, which suffers from reduced yield due to mechanical misalignment during vertical wire bonding, the chip packaging structure of this invention exhibits good electrical connection stability and a high yield. The metal post 320 can be made of copper, titanium, or other materials.

[0033] The bottom of the metal pillar 320 is also provided with a metal transition layer 321. The metal transition layer 322 is sandwiched between the first conductive pillar 32 and the first redistribution layer 51. The metal transition layer 321 is a Ti / Cu transition layer or a TiW / Cu transition layer. The thickness of the metal transition layer is 50-200nm, which makes the adhesion between the first conductive pillar 32 and the first redistribution layer 51 better.

[0034] Specifically, the metal pillar 320 has a metal protective layer 322 near the top of the second redistribution layer 52. The metal protective layer 322 is a nickel layer or a nickel-gold composite layer, so that the first conductive pillar 32 is a copper-nickel composite structure or a copper-nickel-gold composite structure, thereby enhancing the oxidation resistance and welding performance of the first conductive pillar 32.

[0035] An insulating protective layer is formed at the top of the second rewiring layer 52, offset from the conductive connection portion 61. This insulating protective layer is a polyimide layer or a silicon nitride layer, used to prevent oxidation and mechanical damage to the second rewiring layer 52.

[0036] Example 2: refer to Figure 2This utility model discloses a silicon substrate-supported chip packaging structure, including a support plate 10, chip units 20, functional chips 22, electrical connection components, a molding compound 40, a first redistribution layer 51, and a second redistribution layer 52. The first redistribution layer 51 is supported on the support plate 10, which is a silicon substrate. The chip units 20 include one or more bare dies 21 stacked sequentially on the first redistribution layer 51. The functional chips 22 are stacked on the first redistribution layer 51. The molding compound 40 encapsulates the chip units 20 and functional chips 22 on the first redistribution layer 51. The second redistribution layer 52 is located on the side of the molding compound 40 away from the support plate 10. The electrical connection components electrically connect the bare dies 21, the functional chips 22, the first redistribution layer 51, and the second redistribution layer 52 together.

[0037] refer to Figure 2 The second redistribution layer 52 has a conductive connection portion 61 on the side away from the support plate 10, and the conductive connection portion 61 has solder balls 62. The conductive connection portion 61 is a pad formed by metal bumps or metal dots, and the solder balls 62 are implanted solder balls, gold balls, etc.

[0038] The silicon substrate is a silicon substrate without conductive vias. The thickness of the silicon substrate is greater than 40 μm.

[0039] The functional chip 22 is fixed on the first redistribution layer 51, and the functional chip 22 is a logic control chip, a sensor chip, or a SOC chip.

[0040] refer to Figure 2 Multiple bare dies 21 are stacked in a staggered manner on the first multiple wiring layer 51 to form a fan-shaped stacked structure for the chip unit 20. In this embodiment, the bare dies 21 are stacked with 4 layers. However, the bare dies 21 can also be stacked with 2, 3, 5, or even 8 layers, and are not limited to 4 layers. The bare dies 21 are memory chips. The bare dies 21 are attached to the first multiple wiring layer 51 by a DAF film, and multiple bare dies 21 are sequentially attached and fixed together by the DAF film. The multiple bare dies 21 can be stacked in a staggered manner in one direction or in different directions.

[0041] refer to Figure 2The electrical connection assembly includes a first lead 31 electrically connected between the bare die 21 and the first redistribution layer 51, a first conductive post 32 formed between the first redistribution layer 51 and the second redistribution layer 52, a second lead 35 electrically connected between the functional chip 22 and the bare die 21 not at the top layer, and a second conductive post 34 electrically connected between the top of the functional chip 22 and the second redistribution layer 52. The first lead 31 and the second lead 35 are metallic conductive lines such as gold, silver, or copper wires. The arc height of the first lead 31 must be greater than or equal to the stacking spacing between the bare dies 21, and the highest point of the arc of the second lead 35 must not exceed the top of the chip unit 22. In this embodiment, the arc height of the first lead 31 is greater than or equal to 100 μm.

[0042] Of course, in a different way, the bare dies 21 can also be electrically connected together by making leads between them.

[0043] refer to Figure 2 The first lead 31 is electrically connected to the non-top-layer bare die 21. The electrical connection assembly also includes a metal bump 33 on the electrode of the top-layer bare die 21 in the chip unit 20. The metal bump 33 is exposed on the top surface of the molding compound 40 away from the support plate 10. The second redistribution layer 52 is electrically connected to the metal bump 33. The metal bump 33 can be a bump made using bump fabrication technology, or it can be an implanted gold ball, etc.

[0044] In this embodiment, the non-top-layer die 21 leads the electrical signal to the first redistribution layer 51 through the first lead 31. After being connected in series and parallel through the first redistribution layer 51, the signal is led to the second redistribution layer 52 through the first conductive post 32. The top-layer die 21 guides the electrical signal to the second redistribution layer 52 through the metal bump 33. The electrical signal of the functional chip 22 is electrically connected to a die 21 through the second lead 35 and is also led to the second redistribution layer through the second conductive post 34. The second redistribution layer connects the electrical signals of the die 21 and the functional chip 22 in series and parallel and leads them to the conductive connection portion 61, and then leads them out through the solder balls 62 on the conductive connection portion 61.

[0045] The top surface of the first wiring layer 51 has a first line electrically connected to the first lead 31 and the first conductive post 32, and the bottom surface of the second wiring layer 52 has a second line electrically connected to the first conductive post 32, the metal protrusion 33 and the second conductive post 34. The conductive connection part 61 on the top surface of the second wiring layer 52 is electrically connected to the second line through the line in the second wiring layer 52.

[0046] The first conductive pillar 32 and the second conductive pillar 34 include electroplated metal pillars 320. These metal pillars 320 can be copper, titanium, or the like.

[0047] The bottom of the metal pillar 320 is also provided with a metal transition layer 321, which is sandwiched between the first conductive pillar 32 and the first redistribution layer 51. The metal transition layer 321 is a Ti / Cu transition layer or a TiW / Cu transition layer, and the thickness of the metal transition layer is 50-200nm, which makes the adhesion between the metal pillar 320 and the first redistribution layer 51 better.

[0048] Specifically, the metal post 320 of the first conductive post 32 has a metal protective layer 322 near the top of the second redistribution layer 52. The metal protective layer 322 is a nickel layer or a nickel-gold composite layer, so that the first conductive post 32 is a copper-nickel composite structure or a copper-nickel-gold composite structure, thereby enhancing the oxidation resistance and welding performance of the first conductive post 32.

[0049] An insulating protective layer is formed at the top of the second rewiring layer 52, offset from the conductive connection portion 61. This insulating protective layer is a polyimide layer or a silicon nitride layer, used to prevent oxidation and mechanical damage to the second rewiring layer 52.

[0050] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A silicon substrate-supported chip packaging structure, characterized in that: The device includes a support plate, a chip unit, an electrical connection assembly, a molding compound, a first super-wiring layer, and a second super-wiring layer. The first super-wiring layer is supported on the support plate, which is a silicon substrate. The chip unit includes one or more bare dies stacked sequentially on the first super-wiring layer. The molding compound encapsulates the chip unit on the first super-wiring layer. The second super-wiring layer is located on the side of the molding compound away from the support plate. The electrical connection assembly electrically connects the bare dies of the chip unit, the first super-wiring layer, and the second super-wiring layer together.

2. The silicon substrate-supported chip packaging structure as described in claim 1, characterized in that: The bare dies are multiple and stacked in a staggered manner on the first wiring layer, so that the chip unit has a fan-shaped stacked structure.

3. The silicon substrate-supported chip packaging structure as described in claim 1, characterized in that: The electrical connection component includes leads electrically connected between the bare die and the first redistribution layer, and conductive posts formed between the first redistribution layer and the second redistribution layer.

4. The silicon substrate-supported chip packaging structure as described in claim 3, characterized in that: The lead is electrically connected to the non-top-layer bare die, and the electrical connection assembly further includes a metal protrusion protruding on the top-layer bare die in the chip unit. The metal protrusion is exposed on the top surface of the molding compound away from the support plate, and the second redistribution layer is electrically connected to the metal protrusion.

5. The silicon substrate-supported chip packaging structure as described in claim 1, characterized in that: It also includes a functional chip, which is fixed on the first rewiring layer. The molding compound further encapsulates the functional chip therein, and the electrical connection component electrically connects the functional chip to the first rewiring layer and / or the second rewiring layer and / or the bare die.

6. The silicon substrate-supported chip packaging structure as described in claim 5, characterized in that: The functional chip is electrically connected to the bare die (not the top layer) in the chip unit via leads; and / or, The functional chip is electrically connected to the second redistribution layer via conductive pillars.

7. The silicon substrate-supported chip packaging structure as described in claim 5, characterized in that: The functional chip is a logic control chip, a sensor chip, or a SOC chip.

8. The silicon substrate-supported chip packaging structure as described in claim 3 or 6, characterized in that: The conductive pillars include electroplated metal pillars.

9. The silicon substrate-supported chip packaging structure as described in claim 8, characterized in that: The metal pillar has a metal protective layer near the top of the second redistribution layer, which is a nickel layer or a nickel-gold composite layer.

10. The silicon substrate-supported chip packaging structure as described in claim 1, characterized in that: The second redistribution layer has a conductive connection portion on the side away from the support plate, and the conductive connection portion has solder balls.

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