Multi-functional test fixture card and server

Abstract

The utility model provides a kind of multifunctional test fixture card and server, it is related to server technical field.The utility model provides multifunctional test fixture card including substrate, signal processing chip being set on substrate, PCIe gold finger interface being set on the first side of substrate, OCP gold finger interface being set on the second side of substrate and E3.S gold finger interface being set on the third side of substrate, wherein, PCIe gold finger interface is used to insert server PCIe slot, OCP gold finger interface is used to insert server OCP slot, E3.S gold finger interface is used to insert server E3.S hard disk slot;Signal processing chip is electrically connected with PCIe gold finger interface, OCP gold finger interface and E3.S gold finger interface respectively, to simulate the function of PCIe mark card, OCP card and E3.S disk by processing interface signal.The utility model provides a kind of multifunctional test fixture card and server, and server can be tested before relevant product is launched.

Description

Technical Field

[0001] This utility model relates to the field of server technology, and in particular to a multifunctional test fixture card and server. Background Technology

[0002] In today's rapidly developing information technology landscape, servers, as key devices for data processing and storage, are of paramount importance in terms of performance and stability. From design to deployment, servers undergo rigorous and comprehensive testing.

[0003] However, in the existing technology, once the server design is completed, related products such as E3.S (solid-state drive form factor standard), PCIe (high-speed peripheral interconnect standard) cards, and OCP (open computing project) cards are often not launched in a timely manner. However, the server testing work cannot be stopped because of this and needs to be carried out on time to ensure the reliability and functionality of the entire system. Utility Model Content

[0004] To address the problems mentioned in the background art, this utility model provides a multifunctional test fixture card and server, which can test the server before the relevant product is launched.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] In a first aspect, this utility model provides a multifunctional test fixture card, comprising:

[0007] substrate;

[0008] Signal processing chip disposed on substrate;

[0009] The PCIe gold finger interface located on the first side of the substrate is used to connect to the server PCIe slot.

[0010] The OCP gold finger interface, located on the second side of the substrate, is used to connect to the server's OCP slot.

[0011] The E3.S gold finger interface located on the third side of the substrate is used to connect to the server E3.S hard drive slot;

[0012] The signal processing chip is electrically connected to the PCIe gold finger interface, OCP gold finger interface and E3.S gold finger interface respectively, so as to simulate the functions of PCIe standard card, OCP card and E3.S disk by processing interface signals.

[0013] As an optional implementation, the signal processing chip includes a switching chip, which is electrically connected to the PCIe gold finger interface and the OCP gold finger interface, thereby realizing signal verification of the PCIe to OCP link by simulating a PCIe link terminal device.

[0014] As an optional implementation, the signal processing chip also includes a complex programmable logic device (CPLD) electrically connected to the E3.S gold finger interface to verify the E3.S link by generating test signal sequences and detecting feedback responses.

[0015] As an optional implementation, the switching chip supports the sixth generation PCIe protocol and can dynamically identify 16-channel and 4-channel link modes.

[0016] As an optional implementation, the system also includes a support assembly, which includes a PCIe support, an OCP support, and an E3.S support. The PCIe support, OCP support, and E3.S support are detachably connected to the substrate via threaded connectors, so that the fixture card can be adapted to any of the physical forms of the PCIe slot, OCP slot, or E3.S slot.

[0017] As an optional implementation, a sensor module is also included, which is electrically connected to a complex programmable logic device. The sensor module is used at least to detect the temperature and voltage parameters of the fixture card during operation, so as to monitor the operating status of the fixture card in real time.

[0018] As an optional implementation, the fixture card also includes a flash memory module electrically connected to the switching chip, which is used to store at least the configuration information and test data of the switching chip.

[0019] As an alternative implementation, the jig card also includes an oscillator electrically connected to a complex programmable logic device for providing a clock signal to the jig card's circuitry.

[0020] As an optional implementation, the switching chip includes the PEX90104 model chip.

[0021] Secondly, this utility model also provides a server, including a server motherboard under test and the fixture card mentioned in the first aspect. The fixture card is adapted to the PCIe slot, OCP slot or E3.S slot on the motherboard by changing the bracket.

[0022] Secondly, this utility model also provides a scooter, including the scooter steering damping structure described in the first aspect.

[0023] The multifunctional test fixture card provided by this utility model includes a substrate, a signal processing chip disposed on the substrate, a PCIe gold finger interface disposed on a first side of the substrate, an OCP gold finger interface disposed on a second side of the substrate, and an E3.S gold finger interface disposed on a third side of the substrate. The PCIe gold finger interface is used to connect to a server PCIe slot, the OCP gold finger interface is used to connect to a server OCP slot, and the E3.S gold finger interface is used to connect to a server E3.S hard drive slot. The signal processing chip is electrically connected to the PCIe gold finger interface, the OCP gold finger interface, and the E3.S gold finger interface respectively, to simulate the functions of a PCIe card, an OCP card, and an E3.S drive by processing interface signals.

[0024] This utility model provides a multifunctional test fixture with a base plate on which a signal processing chip is integrated. PCIe, OCP, and E3.S gold finger interfaces are respectively provided on different sides of the base plate, which can be plugged into PCIe slots, OCP slots, and E3.S hard drive slots of servers. The signal processing chip is electrically connected to each interface and can process the interface signals to simulate the functions of PCIe cards, OCP cards, and E3.S drives. This allows servers to be tested using this fixture even before related products are released, avoiding test delays due to hardware incompatibility, thus ensuring the timely progress of server testing and verifying the reliability and functionality of the entire system. Furthermore, because this fixture can simulate multiple hardware components simultaneously, it greatly improves testing efficiency and flexibility, and reduces testing costs and time. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A circuit connection diagram of the multifunctional test fixture card provided in this embodiment of the utility model;

[0027] Figure 2 A schematic diagram of the structure of the multifunctional test fixture card provided in this embodiment of the utility model;

[0028] Figure 3 A schematic diagram showing the multifunctional test fixture and PCIe bracket provided in this embodiment of the utility model before and after installation;

[0029] Figure 4A schematic diagram showing the multifunctional test fixture and OCP bracket provided in this embodiment of the utility model before and after installation;

[0030] Figure 5 The diagram shows the multifunctional test fixture card and E3.S bracket before and after installation, as provided in the embodiments of this utility model.

[0031] Explanation of reference numerals in the attached figures:

[0032] 100-Jig Card;

[0033] 110-Substrate;

[0034] 120-PCIe gold finger interface;

[0035] 130-OCP gold finger interface;

[0036] 140-E3.S Gold Finger Interface;

[0037] 150 - Switching chip;

[0038] 160 - Complex Programmable Logic Device;

[0039] 170-PCIe bracket;

[0040] 180-OCP stent;

[0041] 190-E3.S bracket;

[0042] 200 - Threaded connector;

[0043] 210 - Sensor Module;

[0044] 220 - Flash memory module;

[0045] 230 - Oscillator. Detailed Implementation

[0046] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0047] In this application, the terms “upper,” “lower,” “left,” “right,” “front,” “back,” “top,” “bottom,” “inner,” “outer,” “vertical,” “horizontal,” “lateral,” and “longitudinal” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this utility model and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0048] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this utility model according to the specific circumstances.

[0049] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this utility model based on the specific circumstances.

[0050] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.

[0051] In the existing technology, once the server design is completed, related products such as E3.S (solid-state drive form factor standard), PCIe (high-speed peripheral interconnect standard) cards, and OCP (open computing project) cards are often not launched in a timely manner. However, the server testing work cannot be stopped because of this and needs to be carried out on time to ensure the reliability and functionality of the entire system.

[0052] In view of this, the present invention provides a multifunctional test fixture card, including a substrate, a signal processing chip disposed on the substrate, a PCIe gold finger interface disposed on a first side of the substrate, an OCP gold finger interface disposed on a second side of the substrate, and an E3.S gold finger interface disposed on a third side of the substrate. The PCIe gold finger interface is used to connect to a server PCIe slot, the OCP gold finger interface is used to connect to a server OCP slot, and the E3.S gold finger interface is used to connect to a server E3.S hard drive slot. The signal processing chip is electrically connected to the PCIe gold finger interface, the OCP gold finger interface, and the E3.S gold finger interface, respectively, and can simulate the functions of a PCIe card, an OCP card, and an E3.S drive by processing interface signals. This allows servers to be tested using this fixture card even before related products are released, avoiding test work stagnation due to hardware incompatibility, thus ensuring the timely progress of server testing and ensuring the reliability and functionality of the entire system are verified. Furthermore, this fixture card can simulate multiple hardware components simultaneously, greatly improving testing efficiency and flexibility, and reducing testing costs and time.

[0053] Figure 1 A circuit connection diagram of the multifunctional test fixture card provided in this embodiment of the utility model; Figure 2 A schematic diagram of the structure of the multifunctional test fixture card provided in this embodiment of the utility model; Figure 3 A schematic diagram showing the multifunctional test fixture and PCIe bracket provided in this embodiment of the utility model before and after installation; Figure 4 A schematic diagram showing the multifunctional test fixture and OCP bracket provided in this embodiment of the utility model before and after installation; Figure 5 The diagram shows the multifunctional test fixture card and E3.S bracket before and after installation, as provided in the embodiments of this utility model.

[0054] You can refer to this. Figures 1 to 5 This utility model embodiment provides a multifunctional test fixture card 100, including:

[0055] substrate 110;

[0056] Signal processing chip disposed on substrate 110;

[0057] The PCIe gold finger interface 120, located on the first side of the substrate 110, is used to connect to the server PCIe slot.

[0058] The OCP gold finger interface 130, located on the second side of the substrate 110, is used to connect to the server OCP slot.

[0059] The E3.S gold finger interface 140, located on the third side of the substrate 110, is used to connect to the server E3.S hard disk slot.

[0060] The signal processing chip is electrically connected to the PCIe gold finger interface 120, the OCP gold finger interface 130 and the E3.S gold finger interface 140 respectively, so as to simulate the functions of the PCIe standard card, the OCP card and the E3.S disk by processing the interface signals.

[0061] The multifunctional test fixture 100 provided in this embodiment of the invention has a base plate 110, on which a signal processing chip is integrated. PCIe gold finger interfaces 120, OCP gold finger interfaces 130, and E3.S gold finger interfaces 140 are respectively provided on different sides of the base plate 110, which can be plugged into the PCIe slot, OCP slot, and E3.S hard drive slot of a server, respectively. The signal processing chip is electrically connected to each interface and can process the interface signals to simulate the functions of PCIe standard cards (e.g., NIC-network card or GPU-graphics processor), OCP cards, and E3.S hard drives. This allows servers to be tested using the fixture 100 even before related products are released, avoiding test work stagnation due to hardware incompatibility, thus ensuring the timely progress of server testing and verifying the reliability and functionality of the entire system. Furthermore, since the fixture 100 can simulate multiple hardware simultaneously, it greatly improves testing efficiency and flexibility, and reduces testing costs and time.

[0062] In the above embodiments, the signal processing chip may include a switching chip 150, which is electrically connected to the PCIe gold finger interface 120 and the OCP gold finger interface 130, thereby simulating the signal verification of the PCIe to OCP link by simulating the PCIe link terminal device. In server testing, the signal transmission stability of the PCIe and OCP links is crucial to system performance. By simulating the signal interaction of real devices, the switching chip 150 can verify link compatibility, data transmission rate, and protocol consistency in advance, avoiding problems such as signal delay and packet loss caused by hardware incompatibility. For example, in a test scenario of a certain type of server, since the matching OCP card is not yet in mass production, a multi-functional test fixture card 100 integrating the switching chip 150 is used. The PCIe gold finger interface 120 is inserted into the server's PCIe slot, and the OCP gold finger interface 130 is connected to the server's OCP slot. The switching chip 150 simulates the signal interaction logic of the PCIe link terminal device to perform stress testing and protocol verification on the OCP link. It successfully detects the signal timing abnormality problem in the server's OCP slot, completes optimization before the hardware is officially put into use, and significantly improves testing efficiency and system reliability.

[0063] In the above embodiments, the signal processing chip may further include a Complex Programmable Logic Device 160 (CPLD). The CPLD is electrically connected to the E3.S gold finger interface 140 to verify the E3.S link by generating test signal sequences and detecting return responses. It is understood that the CPLD, with its flexible logic programming capabilities, can generate test signal sequences conforming to the E3.S protocol specifications, such as initialization handshake signals, read / write command frames, and data block transfers, simulating the real-world working scenario of a solid-state drive. These test signals are transmitted to the server's E3.S hard drive slot via the E3.S gold finger interface 140, triggering the server's response mechanism. The CPLD can also monitor the response signals returned from the server, comparing the expected response with the actual returned data using its built-in timing analysis module and protocol parsing engine. For example, after performing a write operation, the CPLD verifies whether the write confirmation signal returned by the server conforms to the timing requirements of the E3.S protocol; during a read operation, it checks whether the checksum of the returned data is correct. If an anomaly is detected, the CPLD can accurately record the timestamp of the error, signal characteristics, and other information, and feed it back to the test system through a dedicated channel. This CPLD-based E3.S link verification scheme is highly flexible, allowing dynamic adjustment of test signal parameters (such as signal strength and timing offset) according to different server models and test requirements. It simulates signal transmission under various extreme conditions, comprehensively verifying the reliability and stability of the E3.S link, and ensuring the server's data storage and transmission performance in real-world application environments. Through this simulation and conversion mechanism, even if the actual PCIe standard card, OCP card, and E3.S disk are not yet available, the multi-functional test fixture card 100 can effectively verify the connectivity, compatibility, and performance of each link on the server, providing reliable assurance for server testing.

[0064] In the above embodiments, the switching chip 150 supports the sixth-generation PCIe protocol and can dynamically identify 16-channel and 4-channel link modes. It is understood that the sixth-generation PCIe protocol can significantly increase data transfer rates, reaching up to 32GT / s, while maintaining good compatibility with previous PCIe protocol versions, ensuring device compatibility and a smooth upgrade transition. The switching chip 150's ability to dynamically identify 16-channel and 4-channel link modes allows for faster transmission of large data files, such as high-definition video rendering project files, using the 16-channel mode; while when connecting devices with low bandwidth requirements, such as ordinary printers, switching to the 4-channel mode can meet the needs, saving resources. This dynamic identification capability greatly improves the chip's adaptability to different server architectures and devices, effectively enhancing data transfer efficiency and device versatility.

[0065] The above embodiments may further include a bracket assembly, which includes a PCIe bracket 170, an OCP bracket 180, and an E3.S bracket 190. The PCIe bracket 170, OCP bracket 180, and E3.S bracket 190 are detachably connected to the substrate 110 via threaded connectors 200, allowing the jig card 100 to adapt to any physical form of a PCIe slot, OCP slot, or E3.S slot. By providing a bracket assembly including the PCIe bracket 170, OCP bracket 180, and E3.S bracket 190, and using threaded connectors 200 to detachably connect them to the substrate 110, the jig card 100 achieves adaptation to any physical form of a PCIe slot, OCP slot, or E3.S slot. The threaded connection method is simple and reliable, facilitating installation and disassembly. When different slots need to be adapted, simply unscrew or screw on the threaded connectors 200 of the corresponding brackets. For example, in server hardware testing scenarios, to test a PCIe slot, the PCIe bracket 170 is mounted on the substrate 110 via the threaded connector 200. The bracket's size and structure match the PCIe slot, allowing the jig card 100 to be precisely inserted into the slot for testing. To test an OCP slot, the PCIe bracket 170 is removed and replaced with the OCP bracket 180, ensuring a good connection between the jig card 100 and the OCP slot. Similarly, the E3.S bracket 190 allows the jig card 100 to be adapted to the E3.S slot. This design greatly improves the versatility and flexibility of the jig card 100, avoiding the cumbersome and costly process of customizing a jig card 100 for each slot, effectively improving the convenience and efficiency of testing.

[0066] In the above embodiments, a sensor module 210 may also be included. The sensor module 210 is electrically connected to the complex programmable logic device 160. The sensor module 210 is used at least to detect the temperature and voltage parameters of the fixture card 100 during operation, so as to monitor the operating status of the fixture card 100 in real time. By electrically connecting the sensor module 210 to the complex programmable logic device 160, real-time monitoring of the operating status of the fixture card 100 can be achieved. It can be understood that the sensor module 210 has built-in temperature and voltage sensors to collect the temperature and voltage parameters of the fixture card 100 during operation, respectively. The temperature sensor uses components such as thermistors to sense temperature changes and converts the temperature signal into an electrical signal; the voltage sensor monitors the supply voltage of the fixture card 100 in real time through voltage divider, isolation and other circuit technologies. After the collected analog signals are transmitted to the complex programmable logic device 160, they are converted into digital signals by A / D conversion, and then the complex programmable logic device 160 analyzes and processes these data.

[0067] For example, in long-term high-load server testing scenarios, continuous operation of the jig card 100 may lead to temperature rise and voltage fluctuations. When the temperature sensor detects that the temperature of the core component of the jig card 100 exceeds a preset threshold (e.g., 80°C), or the voltage sensor detects that the supply voltage is below the normal range (e.g., below 90% of the rated voltage), the complex programmable logic device 160 can trigger an alarm mechanism and transmit the abnormal parameters to an external monitoring system via the communication interface. Based on the feedback information, technicians can promptly address the heat dissipation of the jig card 100 or investigate the cause of the voltage abnormality, preventing jig card 100 malfunctions due to overheating or voltage instability, ensuring the continuity and accuracy of server testing, and also helping to extend the service life of the jig card 100.

[0068] In the above embodiments, the fixture card 100 may further include a flash memory module 220, which is electrically connected to the switching chip 150 and is used to store at least the configuration information and test data of the switching chip 150. By electrically connecting the flash memory module 220 to the switching chip 150, stable storage of the configuration information and test data of the switching chip 150 can be achieved. The flash memory module 220, as a non-volatile storage medium, has the characteristic that data is not lost after power failure. When the fixture card 100 is working, during the initialization phase, the switching chip 150 can write its own configuration parameters (such as PCIe protocol version settings, link channel configuration, OCP protocol conversion rules, etc.) into the flash memory module 220 for storage, avoiding reconfiguration every time it restarts and saving test preparation time. During testing, various test data processed by the switching chip 150, such as the signal transmission status of the PCIe to OCP link, error detection records, and data throughput, are also transmitted to the flash memory module 220 for storage in real time. For example, in server PCIe-OCP link compatibility testing, the switch chip 150 stores data such as signal strength, transmission delay, and protocol interaction logs from each round of testing into the flash memory module 220. After the test is completed, technicians can quickly read the data from the flash memory module 220 through a specific interface for detailed analysis and to investigate potential link problems. This design not only ensures the integrity and security of test data but also facilitates the backtracking and optimization of the test process, improving the efficiency and reliability of testing while reducing the cost of repeated testing due to data loss.

[0069] In the above embodiments, the jig card 100 may further include an oscillator 230, which is electrically connected to a complex programmable logic device (CPLD) 160 to provide a clock signal for the circuitry of the jig card 100. By electrically connecting the oscillator 230 to the CPLD 160, a precise clock signal can be provided to the circuitry of the jig card 100, ensuring the coordinated and stable operation of all components. The oscillator 230 utilizes the piezoelectric effect of a crystal or the principle of RC / LC oscillation circuits to generate a periodic electrical signal. This signal, after shaping and amplification, forms a stable clock pulse, providing a time reference for the digital circuitry and logic operations within the jig card 100. After receiving the clock signal, the CPLD 160 performs timing control on data transmission, signal processing, and other operations according to preset logic, ensuring that all functional modules operate at a unified pace. For example, when testing the server E3.S link using the jig card 100, the CPLD precisely controls the generation and transmission frequency of the test signal sequence through the clock signal provided by the oscillator 230, ensuring that each data frame enters the server slot with accurate timing. The stable clock signal also assists the CPLD in accurately timing and analyzing the returned responses, allowing for timely identification of the root cause when response timeouts or timing anomalies are detected. This design ensures the accuracy and reliability of the jig card 100 testing process, avoids testing errors caused by timing irregularities, and significantly improves testing efficiency and data validity.

[0070] In the above embodiments, the switching chip 150 may include a PEX90104 chip. It is understood that the PEX90104 chip, with its powerful programmable logic and high-speed data processing capabilities, first establishes a physical connection with the server's PCIe slot via the PCIe gold finger interface 120, receiving control and data signals from the server according to the PCIe protocol; simultaneously, the OCP gold finger interface 130 connects to the server's OCP slot, preparing to transmit the processed signals to the OCP link. During the simulation process, the logic circuits and firmware built into the PEX90104 chip can accurately simulate the behavior of PCIe link terminal devices (such as PCIe standard cards), quickly parsing the address, instruction, and data information in the PCIe signals. This chip supports multi-channel protocols, enabling high-speed data transmission. Its internally integrated protocol conversion engine can re-encode, format-convert, and rate-adapt PCIe signals according to the OCP protocol specification, converting them into a signal form recognizable by the OCP link, and transmitting them to the server's OCP slot via the OCP gold finger interface 130. During this period, the PEX90104 chip continuously monitors bidirectional signal transmission, utilizing its built-in error detection and correction functions to verify data integrity, protocol consistency, and link stability in real time. If any signal timing anomalies or data errors are detected, the error information is immediately fed back to the server testing system via a dedicated status feedback channel, allowing technicians to locate and repair the problem. Through this simulation and conversion mechanism, even if the actual PCIe and OCP cards are not yet available, the PEX90104 switching chip 150 can effectively verify the connectivity, compatibility, and performance of the server's PCIe to OCP link, providing reliable assurance for server testing. Of course, the switching chip 150 can also be other chip models; no specific restrictions are placed here.

[0071] Furthermore, this utility model embodiment also provides a server, including a server motherboard under test and the fixture card 100 mentioned in the first aspect. The fixture card 100 is adapted to a PCIe slot, OCP slot, or E3.S slot on the motherboard by changing the bracket. The multi-functional test fixture card 100 includes a substrate 110, a signal processing chip disposed on the substrate 110, a PCIe gold finger interface 120 disposed on a first side of the substrate 110, an OCP gold finger interface 130 disposed on a second side of the substrate 110, and an E3.S gold finger interface 140 disposed on a third side of the substrate 110. The PCIe gold finger interface 120 is used to connect to a server PCIe slot, the OCP gold finger interface 130 is used to connect to a server OCP slot, and the E3.S gold finger interface 140 is used to connect to a server OCP slot. The jig card 100 connects to the server's E3.S hard drive slot. The signal processing chip is electrically connected to the PCIe gold finger interface 120, OCP gold finger interface 130, and E3.S gold finger interface 140, respectively, to simulate the functions of a PCIe standard card, OCP card, and E3.S drive by processing interface signals. This allows the server to be tested using the jig card 100 even before related products are released, avoiding testing delays due to hardware incompatibility and ensuring the timely progress of server testing, thus guaranteeing the verification of the entire system's reliability and functionality. Furthermore, because the jig card 100 can simultaneously simulate multiple hardware components, it greatly improves server testing efficiency and flexibility, reducing testing costs and time.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A multifunctional test fixture card, characterized in that, include: substrate; A signal processing chip disposed on the substrate; The PCIe gold finger interface located on the first side of the substrate is used to connect to the server PCIe slot. The OCP gold finger interface located on the second side of the substrate is used to connect to the server OCP slot. The E3.S gold finger interface located on the third side of the substrate is used to connect to the server E3.S hard disk slot; The signal processing chip is electrically connected to the PCIe gold finger interface, OCP gold finger interface and E3.S gold finger interface respectively, so as to simulate the functions of PCIe standard card, OCP card and E3.S disk by processing interface signals.

2. The multifunctional test fixture card according to claim 1, characterized in that, The signal processing chip includes a switching chip, which is electrically connected to the PCIe gold finger interface and the OCP gold finger interface, thereby realizing signal verification of the PCIe to OCP link by simulating a PCIe link terminal device.

3. The multifunctional test fixture card according to claim 2, characterized in that, The signal processing chip also includes a complex programmable logic device (CPLD), which is electrically connected to the E3.S gold finger interface to verify the E3.S link by generating test signal sequences and detecting feedback responses.

4. The multifunctional test fixture card according to claim 3, characterized in that, The switching chip supports the sixth generation PCIe protocol and can dynamically identify 16-channel and 4-channel link modes.

5. The multifunctional test fixture card according to claim 4, characterized in that, It also includes a bracket assembly, which includes a PCIe bracket, an OCP bracket, and an E3.S bracket. The PCIe bracket, OCP bracket, and E3.S bracket are detachably connected to the substrate via threaded connectors, so that the fixture card can be adapted to any physical form of a PCIe slot, an OCP slot, or an E3.S slot.

6. The multifunctional test fixture card according to any one of claims 3-5, characterized in that, It also includes a sensor module, which is electrically connected to the complex programmable logic device. The sensor module is used to detect the temperature and voltage parameters of the fixture card during operation, so as to monitor the operating status of the fixture card.

7. The multifunctional test fixture card according to any one of claims 2-5, characterized in that, The fixture card also includes a flash memory module, which is electrically connected to the switching chip and is used to store at least the configuration information and test data of the switching chip.

8. The multifunctional test fixture card according to any one of claims 3-5, characterized in that, The fixture card also includes an oscillator electrically connected to the complex programmable logic device, which is used to provide a clock signal for the circuitry of the fixture card.

9. The multifunctional test fixture card according to any one of claims 2-5, characterized in that, The switching chip includes the PEX90104 model.

10. A server, characterized in that, The device includes the motherboard of the server under test and the fixture card as described in any one of claims 1-9, wherein the fixture card is adapted to the PCIe slot, OCP slot or E3.S slot on the motherboard by changing the bracket.

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