AI server PCB high-speed transmission structure
By optimizing the differential signal lines and dielectric layer design of the AI server PCB, the problem of high signal loss in traditional AI server PCBs at high frequencies was solved, achieving high-speed signal transmission of 400Gbps and meeting the stability and accuracy requirements of high-frequency bands.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- VICTORY GIANT TECH HUIZHOU CO LTD
- Filing Date
- 2025-08-21
- Publication Date
- 2026-07-28
AI Technical Summary
Traditional AI server PCBs suffer from high signal insertion loss at the 30GHz high-frequency band, making them unable to support high-speed transmission. Furthermore, conductor losses increase significantly, and impedance design cannot meet the transmission requirements of 400Gbps.
The differential signal line uses a width of 15mil-17mil and a spacing of 3mil-4mil. Combined with the dielectric layer design, the differential signal line thickness is 0.4oz-0.6oz, the dielectric layer thickness is 3mil-5mil, the dielectric constant is 2F/m-4F/m, and the optimized differential impedance is 45 ohms, achieving ultra-low insertion loss.
Insertion loss is reduced to less than -1.1dB/inch in the 30GHz band, breaking through traditional bandwidth limitations, supporting high-speed signal transmission of 400Gbps in a single channel, and compatible with low-impedance probe testing to ensure measurement accuracy.
Smart Images

Figure CN224569516U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of printed circuit boards, and more specifically, to a high-speed transmission structure for an AI server PCB. Background Technology
[0002] As the computing demands of AI servers increase, the requirements for data transfer rates between GPU / ASIC clusters also rise. Traditional AI server PCBs generally use a differential impedance standard of 85-100 ohms. In the 30GHz high-frequency band, this conventional impedance design results in high signal insertion loss, which cannot support high-speed transmission. Furthermore, the existing narrow linewidth design exacerbates the skin effect, significantly increasing conductor losses and limiting speed improvements. Utility Model Content
[0003] The purpose of this invention is to provide a high-speed transmission structure for AI server PCBs that optimizes differential impedance and enables high-speed signal transmission.
[0004] A high-speed transmission structure for an AI server PCB includes a dielectric layer and two differential signal lines. The two differential signal lines are disposed within the dielectric layer, with a distance of 3mil-4mil between them, and a width of 15mil-17mil for each differential signal line.
[0005] In the above technical solution, by setting the width of the differential signal line to 15mil-17mil and controlling the spacing to 3mil-4mil, combined with the dielectric layer design, an ultra-low differential impedance of the differential signal line is achieved. The insertion loss can be reduced to less than -1.1dB / inch in the 30GHz band, breaking through the bandwidth limitation of the traditional 85-100 ohm impedance design, enabling the PCB to support single-channel 400Gbps high-speed signal transmission.
[0006] Furthermore, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked together.
[0007] Furthermore, the thickness of the first dielectric layer is 3mil-5mil, and the thickness of the second dielectric layer is 3mil-5mil.
[0008] In the above technical solution, by limiting the thickness of both the first dielectric layer and the second dielectric layer to 3mil-5mil, the uniformity of the dielectric thickness is controlled, impedance fluctuations are reduced, and the stability of high-frequency signal transmission is ensured.
[0009] Furthermore, the dielectric constants of the first dielectric layer and the second dielectric layer are 2F / m-4F / m.
[0010] In the above technical solution, the dielectric constant is controlled between 2F / m and 4F / m, which significantly reduces dielectric loss and reduces insertion loss in the high-frequency band.
[0011] Furthermore, the distance between the two differential signal lines is 3.5 mil.
[0012] In the above technical solution, the differential line spacing is fixed at 3.5 mil, which is optimized for impedance matching in conjunction with the 16 mil line width to achieve a 45 ohm differential impedance.
[0013] Furthermore, the width of each of the differential signal lines is 16 mil.
[0014] In the above technical solution, the 16mil ultra-wide linewidth design maximizes the reduction of conductor loss, optimizes the skin effect, and provides sufficient physical channels for high-frequency signal transmission.
[0015] Furthermore, the thickness of the differential signal line is 0.4oz-0.6oz.
[0016] In the above technical solution, the thickness of the differential signal line is 0.4oz-0.6oz, which balances conductivity and processing precision, reduces high-frequency resistance loss, and ensures signal transmission efficiency.
[0017] Furthermore, the differential impedance of the differential signal line is 45 ohms.
[0018] In the above technical solution, the 45-ohm differential impedance design solves the problem that traditional impedance values cannot meet the 400Gbps transmission requirements. It significantly improves the upper limit of bandwidth through low impedance characteristics, while being compatible with dedicated low-impedance probe testing solutions to ensure measurement accuracy.
[0019] Compared with the prior art, the beneficial effects of this utility model are: by setting the differential signal line width to 15mil-17mil and the spacing to 3mil-4mil, combined with the dielectric layer design, ultra-low differential impedance of differential signal lines is achieved. The insertion loss can be reduced to within -1.1dB / inch in the 30GHz band, breaking through the bandwidth limitation of the traditional 85-100 ohm impedance design, enabling the PCB to support single-channel 400Gbps high-speed signal transmission. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the high-speed transmission structure of the AI server PCB according to an embodiment of the present invention.
[0021] Explanation of icon numbers: Dielectric layer 1, first dielectric layer 11, second dielectric layer 12, differential signal line 2. Detailed Implementation
[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0023] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0024] Please refer to Figure 1 In a preferred embodiment, the high-speed transmission structure of the AI server PCB of this utility model includes a dielectric layer 1 and two differential signal lines 2. The two differential signal lines 2 are disposed in the dielectric layer 1, the distance between the two differential signal lines 2 is 3mil-4mil, and the width of each differential signal line 2 is 15mil-17mil.
[0025] in, Figure 1 S1 represents the distance between the two differential signal lines 2, and W1 represents the width of the differential signal line 2. By setting the width W1 of the differential signal line 2 to 15mil-17mil and controlling the spacing S1 to 3mil-4mil, combined with the design of dielectric layer 1, an ultra-low differential impedance of the differential signal line 2 is achieved. The insertion loss can be reduced to less than -1.1dB / inch in the 30GHz band, breaking through the bandwidth limitation of the traditional 85-100 ohm impedance design, enabling the PCB to support single-channel 400Gbps high-speed signal transmission.
[0026] In this embodiment, the dielectric layer 1 includes a first dielectric layer 11 and a second dielectric layer 12 stacked together. The thickness of the first dielectric layer 11 is 3 mil-5 mil, and the thickness of the second dielectric layer 12 is 3 mil-5 mil. By limiting the thickness of both the first dielectric layer 11 and the second dielectric layer 12 to 3 mil-5 mil, the uniformity of the dielectric thickness is controlled, impedance fluctuations are reduced, and the stability of high-frequency signal transmission is ensured.
[0027] in, Figure 1 H1 represents the thickness of the first dielectric layer 11, and H2 represents the thickness of the second dielectric layer 12. In a preferred embodiment, the thickness of the first dielectric layer 11 is 4 mil, and the thickness of the second dielectric layer 12 is 4.53 mil. Taikoo EM891K material of the M7 UltraLow Loss grade is used to achieve low signal transmission loss.
[0028] In this embodiment, the dielectric constants of the first dielectric layer 11 and the second dielectric layer 12 are 2F / m-4F / m. By controlling the dielectric constant within the range of 2F / m-4F / m, dielectric loss is significantly reduced, thereby reducing insertion loss at high frequencies. As a preferred embodiment, the dielectric constant of the first dielectric layer 11 and the second dielectric layer 12 is 3.05F / m, thus matching the structure of the differential signal line 2 and enabling high-speed signal transmission.
[0029] In a preferred embodiment, the distance between the two differential signal lines 2 is 3.5 mil. By fixing the differential line spacing to 3.5 mil and coordinating with the 16 mil linewidth to optimize impedance matching, a 45-ohm differential impedance is achieved.
[0030] As a preferred implementation, each differential signal line 2 has a width of 16 mil. The 16 mil ultra-wide linewidth design maximizes the reduction of conductor loss, optimizes the skin effect, and provides sufficient physical path for high-frequency signal transmission.
[0031] In this embodiment, the thickness of the differential signal line 2 is 0.4 oz to 0.6 oz. Figure 1 T1 in the figure represents the thickness of differential signal line 2. By limiting the thickness of differential signal line 2 to the range of 0.4oz-0.6oz, conductivity and processing precision can be balanced, high-frequency resistance loss can be reduced, and signal transmission efficiency can be guaranteed. As a preferred embodiment, the thickness of differential signal line 2 is 0.5oz, which can match the line width and spacing of the differential signal to achieve the optimal transmission structure and improve the transmission rate.
[0032] In this embodiment, the differential impedance of differential signal line 2 is 45 ohms. The 45-ohm differential impedance design can solve the problem that traditional impedance values cannot meet the 400Gbps transmission requirements. It significantly increases the upper limit of bandwidth through low impedance characteristics, while being compatible with dedicated low-impedance probe testing solutions to ensure measurement accuracy.
[0033] In the description of this utility model, it should be understood that terms such as "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.
[0035] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A high-speed transmission structure for an AI server PCB, characterized in that, It includes a dielectric layer and two differential signal lines, the two differential signal lines are disposed within the dielectric layer, the distance between the two differential signal lines is 3mil-4mil, and the width of each differential signal line is 15mil-17mil.
2. The high-speed transmission structure of the AI server PCB according to claim 1, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer stacked together.
3. The high-speed transmission structure of the AI server PCB according to claim 2, characterized in that, The thickness of the first dielectric layer is 3mil-5mil, and the thickness of the second dielectric layer is 3mil-5mil.
4. The high-speed transmission structure of the AI server PCB according to claim 3, characterized in that, The dielectric constants of the first and second dielectric layers are 2F / m-4F / m.
5. The high-speed transmission structure of the AI server PCB according to claim 1, characterized in that, The distance between the two differential signal lines is 3.5 mil.
6. The high-speed transmission structure of the AI server PCB according to claim 1, characterized in that, Each of the differential signal lines is 16 mil wide.
7. The high-speed transmission structure of the AI server PCB according to claim 1, characterized in that, The thickness of the differential signal line is 0.4oz-0.6oz.
8. The high-speed transmission structure of the AI server PCB according to claim 1, characterized in that, The differential impedance of the differential signal line is 45 ohms.