An arc real-time detection device

Abstract

The utility model discloses a kind of electric arc real-time detection devices, including full-band sensor, signal conditioning circuit, analog-digital converter, FPGA circuit, microprocessor controller module, host computer, ethernet controller, SoC system chip, program memory, data storage and output interface, power drive circuit and printed circuit board;Full-band sensor, signal conditioning circuit, analog-digital converter, FPGA circuit, microprocessor controller module, host computer are sequentially connected;FPGA circuit is connected with ethernet controller;Ethernet controller is connected with terminal equipment;SoC system chip is integrated with analog-digital converter and FPGA circuit on;Program memory is connected with FPGA circuit;FPGA circuit connects data storage and output interface;Full-band sensor is connected with power drive circuit;Power drive circuit is connected with printed circuit board.The utility model has the advantages of simple structure, high acquisition speed, stable data transmission, low cost.

Description

Technical Field

[0001] This utility model relates to the field of high-speed real-time data acquisition and communication technology, specifically to a real-time arc detection device. Background Technology

[0002] In modern electrical systems, especially in high-efficiency equipment such as photovoltaic power generation systems, the detection and control of electric arcs are crucial factors in ensuring safe operation. Electric arcs can not only damage equipment but also cause serious safety accidents such as fires.

[0003] Traditional arc detection techniques primarily rely on low-frequency sampling systems to monitor abnormal current or voltage fluctuations in electrical circuits. These systems typically suffer from slow response times, high false alarm rates, and ineffective handling of high-frequency noise. Due to limitations in sampling frequency and data processing capabilities, these traditional systems perform poorly in high-risk or highly complex environments.

[0004] Furthermore, most existing technologies fail to fully utilize modern data processing techniques, such as FPGAs (Field-Programmable Gate Arrays) and advanced signal processing algorithms, which limits their ability to detect subtle arc signals. This technological limitation makes it difficult for systems to accurately identify and respond to arc generation under rapidly changing electrical load conditions.

[0005] Given these shortcomings of existing technologies, there is an urgent need for a new arc detection device that can provide a higher sampling frequency and more powerful data processing capabilities to achieve rapid and accurate detection of electric arcs. Utility Model Content

[0006] The technical problem to be solved by this utility model is to provide a real-time arc detection device, which solves the problems of low sampling rate and insufficient data processing capability in the prior art, thereby realizing more accurate and faster arc detection, and effectively reducing system cost and ensuring work efficiency while improving performance.

[0007] To solve the above technical problems, the present invention adopts the following technical solution:

[0008] A real-time arc detection device, comprising:

[0009] Full-band sensors, signal conditioning circuits, analog-to-digital converters, FPGA circuits, microprocessor controller modules, host computers, Ethernet controllers, SoC system chips, program memory, data storage and output interfaces, power drive circuits, and printed circuit boards.

[0010] The full-band sensor, signal conditioning circuit, analog-to-digital converter, FPGA circuit, microprocessor controller module, and host computer are connected in sequence; the FPGA circuit is connected to the Ethernet controller; the Ethernet controller is connected to the terminal device; the SoC system chip integrates the analog-to-digital converter and the FPGA circuit; the program memory is connected to the FPGA circuit; the FPGA circuit is connected to the data storage and output interface; the full-band sensor is connected to the power drive circuit; the power drive circuit is connected to the printed circuit board.

[0011] A full-band sensor collects analog signals from different frequency bands of the electric arc. The signal conditioning circuit processes the analog signal to obtain a conditioned voltage signal. The analog-to-digital converter converts the voltage signal into a digital signal. The FPGA circuit uses an FIR filter to process the digital signal to obtain a denoised signal. The denoised signal is encapsulated and transmitted using an Ethernet controller to obtain a data frame, which is then transmitted to an external device. The microprocessor controller module performs time-frequency domain analysis on the denoised signal to obtain the result of the electric arc detection.

[0012] The power supply drive circuit is used to supply power.

[0013] Furthermore, the signal conditioning circuit includes first to eighth resistors R1 to R8, first to fourth capacitors C1 to C4, first operational amplifier U1, and second operational amplifier U2.

[0014] The full-band sensor is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the inverting input of the first operational amplifier U1, one end of the third resistor R3, and one end of the first capacitor C1. One end of the second resistor R2 is connected to the first DC bias voltage VDC1. The other end of the second resistor R2 is connected to one end of the eighth resistor R8 and the non-inverting input of the first operational amplifier U1. The other end of the eighth resistor R8 is grounded. The output of the first operational amplifier U1 is connected to the other end of the third resistor R3, the other end of the first capacitor C1, and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the first... One end of capacitor C2, one end of resistor R5, and the inverting input of operational amplifier U2 are connected. The other end of capacitor C2 is grounded. One end of resistor R7 is connected to one end of resistor R6, one end of capacitor C3, and the non-inverting input of operational amplifier U2. The other end of resistor R7 is grounded. The other end of capacitor C3 is grounded. The other end of resistor R6 is connected to the second DC bias voltage VDC2. The output of operational amplifier U2 is connected to the other end of resistor R5, one end of capacitor C4, and the input of analog-to-digital converter. The other end of capacitor C4 is grounded.

[0015] Furthermore, the FPGA circuit is connected to the microprocessor controller module through an idle I / O port.

[0016] Furthermore, the analog-to-digital converter is a sampling chip with a sampling rate of 25MHz.

[0017] Furthermore, the microprocessor controller module is an ARM microcontroller.

[0018] Furthermore, the ARM microcontroller processor is the STM32H743 series processor.

[0019] Furthermore, the power drive circuit is connected to the power interface of the printed circuit board.

[0020] Furthermore, the Ethernet controller includes an Ethernet interface and an Ethernet transceiver, with the Ethernet interface and the Ethernet transceiver having the same bandwidth.

[0021] The Ethernet interface is a 5G Ethernet interface, and the Ethernet transceiver is a 5G Ethernet transceiver.

[0022] Furthermore, the program memory is an external FLASH memory chip of W25Q16JVSSIQ.

[0023] Furthermore, data storage and output interfaces include USB, Ethernet, and wireless modules.

[0024] Compared with the prior art, the present invention, by adopting the above technical solution, has the following technical effects:

[0025] 1. This utility model utilizes a high-frequency sampling rate chip design, integrating an analog-to-digital converter, FPGA, and IP core into a single chip. This not only reduces design space and cost but also significantly improves sampling efficiency. Furthermore, the addition of 5G Ethernet wireless data transmission to the microprocessor controller solves the problem of inability to connect wirelessly. It boasts advantages such as higher sampling rate, more accurate analysis, faster transmission speed, and lower cost.

[0026] 2. This utility model can adapt to various working conditions and maintain the stability of detection performance.

[0027] 3. This utility model is small in size and easy to install, making it suitable for rapid deployment in various electrical equipment. Attached Figure Description

[0028] Figure 1 This is an overall structural diagram of the present invention.

[0029] Figure 2 This is a structural diagram of the signal conditioning circuit of this utility model.

[0030] Figure 3 This is a physical image of the utility model. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0032] To achieve the above objectives, this utility model proposes a real-time arc detection device. When an arc occurs, it can detect the transient changes in arc voltage immediately, thus cutting off the hazards caused by the arc. Figure 1 As shown, it includes:

[0033] Full-band sensors, signal conditioning circuits, analog-to-digital converters, FPGA circuits, microprocessor controller modules, host computers, Ethernet controllers, SoC system chips, program memory, data storage and output interfaces, power drive circuits, and printed circuit boards.

[0034] The full-band sensor, signal conditioning circuit, analog-to-digital converter, FPGA circuit, microprocessor controller module, and host computer are connected in sequence; the FPGA circuit is connected to the Ethernet controller; the Ethernet controller is connected to the terminal device; the SoC system chip integrates the analog-to-digital converter and the FPGA circuit; the program memory is connected to the FPGA circuit; the FPGA circuit is connected to the data storage and output interface; the full-band sensor is connected to the power drive circuit; the power drive circuit is connected to the power interface of the printed circuit board.

[0035] The full-band sensor, signal conditioning circuit, analog-to-digital converter, FPGA circuit, microprocessor controller module, host computer, Ethernet controller, SoC system chip, program memory, data storage and output interface and power drive circuit are all printed on the printed circuit board.

[0036] The power supply drive circuit powers the entire printed circuit board.

[0037] Among them, such as Figure 2 As shown, the signal conditioning circuit includes first to eighth resistors R1 to R8, first to fourth capacitors C1 to C4, first operational amplifier U1, and second operational amplifier U2.

[0038] The full-band sensor is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the inverting input of the first operational amplifier U1, one end of the third resistor R3, and one end of the first capacitor C1. One end of the second resistor R2 is connected to the first DC bias voltage VDC1. The other end of the second resistor R2 is connected to one end of the eighth resistor R8 and the non-inverting input of the first operational amplifier U1. The other end of the eighth resistor R8 is grounded. The output of the first operational amplifier U1 is connected to the other end of the third resistor R3, the other end of the first capacitor C1, and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the first... One end of capacitor C2, one end of resistor R5, and the inverting input of operational amplifier U2 are connected. The other end of capacitor C2 is grounded. One end of resistor R7 is connected to one end of resistor R6, one end of capacitor C3, and the non-inverting input of operational amplifier U2. The other end of resistor R7 is grounded. The other end of capacitor C3 is grounded. The other end of resistor R6 is connected to the second DC bias voltage VDC2. The output of operational amplifier U2 is connected to the other end of resistor R5, one end of capacitor C4, and the input of analog-to-digital converter. The other end of capacitor C4 is grounded.

[0039] The FPGA circuit is connected to the microprocessor controller module through an idle I / O port.

[0040] By integrating analog-to-digital converters and FPGA circuits onto a SoC (System-on-a-Chip) using system-on-chip (SoC) technology, a highly integrated SoC is obtained, reducing system size and power consumption while improving data processing efficiency.

[0041] The Ethernet controller includes an Ethernet interface and an Ethernet transceiver. The Ethernet interface and the Ethernet transceiver have the same bandwidth. The Ethernet interface communicates with the Ethernet transceiver and is used to further forward data from the Ethernet transceiver. The Ethernet interface is a 5G Ethernet interface, and the Ethernet transceiver is a 5G Ethernet transceiver.

[0042] The analog-to-digital converter is a sampling chip with a sampling rate of 25MHz. The microprocessor controller module is an STM32H743 series processor. The program memory is an external FLASH memory chip, W25Q16JVSSIQ. Data storage and output interfaces include USB, Ethernet, and wireless modules.

[0043] In operation, the real-time arc detection device is plugged into the inverter circuit of the photovoltaic system. The power drive circuit is then activated, and the device starts working. The full-band sensor continuously collects analog signals from different frequency bands of the arc in the photovoltaic system, providing comprehensive arc signal coverage and ensuring no critical information is missed. The signal conditioning circuit amplifies, filters, and boosts the analog signal to ensure its voltage remains within a set range, resulting in a conditioned voltage signal. The analog-to-digital converter (ADC) is connected to the power supply and performs sampling based on the sampling clock input signal provided by the PLL module in the FPGA circuit. This ADC then converts the conditioned voltage signal into a high-precision digital signal using a high sampling rate, facilitating subsequent digital signal processing. The FPGA circuit within the SoC chip uses an FIR filter to process the digital signal, obtaining a denoised signal, which is then stored in the on-chip memory, reducing external connections and improving data processing efficiency. The data storage and output interface stores and outputs the denoised signal, utilizing the Ethernet communication protocol of the Ethernet controller and 5G... Gigabit Ethernet encapsulates and transmits the denoised signal to obtain data frames conforming to the Ethernet standard. These frames are then transmitted to the control computer via an Ethernet interface and transceiver, enabling remote data monitoring and system integration. When the microprocessor controller module issues instructions to the FPGA circuit, it begins reading data from the on-chip memory and performs time-frequency domain analysis on the denoised signal. This involves calculating zero-time, rise / fall time, peak value, root mean square value, and pulse count to capture rapidly changing characteristics. Fast Fourier Transform is used to extract the proportion of harmonic energy in the high-frequency band and the power spectral density of a specific frequency band. Short-time Fourier Transform is used to extract the time-frequency energy distribution to accurately locate the arc feature region. After feature extraction, a criterion calculation is performed based on preset thresholds to obtain the arc detection results, such as the presence of an arc and the detection time. The host computer uses host computer software and a human-machine interface to visualize and further process the detection results, providing an intuitive arc detection report and monitoring interface. This facilitates user monitoring and decision support; for example, the probability of arc occurrence and the time required for its occurrence can be displayed in real-time on the host computer window.

[0044] The program memory is used to store the FPGA's configuration bit stream and running program, and transfer these data to the FPGA circuitry to ensure its stable operation.

[0045] Figure 3 In this system, the components integrated on the printed circuit board are divided into a sampling control module, a data storage module, and a processing and external communication module. The sampling control module includes a full-band sensor, a signal conditioning circuit, and an analog-to-digital converter. The data storage module includes an FPGA circuit, a program memory, and a data storage and output interface. The processing and external communication module includes a microprocessor controller module, a host computer, an Ethernet controller, and a SoC system chip.

[0046] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. An arc real-time detection device, characterized by, include: Full-band sensors, signal conditioning circuits, analog-to-digital converters, FPGA circuits, microprocessor controller modules, host computers, Ethernet controllers, SoC system chips, program memory, data storage and output interfaces, power drive circuits, and printed circuit boards; The full-band sensor, signal conditioning circuit, analog-to-digital converter, FPGA circuit, microprocessor controller module, and host computer are connected in sequence; the FPGA circuit is connected to the Ethernet controller; the Ethernet controller is connected to the terminal device; the SoC system chip integrates the analog-to-digital converter and the FPGA circuit; the program memory is connected to the FPGA circuit; the FPGA circuit is connected to the data storage and output interface; the full-band sensor is connected to the power drive circuit; the power drive circuit is connected to the printed circuit board. A full-band sensor collects analog signals from different frequency bands of the electric arc. The signal conditioning circuit processes the analog signal to obtain a conditioned voltage signal. The analog-to-digital converter converts the voltage signal into a digital signal. The FPGA circuit uses an FIR filter to process the digital signal to obtain a denoised signal. The denoised signal is encapsulated and transmitted using an Ethernet controller to obtain a data frame, which is then transmitted to the terminal device. The microprocessor controller module performs time-frequency domain analysis on the denoised signal to obtain the result of the electric arc detection. The power supply drive circuit is used to supply power.

2. The arc real-time detection device of claim 1, wherein, The signal conditioning circuit includes first to eighth resistors R1 to R8, first to fourth capacitors C1 to C4, first operational amplifier U1, and second operational amplifier U2; The full-band sensor is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the inverting input of the first operational amplifier U1, one end of the third resistor R3, and one end of the first capacitor C1. One end of the second resistor R2 is connected to the first DC bias voltage VDC1. The other end of the second resistor R2 is connected to one end of the eighth resistor R8 and the non-inverting input of the first operational amplifier U1. The other end of the eighth resistor R8 is grounded. The output of the first operational amplifier U1 is connected to the other end of the third resistor R3, the other end of the first capacitor C1, and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to the first... One end of capacitor C2, one end of resistor R5, and the inverting input of operational amplifier U2 are connected. The other end of capacitor C2 is grounded. One end of resistor R7 is connected to one end of resistor R6, one end of capacitor C3, and the non-inverting input of operational amplifier U2. The other end of resistor R7 is grounded. The other end of capacitor C3 is grounded. The other end of resistor R6 is connected to the second DC bias voltage VDC2. The output of operational amplifier U2 is connected to the other end of resistor R5, one end of capacitor C4, and the input of analog-to-digital converter. The other end of capacitor C4 is grounded.

3. The arc real-time detection device of claim 1, wherein, The FPGA circuit is connected to the microprocessor controller module through an idle I / O port.

4. The arc real-time detection device of claim 1, wherein, The analog-to-digital converter is a sampling chip with a sampling rate of 25MHz.

5. The arc real-time detection device of claim 1, wherein, The microprocessor controller module is an ARM single-chip microcomputer processor.

6. The arc real-time detection device of claim 5, wherein, The ARM microcontroller processor is the STM32H743 series processor.

7. The arc real-time detection device of claim 1, wherein, The power drive circuit is connected to the power interface of the printed circuit board.

8. The arc real-time detection device of claim 1, wherein, The Ethernet controller includes an Ethernet interface and an Ethernet transceiver, with the Ethernet interface and the Ethernet transceiver having the same bandwidth. The Ethernet interface is a 5G Ethernet interface, and the Ethernet transceiver is a 5G Ethernet transceiver.

9. The arc real-time detection device of claim 1, wherein, The program memory is an external FLASH memory chip, W25Q16JVSSIQ.

10. The arc real-time detection device of claim 1, wherein, Data storage and output interfaces include USB, Ethernet, and wireless modules.

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