A power switching device
By managing power switching and interface integration with FPGA chips, and combining strong and weak current separation relay control circuits, the reliability and integration problems of traditional power switching devices are solved, realizing a power switching device with high reliability, flexibility and miniaturization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU BAICHEN AEROSPACE TECHNOLOGY CO LTD
- Filing Date
- 2025-07-29
- Publication Date
- 2026-08-04
AI Technical Summary
Traditional power switching devices are inadequate in terms of reliability, flexibility, and integration. Mechanical relays are prone to damage, have inflexible control, and are bulky.
The system uses an FPGA chip to centrally manage power switching, combined with GPIB and LAN interfaces, to support six independent controls. It integrates a relay control unit and a filter, and employs strong and weak current separation and relay control circuitry to achieve circuit isolation and protection.
It improves the reliability and flexibility of power switching, reduces equipment failure rate, lowers power consumption and size, and adapts to the complex scenarios of modern automated testing systems.
Smart Images
Figure CN224595399U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power switching technology, specifically a power switching device. Background Technology
[0002] In the fields of industrial automation and testing equipment, power switching switches, as critical power management units, directly impact system stability in terms of reliability, flexibility, and security. Traditional power switching solutions generally suffer from the following drawbacks: Insufficient contact life and reliability: Mechanical relays rely on physical contacts to open and close. High current switching can easily generate arcs, leading to contact erosion, shortened life, and a significantly increased failure rate after frequent switching. Limited control flexibility: Multi-output channels often use centralized control, which cannot independently manage the on / off state of a single channel, making it difficult to adapt to modern automated testing systems; The conflict between size and integration: To meet the demand for multiple outputs, traditional designs need to stack multiple independent modules, resulting in large device size, high power consumption and high heat dissipation pressure. Utility Model Content
[0003] The purpose of this utility model is to provide a power switching device to address the problems mentioned above.
[0004] The technical solution adopted by this utility model is as follows: a power switching device includes a device body, a first panel is provided on the front end face of the device body, and a second panel is provided on the rear end face of the device body, wherein a power switching channel is provided on the first panel, and a LAN interface and a GPIB interface are provided on the second panel. The device body is equipped with a first power module, a second power module, an FPGA chip, and a relay control unit; The first power module is used to provide one drive power supply to the relay control unit; The second power module is used to power the FPGA chip and, through the FPGA chip, to provide a main control input power to the relay control unit; The relay control unit receives one external power input and switches the output; The FPGA chip is used to provide a main control input power supply to the relay control unit and output signals via the LAN interface and GPIB interface.
[0005] Furthermore, the relay control unit includes a relay and a relay control circuit.
[0006] Furthermore, the device body is equipped with a six-channel relay control unit, including a first relay, a second relay, a third relay, a fourth relay, a fifth relay, and a sixth relay, and each of the relays is paired with a relay control circuit.
[0007] Furthermore, the relay model is G6K-2P0Y, and the relay control circuit includes a main control power input circuit, a delay circuit, and an output circuit.
[0008] Furthermore, the main control power input circuit includes diode D1, resistor R1, resistor R2, resistor R3, field-effect transistor Q1, and transistor Q2; The output terminal of the FPGA chip is connected to the anode of diode D1; The current output from the cathode of diode D1 is divided into two paths through resistor R1. One path is connected to the source of field-effect transistor Q1, and the other path is connected to the gate of field-effect transistor Q1 and the collector of transistor Q2 through resistor R2. The current output from the cathode of diode D1 is connected to the base of transistor Q2; The current output from the cathode of diode D1 is grounded through resistor R3, and the emitter of transistor Q2 is grounded. The drain of the field-effect transistor Q1 outputs a control current and is connected to a relay.
[0009] Furthermore, the delay circuit includes resistors R4, R5, and R6, capacitor C1, transistor Q3, and diode D2; The base of transistor Q3 is connected to resistor R4, the emitter of transistor Q3 is grounded, and the collector of transistor Q3 is connected to a relay. The resistor R5 and capacitor C1 are connected in parallel across the base and emitter of transistor Q3; The diode D2 is connected in parallel with the relay; The resistor R6 is connected to the anode of the diode D2.
[0010] Furthermore, the output circuit includes a resistor R7, a diode D3, and a connector CN1; The anode of diode D3 is connected to resistor R7 and grounded, and the cathode of diode D3 is connected to the relay. The connector CN1 is connected in parallel with diode D3.
[0011] Furthermore, the device body is also equipped with a filter, which is used to convert external AC power into low-voltage DC power and output it to the first power module and the second power module respectively.
[0012] The beneficial effects of this utility model include at least one of the following; 1. By integrating GPIB and LAN dual interfaces on the basis of the existing structure, supporting independent control of six outputs to adapt to complex test scenarios, and centrally managing power switching, acquisition and communication functions through FPGA, the six-channel control, display and protection units are integrated into the device body in a 4U standard chassis.
[0013] 2. Each relay control unit is equipped with a relay control circuit, which includes a main control power input circuit, a delay circuit, and an output circuit. Strong and weak currents are separated by physical isolation through contacts to prevent the control circuit from being affected by high voltage, surges, or noise interference from the load. At the same time, diodes in the circuit work with the relay to absorb the back electromotive force when the power is off, preventing the induced voltage from breaking down the control circuit components and further improving isolation safety. Attached Figure Description
[0014] Figure 1 A schematic diagram of the front structure of a power switching device; Figure 2 A schematic diagram of the back structure of a power switching device; Figure 3 This is a schematic diagram of a power switching device. Figure 4 This is a schematic diagram of a relay control circuit.
[0015] In the picture: 1 is the device body, 2 is the first panel, 3 is the second panel, 4 is the LAN interface, 5 is the GPIB interface, 6 is the power switching channel, and 7 is the digital tube. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can typically be arranged and designed in various different configurations.
[0017] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0018] It should be noted that, where there is no conflict, the embodiments and features in the embodiments of this utility model can be combined with each other.
[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0020] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this utility model is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0021] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0022] like Figures 1 to 3 As shown, a power switching device includes a device body 1, a first panel 2 is provided on the front end of the device body 1, and a second panel 3 is provided on the rear end of the device body 1. The first panel 2 is provided with a power switching channel 6, and the second panel 3 is provided with a LAN interface 4 and a GPIB interface 5. The device body 1 is equipped with a first power module, a second power module, an FPGA chip, and a relay control unit. The first power module is used to provide one drive power supply to the relay control unit; The second power module is used to power the FPGA chip and, through the FPGA chip, to provide a main control input power to the relay control unit; The relay control unit receives one external power input and switches the output; The FPGA chip is used to provide a main control input power supply to the relay control unit and output signals via LAN interface 4 and GPIB interface 5.
[0023] The purpose of this design is to integrate GPIB and LAN dual interfaces on the basis of the existing structure, support independent control of six outputs to adapt to complex test scenarios, and integrate the six-channel control, display and protection units into the device body of a 4U standard chassis through centralized management of power switching, acquisition and communication functions by FPGA.
[0024] It should be noted that in practical applications, the FPGA chip can be manufactured by Xilinx, model XC7Z020-2CLG400E, from the Xilinx Zynq®-7000 All Programmable SoC (AP SoC) series. This device is equipped with a dual-core ARM® Cortex™-A9 processor, integrates programmable logic based on 28nm Artix®-7 or Kintex®-7, up to 6.6M logic cells and 12.5Gb / s transceivers, has excellent power performance, maximum design flexibility, and is suitable for a variety of embedded application designs.
[0025] The inclusion of both LAN and GPIB interfaces enables external communication. The GPIB, LAN, and USB interfaces are located on the second panel (rear panel). Communication interfaces are directly brought out from the FPGA chip, and all interfaces are designed with ESD protection. The GPIB interface is converted to RS232 serial communication via a converter for communication with the FPGA chip. The converter supports bidirectional transmission, achieving standard physical and electrical conversion between IEEE488 and RS232, and is compatible with IEEE488.1 and IEEE488.2 standards. The serial port speed is 500kb / s. The power supply is 5V, and the operating current is 120mA.
[0026] Meanwhile, in this embodiment, the relay control unit includes a relay and a relay control circuit. Taking a six-way power switching switch as an example, the device body 1 is equipped with a six-way relay control unit, including a first relay, a second relay, a third relay, a fourth relay, a fifth relay and a sixth relay, and each of the relays is equipped with a relay control circuit.
[0027] The purpose of this design is to equip each relay control unit with a relay control circuit, which can independently manage the on / off state of a single circuit.
[0028] In this embodiment, as Figure 4 As shown, the relay model is G6K-2P0Y, and the relay control circuit includes a main control power input circuit, a delay circuit, and an output circuit.
[0029] The main control power input circuit includes diode D1, resistor R1, resistor R2, resistor R3, field-effect transistor Q1, and transistor Q2. The output terminal of the FPGA chip is connected to the anode of diode D1; The current output from the cathode of diode D1 is divided into two paths through resistor R1. One path is connected to the source of field-effect transistor Q1, and the other path is connected to the gate of field-effect transistor Q1 and the collector of transistor Q2 through resistor R2. The current output from the cathode of diode D1 is connected to the base of transistor Q2; The current output from the cathode of diode D1 is grounded through resistor R3, and the emitter of transistor Q2 is grounded. The drain of the field-effect transistor Q1 outputs a control current and is connected to a relay.
[0030] Meanwhile, the delay circuit includes resistors R4, R5, and R6, capacitor C1, transistor Q3, and diode D2; The base of transistor Q3 is connected to resistor R4, the emitter of transistor Q3 is grounded, and the collector of transistor Q3 is connected to a relay. The resistor R5 and capacitor C1 are connected in parallel across the base and emitter of transistor Q3; The diode D2 is connected in parallel with the relay; The resistor R6 is connected to the anode of the diode D2.
[0031] Meanwhile, the output circuit includes resistor R7, diode D3, and connector CN1; The anode of diode D3 is connected to resistor R7 and grounded, and the cathode of diode D3 is connected to the relay. The connector CN1 is connected in parallel with the diode D3.
[0032] The purpose of this design is to have the ability to switch power outputs, with each power supply being controllable independently. The relay control circuit drives the relay, and the control is completed by the FPGA chip. After the FPGA chip receives the control command, the IO port will drive the field-effect transistor to conduct, drive the relay to close and conduct the 5V power supply, and then drive the solid-state relay to conduct the output power supply.
[0033] It should also be noted that in practical applications, solid-state relays of model JGX-1685FXC and Baocheng brand relays of Shaanxi Qunli Company with specification serial number 005-50 can also be selected. These relays feature TTL logic circuit compatible input, DC input, magnetic isolation technology for input and output, flame-retardant engineering plastic shell, epoxy potting, brass metal base plate, power MOSFET, IGBT output, high voltage output, and a safety protective cover.
[0034] In this embodiment, in addition to the first and second power modules mentioned above, the power supply section also includes a filter. Its main function is to convert the external single-phase AC220V / 50Hz AC to DC5V to power the FPGA chip and relay. The two power modules are model LRS-50-5 and use switching power supplies manufactured by Mean Well Electronics Co., Ltd. It can also include an LDO power supply, which uses the AMS1117-3V3 power chip from Yutai Semiconductor Technology Co., Ltd. to convert the 5V power supply to a stable 3.3V.
[0035] In this embodiment, the filter adopts a military-grade two-stage input filter circuit, manufactured by Chongqing Zhongxiao Technology Co., Ltd., model number ZXJLC-2320. It can effectively suppress both common-mode and differential-mode interference across the entire frequency band. It is particularly suitable for military equipment containing switching power supplies, digital circuits, and those susceptible to interference. Furthermore, it features low leakage current, high insulation resistance, and excellent safety and reliability.
[0036] It should also be noted that the first panel is equipped with a six-channel digital tube display (STV) adapted to the six-channel relays, which can display the current channel output voltage and current with a display accuracy of 0.01. The STV is driven by a TM1638 chip, which integrates a digital interface connected to the FPGA chip, a data latch, LED driver, keyboard scanning circuit, etc. It features reliability, good stability, and strong anti-interference capability.
[0037] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A power switching device, comprising a device body (1), wherein a first panel (2) is disposed on the front end face of the device body (1), and a second panel (3) is disposed on the rear end face of the device body (1), characterized in that, The first panel (2) is provided with a power switching channel (6), and the second panel (3) is provided with a LAN interface (4) and a GPIB interface (5). The device body (1) is provided with a first power module, a second power module, an FPGA chip, and a relay control unit; The first power module is used to provide one drive power supply to the relay control unit; The second power module is used to power the FPGA chip and, through the FPGA chip, to provide a main control input power to the relay control unit; The relay control unit receives one external power input and switches the output; The FPGA chip is used to provide a main control input power supply to the relay control unit and output signals via the LAN interface (4) and the GPIB interface (5).
2. The power switching device according to claim 1, characterized in that, The relay control unit includes a relay and a relay control circuit.
3. The power switching device according to claim 2, characterized in that, The device body (1) is equipped with a six-channel relay control unit, including a first relay, a second relay, a third relay, a fourth relay, a fifth relay and a sixth relay, and each of the relays is equipped with a relay control circuit.
4. A power switching device according to claim 2, characterized in that, The relay model is G6K-2P0Y, and the relay control circuit includes a main control power input circuit, a delay circuit, and an output circuit.
5. A power switching device according to claim 4, characterized in that, The main control power input circuit includes diode D1, resistor R1, resistor R2, resistor R3, field-effect transistor Q1, and transistor Q2; The output terminal of the FPGA chip is connected to the anode of diode D1; The current output from the cathode of diode D1 is divided into two paths through resistor R1. One path is connected to the source of field-effect transistor Q1, and the other path is connected to the gate of field-effect transistor Q1 and the collector of transistor Q2 through resistor R2. The current output from the cathode of diode D1 is connected to the base of transistor Q2; The current output from the cathode of diode D1 is grounded through resistor R3, and the emitter of transistor Q2 is grounded. The drain of the field-effect transistor Q1 outputs a control current and is connected to a relay.
6. A power switching device according to claim 4, characterized in that, The delay circuit includes resistors R4, R5, and R6, capacitor C1, transistor Q3, and diode D2. The base of transistor Q3 is connected to resistor R4, the emitter of transistor Q3 is grounded, and the collector of transistor Q3 is connected to a relay. The resistor R5 and capacitor C1 are connected in parallel across the base and emitter of transistor Q3; The diode D2 is connected in parallel with the relay; The resistor R6 is connected to the anode of the diode D2.
7. A power switching device according to claim 4, characterized in that, The output circuit includes a resistor R7, a diode D3, and a connector CN1; The anode of diode D3 is connected to resistor R7 and grounded, and the cathode of diode D3 is connected to the relay. The connector CN1 is connected in parallel with the diode D3.
8. A power switching device according to any one of claims 1 to 7, characterized in that, The device body (1) is also equipped with a filter, which is used to convert external AC power into low-voltage DC power and output it to the first power module and the second power module respectively.