A low-power electronic timer wake-up system and method based on ambient light sensing

Abstract

The present application relates to the technical field of electronic timer, especially to a low-power electronic timer wake-up system and method based on ambient light sensing, which comprises an ambient light sensing unit, a signal processing unit, a wake-up control unit, an electronic timer main control module and a power management module. The sensing unit works in an intermittent sampling mode with duty cycle dynamic configuration to output original photoelectric signals. The signal processing unit tracks the dynamic reference value of ambient light in real time based on a sliding time window difference algorithm, and decouples the light intensity change gradient and the reference deviation. The wake-up control unit builds a two-stage asymmetric verification architecture through a nano-level coarse sieve comparator and a fine verification state mechanism, and outputs the final wake-up enable signal combined with an adaptive weighted matching model. The present application solves the problems of high standby power consumption, susceptibility to ambient light interference and rough energy efficiency management of traditional wake-up circuits, and realizes nano-level ultra-low standby, high confidence wake-up and full-cycle energy efficiency optimization.

Description

Technical Field

[0001] This invention relates to the field of electronic timer technology, specifically to a low-power electronic timer wake-up system and method based on ambient light sensing. Background Technology

[0002] Electronic timers are widely used in industrial control, smart homes, wearable devices, and IoT terminals. To extend device battery life, existing technologies typically employ a low-power operating mechanism that combines deep sleep with externally triggered wake-up. However, traditional wake-up schemes suffer from the following technical bottlenecks in practical applications:

[0003] High standby power consumption: Most light-controlled wake-up circuits use continuous power supply or fixed threshold comparators. The photoelectric detection front end and signal processing circuit are in a conducting state for a long time, and the static current is difficult to reduce to below the microampere level, which cannot meet the nanoampere level standby requirements of ultra-long battery life devices.

[0004] Weak anti-interference capability and high false trigger rate: Complex changes in ambient light, single threshold detection or simple software filtering cannot effectively distinguish between real human wake-up operations and natural light drift, resulting in frequent false wake-ups or missed wake-ups of the system and poor reliability.

[0005] The wake-up process suffers from rudimentary energy efficiency management: traditional systems lack hierarchical power timing control and context recovery mechanisms, which can easily cause power surges or clock asynchrony at power-up, leading to initialization failures; and after entering full-function operation, the power supply voltage and main frequency are fixed, making it impossible to dynamically adjust energy consumption according to real-time computing load, resulting in unnecessary energy waste.

[0006] Therefore, there is an urgent need in this field for an electronic timer wake-up system and method that can achieve ultra-low standby power consumption, high anti-interference wake-up accuracy, and full-cycle energy efficiency adaptive optimization. Summary of the Invention

[0007] The purpose of this invention is to provide a low-power electronic timer wake-up system and method based on ambient light sensing, so as to solve the problems mentioned in the background art.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] A low-power electronic timer wake-up system based on ambient light sensing is provided. The wake-up system is configured as a two-level asymmetric verification and power adaptive routing architecture based on the dynamic characteristics of ambient light, including an ambient light sensing unit, a signal processing unit, a wake-up control unit, an electronic timer main control module, and a power management module.

[0010] The ambient light sensing unit operates in an intermittent sampling mode with a controllable duty cycle, and is used to output raw photoelectric signals characterizing changes in ambient illuminance.

[0011] The signal processing unit is cascaded with the ambient light sensing unit to perform analog-to-digital conversion on the original photoelectric signal and to track the dynamic reference value of ambient light in real time based on the sliding time window differential algorithm, and to calculate the gradient of light intensity change and the deviation from the reference.

[0012] The wake-up control unit is connected to the signal processing unit and has a built-in coarse screening comparator and fine verification state machine. The coarse screening comparator continuously operates in a nanoampere-level low-power standby state, which is used to compare the light intensity change gradient with the first-level hysteresis threshold and output the primary trigger pulse. The fine verification state machine is activated only after capturing the primary trigger pulse, extracts the reference deviation, light intensity change gradient and signal duration to construct a multi-dimensional light event feature vector, performs validity verification through a preset adaptive weighted matching model, and outputs the final wake-up enable signal only when the verification result meets the wake-up confidence condition.

[0013] The electronic timing master control module is connected to the wake-up control unit and the power management module. During deep sleep, the power supply to the master clock tree and digital logic is cut off, and only the real-time clock counter is maintained. After receiving the final wake-up enable signal, the power management module restores the power supply to the analog front end, digital core and peripheral bus in sequence according to the preset power-on sequence. After the electronic timing master control module completes clock synchronization, register reloading and timing task queue scheduling, it enters the full-function running state.

[0014] The power management module is coupled to the power rails of the ambient light sensing unit, signal processing unit, wake-up control unit, and electronic timing master control module respectively. Based on the inter-level state switching signal of the wake-up control unit, the power supply voltage level and working clock frequency of each unit are dynamically configured to realize on-demand energy routing and subthreshold power consumption control throughout the entire process from intermittent sampling, feature verification to master control wake-up.

[0015] A low-power electronic timer wake-up method based on ambient light sensing includes the following steps:

[0016] S1. Duty Cycle Dynamic Configuration and Intermittent Sampling Steps: A low-power oscillator generates a reference sampling clock signal. The duty cycle dynamic configuration circuit combines the current power supply rail voltage margin command with the historical average value of the reference deviation in the previous cycle to perform pulse width modulation processing on the reference sampling clock signal, and outputs a sampling enable pulse with an adjustable duty cycle. The photoelectric detection front end uses the sampling enable pulse as the bias enable control input, and only conducts the internal photoelectric conversion circuit during the effective level to convert the captured instantaneous ambient illuminance into transient photovoltage. The signal latch output stage performs impedance isolation and peak hold processing on the transient photovoltage to stably output the original photoelectric signal.

[0017] S2. Sliding Window Differential and Dynamic Feature Calculation Steps: The original photoelectric signal is received. The analog-to-digital converter performs cycle-by-cycle quantization on the original photoelectric signal under the effective edge triggering of the system sampling enable pulse, generating a discrete digital light intensity sequence. The sliding data buffer array performs sliding overlay shift storage on the discrete digital light intensity sequence to form the current sliding window light intensity data frame. The dynamic reference tracker performs point-by-point differential and low-pass smoothing filtering on the current sliding window light intensity data frame to extract the steady-state differential reference, and performs attenuation-weighted fusion with the historical reference value to update the real-time ambient light dynamic reference value. The gradient and deviation calculation module receives the real-time ambient light dynamic reference value and the window differential sequence, performs amplitude accumulation and dimension normalization on consecutive valid differential segments with the same sign to obtain the light intensity change gradient, and simultaneously performs a difference comparison operation between the latest cycle discrete digital light intensity value and the real-time ambient light dynamic reference value to obtain the reference deviation, and synchronously outputs the light intensity change gradient and the reference deviation.

[0018] S3, Subthreshold Hysteresis Coarse Screening and Primary Triggering Steps: Receive the light intensity change gradient. In the nanoampere-level low-power standby state, the coarse screening comparator compares the light intensity change gradient with the first-level hysteresis threshold in real time through the subthreshold hysteresis comparison circuit. When the light intensity change gradient crosses the triggering upper limit of the first-level hysteresis threshold and meets the preset anti-interference dwell condition, a primary trigger pulse with level transition is generated and output through the pulse shaping stage.

[0019] S4. Multidimensional Feature Verification and Confidence Determination Steps: The initial trigger pulse is captured; the fine verification state machine switches from the off state to the feature extraction state and opens the verification time window; the baseline deviation, light intensity gradient, and signal duration are continuously collected; after baseline drift compensation, trend smoothing filtering, and effective pulse width accumulation, a multidimensional optical event feature parameter set is output; the feature splicing and encoding module performs data alignment and quantization encapsulation on the multidimensional optical event feature parameter set to construct a multidimensional optical event feature vector; the adaptive weighted matching model dynamically updates the weighting coefficients based on recent ambient light noise baseline statistics and historical false trigger frequency records, performing similarity mapping calculations on the multidimensional optical event feature vector to output a matching confidence score; the confidence verification and output logic compares the matching confidence score with the second-level dynamic confidence threshold step by step; when the matching confidence score is better than the second-level dynamic confidence threshold within a continuous preset verification period, the wake-up confidence condition is met, and the final wake-up enable signal with de-jittering and anti-re-triggering characteristics is output;

[0020] S5. Hierarchical Power-On Sequence Control and Context Recovery Steps: In response to the final wake-up enable signal, the power management module triggers the hierarchical power-on sequence control logic, sequentially recovering the analog front-end power rail, digital core power rail, and peripheral bus power rail according to the preset gradual ramp rate. After the voltage of each power rail reaches the locking threshold, a reference oscillation signal is injected into the main clock tree to complete phase locking and frequency reconstruction. After receiving the clock tree synchronization completion signal, the electronic timing main control module reads the key configuration register array saved in the snapshot before hibernation from the non-volatile memory area and performs parity check and logic boundary check. After the check passes, a system context recovery completion flag is generated. The hibernation timestamp accumulated by the real-time clock counter is phase aligned and temperature drift compensated with the full-speed running clock domain to complete clock synchronization. The timing task queue to be executed is parsed and the scheduling parameters are loaded. The task queue activation instruction is output.

[0021] S6. Load Awareness and Full-Cycle Energy Routing Steps: Based on the task queue activation command, the power management module switches the voltage level of each power rail and the working clock frequency from the low-power intermittent routing mode to the full-load performance routing mode. The energy efficiency feedback control loop continuously collects the real-time computing power load characteristics of the digital kernel and the scheduling pressure value of the timed task queue. The collected results are compared and calculated with the preset energy efficiency inflection point curve. When the load is below the inflection point, the frequency and voltage are automatically reduced and redundant peripheral power rails are cut off. When the load crosses the performance inflection point, the full-voltage and full-clock configuration is restored immediately. By real-time correction of the output parameters of the multi-rail voltage regulation array and the frequency division ratio of the global clock gating network, energy on-demand routing and sub-threshold power consumption control are realized throughout the entire process from intermittent sampling, feature verification to main control wake-up.

[0022] As can be seen from the technical solution provided by the present invention above, the beneficial effects of the low-power electronic timer wake-up system and method based on ambient light sensing provided by the present invention are:

[0023] The two-stage asymmetric verification architecture achieves a deep balance between ultra-low power consumption and high wake-up accuracy: small light intensity interference is continuously filtered through a nanoampere-level subthreshold coarse screening comparator, and the fine verification state machine is activated only as needed after the primary trigger pulse is captured; dynamic confidence verification is performed by combining multi-dimensional light event feature vectors and an adaptive weighted matching model, which effectively decouples the light intensity change rate and amplitude characteristics, and significantly reduces the false trigger rate and missed trigger rate under complex lighting conditions;

[0024] Dynamic duty cycle intermittent sampling and sliding window differential tracking technology significantly reduce the average power consumption of the system: The ambient light sensing unit adopts a duty cycle dynamic configuration mechanism with dual feedback of power supply margin and historical deviation, which completely eliminates the static dark current loss during non-sampling periods; The signal processing unit extracts dynamic reference values ​​in real time based on the sliding time window differential algorithm, separates transient interference and slow drift, and suppresses the power consumption of the front-end circuit to the nanowatt level while ensuring sensing sensitivity;

[0025] Full-cycle energy on-demand routing and load-aware dynamic optimization achieve global energy efficiency optimization: The power management module dynamically allocates multi-rail voltage and global clock frequency according to the system's operating phase state, achieving a smooth transition from subthreshold standby to full-load operation; The energy efficiency feedback control loop monitors the digital kernel's computing power load and task scheduling pressure in real time, automatically performing frequency and voltage reduction or restoring full voltage and full frequency to avoid redundant energy consumption under full-function operation.

[0026] Hierarchical power-on timing control and rapid context recovery ensure wake-up reliability and timing accuracy: Stepped power-on is performed according to the priority of analog front-end, digital kernel, and peripheral bus to avoid power surges and timing conflicts; combined with non-volatile memory snapshot reload, parity check and temperature drift compensation clock synchronization technology, microsecond-level lossless recovery of system context and high-precision timing continuity across the entire temperature range are achieved. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a low-power electronic timer wake-up system based on ambient light sensing according to the present invention.

[0028] Figure 2 This is a schematic diagram of the steps of a low-power electronic timer wake-up method based on ambient light sensing according to the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific embodiments.

[0031] like Figure 1-2 As shown, this embodiment of the invention provides a low-power electronic timer wake-up system based on ambient light sensing. The wake-up system is configured as a two-level asymmetric verification and power adaptive routing architecture based on the dynamic characteristics of ambient light, including an ambient light sensing unit, a signal processing unit, a wake-up control unit, an electronic timer main control module, and a power management module.

[0032] The ambient light sensing unit operates in an intermittent sampling mode with a controllable duty cycle, and is used to output raw photoelectric signals characterizing changes in ambient illuminance.

[0033] The signal processing unit is cascaded with the ambient light sensing unit to perform analog-to-digital conversion on the original photoelectric signal and to track the dynamic reference value of ambient light in real time based on the sliding time window differential algorithm, and to calculate the gradient of light intensity change and the deviation from the reference.

[0034] The wake-up control unit is connected to the signal processing unit and has a built-in coarse screening comparator and fine verification state machine. The coarse screening comparator continuously operates in a nanoampere-level low-power standby state, which is used to compare the light intensity change gradient with the first-level hysteresis threshold and output the primary trigger pulse. The fine verification state machine is activated only after capturing the primary trigger pulse, extracts the reference deviation, light intensity change gradient and signal duration to construct a multi-dimensional light event feature vector, performs validity verification through a preset adaptive weighted matching model, and outputs the final wake-up enable signal only when the verification result meets the wake-up confidence condition.

[0035] The electronic timing master control module is connected to the wake-up control unit and the power management module. During deep sleep, the power supply to the master clock tree and digital logic is cut off, and only the real-time clock counter is maintained. After receiving the final wake-up enable signal, the power management module restores the power supply to the analog front end, digital core and peripheral bus in sequence according to the preset power-on sequence. After the electronic timing master control module completes clock synchronization, register reloading and timing task queue scheduling, it enters the full-function running state.

[0036] The power management module is coupled to the power rails of the ambient light sensing unit, signal processing unit, wake-up control unit, and electronic timing master control module respectively. Based on the inter-level state switching signal of the wake-up control unit, the power supply voltage level and working clock frequency of each unit are dynamically configured to realize on-demand energy routing and subthreshold power consumption control throughout the entire process from intermittent sampling, feature verification to master control wake-up.

[0037] In this embodiment, the ambient light sensing unit is the core of the low-power electronic timer wake-up system based on ambient light sensing. It provides the original data basis for subsequent signal processing and wake-up determination by intermittently and accurately collecting and stably outputting ambient illuminance.

[0038] The ambient light sensing unit operates in an intermittent sampling mode with a controllable duty cycle, outputting raw photoelectric signals characterizing changes in ambient illuminance. It dynamically adjusts the sampling duty cycle based on the system power supply status and historical light intensity deviations, minimizing its own power consumption while ensuring sensing sensitivity and response speed. It is a key fundamental unit for achieving nanoampere-level standby power consumption in the entire wake-up system, directly determining the system's low-power performance and the reliability of wake-up triggering. The ambient light sensing unit includes:

[0039] Micropower oscillator:

[0040] The low-power oscillator is the timing reference source of the ambient light sensing unit. It operates in a subthreshold low-power mode and is used to generate a reference sampling clock signal with stable frequency and extremely low power consumption. This signal serves as a unified timing reference for the entire unit and is transmitted to the duty cycle dynamic configuration circuit to ensure the timing consistency and accuracy of all sampling operations. Its own static current is controlled at the nanoamp level and will not have a significant impact on the overall power consumption of the system.

[0041] Duty cycle dynamic configuration circuit:

[0042] The duty cycle dynamic configuration circuit receives the reference sampling clock signal output by the low-power oscillator. At the same time, it combines the current power rail voltage margin command issued by the power management module with the historical average value of the reference deviation output by the signal processing unit in the previous cycle to perform pulse width modulation processing on the reference sampling clock signal and output a sampling enable pulse with adjustable duty cycle.

[0043] Its duty cycle is dynamically calculated according to the following formula: ,in, The duty cycle of the current sampling enable pulse; The baseline duty cycle; This is the voltage margin adjustment coefficient for the power supply rail; This is the difference between the current power supply rail voltage and the nominal voltage. This is the adjustment coefficient for the benchmark deviation. This represents the historical average of the benchmark deviation from the previous period.

[0044] This circuit achieves a dynamic balance between power consumption and sensitivity by adjusting the effective duration of the sampling enable pulse in real time. When the ambient light changes gradually, the sampling duty cycle is reduced to reduce power consumption, while when the ambient light changes drastically, the sampling duty cycle is increased to ensure sensing accuracy.

[0045] Photoelectric detection front end:

[0046] The photoelectric detection front end receives the sampling enable pulse and uses it as its bias enable control input. It only turns on the internal photoelectric conversion circuit during the effective level of the sampling enable pulse to convert the captured instantaneous ambient illuminance into transient photovoltage. It uses a high-sensitivity, low-dark-current photodiode as the core detection element. During non-sampling periods, it completely turns off the bias circuit and the photoelectric conversion circuit, completely eliminating static dark current loss and further reducing the overall power consumption of the unit.

[0047] Signal latch output stage:

[0048] The signal latch output stage performs impedance isolation and peak hold processing on the transient photovoltage output from the photodetector front end, and continues to output the hold level after the sampling enable pulse ends until the next effective period of the cycle, thereby stabilizing the output of the original photoelectric signal characterizing the change in ambient illuminance. It has high input impedance and low output impedance characteristics, which can effectively isolate the mutual interference between the front and rear circuits, ensure that the original photoelectric signal remains stable within the sampling interval, and provide accurate and continuous input data for the subsequent signal processing unit.

[0049] The duty cycle adaptive adjustment technology is based on a dual feedback mechanism of system power supply status and ambient light variation characteristics. By introducing two adjustment dimensions—power supply rail voltage margin and historical average of reference deviation—a linearly weighted dynamic calculation model for the duty cycle is constructed. When the power supply rail voltage margin is sufficient and the ambient light variation is gradual, the sampling duty cycle is reduced to minimize power consumption. When the power supply rail voltage margin is insufficient or the ambient light variation is drastic, the sampling duty cycle is increased to ensure sampling accuracy and response speed. This technology can dynamically adjust the sampling strategy according to the actual operating status of the system to achieve the optimal match between power consumption and performance.

[0050] Intermittent photoelectric conversion technology controls the power supply and bias state of the photodetector front end through sampling enable pulses. The photoelectric conversion circuit and related active circuits are only turned on during the valid sampling period, and all power-consuming components are completely turned off during non-sampling periods. This working mode completely eliminates the static dark current loss in the traditional continuous sampling mode and reduces the average power consumption of the photodetector front end to the nanowatt level. At the same time, by precisely controlling the width and interval of the sampling pulses, the complete photoelectric conversion process is ensured to be completed within a limited sampling time, thus ensuring the accuracy of the sampling data.

[0051] Peak hold and impedance isolation technology is based on a voltage follower circuit composed of operational amplifiers and a capacitor energy storage circuit. The signal latch output stage utilizes the high input impedance characteristics of the voltage follower to avoid the load effect on the transient photovoltage of the photodetector front end, ensuring the integrity of the photoelectric conversion process. At the same time, it utilizes the charge retention characteristics of the energy storage capacitor to maintain the stability of the output voltage within the sampling interval. This technology can effectively solve the problem of signal discontinuity in intermittent sampling mode, providing a continuous and stable original photoelectric signal input for subsequent signal processing units.

[0052] After the system is powered on, the ambient light sensing unit completes hardware initialization, the low-power oscillator starts and outputs a stable reference sampling clock signal; the duty cycle dynamic configuration circuit loads the reference duty cycle parameter and the initial adjustment coefficient, and the photoelectric detection front end and the signal latch output stage enter the standby shutdown state, waiting for the sampling enable pulse to trigger.

[0053] The duty cycle dynamic configuration circuit receives the current power supply rail voltage margin command issued by the power management module, and at the same time obtains the historical average value of the reference deviation output by the signal processing unit in the previous cycle; calculates the sampling enable pulse duty cycle of the current cycle according to the duty cycle dynamic calculation model, generates the corresponding sampling enable pulse and sends it to the photoelectric detection front end.

[0054] After receiving the effective level of the sampling enable pulse, the photoelectric detection front end turns on the internal photoelectric conversion circuit and bias circuit, starts to capture the ambient illuminance and convert it into transient photovoltage; during the duration of the effective level of the sampling enable pulse, the complete photoelectric conversion process is completed, and a stable transient photovoltage is output to the signal latch output stage;

[0055] The signal latch output stage triggers peak hold operation at the effective edge of the sampling enable pulse to latch the current transient photovoltage. When the sampling enable pulse becomes invalid, the photodetector front end turns off all active circuits, and the signal latch output stage continues to output the latched photovoltage value until the effective level of the next sampling enable pulse arrives.

[0056] After completing one sampling cycle, the duty cycle dynamic configuration circuit recalculates the sampling duty cycle for the next cycle based on the latest power supply rail voltage margin and the historical average of the reference deviation. The above-mentioned dynamic duty cycle calculation, intermittent sampling and photoelectric conversion, signal latching and output process are repeated to achieve continuous intermittent monitoring of ambient illuminance.

[0057] In this embodiment, the signal processing unit is the core data processing hub of the low-power electronic timer wake-up system based on ambient light sensing. It receives the raw photoelectric signal output by the ambient light sensing unit, completes analog-to-digital conversion and multi-dimensional light feature extraction, and provides standardized feature input for the subsequent two-level verification of the wake-up control unit.

[0058] The signal processing unit is cascaded with the ambient light sensing unit to perform analog-to-digital conversion on the raw photoelectric signal and to track the dynamic reference value of ambient light in real time based on a sliding time window differential algorithm, calculating the gradient of light intensity change and the reference deviation. It operates in an intermittent triggering mode synchronized with the ambient light sensing unit, activating the core computing circuit only during the effective sampling period and maintaining a low-power standby state during non-sampling periods. While ensuring feature extraction accuracy and real-time performance, it strictly controls its own power consumption level, making it a key component in achieving a balance between low power consumption and high anti-interference capabilities. The signal processing unit includes:

[0059] Analog-to-digital conversion stage:

[0060] The analog-to-digital conversion stage is cascaded with the ambient light sensing unit to receive the raw photoelectric signal. Under the effective edge triggering of the system sampling enable pulse, it performs cycle-by-cycle quantization processing to generate a discrete digital light intensity sequence. It adopts a low-power successive approximation architecture, turning on the internal comparator and digital-to-analog conversion circuit only during the quantization cycle, and immediately turning off all active circuits after quantization, keeping the power consumption of a single quantization at the nanojoule level. Its quantization resolution and sampling rate can be dynamically configured through the power management module to match the accuracy requirements under different ambient light conditions.

[0061] Sliding data cache array:

[0062] The sliding data buffer array is cascaded with the analog-to-digital converter stage. It receives discrete digital light intensity sequences and performs sliding overlay shift storage according to a preset window depth. When writing new period data, it automatically discards the oldest period historical data to form the current sliding window light intensity data frame. It adopts a ring buffer structure composed of static random access memory, which has extremely low read and write power consumption and access latency. It can complete data shifting and update operations within a single clock cycle. The preset window depth can be configured according to the application scenario to balance the smoothness and response speed of dynamic reference tracking.

[0063] Dynamic benchmark tracker:

[0064] The dynamic reference tracker is cascaded with the sliding data buffer array. It receives the current sliding window light intensity data frame, performs point-by-point difference operation on adjacent period data within the frame to obtain the window difference sequence, performs abrupt extreme value removal and low-pass smoothing filtering on the window difference sequence to separate transient interference components, extracts the steady-state difference reference that characterizes the slow evolution trend of ambient light, and performs attenuation weighted fusion operation with the historical reference value output from the previous period to update and generate the real-time ambient light dynamic reference value.

[0065] Its attenuation-weighted fusion operation follows the following formula: ,in, This is the current real-time dynamic baseline value for ambient light; The historical baseline attenuation coefficient; This is the historical benchmark value from the previous period; This serves as the current steady-state differential benchmark within the window.

[0066] This tracker can effectively filter out the slow drift and random spike interference of ambient light, ensuring that the dynamic reference value can accurately reflect the long-term change trend of ambient light, and provide a stable reference for subsequent feature calculations.

[0067] Gradient and Deviation Calculation Module:

[0068] The gradient and deviation calculation module is cascaded with the dynamic reference tracker. It receives the window difference sequence and the real-time ambient light dynamic reference value. It performs amplitude accumulation and halo normalization on the consecutive valid difference segments with the same sign in the window difference sequence, and outputs the light intensity change gradient that represents the instantaneous rate of change of light intensity. At the same time, it performs a difference comparison operation between the latest periodic discrete digital light intensity value and the real-time ambient light dynamic reference value to obtain the reference deviation.

[0069] The calculation of its light intensity gradient follows the formula below: ,in, The gradient represents the change in light intensity. The length of consecutive valid difference segments with the same sign; The first in the window difference sequence The amplitude of each effective fraction point;

[0070] This module decouples the rate and amplitude characteristics of light intensity changes, providing two independent judgment dimensions for the subsequent two-level verification of the wake-up control unit, significantly improving the system's ability to identify different types of wake-up light events.

[0071] Feature synchronization output interface:

[0072] The feature synchronization output interface is cascaded with the gradient and deviation calculation module to receive the light intensity change gradient and the reference deviation. Under the reference clock domain of the wake-up control unit, it performs cross-clock domain synchronous latching and data frame encapsulation, and synchronously outputs the encapsulated multi-dimensional optical event feature vector to the coarse screening comparator and the fine verification state machine. It adopts a two-level synchronous latching architecture, which can effectively eliminate the metastability risk caused by cross-clock domain transmission and ensure the reliability and timing consistency of feature data transmission.

[0073] Among them, the sliding time window differential dynamic benchmark tracking technology is based on the fusion of time-domain differential and statistical filtering. By performing point-by-point differential operations on the light intensity sequence within the sliding window, the absolute light intensity value is converted into a relative change, eliminating the influence of slow ambient light drift on feature calculation. Through abrupt extreme value elimination and low-pass smoothing filtering, the steady-state change component and transient interference component of ambient light are separated. Through attenuation weighted fusion mechanism, the historical benchmark value is combined with the current steady-state differential benchmark, so that the dynamic benchmark value can smoothly follow the long-term change trend of ambient light, while avoiding benchmark jumps caused by transient interference. This technology can adapt to slow-changing ambient light conditions such as day-night alternation and seasonal changes, ensuring the stable operation of the system under different lighting environments.

[0074] Multi-dimensional light feature decoupling calculation technology extracts the rate and amplitude features of light intensity changes separately, decomposing a single light intensity signal into two independent feature dimensions. The light intensity change gradient reflects the speed of light intensity change and can effectively distinguish between rapid human-induced wake-up operations and slow natural light changes. The baseline deviation reflects the degree of difference between the current light intensity and the long-term baseline and can effectively determine the magnitude of light intensity change. By decoupling these two feature dimensions, the system can construct a more comprehensive and accurate description of light event features, significantly reducing the probability of false triggering and missed triggering.

[0075] Intermittent low-power computing technology is based on a triggering mechanism synchronized with the ambient light sensing unit. All computing circuits in the signal processing unit are activated only during the valid sampling period. After completing the quantization, buffering, benchmark update, and feature calculation tasks of the current cycle, all active circuits are immediately shut down, and the unit enters a low-power standby state. At the same time, each submodule adopts gated clock technology to cut off the clock supply of irrelevant logic during non-computation periods, further reducing static power consumption. This technology controls the average power consumption of the signal processing unit to the nanowatt level and will not have a significant impact on the overall standby power consumption of the system.

[0076] After the system is powered on, the signal processing unit completes hardware initialization, the sliding data buffer array clears all storage units, the dynamic reference tracker loads the initial reference value and historical reference attenuation coefficient, the gradient and deviation calculation module loads the dimension normalization parameter, and the feature synchronization output interface completes the calibration of the cross-clock domain synchronization link; all arithmetic circuits enter a low-power standby state, waiting for the sampling enable pulse to trigger.

[0077] Upon receiving the effective edge of the system sampling enable pulse, the analog-to-digital converter stage starts and completes the quantization processing of the original photoelectric signal to generate a discrete digital light intensity sequence; the sliding data buffer array writes the newly generated discrete digital light intensity sequence into the buffer, while automatically eliminating the earliest period's historical data and updating to form the current sliding window light intensity data frame;

[0078] The dynamic reference tracker reads the current sliding window light intensity data frame, performs point-by-point difference operation to obtain the window difference sequence; performs abrupt extreme value removal and low-pass smoothing filtering on the window difference sequence to extract the current window steady-state difference reference; calculates and updates the real-time ambient light dynamic reference value according to the attenuation weighted fusion formula, and saves the reference value as the historical reference value for the next cycle.

[0079] The gradient and deviation calculation module reads the in-window difference sequence and the real-time ambient light dynamic reference value, identifies the consecutive valid difference segments with the same sign in the in-window difference sequence, and calculates the gradient of light intensity change; it then performs a difference operation between the latest periodic discrete digital light intensity value and the real-time ambient light dynamic reference value to obtain the reference deviation.

[0080] The feature synchronization output interface receives the gradient of light intensity change and the reference deviation, performs two-level synchronization latching and data frame encapsulation under the reference clock domain of the wake-up control unit, generates a standardized multi-dimensional light event feature vector, and synchronously outputs it to the coarse screening comparator and the fine verification state machine.

[0081] After completing all processing tasks in the current cycle, the signal processing unit shuts off the clock and power supply of all arithmetic circuits and returns to a low-power standby state; it waits for the next cycle's sampling enable pulse to arrive, and repeats the above data quantization and buffering, dynamic reference update, feature parameter calculation, and synchronous output process to achieve continuous real-time extraction of ambient light features.

[0082] In this embodiment, the wake-up control unit is the core decision-making center of the low-power electronic timer wake-up system based on ambient light sensing. It achieves a deep balance between low-power standby and high-accuracy wake-up through a two-level asymmetric verification architecture and is a key module that determines the system's false trigger rate and wake-up response speed.

[0083] The wake-up control unit is connected to the signal processing unit and incorporates a coarse-screen comparator and a fine-verification state machine. The coarse-screen comparator continuously operates in a nano-ampere low-power standby state, comparing the light intensity change gradient with the first-level hysteresis threshold and outputting a primary trigger pulse. The fine-verification state machine is activated only after capturing the primary trigger pulse, extracting the reference deviation, light intensity change gradient, and signal duration to construct a multi-dimensional optical event feature vector. It performs validity verification using a preset adaptive weighted matching model, outputting the final wake-up enable signal only when the verification result meets the wake-up confidence condition. It can dynamically adjust the verification threshold and feature weights, ensuring nano-ampere standby power consumption while keeping the system's false trigger rate extremely low. The wake-up control unit includes:

[0084] Coarse sieve comparator:

[0085] The coarse screening comparator continuously receives light intensity gradient changes in nanoamp-level low-power standby mode. It compares the light intensity gradient with the first-level hysteresis threshold in real time using a built-in subthreshold hysteresis comparison circuit. When the light intensity gradient crosses the trigger limit of the first-level hysteresis threshold and the duration meets the preset anti-interference dwell condition, a primary trigger pulse with a level transition is generated and output through the pulse shaping stage. It employs a fully custom subthreshold analog circuit design, with a static current below ten nanoamps, serving as the core support for maintaining ultra-low standby power consumption throughout the system. Its first-level hysteresis threshold has temperature compensation characteristics, enabling it to maintain stable trigger sensitivity over a wide temperature range.

[0086] Fine-grained verification state machine:

[0087] After capturing the primary trigger pulse, the fine verification state machine switches from the off state to the feature extraction state, opens a preset verification time window, and continuously acquires the reference deviation, light intensity change gradient, and signal duration output by the signal processing unit within the verification time window. It performs baseline drift compensation on the reference deviation, trend smoothing filtering on the light intensity change gradient, and effective pulse width accumulation on the signal duration, outputting a denoised and normalized multi-dimensional optical event feature parameter set. It adopts a gated clock design, completely cutting off the clock supply in the off state and retaining only the power supply to the primary trigger pulse capture circuit, ensuring zero additional power consumption during non-verification periods.

[0088] Feature concatenation and encoding module:

[0089] The feature splicing and encoding module receives a set of multidimensional optical event feature parameters, aligns and quantizes the multidimensional optical event feature parameter set according to a preset spatiotemporal mapping order, and constructs a multidimensional optical event feature vector. It maps the three feature parameters, namely the reference deviation, the gradient of light intensity change, and the signal duration, into a sixteen-bit encoding sequence with unified dimensions, ensuring the efficiency and consistency of subsequent matching operations. Its quantization accuracy can be dynamically adjusted according to the application scenario to balance matching accuracy and computational power consumption.

[0090] Adaptive weighted matching model:

[0091] The adaptive weighted matching model receives multi-dimensional light event feature vectors, dynamically updates the weighting coefficients of each feature dimension based on recent ambient light noise baseline statistics and historical false trigger frequency records, performs similarity mapping calculations between the weighted multi-dimensional light event feature vectors and a pre-set standard wake-up light mode feature library, and outputs a matching confidence score that characterizes the legality of the light event.

[0092] The matching confidence score is calculated according to the following formula: ,in, To match confidence scores; For the first Weighting coefficients for each feature dimension; For the first Normalized feature parameters;

[0093] The dynamic update of its weighting coefficients follows the formula below: ,in, For the current cycle number Weighting coefficients for each feature dimension; For the previous cycle Weighting coefficients for each feature dimension; The learning rate; This is a correction factor for the frequency of historical false triggers; For the first Normalized feature parameters;

[0094] The model can automatically adapt to noise characteristics in different environments, continuously optimize matching accuracy, and effectively reduce false triggering caused by changes in ambient light.

[0095] Confidence verification and output logic:

[0096] The confidence verification and output logic receives the matching confidence score and compares it step by step with the second-level dynamic confidence threshold. When the matching confidence score is better than the second-level dynamic confidence threshold for a continuous preset verification period, the verification result is determined to meet the wake-up confidence condition. A final wake-up enable signal with de-jitter and anti-re-trigger characteristics is generated and sent to the power management module. If the matching confidence score does not meet the wake-up confidence condition, the fine verification state machine clears the feature cache and forces a return to the shutdown state to maintain the static current level of the nanoampere-level low-power standby state. The second-level dynamic confidence threshold will be automatically adjusted according to the recent false trigger frequency. When the false trigger rate is high, the threshold will be appropriately increased to enhance the system's anti-interference capability.

[0097] The dual-level asymmetric verification technology is based on the hierarchical optimization of power consumption and accuracy. The first-level coarse screening uses an extremely low-power analog comparison circuit that runs continuously in nanoampere-level standby mode, performing only simple threshold comparisons on light intensity gradient changes to quickly filter out most meaningless small interferences. The second-level fine verification uses digital logic circuits that are activated only as needed after the coarse screening is triggered, achieving high-accuracy wake-up determination through multi-dimensional feature matching and confidence verification. This architecture concentrates most of the power consumption in the nanoampere-level coarse screening stage, activating the high-power fine verification stage only in the rare case of suspected wake-up events, achieving a perfect balance between ultra-low standby power consumption and high wake-up accuracy.

[0098] The adaptive weighted matching technology is based on online learning and statistical feedback mechanisms. By continuously analyzing the recent ambient light noise baseline and historical false trigger frequency, it dynamically adjusts the weighting coefficients of each feature dimension. When the ambient light noise is high, it increases the weight of the light intensity change gradient and signal duration, and decreases the weight of the baseline deviation, thereby reducing false triggers caused by noise. When the historical false trigger frequency is high, it increases the overall second-level dynamic confidence threshold to enhance the system's anti-interference capability. This technology enables the system to automatically adapt to different application environments and maintain stable wake-up performance.

[0099] The anti-shake and anti-re-triggering technology is based on a continuous multi-cycle verification and state locking mechanism. The confidence verification and output logic require that the matching confidence score be better than the second-level dynamic confidence threshold within a continuous preset verification cycle before the final wake-up enable signal is output, effectively filtering out false triggers caused by single spike interference. At the same time, after outputting the final wake-up enable signal, it will automatically enter the re-trigger lock state, ignoring all new trigger requests within a preset lock time to prevent multiple repeated wake-ups caused by the same wake-up light event.

[0100] After the system is powered on, the wake-up control unit completes hardware initialization, the coarse screening comparator loads the first-level hysteresis threshold and anti-interference dwell time parameters, the adaptive weighted matching model loads the initial weighting coefficients and the standard wake-up light mode feature library, and the confidence verification and output logic loads the second-level dynamic confidence threshold and continuous verification period parameters; the fine verification state machine, feature splicing and encoding module and adaptive weighted matching model enter the shutdown state, and only the coarse screening comparator continues to run in the nanoampere-level low-power standby state;

[0101] The coarse screening comparator continuously receives the light intensity change gradient output by the signal processing unit and compares it with the first-level hysteresis threshold in real time through the subthreshold hysteresis comparison circuit. When the light intensity change gradient does not cross the trigger limit, it maintains a low-level output and the system remains in standby mode. When the light intensity change gradient crosses the trigger limit and the duration meets the anti-interference dwell condition, a primary trigger pulse is generated and output to the fine verification state machine.

[0102] After the fine verification state machine captures the primary trigger pulse, it immediately switches from the shutdown state to the feature extraction state and opens the preset verification time window; at the same time, it sends an inter-stage state switching signal to the power management module, requesting to increase its own power supply rail voltage and working clock frequency, so as to provide the necessary hardware support for subsequent feature extraction and matching operations.

[0103] Within the verification time window, the fine verification state machine continuously collects three feature parameters: baseline deviation, light intensity change gradient, and signal duration. It then performs baseline drift compensation, trend smoothing filtering, and effective pulse width accumulation processing to generate a denoised and normalized multidimensional optical event feature parameter set. The feature splicing and encoding module performs data alignment and quantization encapsulation on the feature parameter set to construct a standardized multidimensional optical event feature vector.

[0104] The adaptive weighted matching model reads multi-dimensional light event feature vectors, updates the weighting coefficients of each feature dimension based on recent ambient light noise baseline statistics and historical false trigger frequency records, performs similarity mapping calculations between the weighted feature vectors and the standard wake-up light mode feature library, and outputs a matching confidence score.

[0105] The confidence verification and output logic compares the confidence score with the second-level dynamic confidence threshold. If the score is better than the threshold within a consecutive preset verification period, it is determined to be a valid wake-up event. A final wake-up enable signal is generated and sent to the power management module. At the same time, the historical false trigger frequency record and feature weights are updated. If the score does not meet the conditions, it is determined to be an interference event. All feature caches are cleared, the fine verification state machine is forced to return to the shutdown state, and the system is restored to the nanoampere-level low-power standby state.

[0106] After outputting the final wake-up enable signal, the confidence verification and output logic automatically enters the re-trigger lockout state. During the preset lockout time, all new primary trigger pulses are ignored to prevent multiple repeated wake-ups caused by the same wake-up light event. After the lockout time ends, the system automatically returns to the subthreshold hysteresis coarse screening stage to prepare to respond to the next wake-up request.

[0107] In this embodiment, the electronic timing master control module is the core execution and calculation unit of the low-power electronic timer wake-up system based on ambient light sensing. It undertakes the core responsibilities of realizing the system timing function, task scheduling management and operation status control, and is a key bridge connecting the low-power wake-up mechanism and actual timing applications.

[0108] The electronic timing master control module is connected to the wake-up control unit and the power management module. During deep sleep, it cuts off the power supply to the main clock tree and digital logic, maintaining only the real-time clock counter. Upon receiving the final wake-up enable signal, the power management module restores power to the analog front-end, digital core, and peripheral bus sequentially according to the preset power-on sequence. After completing clock synchronization, register reloading, and timing task queue scheduling, the electronic timing master control module enters full-function operation mode. It can quickly switch between nanoampere-level deep sleep and full-speed operation mode, minimizing system power consumption while ensuring timing accuracy and task execution reliability. The electronic timing master control module includes:

[0109] Real-time clock counter:

[0110] The real-time clock counter is the only continuously running functional module during deep sleep. It uses a low-power temperature-compensated crystal oscillator as the clock source to accumulate system sleep timestamps. Its static current is controlled at the nanoamp level, enabling it to run continuously for several years even when the main power supply is completely cut off. It has independent power rails and clock domains, and is not affected by the main system power supply status, ensuring the continuity and accuracy of timing during sleep.

[0111] Master clock tree and clock synchronization unit:

[0112] The master clock tree and clock synchronization unit are responsible for generating the multi-clock domain signals required for full-speed system operation, and for performing phase alignment and temperature drift compensation between the real-time clock counter and the full-speed operating clock domain. The master clock tree has a built-in phase-locked loop, which can quickly generate clock signals of different frequencies based on the reference oscillation signal to meet the different clock requirements of the digital core and peripheral bus. The clock synchronization unit corrects the impact of temperature changes on timing accuracy through a temperature drift compensation algorithm, ensuring that the timing error is controlled within five parts per million across the entire temperature range. Its temperature compensation calculation follows the following formula: ,in, This is the actual time after temperature compensation; This is the original count value of the real-time clock counter; This is the temperature drift coefficient; The current ambient temperature; This is the nominal reference temperature;

[0113] Non-volatile memory management unit:

[0114] The non-volatile memory management unit is responsible for managing the system's non-volatile memory area, enabling snapshot saving and rapid recovery of the system context. Before the system enters deep hibernation, it writes the critical configuration register array, task queue status, and system operating parameters into the non-volatile memory area. When the system wakes up, it quickly reads the stored context data and transmits it to the register reload and verification unit to ensure that the system can quickly recover to the operating state before hibernation.

[0115] Register overload and verification unit:

[0116] The register reload and verification unit receives the context data output by the non-volatile memory management unit, reloads it into the volatile configuration area of ​​the digital kernel, and performs parity and logical boundary checks. It verifies the integrity of data transmission through bit-by-bit parity checks and ensures that register values ​​are within the legal range through logical boundary checks. After the verification passes, a system context recovery completion flag is generated. If the verification fails, a system reset process is triggered to prevent system anomalies caused by data errors.

[0117] Timed task queue scheduling engine:

[0118] The timed task queue scheduling engine is responsible for parsing the queue of timed tasks to be executed and scheduling tasks for execution according to task priority and time slice round-robin strategy; it supports multi-level task priority configuration and can dynamically allocate system resources according to the urgency and importance of tasks; it has the functions of suspending, resuming and deleting tasks, and can flexibly handle complex timed task scenarios to ensure that all timed tasks are executed on time and accurately.

[0119] System status control unit:

[0120] The system status control unit is responsible for managing the system's operating status and coordinating the workflow between various sub-modules. It receives the power supply status signal from the power management module and the wake-up enable signal from the wake-up control unit, and controls the system to switch between deep sleep state, power-on initialization state, context recovery state, and full-function operation state. It is also responsible for generating system status indication signals and feeding them back to the power management module and the wake-up control unit to enable collaborative work between various modules of the system.

[0121] Among them, the deep hibernation context snapshot technology is based on non-volatile storage and incremental backup mechanism. Before the system enters deep hibernation, only the key configuration registers and task queue status that affect the system's operating status are snapshotted and saved, rather than all memory data. This incremental backup method greatly reduces the amount of data written before hibernation and the amount of data read when waking up, shortens the system hibernation and wake-up switching time, and at the same time reduces the number of erase and write cycles of non-volatile storage, extending the service life of the storage medium.

[0122] The tiered power-on and clock synchronization technology is based on the coordinated timing control of power supply and clock. The power management module powers on sequentially in the order of analog front-end, digital core, and peripheral bus, ensuring that the previous stage circuit is stable before starting the next stage circuit, thus avoiding system instability caused by power surges. The main clock tree starts the phase-locking process after the digital core power supply is stable, and then performs register reloading and task scheduling after the clock signal is stable. This timing control method ensures the reliability and stability of the system wake-up process.

[0123] The temperature drift compensation high-precision timing technology is based on a temperature sensor feedback and real-time correction mechanism. The system has a built-in temperature sensor to collect the ambient temperature in real time. The clock synchronization unit dynamically corrects the count value of the real-time clock counter according to the temperature value and the preset temperature drift coefficient. By establishing a mathematical model of temperature and timing error, the influence of temperature changes on the crystal oscillator frequency can be effectively offset, ensuring the timing accuracy of the system over a wide temperature range.

[0124] Priority-driven task scheduling technology is based on a preemptive time-slice round-robin mechanism. The timed task queue scheduling engine assigns a unique priority to each task, and higher-priority tasks can preempt the execution rights of lower-priority tasks. For tasks with the same priority, execution time is allocated using a time-slice round-robin method. This scheduling mechanism ensures that urgent timed tasks can be processed in a timely manner, while guaranteeing the fair allocation of system resources and improving the overall operating efficiency of the system.

[0125] After the system is powered on, the electronic timing main control module completes hardware initialization, the real-time clock counter starts and begins timing, the non-volatile memory management unit loads the factory default configuration parameters, the system status control unit sets the system to deep sleep state, the main clock tree, register reload and verification unit and timing task queue scheduling engine enter the shutdown state, and only the real-time clock counter continues to run.

[0126] After the system enters deep sleep mode, the power management module cuts off the power supply to the main clock tree and digital logic, leaving only the independent power rail of the real-time clock counter; the real-time clock counter continues to accumulate sleep timestamps, and the system state control unit monitors the output signal of the wake-up control unit, waiting for the arrival of the final wake-up enable signal;

[0127] After receiving the final wake-up enable signal, the system status control unit immediately sends a power-on request to the power management module; the power management module triggers a tiered power-on sequence to restore power to the analog front-end, digital core, and peripheral bus in sequence; the master clock tree receives the reference oscillation signal, initiates the phase-locking and frequency reconstruction process, and generates a full-speed operating clock domain.

[0128] After the master clock tree is synchronized, the non-volatile memory management unit reads the critical configuration register array and task queue status saved before hibernation from the non-volatile memory area; the register reload and verification unit reloads the read data into the volatile configuration area and performs parity and logical boundary verification; if the verification passes, a system context recovery completion flag is generated; if the verification fails, a system reset is triggered.

[0129] After the system context is restored, the clock synchronization unit reads the accumulated sleep timestamps from the real-time clock counter, performs temperature drift compensation calculations in conjunction with the current ambient temperature, and obtains the accurate sleep duration. The compensated timestamps are then phase-aligned with the full-speed running clock domain to complete system clock synchronization and ensure the continuity and accuracy of timing.

[0130] After clock synchronization is complete, the timing task queue scheduling engine parses the queue of timing tasks to be executed, loads scheduling parameters according to task priority and time slice round-robin strategy, and starts task execution; the system enters full-function running state, executing various timing tasks and user interaction operations; the power management module dynamically adjusts power supply parameters according to the real-time load of the system to maintain optimal system energy efficiency;

[0131] After all timing tasks are completed and the system idle time reaches the preset threshold, the system state control unit triggers the hibernation process; the non-volatile memory management unit writes the current critical system state into the non-volatile memory area and completes the context snapshot saving; the power management module sequentially cuts off the power supply to the peripheral bus, digital core and analog front end, and the system returns to deep hibernation state, with only the real-time clock counter continuing to run.

[0132] In this embodiment, the power management module is the energy scheduling center of the low-power electronic timer wake-up system based on ambient light sensing. It realizes on-demand energy allocation throughout the entire cycle from intermittent sampling to full-function operation through multi-track voltage dynamic adjustment and global clock gating technology. It is the core support module to ensure the ultra-low power operation and stable and reliable wake-up of the system.

[0133] The power management module is coupled to the power rails of the ambient light sensing unit, signal processing unit, wake-up control unit, and electronic timing master control module. Based on the inter-stage state switching signals of the wake-up control unit, it dynamically configures the power supply voltage level and operating clock frequency of each unit, achieving on-demand energy routing and sub-threshold power consumption control throughout the entire process from intermittent sampling and feature verification to master control wake-up. It can accurately identify different phases of system operation and match the optimal power supply and distribution strategy for each phase, ensuring system performance requirements while controlling the average power consumption throughout the entire cycle to the nanoampere level. The power management module includes:

[0134] Phase interpreter:

[0135] The phase state interpreter continuously monitors the inter-stage state switching signals output by the wake-up control unit, and parses them into four types of phase state identifiers: intermittent sampling phase, coarse screening trigger phase, fine verification phase, and master control wake-up phase. Based on the phase state identifiers, it generates corresponding power rail enable command sequences and clock frequency configuration words, and sends them to the multi-rail voltage regulation array and global clock gating network. It uses a hardware state machine to realize fast phase state switching and identification, with a switching delay of less than microseconds, ensuring the continuity and timeliness of energy supply during system state transitions.

[0136] Multi-rail voltage regulation array:

[0137] The multi-rail voltage regulation array receives the power rail enable command sequence from the phase state interpreter, providing independently adjustable power rail voltages for each unit of the system. It integrates multiple low-power linear regulators, each corresponding to an independent power rail, enabling continuous adjustment from the subthreshold lower limit to the nominal voltage. Its output voltage accuracy is better than one percent, and its load response time is less than ten microseconds, allowing for rapid response to load changes under different phase states. Its dynamic output voltage adjustment follows the formula below: ,in, This is the current output voltage of the power supply electromechanical equipment; This is the lower threshold voltage. This is the voltage regulation coefficient; This serves as the current system operating phase identifier.

[0138] Global clock gating network:

[0139] The global clock gating network receives the clock frequency configuration word from the phase interpreter and performs fine-grained gating management of all clock domains in the system. It can independently control the clock supply of each functional module, completely cut off the clock signals of irrelevant modules during non-working periods, and eliminate the dynamic power consumption of the clock tree. It supports multi-frequency clock output and can dynamically adjust the clock frequency according to the operation requirements of different modules to achieve the optimal match between performance and power consumption.

[0140] Energy efficiency feedback control loop:

[0141] After the electronic timing main control module enters full-function operation, the energy efficiency feedback control loop continuously collects the real-time computing load characteristics of the digital kernel and the scheduling pressure value of the timing task queue. It compares the collected results with the preset energy efficiency inflection point curve and performs calculations to adjust the output parameters of the multi-track voltage regulation array and the frequency division ratio of the global clock gating network in real time. The energy efficiency inflection point determination follows the following formula: ,in, This represents the current system energy efficiency ratio; This refers to the system's real-time power consumption. For real-time computing power load of digital kernel;

[0142] When the energy efficiency ratio is lower than the preset inflection point, the system automatically reduces frequency and voltage to improve energy efficiency; when the energy efficiency ratio is higher than the preset inflection point, the system restores the full voltage and full clock configuration to ensure performance.

[0143] Among them, the full-cycle phased energy routing technology is based on the phase division and energy demand modeling of the system operation process. By dividing the complete operation process of the system from standby to wake-up into four distinct operating phases, a precise energy demand model is established for each phase, and the corresponding power supply voltage and clock frequency configuration is matched. This technology breaks the limitations of the traditional fixed power supply mode, realizes precise on-demand energy allocation, ensures that every bit of energy is used for necessary system operations, and minimizes energy waste.

[0144] Subthreshold power consumption control technology reduces the circuit's supply voltage to below the transistor's threshold voltage, enabling the circuit to operate in the subthreshold region. In the subthreshold region, the transistor's drain current and gate-source voltage are exponentially related, which can significantly reduce the circuit's static and dynamic power consumption. The power management module clamps the power rail voltages of the ambient light sensing unit and the signal processing unit to the lower limit of the subthreshold range during the intermittent sampling phase and the coarse screening trigger phase, reducing the average power consumption of these two units to the nanowatt level. This is the core technology for achieving nanoampere-level standby power consumption in the system.

[0145] The tiered power-on and inter-rail synchronization technology is based on fine-grained control of power timing. During the main control wake-up phase, the power management module performs a tiered power-on operation according to the priority sequence of analog front-end, digital core, and peripheral bus, ensuring that the previous stage circuit is completely stable before starting the next stage circuit. At the same time, after the voltage of each power supply rail reaches the locking threshold, it outputs an inter-rail synchronization ready pulse to trigger the global clock gating network to start the main clock tree. This technology can effectively avoid power surges and timing conflicts, and ensure the stability and reliability of the system wake-up process.

[0146] Load-aware dynamic energy efficiency optimization technology is based on real-time load feedback and closed-loop control mechanisms. The energy efficiency feedback control loop continuously monitors the computing load and task scheduling pressure of the digital kernel, and dynamically adjusts the power supply voltage and clock frequency. When the system load is low, the voltage and frequency are automatically reduced to reduce unnecessary energy consumption. When the system load is high, the voltage and frequency are immediately increased to ensure the real-time performance of tasks. This technology can continuously maintain the optimal energy efficiency ratio of the system under full-function operation.

[0147] After the system is powered on, the power management module completes hardware initialization, the multi-track voltage regulation array outputs the default subthreshold supply voltage, and the global clock gating network only enables the clock supply of the reference sampling clock and the phase state interpreter; the phase state interpreter sets the initial state of the system to intermittent sampling phase, generates the corresponding power supply and clock configuration commands, and sends them to the multi-track voltage regulation array and the global clock gating network.

[0148] During the intermittent sampling phase, the multi-track voltage regulation array clamps the power rail voltages of the ambient light sensing unit and the signal processing unit to the subthreshold lower limit range; the global clock gating network performs gate shutdown on the peripheral bus and digital logic during non-sampling periods, maintaining only the reference sampling clock and the minimal pulse drive of the sliding data buffer array; the system is in a nanowatt-level static leakage current suppression state, waiting for the arrival of the coarse screening trigger signal;

[0149] When the phase interpreter resolves the coarse-screened trigger phase identifier based on the primary trigger pulse, the multi-track voltage regulation array raises the analog front-end power supply rail of the signal processing unit to the first operating threshold along a preset slope, and simultaneously releases the subthreshold current limiting state of the dynamic reference tracker; the global clock gating network enables the local clock domain of the gradient and deviation calculation module to match the real-time computing bandwidth requirements of the light intensity change gradient; the system enters a medium power supply and distribution state to support dynamic reference separation and gradient calculation;

[0150] When the phase interpreter parses the instruction for extracting multidimensional optical event feature vectors to the fine verification phase identifier, the multi-track voltage regulation array further increases the power supply rail voltage of the wake-up control unit to the nominal value of the linear region, and allocates independent high-speed clock branches to the feature splicing encoding module and the adaptive weighted matching model; the global clock gating network synchronously opens the synchronous sampling clock of the verification time window to ensure the timing alignment of the multidimensional optical event feature vectors and the glitches-free transmission across clock domains; the system enters a high-dynamic power supply and distribution state to support similarity mapping and confidence verification;

[0151] When the phase state decoder captures the final wake-up enable signal and resolves the master control wake-up phase identifier, the multi-rail voltage regulation array performs a step-by-step power-up operation according to the priority sequence of analog front-end, digital core, and peripheral bus; after the voltage of each power supply rail reaches the locking threshold, it outputs an inter-rail synchronization ready pulse; after the global clock gating network receives the pulse, it unlocks the gating lock of the master clock tree, injects a reference oscillation signal and starts the phase-locked loop, gradually multiplying the operating clock frequency from the low-frequency wake-up state to the full-speed operating state; the system enters the full-load power supply and distribution initialization state, and completes system context recovery and task queue scheduling;

[0152] After the electronic timing main control module enters full-function operation mode, the energy efficiency feedback control loop is activated. It continuously collects the real-time computing power load characteristics of the digital kernel and the scheduling pressure value of the timing task queue to calculate the current system energy efficiency ratio. It compares the energy efficiency ratio with the preset energy efficiency inflection point curve. When the load is below the inflection point, it automatically reduces the frequency and voltage and cuts off the power supply rails of redundant peripherals. When the load crosses the performance inflection point, it immediately restores the full voltage and full clock configuration. By adjusting the power supply and clock parameters in real time, it maintains the optimal energy efficiency of the system in full-function operation mode.

[0153] Once all timing tasks are completed and the system idle time reaches a preset threshold, the electronic timing master control module sends a hibernation request to the power management module. The power management module sequentially cuts off the power supply to the peripheral bus, digital core, and analog front end, and shuts down the master clock tree and all high-speed clock domains. Only the independent power supply rail of the real-time clock counter and the reference sampling clock are retained. The system returns to the nanowatt-level low-power standby state of the intermittent sampling phase, waiting for the next wake-up request.

[0154] A low-power electronic timer wake-up method based on ambient light sensing includes the following steps:

[0155] Step S1: Duty Cycle Dynamic Configuration and Intermittent Sampling Steps:

[0156] The core function of S1 is to achieve low-power intermittent ambient light acquisition. It dynamically adjusts the sampling duty cycle based on the system power supply status and historical light intensity variation characteristics, minimizing power consumption during the sensing stage while ensuring sensing sensitivity, thus providing a stable raw photoelectric signal for subsequent signal processing. The detailed steps are as follows:

[0157] Step S1-1: Reference sampling clock generation: The low-power oscillator operates in subthreshold low-power mode to generate a stable reference sampling clock signal and transmit it to the duty cycle dynamic configuration circuit; this clock signal serves as the unified timing reference for the entire ambient light sensing unit, ensuring the timing consistency of all sampling operations, and its own static current is controlled at the nanoamp level.

[0158] Step S1-2: Dynamic calculation of sampling duty cycle: The duty cycle dynamic configuration circuit receives the current power supply rail voltage margin command issued by the power management module, and at the same time obtains the historical average value of the reference deviation output by the signal processing unit in the previous cycle, and calculates the duty cycle of the current sampling enable pulse based on the linear weighted model.

[0159] Step S1-3: Intermittent photoelectric conversion: The photoelectric detection front end receives the sampling enable pulse and uses it as the bias enable control input. It only turns on the internal photoelectric conversion circuit and bias circuit during the period when the sampling enable pulse is at an effective level, converting the captured instantaneous ambient illuminance into transient photovoltage. During non-sampling periods, all active circuits are completely turned off to completely eliminate static dark current loss.

[0160] Step S1-4: Signal latching and stable output: The signal latching output stage performs impedance isolation and peak hold processing on the transient photovoltage output by the photodetector front end. After the sampling enable pulse ends, it continues to output the hold level until the next effective period of the cycle arrives, and stably outputs the original photoelectric signal representing the change in ambient illuminance to the signal processing unit.

[0161] Step S2: Sliding window difference and dynamic feature calculation:

[0162] The core function of step S2 is to quantize and extract features from the original photoelectric signal. Based on the sliding time window difference algorithm, it tracks the dynamic reference value of ambient light in real time, decouples the calculation of the two core features of light intensity change gradient and reference deviation, and provides standardized input for subsequent wake-up verification. The detailed steps are as follows:

[0163] Step S2-1: Cycle-by-cycle analog-to-digital conversion: The analog-to-digital conversion stage is cascaded with the ambient light sensing unit. Under the effective edge triggering of the system sampling enable pulse, cycle-by-cycle quantization is performed to convert the original analog photoelectric signal into a discrete digital light intensity sequence. After quantization is completed, the internal comparator and the digital-to-analog conversion circuit are immediately turned off to control the power consumption of a single quantization at the nanojoule level.

[0164] Step S2-2: Sliding window data caching: The sliding data caching array receives discrete digital light intensity sequences and performs sliding overlay shift storage according to a preset window depth. Each time a new period of data is written, the historical data of the earliest period is automatically eliminated to form the current sliding window light intensity data frame. The preset window depth can be configured according to the application scenario to balance the smoothness and response speed of dynamic benchmark tracking.

[0165] Step S2-3: Real-time dynamic benchmark update: The dynamic benchmark tracker reads the current sliding window light intensity data frame, performs point-by-point difference operation on adjacent period data within the frame to obtain the window difference sequence; performs abrupt extreme value removal and low-pass smoothing filtering on the window difference sequence to separate the steady-state difference benchmark that characterizes the slow evolution trend of ambient light; and updates and generates the real-time ambient light dynamic benchmark value through attenuation weighted fusion operation.

[0166] Step S2-4: Multi-dimensional feature parameter calculation: The gradient and deviation calculation module receives the window-in-difference sequence and the real-time ambient light dynamic reference value, identifies consecutive valid difference segments with the same sign in the window-in-difference sequence, accumulates and normalizes the difference amplitude within the segment to obtain the light intensity change gradient, which characterizes the instantaneous rate of change of light intensity; at the same time, it performs a difference comparison operation between the latest periodic discrete digital light intensity value and the real-time ambient light dynamic reference value to obtain the reference deviation.

[0167] Step S2-5: Cross-clock domain synchronous output: The feature synchronous output interface receives the gradient of light intensity change and the reference deviation, performs two-level synchronous latching and data frame encapsulation under the reference clock domain of the wake-up control unit, generates a standardized multi-dimensional light event feature vector, and synchronously outputs it to the coarse screening comparator and fine verification state machine of the wake-up control unit.

[0168] Step S3: Subthreshold Hysteresis Coarse Screening and Primary Triggering:

[0169] The core function of step S3 is to quickly filter out most meaningless small-amplitude ambient light interference through a nanoampere-level low-power analog comparator circuit, and only output a primary trigger pulse when a suspected wake-up light event is detected, thereby activating the subsequent high-power fine verification process and achieving an initial balance between standby power consumption and wake-up response speed. The detailed steps are as follows:

[0170] Step S3-1: Continuous gradient real-time comparison: The coarse screening comparator continuously operates in nanoampere-level low-power standby mode, continuously receiving the light intensity change gradient output by the signal processing unit; through the built-in subthreshold hysteresis comparison circuit, the light intensity change gradient is compared with the first-level hysteresis threshold in real time; the first-level hysteresis threshold has temperature compensation characteristics, maintaining stable trigger sensitivity over a wide temperature range.

[0171] Step S3-2: Anti-interference dwell time verification: When the light intensity change gradient crosses the trigger upper limit of the first-level hysteresis threshold, start the anti-interference dwell timer; if the light intensity change gradient remains above the trigger upper limit within the preset dwell time, it is determined to be a suspected wake-up event; if the gradient falls back to below the trigger upper limit within the dwell time, it is determined to be random interference, the timer is reset and monitoring continues.

[0172] Step S3-3: Primary trigger pulse output: After the anti-interference dwell test passes, the coarse screening comparator generates a primary trigger pulse with level transition, which is processed by the pulse shaping stage and output to the fine verification state machine; at the same time, it sends a coarse screening trigger phase switching signal to the power management module, requesting an increase in the power supply voltage and operation clock frequency of the signal processing unit;

[0173] Step S4: Multidimensional feature verification and confidence level determination:

[0174] The core function of step S4 is to accurately distinguish between valid wake-up light events and complex environmental interference through multi-dimensional light event feature matching and adaptive weighted verification, and output the final wake-up enable signal only when the wake-up confidence condition is met, thereby controlling the system's false trigger rate to an extremely low level. The detailed steps are as follows:

[0175] Step S4-1: Fine verification state activation: After the fine verification state machine captures the primary trigger pulse, it immediately switches from the off state to the feature extraction state and opens the preset verification time window; at the same time, it sends a fine verification phase state switching signal to the power management module, requests to increase its own power supply rail voltage to the nominal value of the linear region, and enables the high-speed operation clock branch;

[0176] Step S4-2: Multidimensional feature preprocessing: Within the verification time window, the fine verification state machine continuously collects three feature parameters: baseline deviation, light intensity change gradient, and signal duration; baseline drift compensation is performed on the baseline deviation, trend smoothing filtering is performed on the light intensity change gradient, and effective pulse width accumulation is performed on the signal duration, outputting a denoised and normalized multidimensional optical event feature parameter set.

[0177] Step S4-3: Standardized feature vector construction: The feature splicing and encoding module receives the multidimensional optical event feature parameter set, performs data alignment and quantization encapsulation on the three feature parameters according to the preset spatiotemporal mapping order, converts them into a sixteen-bit encoding sequence with uniform dimensions, and constructs a standardized multidimensional optical event feature vector.

[0178] Step S4-4: Adaptive weighted matching calculation: The adaptive weighted matching model reads the multi-dimensional light event feature vector, dynamically updates the weighting coefficients of each feature dimension based on the recent ambient light noise baseline statistics and historical false trigger frequency records; performs similarity mapping calculation between the weighted feature vector and the pre-set standard wake-up light mode feature library, and outputs a matching confidence score that represents the legality of the light event;

[0179] Step S4-5: Confidence Verification and Wake-up Output: The confidence verification and output logic compares the matching confidence score with the second-level dynamic confidence threshold step by step. If the matching confidence score is better than the second-level dynamic confidence threshold within a continuous preset verification period, it is determined to be a valid wake-up event. A final wake-up enable signal with debouncing and anti-re-triggering characteristics is generated and sent to the power management module. If the score does not meet the conditions, it is determined to be an interference event. All feature caches are cleared, the fine verification state machine is forced to return to the shutdown state, and the system is restored to the nanoampere-level low-power standby state.

[0180] Step S5: Hierarchical power-on timing control and context recovery:

[0181] The core function of step S5 is to gradually restore the power supply and clock of each module of the system according to the preset safety sequence, quickly and accurately restore the operating context of the system before hibernation, ensure that the system smoothly switches from deep hibernation to full-function operation, and avoid system anomalies caused by power surges and timing conflicts; the detailed steps are as follows:

[0182] Step S5-1: Simulated front-end hierarchical power-on: After receiving the final wake-up enable signal, the power management module triggers the hierarchical power-on sequence control logic; firstly, it generates the simulated front-end power supply rail enable signal and injects bias current into the simulated front-end circuit according to the preset gradual ramp rate; after the simulated front-end power rail voltage reaches the first locking threshold, it outputs the simulated front-end ready status flag.

[0183] Step S5-2: Digital kernel and clock system startup: After the power management module captures the analog front-end ready status flag, it releases the subthreshold current limiting state of the digital kernel power supply rail and turns on the peripheral bus power supply rail; at the same time, it injects a reference oscillation signal into the main clock tree of the electronic timing master control module. The main clock tree performs phase locking and frequency reconstruction operations based on the reference oscillation signal, generates a full-speed running clock domain and outputs a clock tree synchronization completion signal.

[0184] Step S5-3: System Context Reload and Verification: After receiving the clock tree synchronization completion signal, the electronic timing master control module triggers a non-volatile memory area read instruction to read the key configuration register array saved in the snapshot before hibernation into the volatile configuration area of ​​the digital kernel; parity check and logical boundary check are performed on the reloaded register array through the built-in state machine, and a system context recovery completion flag is generated after the verification is passed;

[0185] Step S5-4: Clock Synchronization and Temperature Drift Compensation: After the system context is restored, the accumulated sleep timestamps of the real-time clock counter are read, and temperature compensation calculations are performed in combination with the current ambient temperature to obtain the accurate sleep duration; the compensated timestamps are phase-aligned with the full-speed running clock domain to complete system clock synchronization and ensure the continuity and accuracy of timing.

[0186] Step S5-5: Timing Task Queue Scheduling Startup: The electronic timing main control module parses the timing task queue to be executed, loads parameters into the timing task queue scheduling engine according to task priority and time slice round-robin strategy, and outputs task queue activation command; the system officially enters full-function operation state, executing various timing tasks and user interaction operations;

[0187] Step S6: Load Awareness and Full-Cycle Energy Routing

[0188] The core function of step S6 is to dynamically adjust the power supply voltage and clock frequency based on the real-time computing load and task scheduling pressure during the full-function operation of the system, thereby achieving on-demand energy allocation and maximizing the system's overall energy efficiency ratio while ensuring the real-time performance of tasks. The detailed steps are as follows:

[0189] Step S6-1: Full load power supply mode switching: According to the task queue activation command, the power management module switches the voltage level and working clock frequency of each power supply rail from low power intermittent routing mode to full load performance routing mode; at the same time, it starts the energy efficiency feedback control loop to prepare for real-time load monitoring and energy efficiency adjustment.

[0190] Step S6-2: Real-time system load acquisition: The energy efficiency feedback control loop continuously acquires the real-time computing load characteristics of the digital kernel and the scheduling pressure value of the timed task queue; the computing load characteristics include CPU utilization, instruction execution rate, etc., and the scheduling pressure value includes the number of tasks to be executed, task priority distribution, etc.

[0191] Step S6-3: System energy efficiency inflection point determination: Calculate the current system energy efficiency ratio based on the collected real-time load data and system power consumption data; compare the calculated energy efficiency ratio with the preset energy efficiency inflection point curve to determine whether the current system operating state is in the optimal energy efficiency range.

[0192] Step S6-4: Dynamic energy efficiency adjustment: When the comparison result indicates that the system load is below the energy efficiency inflection point, the multi-rail voltage regulation array automatically reduces the supply voltage, the global clock gating network reduces the operating clock frequency, and cuts off the power supply rails of redundant peripherals; when the comparison result indicates that the system load crosses the performance inflection point, the full voltage and full clock configuration is restored in real time to ensure the real-time performance of the task.

[0193] Step S6-5: Sleep Return Control: When all timing tasks are completed and the system idle time reaches the preset threshold, the electronic timing master control module triggers the sleep process; the non-volatile memory management unit writes the current system key state into the non-volatile memory area and completes the context snapshot saving; the power management module sequentially cuts off the power supply to the peripheral bus, digital core and analog front end, and the system returns to the nanoampere-level low-power standby state of the intermittent sampling phase, waiting for the next wake-up request.

[0194] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A low-power electronic timer wake-up system based on ambient light sensing, characterized in that: The wake-up system is configured as a two-level asymmetric verification and power adaptive routing architecture based on the dynamic characteristics of ambient light, including an ambient light sensing unit, a signal processing unit, a wake-up control unit, an electronic timing main control module, and a power management module. The ambient light sensing unit operates in an intermittent sampling mode with a controllable duty cycle, and is used to output raw photoelectric signals characterizing changes in ambient illuminance. The signal processing unit is cascaded with the ambient light sensing unit to perform analog-to-digital conversion on the original photoelectric signal and to track the dynamic reference value of ambient light in real time based on the sliding time window differential algorithm, and to calculate the gradient of light intensity change and the deviation from the reference. The wake-up control unit is connected to the signal processing unit and has a built-in coarse screening comparator and a fine verification state machine. The coarse screening comparator continuously operates in a nanoampere-level low-power standby state, which is used to compare the light intensity change gradient with the first-level hysteresis threshold and output the primary trigger pulse. The fine verification state machine is activated only after capturing the primary trigger pulse, extracts the reference deviation, light intensity change gradient and signal duration to construct a multi-dimensional light event feature vector, performs validity verification through a preset adaptive weighted matching model, and outputs the final wake-up enable signal only when the verification result meets the wake-up confidence condition. The electronic timing master control module is connected to the wake-up control unit and the power management module. During deep sleep, the power supply to the master clock tree and digital logic is cut off, and only the real-time clock counter is maintained. After receiving the final wake-up enable signal, the power management module restores the power supply to the analog front end, digital core and peripheral bus in sequence according to the preset power-on sequence. After the electronic timing master control module completes clock synchronization, register reloading and timing task queue scheduling, it enters the full-function running state. The power management module is coupled to the power rails of the ambient light sensing unit, signal processing unit, wake-up control unit, and electronic timing main control module respectively. Based on the inter-level state switching signal of the wake-up control unit, the power supply voltage level and working clock frequency of each unit are dynamically configured to realize on-demand energy routing and subthreshold power consumption control throughout the entire process from intermittent sampling and feature verification to main control wake-up.

2. The low-power electronic timer wake-up system based on ambient light sensing according to claim 1, characterized in that: The ambient light sensing unit includes a low-power oscillator, a duty cycle dynamic configuration circuit, a photoelectric detection front-end, and a signal latch output stage; the specific implementation process of the ambient light sensing unit operating in a duty cycle-controllable intermittent sampling mode is as follows: The low-power oscillator generates a reference sampling clock signal and transmits it to the duty cycle dynamic configuration circuit. The duty cycle dynamic configuration circuit receives the reference sampling clock signal and, in conjunction with the current power supply rail voltage margin command issued by the power management module and the historical average value of the reference deviation output by the signal processing unit in the previous cycle, performs pulse width modulation processing on the reference sampling clock signal and outputs a sampling enable pulse with adjustable duty cycle. The photoelectric detection front end receives the sampling enable pulse and uses it as its bias enable control input. It only turns on the internal photoelectric conversion circuit during the period when the sampling enable pulse is at an effective level, converting the captured instantaneous ambient illuminance into transient photovoltage. The signal latching output stage performs impedance isolation and peak hold processing on transient photovoltages to generate a corresponding hold level. After the sampling enable pulse ends, it continues to output the hold level until the effective period of the next sampling enable pulse arrives, thereby stabilizing the output of the original photoelectric signal characterizing changes in ambient illuminance.

3. The low-power electronic timer wake-up system based on ambient light sensing according to claim 1, characterized in that: The signal processing unit includes an analog-to-digital conversion stage, a sliding data buffer array, a dynamic reference tracker, a gradient and deviation calculation module, and a feature synchronization output interface. The specific implementation process of performing analog-to-digital conversion on the original photoelectric signal and, based on a sliding time window difference algorithm, tracking the dynamic reference value of ambient light in real time, and calculating the gradient of light intensity changes and the reference deviation is as follows: The analog-to-digital conversion stage is cascaded with the ambient light sensing unit to receive the original photoelectric signal and perform cycle-by-cycle quantization processing under the effective edge triggering of the system sampling enable pulse to generate a discrete digital light intensity sequence. The sliding data cache array is cascaded with the analog-to-digital converter stage, receives discrete digital light intensity sequences and performs sliding overlay shift storage according to a preset window depth, and automatically eliminates the earliest period historical data each time a new period data is written to form the current sliding window light intensity data frame. The dynamic reference tracker is cascaded with the sliding data buffer array, receives the current sliding window light intensity data frame, performs point-by-point difference operation on adjacent period data within the frame to obtain the window difference sequence, performs abrupt extreme value removal and low-pass smoothing filtering on the window difference sequence to separate transient interference components, extracts the steady-state difference reference characterizing the slow evolution trend of ambient light, and performs attenuation weighted fusion operation with the historical reference value output in the previous period to update and generate the real-time ambient light dynamic reference value; The gradient and deviation calculation module is cascaded with the dynamic reference tracker. It receives the window difference sequence and the real-time ambient light dynamic reference value. It performs amplitude accumulation and dimension normalization processing on the consecutive valid difference segments with the same sign in the window difference sequence, and outputs the light intensity change gradient that represents the instantaneous rate of change of light intensity. At the same time, it performs a difference comparison operation between the latest periodic discrete digital light intensity value and the real-time ambient light dynamic reference value to obtain the reference deviation. The feature synchronization output interface is cascaded with the gradient and deviation calculation module, receives the light intensity change gradient and the reference deviation, performs cross-clock domain synchronous latching and data frame encapsulation under the reference clock domain of the wake-up control unit, and synchronously outputs the encapsulated multidimensional light event feature vector to the coarse screening comparator and the fine verification state machine.

4. The low-power electronic timer wake-up system based on ambient light sensing according to claim 1, characterized in that: The wake-up control unit integrates a coarse-screen comparator, a fine-verification state machine, a feature splicing and encoding module, an adaptive weighted matching model, and confidence verification and output logic. The coarse-screen comparator continuously operates in a nanoampere-level low-power standby state, used to compare the light intensity change gradient with the first-level hysteresis threshold and output a primary trigger pulse. The fine-verification state machine is activated only after capturing the primary trigger pulse, extracting the reference deviation, light intensity change gradient, and signal duration to construct a multi-dimensional light event feature vector, and performing validity verification through a preset adaptive weighted matching model. It outputs the final wake-up enable signal only when the verification result meets the wake-up confidence condition. Specifically, it includes: The coarse screening comparator continuously receives the light intensity change gradient in the nanoampere-level low-power standby state. It compares the light intensity change gradient with the first-level hysteresis threshold in real time through the built-in subthreshold hysteresis comparison circuit. When the light intensity change gradient crosses the trigger upper limit of the first-level hysteresis threshold and the duration meets the preset anti-interference dwell condition, it generates a primary trigger pulse with level jump and outputs it through the pulse shaping stage. After capturing the primary trigger pulse, the fine verification state machine switches from the off state to the feature extraction state, opens a preset verification time window, and continuously collects the reference deviation, light intensity change gradient and signal duration output by the signal processing unit within the verification time window. It performs baseline drift compensation on the reference deviation, trend smoothing filtering on the light intensity change gradient, and effective pulse width accumulation on the signal duration, and outputs a denoised and normalized multidimensional optical event feature parameter set. The feature splicing and encoding module receives a multidimensional optical event feature parameter set, performs data alignment and quantization encapsulation on the multidimensional optical event feature parameter set according to a preset spatiotemporal mapping order, and constructs a multidimensional optical event feature vector. The adaptive weighted matching model receives a multi-dimensional light event feature vector, dynamically updates the weighting coefficients of each feature dimension based on recent ambient light noise baseline statistics and historical false trigger frequency records, performs similarity mapping calculation between the weighted multi-dimensional light event feature vector and a pre-set standard wake-up light mode feature library, and outputs a matching confidence score characterizing the legality of the light event. The confidence verification and output logic receives the matching confidence score and compares it step by step with the second-level dynamic confidence threshold. When the matching confidence score is better than the second-level dynamic confidence threshold for a continuous preset verification period, the verification result is determined to meet the wake-up confidence condition. A final wake-up enable signal with de-jitter and anti-re-trigger characteristics is generated and sent to the power management module. If the matching confidence score does not meet the wake-up confidence condition, the fine verification state machine clears the feature cache and forces a return to the shutdown state to maintain the static current level of the nanoampere-level low-power standby state.

5. The low-power electronic timer wake-up system based on ambient light sensing according to claim 1, characterized in that: During deep sleep, the electronic timing master control module cuts off the power supply to the main clock tree and digital logic, maintaining only the real-time clock counter. Upon receiving the final wake-up enable signal, the power management module restores power to the analog front-end, digital core, and peripheral bus sequentially according to a preset power-on sequence. After completing clock synchronization, register reloading, and timing task queue scheduling, the electronic timing master control module enters a full-function operating state. Specifically, this includes: After receiving the final wake-up enable signal, the power management module triggers the hierarchical power-on sequence control logic. First, it generates an enable signal for the analog front-end power supply rail, injects bias current into the analog front-end circuit at a preset gradual ramp rate, and outputs an analog front-end ready status flag after the analog front-end power supply rail voltage reaches the first locking threshold. After capturing the analog front-end ready status flag, the power management module releases the subthreshold current limiting state of the digital core power supply rail and turns on the peripheral bus power supply rail. At the same time, it injects a reference oscillation signal into the main clock tree of the electronic timing master control module. The main clock tree performs phase locking and frequency reconstruction operations based on the reference oscillation signal to generate a full-speed running clock domain and outputs a clock tree synchronization completion signal. After receiving the clock tree synchronization completion signal, the electronic timing master control module triggers a non-volatile memory area read instruction to reload the key configuration register array saved in the snapshot before hibernation to the volatile configuration area of ​​the digital kernel. The built-in state machine performs parity check and logical boundary check on the reloaded register array. After the check passes, a system context recovery completion flag is generated. After obtaining the system context recovery completion flag, the electronic timing master control module performs phase alignment and temperature drift compensation calculations on the sleep timestamp accumulated by the real-time clock counter and the full-speed running clock domain to complete clock synchronization. It also parses the timing task queue to be executed according to the overloaded key configuration register array, loads parameters into the timing task queue scheduling engine according to task priority and time slice round-robin strategy, and outputs the task queue activation instruction. After responding to the task queue activation command, the electronic timing master control module officially enters the full-function operation state. At the same time, based on the task queue activation command, the power management module switches the voltage level and working clock frequency of each power supply rail from the low-power intermittent routing mode to the full-load performance routing mode, and continuously collects the real-time computing power load characteristics of the digital kernel, dynamically adjusts the power supply rail output parameters, and maintains the optimal energy efficiency under the full-function operation state.

6. The low-power electronic timer wake-up system based on ambient light sensing according to claim 1, characterized in that: The power management module is coupled to the power rails of the ambient light sensing unit, signal processing unit, wake-up control unit, and electronic timing main control module, respectively. Based on the inter-stage state switching signals of the wake-up control unit, it dynamically configures the power supply voltage level and operating clock frequency of each unit, achieving on-demand energy routing and subthreshold power consumption control throughout the entire process from intermittent sampling and feature verification to main control wake-up; specifically including: The power management module integrates a phase state interpreter, a multi-track voltage regulation array, a global clock gating network, and an energy efficiency feedback control loop; The phase state interpreter continuously monitors the inter-stage state switching signal output by the wake-up control unit, and parses it into four types of phase state identifiers: intermittent sampling phase, coarse screening trigger phase, fine verification phase, and main control wake-up phase. Based on the phase state identifiers, it generates corresponding power rail enable command sequences and clock frequency configuration words, and sends them to the multi-rail voltage regulation array and global clock gating network. During the intermittent sampling phase, the multi-rail voltage regulation array receives the power supply rail enable command sequence, clamps the power supply rail voltage of the ambient light sensing unit and the signal processing unit to the subthreshold lower limit range, and the global clock gating network performs gate shutdown on the peripheral bus and digital logic during non-sampling periods according to the clock frequency configuration word, maintaining only the reference sampling clock and the minimal pulse drive of the sliding data buffer array, and outputting the power supply and distribution basic environment in a nanowatt-level static leakage current suppression state; When the phase interpreter resolves the coarse-screened trigger phase identifier based on the primary trigger pulse, the multi-rail voltage regulation array responds to the power supply rail enable command sequence, raises the analog front-end power supply rail of the signal processing unit to the first working threshold along the preset slope, and simultaneously releases the subthreshold current limiting state of the dynamic reference tracker. The global clock gating network enables the local clock domain of the gradient and deviation calculation module according to the clock frequency configuration word to match the real-time computing bandwidth requirements of the light intensity change gradient, and outputs a medium power supply and distribution state that supports dynamic reference separation and gradient calculation. When the phase interpreter parses the instruction for extracting multidimensional optical event feature vectors to the fine verification phase identifier, the multi-track voltage regulation array further increases the power supply rail voltage of the wake-up control unit to the nominal value of the linear region, and allocates independent high-speed clock branches to the feature splicing encoding module and the adaptive weighted matching model. The global clock gating network synchronously opens the synchronous sampling clock of the verification time window to ensure the timing alignment of the multidimensional optical event feature vectors and the glitch-free transmission across clock domains. The output supports the high dynamic power supply and distribution status of similarity mapping and confidence verification. When the phase state decoder captures the final wake-up enable signal and resolves the master control wake-up phase identifier, the multi-rail voltage regulation array performs a step-by-step power-up operation according to the priority sequence of analog front-end, digital core, and peripheral bus. After the voltage of each power supply rail reaches the locking threshold, it outputs an inter-rail synchronization ready pulse. After the global clock gating network receives the inter-rail synchronization ready pulse, it releases the gating lock of the master clock tree, injects a reference oscillation signal and starts the phase-locked loop, gradually multiplies the working clock frequency from the low-frequency wake-up state to the full-speed running state, and outputs the full-load power supply and distribution initialization state after completing system context recovery and task queue scheduling. After the electronic timing main control module enters full-function operation mode, the energy efficiency feedback control loop continuously collects the real-time computing load characteristics of the digital kernel and the scheduling pressure value of the timing task queue. The collected results are compared with the preset energy efficiency inflection point curve. When the comparison result indicates that the load is below the inflection point, the multi-track voltage regulation array automatically reduces the frequency and voltage and cuts off the power supply rails of redundant peripherals. When the comparison result indicates that the load crosses the performance inflection point, the full voltage and full clock configuration is restored in real time. Based on the load characteristic comparison result, the output parameters of the multi-track voltage regulation array and the frequency division ratio of the global clock gating network are corrected in real time to maintain energy on-demand routing and subthreshold power consumption control throughout the process.

7. A low-power electronic timer wake-up method based on ambient light sensing, the method being implemented by the low-power electronic timer wake-up system based on ambient light sensing according to any one of claims 1-6, characterized in that: The method includes the following steps: S1. Duty Cycle Dynamic Configuration and Intermittent Sampling: A low-power oscillator generates a reference sampling clock signal. The duty cycle dynamic configuration circuit combines the current power supply rail voltage margin command with the historical average of the reference deviation in the previous cycle to perform pulse width modulation processing on the reference sampling clock signal, and outputs a sampling enable pulse with an adjustable duty cycle. The photoelectric detection front end uses the sampling enable pulse as the bias enable control input, and only conducts the internal photoelectric conversion circuit during the effective level to convert the captured instantaneous ambient illuminance into transient photovoltage. The signal latch output stage performs impedance isolation and peak hold processing on the transient photovoltage to stably output the original photoelectric signal. S2. Sliding Window Differential and Dynamic Feature Calculation: The original photoelectric signal is received. The analog-to-digital converter performs cycle-by-cycle quantization on the original photoelectric signal under the effective edge triggering of the system sampling enable pulse, generating a discrete digital light intensity sequence. The sliding data buffer array performs sliding-over-shift storage on the discrete digital light intensity sequence to form the current sliding window light intensity data frame. The dynamic reference tracker performs point-by-point differential and low-pass smoothing filtering on the current sliding window light intensity data frame to extract the steady-state differential reference, and performs attenuation-weighted fusion with historical reference values ​​to update the real-time ambient light dynamic reference value. The gradient and deviation calculation module receives the real-time ambient light dynamic reference value and the window differential sequence. It performs amplitude accumulation and dimension normalization on consecutive valid differential segments with the same sign to obtain the light intensity change gradient. Simultaneously, it performs a difference comparison operation between the latest cycle discrete digital light intensity value and the real-time ambient light dynamic reference value to obtain the reference deviation, and outputs the light intensity change gradient and the reference deviation synchronously. S3, Subthreshold Hysteresis Coarse Screening and Primary Trigger: Receives the light intensity change gradient. In the nanoampere-level low-power standby state, the coarse screening comparator compares the light intensity change gradient with the first-level hysteresis threshold in real time through the subthreshold hysteresis comparison circuit. When the light intensity change gradient crosses the trigger upper limit of the first-level hysteresis threshold and meets the preset anti-interference dwell condition, a level-changing primary trigger pulse is generated and output through the pulse shaping stage. S4. Multidimensional Feature Verification and Confidence Determination: The initial trigger pulse is captured, and the fine-tuning verification state machine switches from the off state to the feature extraction state and opens the verification time window. The baseline deviation, light intensity gradient, and signal duration are continuously collected. After baseline drift compensation, trend smoothing filtering, and effective pulse width accumulation, a multidimensional optical event feature parameter set is output. The feature splicing and encoding module performs data alignment and quantization encapsulation on the multidimensional optical event feature parameter set to construct a multidimensional optical event feature vector. The adaptive weighted matching model dynamically updates the weighting coefficients based on recent ambient light noise baseline statistics and historical false trigger frequency records, performing similarity mapping calculations on the multidimensional optical event feature vector to output a matching confidence score. The confidence verification and output logic compares the matching confidence score with the second-level dynamic confidence threshold step by step. When the matching confidence score is better than the second-level dynamic confidence threshold within a continuous preset verification period, the wake-up confidence condition is met, and the final wake-up enable signal with de-jittering and anti-re-triggering characteristics is output. S5, Hierarchical Power-On Sequence Control and Context Recovery: In response to the final wake-up enable signal, the power management module triggers the hierarchical power-on sequence control logic, sequentially recovering the analog front-end power rail, digital core power rail, and peripheral bus power rail according to the preset gradual ramp rate. After the voltage of each power rail reaches the locking threshold, a reference oscillation signal is injected into the main clock tree to complete phase locking and frequency reconstruction. After receiving the clock tree synchronization completion signal, the electronic timing main control module reads the key configuration register array saved in the snapshot before hibernation from the non-volatile memory area and performs parity check and logic boundary check. After the check passes, a system context recovery completion flag is generated. The hibernation timestamp accumulated by the real-time clock counter is phase aligned and temperature drift compensated with the full-speed running clock domain to complete clock synchronization. The timing task queue to be executed is parsed and the scheduling parameters are loaded. The task queue activation instruction is output. S6. Load Awareness and Full-Cycle Energy Routing: Based on the task queue activation command, the power management module switches the voltage level of each power rail and the working clock frequency from the low-power intermittent routing mode to the full-load performance routing mode. The energy efficiency feedback control loop continuously collects the real-time computing power load characteristics of the digital kernel and the scheduling pressure value of the timed task queue. The collected results are compared and calculated with the preset energy efficiency inflection point curve. When the load is below the inflection point, the frequency and voltage are automatically reduced and redundant peripheral power rails are cut off. When the load crosses the performance inflection point, the full-voltage and full-clock configuration is restored immediately. By real-time correction of the output parameters of the multi-rail voltage regulation array and the frequency division ratio of the global clock gating network, energy on-demand routing and sub-threshold power consumption control are realized throughout the entire process from intermittent sampling, feature verification to main control wake-up.

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