Inverter topology

Abstract

The application discloses an inverter topology structure, which has three-phase bridge arms between a positive direct current connection end and a negative direct current connection end, each of the three-phase bridge arms comprises two switch tubes connected in series, a common connection point of A-phase switch tubes, a common connection point of B-phase switch tubes and a common connection point of C-phase switch tubes form an alternating current output end; the first alternating current output end and a midpoint connection end have a seventh switch tube and an eighth switch tube; a ninth switch tube is connected between a positive direct current input end and the positive direct current connection end, and a tenth switch tube is connected between a negative direct current input end and the negative direct current connection end; a first direct current bus capacitor is connected between the positive direct current input end and the midpoint connection end, and a second direct current bus capacitor is connected between the negative direct current input end and the midpoint connection end. The three-phase ten-switch inverter topology structure formed by the ten switch tubes can reduce the high-frequency common-mode voltage and the high-frequency leakage current, and the number of switch tubes is less than that of a three-level topology.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to an inverter topology and its control method. Background Technology

[0002] Three-phase voltage source inverters have been widely used in frequency conversion drives and grid-connected photovoltaic power generation applications, among which the six-switch two-level inverter topology is the most widely used.

[0003] However, this transformerless topology lacks an electrical isolation layer. When modulation strategies such as space vector modulation or sinusoidal pulse width modulation are applied to this topology, the high-frequency switching action of power devices forms a common-mode loop through parasitic capacitance to ground of photovoltaic modules, resulting in high-frequency common-mode voltage and excessive leakage current. This not only violates the IEC 62109-2 safety standard but also reduces the grid-connected power quality.

[0004] Current technological improvements often employ a segmented approach: at the hardware level, common-mode voltage is suppressed through a three-level topology, or passive filtering is achieved by adding a common-mode inductor; at the control level, repetitive control or proportional resonant compensators are used to optimize harmonics. However, these methods suffer from high topology complexity, slow dynamic response, and efficiency losses, failing to achieve a synergistic optimization of safety and economy. Therefore, a novel topology is urgently needed that combines high-frequency common-mode voltage suppression, high stability, and fast response speed. Utility Model Content

[0005] This application provides an inverter topology and its control method to provide a novel topology that combines high-frequency common-mode voltage suppression, high stability, and fast response speed.

[0006] This application provides an inverter topology, including a positive DC input terminal, a positive DC connection terminal, a negative DC input terminal, a negative DC connection terminal, and a midpoint connection terminal;

[0007] The positive DC connection terminal and the negative DC connection terminal are connected in parallel with an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm. The A-phase bridge arm includes a first switch and a second switch connected in series. The B-phase bridge arm includes a third switch and a fourth switch connected in series. The C-phase bridge arm includes a fifth switch and a sixth switch connected in series. The common connection point of the first switch and the second switch forms a first AC output terminal. The common connection point of the third switch and the fourth switch forms a second AC output terminal. The common connection point of the fifth switch and the sixth switch forms a third AC output terminal.

[0008] A seventh switch and an eighth switch are connected in series between the first AC output terminal and the midpoint connection terminal; a ninth switch is connected between the positive DC input terminal and the positive DC connection terminal; and a tenth switch is connected between the negative DC input terminal and the negative DC connection terminal.

[0009] A first DC bus capacitor is connected between the positive DC input terminal and the midpoint connection terminal, and a second DC bus capacitor is connected between the negative DC input terminal and the midpoint connection terminal.

[0010] The inverter topology provided in this application is a three-phase ten-switch inverter topology composed of ten switching transistors. The number of switching transistors is less than that of a three-level topology, which can reduce high-frequency common-mode voltage and high-frequency leakage current. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the inverter topology provided in the embodiments of this application;

[0012] Figure 2 A schematic diagram of the inverter topology provided in the embodiments of this application in the first operating mode;

[0013] Figure 3 A schematic diagram of the inverter topology provided in the embodiments of this application in the second operating mode;

[0014] Figure 4 A schematic diagram of the inverter topology provided in the embodiments of this application in the third operating mode;

[0015] Figure 5 A schematic diagram of the inverter topology provided in the embodiments of this application in the fourth operating mode;

[0016] Figure 6 A schematic diagram of the inverter topology provided in the embodiments of this application in the fifth operating mode;

[0017] Figure 7 A schematic diagram of the inverter topology provided in the embodiments of this application in the sixth operating mode;

[0018] Figure 8 A schematic diagram of the inverter topology provided in the embodiments of this application in the seventh operating mode;

[0019] Figure 9 A schematic diagram of the inverter topology provided in the embodiments of this application in the eighth operating mode;

[0020] Figure 10 A schematic diagram of the inverter topology provided in the embodiments of this application in the ninth operating mode;

[0021] Figure 11 A schematic diagram of the inverter topology provided in the embodiments of this application in the tenth operating mode;

[0022] Figure 12 A schematic diagram of the inverter topology provided in the embodiments of this application in the eleventh operating mode;

[0023] Figure 13 A schematic diagram of the inverter topology provided in the embodiments of this application in the twelfth operating mode;

[0024] Figure 14 A schematic diagram of the space vectors corresponding to different operating modes of the inverter topology provided in the embodiments of this application;

[0025] Figure 15 This is a schematic diagram of another inverter topology provided in an embodiment of this application;

[0026] Figure 16 This is a schematic diagram of the control process of the BOOST converter in another inverter topology provided in this application embodiment;

[0027] Figure 17 This is a schematic diagram of the control process of the bidirectional converter in another inverter topology provided in this application embodiment.

[0028] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0029] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer and more understandable, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit the scope of this application.

[0030] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] like Figure 1 As shown, this application provides an inverter topology, including a positive DC input terminal A, a positive DC connection terminal B, a negative DC input terminal C, a negative DC connection terminal D, and a midpoint connection terminal O;

[0032] The positive DC connection terminal B and the negative DC input terminal C have parallel-connected A-phase bridge arms, B-phase bridge arms, and C-phase bridge arms. The A-phase bridge arm includes a first switch S1 and a second switch S2 connected in series. The B-phase bridge arm includes a third switch S3 and a fourth switch S4 connected in series. The C-phase bridge arm includes a fifth switch S5 and a sixth switch S6 connected in series. The common connection point of the first switch S1 and the second switch S2 forms the first AC output terminal V. A The common connection point of the third switch S3 and the fourth switch S4 forms the second AC output terminal V. B The common connection point of the fifth switch S5 and the sixth switch S6 forms the third AC output terminal V. C ;

[0033] First AC output terminal V A The seventh switch S7 and the eighth switch S8 are connected in series with the midpoint connection terminal O; the ninth switch S9 is connected between the positive DC input terminal A and the positive DC connection terminal B; and the tenth switch S10 is connected between the negative DC input terminal C and the negative DC connection terminal D.

[0034] A first DC bus capacitor C3 is connected between the positive DC input terminal A and the midpoint connection terminal O, and a second DC bus capacitor C4 is connected between the negative DC input terminal B and the midpoint connection terminal O.

[0035] The above three-phase ten-switch inverter topology, consisting of ten switching transistors, has fewer switching transistors than the three-level topology, which can reduce high-frequency common-mode voltage and high-frequency leakage current.

[0036] In some examples, any one of the first switching transistors S1 to the tenth switching transistors S10 includes any one of IGBT, IGCT, and MOSFET. In the figure, the first switching transistors S1 to the tenth switching transistors S10 are all IGBTs.

[0037] In some examples, the control terminal of any one of the first to tenth switching transistors S10 is used to receive a switching signal and operates in different operating modes under the action of the switching signal. Among them, the operating modes shown include 12 different operating modes. Figures 2-13 The diagram illustrates the on / off states of each switching transistor under different operating modes. Figure 14 The corresponding space vector is shown. Specifically:

[0038] Figure 2 In the operating mode shown, switches S1, S4, S6, S9, and S10 are turned on, while switches S2, S3, S5, S7, and S8 are turned off, corresponding to a space vector of 200.

[0039] Figure 3In the operating mode shown, switches S1, S4, S5, S9, and S10 are turned on, while switches S2, S3, S6, S7, and S8 are turned off, corresponding to a space vector of 202.

[0040] Figure 4 In the operating mode shown, switches S1, S3, S6, S9, and S10 are turned on, while switches S2, S4, S5, S7, and S8 are turned off, corresponding to a space vector of 220.

[0041] Figure 5 In the operating mode shown, switches S1, S3, and S5 are turned on, while switches S2, S4, S6, S7, S8, S9, and S10 are turned off, corresponding to a space vector of 222.

[0042] Figure 6 In the operating mode shown, switches S4, S6, S7, S8, S9, and S10 are turned on, while switches S1, S2, S3, and S5 are turned off, corresponding to a space vector of 100.

[0043] Figure 7 In the operating mode shown, switches S4, S5, S7, S8, S9, and S10 are turned on, while switches S1, S2, S3, and S6 are turned off, corresponding to a space vector of 102.

[0044] Figure 8 In the operating mode shown, switches S2, S4, and S6 are turned on, while switches S1, S3, S5, S7, S8, S9, and S10 are turned off, corresponding to a space vector of 000.

[0045] Figure 9 In the operating mode shown, switches S2, S4, S5, S9, and S10 are turned on, while switches S1, S3, S6, S7, and S8 are turned off, corresponding to space vector 002.

[0046] Figure 10 In the operating mode shown, switches S2, S3, S6, S9, and S10 are turned on, while switches S1, S4, S5, S7, and S8 are turned off, corresponding to a space vector of 020.

[0047] Figure 11 In the operating mode shown, switches S2, S3, S5, S9, and S10 are turned on, while switches S1, S4, S6, S7, and S8 are turned off, corresponding to a space vector of 022.

[0048] Figure 12 In the operating mode shown, switches S3, S6, S7, S8, S9, and S10 are turned on, while switches S1, S2, S4, and S5 are turned off, corresponding to a space vector of 120.

[0049] Figure 13In the operating mode shown, switches S3, S5, S7, S8, S9, and S10 are turned on, while switches S1, S2, S4, and S6 are turned off, corresponding to a space vector of 122.

[0050] In some examples, the inverter topology also includes a photovoltaic cell (shown as PV in the figure), with the positive DC input terminal A and the negative DC input terminal C connected to the photovoltaic cell.

[0051] Please refer to Figure 15 As shown, in some examples, the inverter topology also includes a third DC bus capacitor C2, one end of which is connected to the positive DC input terminal A, and the other end of which is connected to the negative DC input terminal C.

[0052] Please refer to Figure 15 As shown, in some examples, the inverter topology also includes a BOOST converter, through which the positive DC input terminal A and the negative DC input terminal C are connected to the photovoltaic cell.

[0053] Specifically, the BOOST converter consists of a capacitor C1, an inductor L1, a diode D1, and a switching transistor S11. The BOOST converter employs two control methods, such as... Figure 16 As shown, when the battery SOC is less than 100%, maximum power point tracking (MPPT) control is used to ensure that the maximum power can still be obtained from the photovoltaic cells under changing weather conditions. Excess power exceeding the load demand will be directed to the energy storage battery to charge it. When the battery SOC is 100%, constant DC bus voltage control is used, and the photovoltaic cells only provide the power required by the load to prevent the energy storage battery from being overcharged, which would lead to performance degradation and shortened lifespan.

[0054] Please refer to Figure 15 As shown, in some examples, the inverter topology further includes an energy storage battery and a first bidirectional converter, with the positive DC input terminal A and the negative DC input terminal C connected to the energy storage battery via the first bidirectional converter. The inverter topology also includes a supercapacitor and a second bidirectional converter, with the positive DC input terminal A and the negative DC input terminal C connected to the supercapacitor via the second bidirectional converter.

[0055] Specifically, the first bidirectional converter consists of inductor L3, switch S14, and switch S15. The second bidirectional converter consists of inductor L2, switch S12, and switch S13. The use of a hybrid energy storage unit combining supercapacitors and batteries improves system stability and dynamic response speed.

[0056] refer to Figure 17 As shown, when controlling the first bidirectional converter, the DC bus voltage setpoint V is first set.dc_ref With feedback value V dc The error is compared, and the total current required by the energy storage system is obtained through a PI controller. Then, the low-frequency component i of this current is extracted through a low-pass filter LPF. LF_ref Then, the charging and discharging speed of the energy storage battery is controlled by a rate limiter (shown in the figure), thereby obtaining the given value i of the energy storage battery current. bat_ref Finally, the energy storage battery current setpoint i is set. bat_ref With feedback value i bat The error obtained is compared and then passed through another PI controller and PWM waveform generation module to obtain the drive signals for switching transistors S14 and S15.

[0057] Supercapacitors are primarily used to mitigate transient peak energy surges caused by sudden load changes or weather variations, thus reducing the charging and discharging stress on energy storage batteries. When controlling the second bidirectional converter, the uncompensated power is divided by the supercapacitor voltage V. sc The corresponding supercapacitor current setpoint i is obtained. sc_ref Then, given value i sc_ref With feedback value i sc The error obtained is compared and then passed through another PI controller and PWM waveform generation module to obtain the drive signals for switching transistors S12 and S13.

[0058] In some examples, the inverter topology also includes a filter, and a first AC output terminal V A Second AC output terminal V B and the third AC output terminal V C The filter is connected to an AC voltage source (e.g., e in the figure). A e B e C (As shown) Connection. The filter can be Figure 1 The filter inductor in the middle can also be Figure 15 LCL filter in.

[0059] Please refer to this again. Figure 14 As shown in the table below, during the active vector V1 to V10 states, switches S9 and S10 are turned on to maintain normal system operation; during the zero vector V11 and V12 states, switches S9 and S10 are turned off to ensure isolation from the power grid, thereby eliminating common-mode voltage and leakage current during this period, and limiting the common-mode voltage to within a certain range throughout the entire switching cycle. and This significantly reduced the overall range of common-mode voltage variation and limited the common-mode voltage step change rate to within a certain range. This minimizes leakage current and reduces harmonic content in grid-connected current.

[0060]

[0061] The preferred embodiments of this application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of this application shall be within the scope of the claims.

Claims

1. An inverter topology, characterized in that, Includes positive DC input terminal, positive DC connection terminal, negative DC input terminal, negative DC connection terminal, and midpoint connection terminal; The positive DC connection terminal and the negative DC connection terminal are connected in parallel with an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm. The A-phase bridge arm includes a first switch and a second switch connected in series. The B-phase bridge arm includes a third switch and a fourth switch connected in series. The C-phase bridge arm includes a fifth switch and a sixth switch connected in series. The common connection point of the first switch and the second switch forms a first AC output terminal. The common connection point of the third switch and the fourth switch forms a second AC output terminal. The common connection point of the fifth switch and the sixth switch forms a third AC output terminal. A seventh switch and an eighth switch are connected in series between the first AC output terminal and the midpoint connection terminal; a ninth switch is connected between the positive DC input terminal and the positive DC connection terminal; and a tenth switch is connected between the negative DC input terminal and the negative DC connection terminal. A first DC bus capacitor is connected between the positive DC input terminal and the midpoint connection terminal, and a second DC bus capacitor is connected between the negative DC input terminal and the midpoint connection terminal.

2. The inverter topology according to claim 1, characterized in that, Any one of the first to the tenth switching transistors includes any one of IGBT, IGCT, and MOSFET.

3. The inverter topology according to claim 1, characterized in that, The control terminal of any one of the first to tenth switching transistors is used to receive a switching signal and operate in different working modes under the action of the switching signal.

4. The inverter topology according to claim 3, characterized in that, The working modes shown include 12 different working modes.

5. The inverter topology according to claim 1, characterized in that, The inverter topology also includes a photovoltaic cell, and the positive DC input terminal and the negative DC input terminal are connected to the photovoltaic cell.

6. The inverter topology according to claim 5, characterized in that, The inverter topology also includes a third DC bus capacitor, one end of which is connected to the positive DC input terminal, and the other end of which is connected to the negative DC input terminal.

7. The inverter topology according to claim 5, characterized in that, The inverter topology also includes a BOOST converter, through which the positive DC input terminal and the negative DC input terminal are connected to the photovoltaic cell.

8. The inverter topology according to claim 5, characterized in that, The inverter topology also includes an energy storage battery and a first bidirectional converter, with the positive DC input terminal and the negative DC input terminal connected to the energy storage battery through the first bidirectional converter.

9. The inverter topology according to claim 5, characterized in that, The inverter topology also includes a supercapacitor and a second bidirectional converter, with the positive DC input terminal and the negative DC input terminal connected to the supercapacitor via the second bidirectional converter.

10. The inverter topology according to claim 1, characterized in that, The inverter topology also includes a filter, and the first AC output terminal, the second AC output terminal, and the third AC output terminal are connected to an AC voltage source through the filter.

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