Display device and electronic device

Abstract

A display device and an electronic device are provided. The display device includes: a first electrode; a pixel defining layer on the first electrode; a light-emitting member on the first electrode and the pixel defining layer; a second electrode on the light-emitting member; an organic layer on the second electrode; a first reflective layer in the organic layer; and a second reflective layer disposed on the first reflective layer in the organic layer, wherein, in the thickness direction, the first reflective layer overlaps with the pixel defining layer, and the second reflective layer overlaps with the light-emitting member.

Description

Technical Field

[0001] This disclosure generally relates to display devices and electronic devices. More specifically, this disclosure relates to display devices capable of improving light emission efficiency. Background Technology

[0002] Recently, due to the increasing interest in display devices, research and development of display devices has continued. Utility Model Content

[0003] The purpose of this disclosure is to improve the light emission efficiency of display devices.

[0004] The embodiments disclosed herein are not limited to those mentioned above, and other technical objectives not mentioned may be clearly understood by those skilled in the art through the following description.

[0005] An embodiment provides a display device, including: a first electrode; a pixel defining layer disposed on the first electrode; a light-emitting member disposed on the first electrode and the pixel defining layer; a second electrode disposed on the light-emitting member; an organic layer disposed on the second electrode; a first reflective layer in the organic layer; and a second reflective layer disposed on the first reflective layer in the organic layer, wherein, in the thickness direction, the first reflective layer overlaps with the pixel defining layer, and the second reflective layer overlaps with the light-emitting member.

[0006] The planar area of ​​the first reflective layer can be larger than the planar area of ​​the second reflective layer.

[0007] The pixel defining layer may include an opening that overlaps with the first electrode in the thickness direction, and the second reflective layer may overlap with the opening in the thickness direction.

[0008] The first reflective layer may include a first opening.

[0009] The second reflective layer may include a second opening.

[0010] The planar dimensions of the first opening can be larger than the planar dimensions of the second opening.

[0011] The first and second reflective layers may include inclined surfaces.

[0012] The first and second reflective layers may include spherical surfaces.

[0013] The pixel-defining layer may include a separator, and the light-emitting components may be at least partially separated by the separator.

[0014] Another embodiment provides a display device, including: a first electrode; a pixel defining layer disposed on the first electrode; a light-emitting member disposed on the first electrode and the pixel defining layer; a second electrode disposed on the light-emitting member; a first organic layer disposed on the second electrode; a first reflective layer disposed on the first organic layer; a second organic layer disposed on the first reflective layer; and a second reflective layer disposed on the second organic layer, wherein, in the thickness direction, the first reflective layer overlaps with the pixel defining layer, and the second reflective layer overlaps with the light-emitting member.

[0015] The first organic layer may include a first inclined surface, and the first reflective layer may be disposed on the first inclined surface.

[0016] The second organic layer may include a second inclined surface, and the second reflective layer may be disposed on the second inclined surface.

[0017] The first reflective layer may include a first opening.

[0018] The first organic layer can be disposed in the first opening.

[0019] The second reflective layer may include a second opening.

[0020] The second organic layer can be disposed in the second opening.

[0021] The planar area of ​​the first reflective layer can be larger than the planar area of ​​the second reflective layer.

[0022] The display device may also include a third organic layer on the second reflective layer.

[0023] The first organic layer, the second organic layer, and / or the third organic layer may comprise the same material.

[0024] The first organic layer, the second organic layer, and / or the third organic layer may have different refractive indices.

[0025] According to embodiments of this disclosure, an electronic device may include a display device, which includes a light-emitting element disposed on a substrate. The light-emitting element includes: a first electrode; a pixel defining layer disposed on the first electrode; a light-emitting member disposed on the first electrode and the pixel defining layer; a second electrode disposed on the light-emitting member; an organic layer disposed on the second electrode; a first reflective layer in the organic layer; and a second reflective layer disposed on the first reflective layer in the organic layer. In the thickness direction, the first reflective layer may overlap with the pixel defining layer, and the second reflective layer may overlap with the light-emitting member.

[0026] The electronic device can be at least one of the following: smartwatch, mobile phone, smartphone, portable computer, tablet PC, watch phone, car display, smart glasses, portable multimedia player (PMP), navigation system, ultra-mobile computer (UMPC), head-mounted display (HMD) device, virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0027] Features of other embodiments are included in the detailed description and accompanying drawings.

[0028] According to the above embodiments, by using an organic layer and a reflective layer to form an optical layer, the manufacturing process can be simplified and the light emission efficiency can be improved.

[0029] The effects of the embodiments disclosed herein are not limited to those described above, and many more effects are included in this specification. Attached Figure Description

[0030] Figure 1 A schematic block diagram of a display device according to an embodiment is shown.

[0031] Figure 2 An embodiment is shown. Figure 1 A schematic block diagram of one of the sub-pixels.

[0032] Figure 3 An embodiment is shown. Figure 2 A schematic diagram of the equivalent circuit of a sub-pixel.

[0033] Figure 4 An embodiment is shown. Figure 1 A schematic top plan view of the display panel.

[0034] Figure 5 It shows Figure 4 An exploded schematic perspective view of a portion of the display panel.

[0035] Figure 6 An embodiment is shown. Figure 5 A schematic top plan view of one of the pixels.

[0036] Figures 7 to 11 It shows along Figure 6 A schematic cross-sectional view taken from line I-I'.

[0037] Figure 12 An embodiment is shown. Figure 7 An enlarged schematic diagram of the reflective layer.

[0038] Figure 13 An example of an embodiment along [the path] is shown. Figure 6A schematic cross-sectional view taken from line I-I'.

[0039] Figure 14 It shows Figure 13 An enlarged diagram of region "A".

[0040] Figure 15 The embodiment shown includes Figures 7 to 11 or Figure 13 A schematic cross-sectional view of a portion of the light-emitting structure in one of the first to third light-emitting elements.

[0041] Figure 16 An embodiment according to another embodiment is shown, including Figures 7 to 11 or Figure 13 A schematic cross-sectional view of a portion of the light-emitting structure in one of the first to third light-emitting elements.

[0042] Figure 17 An embodiment according to another embodiment is shown. Figure 5 A schematic top plan view of one of the pixels.

[0043] Figure 18 An embodiment according to another embodiment is shown. Figure 5 A schematic top plan view of one of the pixels.

[0044] Figure 19 A schematic block diagram of a display system according to an embodiment is shown.

[0045] Figure 20 It shows Figure 19 A schematic 3D diagram illustrating an application example of the display system.

[0046] Figure 21 It shows the wearable by the user Figure 20 An illustrative head-mounted display device.

[0047] Figures 22 to 28 A schematic cross-sectional view is shown of the process steps of a method for manufacturing a display device according to an embodiment. Detailed Implementation

[0048] In the following, exemplary embodiments of this disclosure will be described in detail with reference to the accompanying drawings. The following description is intended to provide only sufficient disclosure to enable understanding of the operation of this disclosure, and any other disclosure is omitted to avoid obscuring the scope of this disclosure. This disclosure may be implemented in various forms and is not limited to the embodiments set forth herein. The embodiments described herein are provided to provide a sufficient detail to describe the technical concept of this disclosure so that those skilled in the art can readily practice it.

[0049] Throughout this specification, when describing an element as "connected" to another element, this includes not only "direct connection" but also "indirect connection" with another device in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the scope of this disclosure. Throughout this specification, unless expressly stated otherwise, the word "comprising" and variations such as "including" or "containing" are to be understood as implying inclusion of the stated element but not excluding any other element. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although the terms “first,” “second,” etc., may be used herein to describe various constituent elements, these constituent elements should not be limited by these terms. These terms are used to distinguish one constituent element from another. Therefore, without departing from the teachings of this disclosure, the first constituent element discussed below may be referred to as the second constituent element.

[0051] For descriptive purposes, spatial relative terms such as “below,” “under,” “down,” “above,” and “up” may be used herein to describe the relationship between one element or feature and another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein are interpreted accordingly.

[0052] Various embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized implementations. Therefore, variations in the shape of the figures should be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the exemplary embodiments disclosed herein should not be construed as limited to the shapes of the specifically shown areas, but should include, for example, deviations in shape due to manufacturing processes. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shapes of areas of the device, nor are they intended to be limiting.

[0053] Figure 1 A schematic block diagram of a display device according to an embodiment is shown.

[0054] refer to Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0055] The display panel 110 may include sub-pixels SP. Sub-pixels SP can be electrically connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be electrically connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0056] Each subpixel SP can include at least one light-emitting element that generates light. Therefore, subpixels SP can each produce light of a specific color, such as red, green, blue, cyan, magenta, yellow, etc. Two or more subpixels SP can constitute a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a pixel PXL.

[0057] Gate driver 120 can be electrically connected to sub-pixels SP arranged in the row direction via first gate line GL1 to m-th gate line GLm. Gate driver 120 can output gate signals to first gate line GL1 to m-th gate line GLm in response to gate control signal GCS. Gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for timing-synchronizing gate signals with applied data signals, etc.

[0058] It may also provide first light emission control lines EL1 to m-th light emission control lines ELm electrically connected in the row direction to the sub-pixel SP. Gate driver 120 may include light emission control drivers that control the first light emission control lines EL1 to m-th light emission control lines ELm, and the light emission control drivers may operate under the control of controller 150.

[0059] The gate driver 120 may be disposed on one side of the display panel 110. However, the implementation is not limited to this. For example, the gate driver 120 may be divided into two or more physically and / or logically separate drivers, and the drivers may be disposed on one side of the display panel 110, with the other side of the display panel 110 opposite to that side. As described above, according to the implementation, the gate driver 120 may be disposed around the display panel 110 in various forms.

[0060] Data driver 130 can be electrically connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. Data control signal DCS may include source start pulse, source shift clock, source output enable signal, etc.

[0061] The data driver 130 can use voltage from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLm. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel 110.

[0062] Gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0063] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can generate multiple voltages and provide the generated voltages to the components of display device 100. For example, voltage generator 140 can generate multiple voltages by receiving an input voltage from outside display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0064] Voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS can be provided to sub-pixels SP. The first power voltage VDD can have a relatively high voltage level, and the second power voltage VSS can have a lower voltage level than the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external device of display device 100.

[0065] Voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to sub-pixel SP. For example, during sensing operation for sensing the electrical characteristics of the transistor and / or light-emitting element of sub-pixel SP, a predetermined reference voltage can be applied to the first data line DL1 to the nth data line DLn, and voltage generator 140 can generate the reference voltage.

[0066] The controller 150 controls various operations of the display device 100. The controller 150 receives an input image (IMG) and a control signal (CTRL) for controlling the display of the input image data from an external source. The controller 150 can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS) in response to the control signal (CTRL).

[0067] The controller 150 can convert the input image input IMG into image data DATA suitable for display device 100 or display panel 110. The controller 150 can output image data DATA by aligning the input image input IMG to the sub-pixels SP of the row cells.

[0068] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component separate from the driver integrated circuit (DIC).

[0069] Display device 100 may include at least one temperature sensor 160. Temperature sensor 160 can sense the ambient temperature of display device 100 and generate temperature data TEP representing the sensed temperature. Temperature sensor 160 may be disposed adjacent to display panel 110 and / or driver integrated circuit DIC.

[0070] The controller 150 can control various operations of the display device 100 in response to the temperature data TEP. The controller 150 can adjust the brightness of the image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 can control data signals and a first power voltage VDD and a second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0071] Figure 2 An embodiment is shown. Figure 1 A schematic block diagram of one of the sub-pixels. (See attached image.) Figure 2 As described in Figure 1 Among the sub-pixels SP, sub-pixels SPij set in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) are shown as an example.

[0072] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0073] The light-emitting element (LD) can be electrically connected between the first power voltage node VDDN and the second power voltage node VSSN. For example, the first power voltage node VDDN can be a transmission... Figure 1 The first power voltage node VDD, and the second power voltage node VSSN can be the transmission node. Figure 1 The node of the second power voltage VSS.

[0074] The anode electrode AE ​​of the light-emitting element LD can be electrically connected to the first power voltage node VDDN via the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be electrically connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be electrically connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0075] The sub-pixel circuit SPC can be electrically connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm Figure 1 The first light emission control line EL1 to the m-th light emission control line ELm, and the i-th light emission control line ELi and Figure 1 The first data line DL1 to the nth data line DLn is the j-th data line DLj. The sub-pixel circuit SPC can control the light-emitting element LD based on the signals received through these signal lines.

[0076] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. For example... Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the respective sub-gate lines.

[0077] The sub-pixel circuit SPC can operate in response to an emission control signal received via the i-th emission control line ELi. The i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to an emission control signal received via the respective sub-emission control line.

[0078] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. In response to a light emission control signal received via the i-th light emission control line ELi, the sub-pixel circuit SPC can adjust the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN based on the stored voltage. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0079] Figure 3 An embodiment is shown. Figure 2 A schematic diagram of the equivalent circuit of a sub-pixel.

[0080] refer to Figure 3 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0081] The sub-pixel circuit (SPC) can be electrically connected to the i-th gate line GLi', the i-th light emission control line ELi', and the j-th data line DLj. Figure 2 Compared to the i-th gate line GLi, the i-th gate line GLi' may also include a third sub-gate line SGL3. Compared to... Figure 2 Compared to the i-th light emission control line ELi, the i-th light emission control line ELi' may include a first sub-light emission control line SEL1 and a second sub-light emission control line SEL2.

[0082] The sub-pixel circuit SPC may include a first transistor T1 to a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0083] The first transistor T1 can be electrically connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 can be electrically connected to the second node N2, and therefore, the first transistor T1 can be turned on according to the voltage level of the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0084] The second transistor T2 can be electrically connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 can be electrically connected to the first sub-gate line SGL1, and therefore, the second transistor T2 can be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0085] The third transistor T3 can be electrically connected between the first node N1 and the second node N2. The gate of the third transistor T3 can be electrically connected to the second sub-gate line SGL2, and therefore, the third transistor T3 can be turned on in response to the gate signal of the second sub-gate line SGL2.

[0086] The fourth transistor T4 can be electrically connected between the first node N1 and the anode electrode AE ​​of the light-emitting element LD. The gate of the fourth transistor T4 can be electrically connected to the second sub-light-emitting control line SEL2, and therefore, the fourth transistor T4 can be turned on in response to the light-emitting control signal of the second sub-light-emitting control line SEL2.

[0087] The fifth transistor T5 can be electrically connected between the anode electrode AE ​​of the light-emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN can transmit the initialization voltage. The initialization voltage can be... Figure 1 The voltage generator 140 provides the initialization voltage. In other embodiments, the initialization voltage may be provided to the display device 100 by an external device. The gate of the fifth transistor T5 may be electrically connected to the third sub-gate line SGL3, and therefore, the fifth transistor T5 may be turned on in response to a gate signal on the third sub-gate line SGL3.

[0088] The sixth transistor T6 can be electrically connected between the first power voltage node VDDN and the first transistor T1. The gate of the sixth transistor T6 can be electrically connected to the first sub-light emission control line SEL1, and therefore, the sixth transistor T6 can be turned on in response to the light emission control signal of the first sub-light emission control line SEL1.

[0089] The first capacitor C1 can be electrically connected between the second transistor T2 and the second node N2. The second capacitor C2 can be electrically connected between the first power voltage node VDDN and the second node N2.

[0090] As described above, the sub-pixel circuit SPC may include first transistors T1 to sixth transistors T6, a first capacitor C1, and a second capacitor C2. However, the implementation is not limited to this. The sub-pixel circuit SPC can be implemented as one of various circuits including multiple transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the implementation of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-light emission control lines included in the i-th light emission control line ELi' can vary.

[0091] The first transistor T1 through the sixth transistor T6 can be P-type transistors. Each of the first transistor T1 through the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the implementation is not limited to this. For example, at least one of the first transistor T1 through the sixth transistor T6 can be replaced with an N-type transistor.

[0092] The first transistor T1 to the sixth transistor T6 may include amorphous silicon semiconductor, monocrystalline silicon semiconductor, polycrystalline silicon semiconductor and oxide semiconductor.

[0093] The light-emitting element (LD) may include an anode electrode AE, a cathode electrode CE, and a light-emitting layer. The light-emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted via the j-th data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 may be turned on when the light emission control signals of the first sub-light emission control line SEL1 and the second sub-light emission control line SEL2 are enabled to a low level. The first transistor T1 may be turned on according to the voltage of the second node N2, and therefore, current may flow from the first power voltage node VDDN to the second power voltage node VSSN. The light-emitting element LD may emit light according to the amount of current flowing.

[0094] Figure 4 It shows Figure 1 A schematic top plan view of an embodiment of the display panel.

[0095] refer to Figure 4 As Figure 1 The display panel DP of the embodiment of the display panel 110 may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA may be disposed around the display area DA.

[0096] The display panel (DP) may include a substrate (SUB), sub-pixels (SP), and pads (PD).

[0097] When the display panel DP is used as a display for a head-mounted display (HMD), virtual reality (VR) device, mixed reality (MR) device, or augmented reality (AR) device, the display panel DP may be positioned very close to the user's eyes. For example, it may require subpixels SP with relatively high integration. To increase the integration of the subpixel SP, the substrate SUB can be provided as a silicon substrate. The subpixel SP and / or the display panel DP can be formed on the substrate SUB, which is a silicon substrate. Display device 100 including a display panel DP formed on a substrate SUB, which is a silicon substrate (see...) Figure 1 This can be referred to as an OLED on silicon (OLEDoS) display device.

[0098] Subpixels SP can be disposed on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix format on a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the implementation is not limited to this. For example, subpixels SP can be arranged in a sawtooth pattern on the first direction DR1 and the second direction DR2. For example, subpixels SP can be configured as pentile.® Shape. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0099] Two or more of the multiple sub-pixels SP can form a pixel PXL.

[0100] The components used to control the sub-pixel SP can be disposed on the substrate SUB in the non-display area NDA. For example, such as Figure 1 The wires connecting the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn to the sub-pixel SP can be set in the non-display area NDA.

[0101] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150 and temperature sensor 160 can be integrated into the non-display area NDA of the display panel DP. Figure 1 The gate driver 120 can be mounted on the display panel DP and can be located in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. The temperature sensor 160 can be located in the non-display area NDA to detect the temperature of the display panel DP.

[0102] The pad PD can be disposed on the substrate SUB in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wires. For example, the pad PD can be electrically connected to the sub-pixel SP via the first data line DL1 to the nth data line DLn.

[0103] The pad PD can connect the display panel DP to the display device 100 (see...) Figure 1 The other components interact with each other. The voltages and signals required for the operation of the components included in the display panel DP can be transmitted from the pads PD via... Figure 1 The driver integrated circuit (DIC) is provided. For example, the first data line DL1 to the nth data line DLn can be electrically connected to the driver integrated circuit (DIC) via the pad PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit (DIC) via the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad PD.

[0104] The display area DA can have various shapes. The display area DA can have a closed loop shape with sides including straight lines and / or curves. For example, the display area DA can have shapes such as polygonal shapes, circular shapes, semi-circular shapes, and elliptical shapes.

[0105] The display panel DP can have a flat display surface. In other embodiments, the display panel DP can have a display surface that can be at least partially rounded. The display panel DP can be flexible, foldable, or rollable. For example, the display panel DP and / or the substrate SUB can include a material with flexible properties.

[0106] Figure 5 It shows Figure 4 An exploded perspective view of a portion of the display panel. (See diagram below.) Figure 5 As depicted herein, for the sake of clarity and conciseness, the display panel DP is schematically shown alongside... Figure 4 The portion corresponding to pixels PXL1 and PXL2 within the pixel PXL. The portion corresponding to the remaining pixels of the display panel DP can be configured similarly.

[0107] refer to Figure 5 Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the implementation is not limited to this. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0108] like Figure 5 As depicted, when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2 (or in a planar view), the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a quadrilateral shape and have the same size. However, the implementation is not limited to this. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be modified to have various shapes in a planar view.

[0109] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical functional layer OFL, an outer coating OC, and a cover window CW. For example, the substrate SUB, pixel circuit layer PCL, light-emitting element layer LDL, packaging layer TFE, optical functional layer OFL, outer coating OC, and cover window CW may be arranged sequentially in a third direction DR3 (e.g., the thickness direction).

[0110] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0111] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). The substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) can be used as at least some of circuit elements, wires, etc.

[0112] The conductive pattern may include copper, but the implementation is not limited to this.

[0113] The circuit elements may include a sub-pixel circuit SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see [link to circuit diagram]). Figure 2 The sub-pixel circuit (SPC) may include transistors and one or more capacitors. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. When the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer (PCL) as a conductive pattern of the PCL. When the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer (PCL). Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other on a third direction DR3 (e.g., the thickness direction) with an insulating layer between them.

[0114] The conductors of the pixel circuit layer (PCL) may include signal lines, such as gate lines, light emission control lines, and data lines, electrically connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The conductors may also include electrically connected... Figure 2 The conductor of the first power voltage node VDDN. The conductor may also include electrical connections to... Figure 2 The conductor of the second power voltage node VSSN.

[0115] The light-emitting element layer (LDL) may include an anode electrode (AE) (or a first electrode), a pixel-defining layer (PDL), a light-emitting structure (or light-emitting component) (EMS), and a cathode electrode (CE) (or a second electrode).

[0116] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL. The anode electrode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the implementation is not limited to this.

[0117] A pixel-defining layer (PDL) may be disposed on an anode electrode (AE). The PDL may include an opening (OP) exposing a portion of each of the anode electrodes (AE). Each of the light-emitting regions corresponding to each of the first sub-pixels (SP1) to the third sub-pixels (SP3) may be defined by the opening (OP) of the PDL. For example, each of the light-emitting regions corresponding to each of the first sub-pixels (SP1) to the third sub-pixels (SP3) may be defined by an anode electrode (AE). In regions adjacent to the boundaries of adjacent sub-pixels, the PDL may include a separator that creates a discontinuity in the light-emitting structure (EMS). For example, each of the light-emitting regions corresponding to each of the first sub-pixels (SP1) to the third sub-pixels (SP3) may be defined by a separator of the PDL.

[0118] The pixel-defining layer (PDL) may include inorganic materials. For example, the pixel-defining layer (PDL) may include multiple stacked inorganic layers. For example, the pixel-defining layer (PDL) may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x In other embodiments, the pixel defining layer (PDL) may include an organic material. However, the material of the pixel defining layer (PDL) is not limited to this.

[0119] The light-emitting structure (EMS) can be disposed on the anode electrode (AE) exposed by the opening (OP) of the pixel-defined layer (PDL). The light-emitting structure (EMS) may include a light-emitting layer for generating light, an electron transport layer for transporting electrons, and a hole transport layer for transporting holes.

[0120] The light-emitting structure EMS can fill the opening OP of the pixel-defining layer PDL and can be disposed (e.g., fully disposed) on the upper portion of the pixel-defining layer PDL. For example, the light-emitting structure EMS can extend across the first sub-pixel SP1 to the third sub-pixel SP3. For example, at least some of the functional layers in the light-emitting structure EMS can be separated or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3. However, the implementation is not limited to this. For example, the portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 can be separated from each other, and each of these portions of the light-emitting structure EMS can be disposed in the opening OP of the pixel-defining layer PDL.

[0121] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can extend across the first sub-pixel SP1 to the third sub-pixel SP3. Therefore, the cathode electrode CE can be provided as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0122] The cathode electrode CE can be a thin metal layer with a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode electrode CE can be made of a metallic material or a transparent conductive material to have a relatively thin thickness. The cathode electrode CE can include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE can include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited to these.

[0123] One of the anode electrodes AE, the portion of the light-emitting structure EMS overlapping with the anode electrode AE, and the portion of the cathode electrode CE overlapping with the anode electrode AE ​​can constitute a light-emitting element LD (see [link to LD]). Figure 2 For example, each of the light-emitting elements (LDs) in the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AE, a portion of the light-emitting structure EMS overlapping with it, and a portion of the cathode electrode CE overlapping with it. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE can be transferred to the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from an excited state to a ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined based on the configuration of the light-emitting layer.

[0124] The encapsulation layer TFE can be disposed on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. The encapsulation layer TFE can include a structure in which one or more inorganic films and one or more organic films can be stacked alternately. For example, the inorganic film can include silicon nitride (SiN). x ), silicon oxide (SiO) x ) or silicon nitride oxide (SiO) x N y For example, organic films can include organic insulating materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, or benzocyclobutene. However, the materials of the organic and inorganic films of the encapsulation layer TFE are not limited to these.

[0125] The encapsulation layer TFE may also include aluminum oxide (AlO) x A thin film containing aluminum oxide can be disposed on the upper surface of the encapsulation layer TFE facing the optical functional layer OFL and / or the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL, in order to improve the encapsulation efficiency of the encapsulation layer TFE.

[0126] The optical functional layer (OFL) can be disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include the optical layer (OPL) and the color filter layer (CFL).

[0127] The optical layer (OPL) can be disposed between the encapsulation layer (TFE) and the color filter layer (CFL). The OPL may include reflective layers corresponding to the first sub-pixels SP1 through SP3, respectively. Each of the reflective layers can improve light efficiency by controlling the light emission direction by reflecting light emitted from the light-emitting structure (EMS) along a desired path. See below for further details. Figures 7 to 12 A detailed description of the optical layer OPL.

[0128] A color filter layer (CFL) can be disposed on the optical layer (OPL). By filtering the light emitted from the light-emitting structure (EMS), the color filter layer (CFL) can selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer (CFL) may include color filters (CF) corresponding to the first sub-pixels SP1 to the third sub-pixels SP3, respectively, and each of the color filters (CF) allows light within the wavelength range corresponding to the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the light-emitting structure (EMS) of each sub-pixel, at least some of the color filters (CF) may be omitted.

[0129] The outer coating OC can be disposed on the color filter layer CFL. The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting its underlying layers from foreign matter such as dust and moisture. For example, the outer coating OC can include at least one of inorganic and organic insulating films. For example, the outer coating OC can include epoxy resin, but the implementation is not limited thereto.

[0130] A cover window (CW) may be disposed on the outer coating (OC). The cover window (CW) protects the underlying layer. The cover window (CW) may have a higher refractive index than the outer coating (OC). The cover window (CW) may include glass, but the implementation is not limited thereto. For example, the cover window (CW) may be encapsulation glass protecting the components disposed beneath it. In other implementations, the cover window (CW) may be omitted.

[0131] Figure 6 An embodiment is shown. Figure 5 A schematic top plan view of one of the pixels. Figures 7 to 11 The following is illustrated along the embodiments according to this disclosure. Figure 6 A schematic cross-sectional view taken from line I-I'. Figure 12 An embodiment is shown. Figure 7 An enlarged schematic diagram of the reflective layer.

[0132] In order to Figure 6 The clear and concise description illustrates the schematic representation. Figure 5 The first pixel PXL1 is one of the first pixels PXL1 and the second pixel PXL2. The remaining pixels can be configured similarly to the first pixel PXL1.

[0133] refer to Figure 5 and Figure 6 The first pixel PXL1 may include the first sub-pixel SP1 to the third sub-pixel SP3 set on the first direction DR1.

[0134] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0135] The first emitting region EMA1 can be where light emanates from the emitting structure EMS (see...). Figure 5 The second emitting region EMA2 can be the region in which light is emitted from the portion of the emitting structure EMS corresponding to the second sub-pixel SP1. The third emitting region EMA3 can be the region in which light is emitted from the portion of the emitting structure EMS corresponding to the third sub-pixel SP3.

[0136] Reflective layers RF1 and RF2 can be configured to correspond to the first sub-pixels SP1 to SP3, respectively. The planar shapes of reflective layers RF1 and RF2 can respectively follow the planar shapes of the first light-emitting regions EMA1 to EMA3. For example, the planar shapes of reflective layers RF1 and RF2 can be similar to the planar shapes of the first light-emitting regions EMA1 to EMA3, respectively.

[0137] The size (or planar area) of the first reflective layer RF1 may be larger than the size (or planar area) of the first light-emitting region EMA1 to the third light-emitting region EMA3. The width of the first reflective layer RF1 in the first direction DR1 and / or the second direction DR2 may be larger than the width of the first light-emitting region EMA1 to the third light-emitting region EMA3 in the first direction DR1 and / or the second direction DR2.

[0138] The size (or planar area) of the first reflective layer RF1 may be larger than the size (or planar area) of the opening OP of the pixel-defining layer PDL. The width of the first reflective layer RF1 in the first direction DR1 and / or the second direction DR2 may be larger than the width of the opening OP of the pixel-defining layer PDL in the first direction DR1 and / or the second direction DR2.

[0139] The size (or planar area) of the second reflective layer RF2 can be larger than the size of the first light-emitting area EMA1 to the third light-emitting area EMA3. The width of the second reflective layer RF2 in the first direction DR1 and / or the second direction DR2 can be larger than the width of the first light-emitting area EMA1 to the third light-emitting area EMA3 in the first direction DR1 and / or the second direction DR2.

[0140] The size (or planar area) of the second reflective layer RF2 can be larger than the size (or planar area) of the opening OP of the pixel-defining layer PDL. The width of the second reflective layer RF2 in the first direction DR1 and / or the second direction DR2 can be larger than the width of the opening OP of the pixel-defining layer PDL in the first direction DR1 and / or the second direction DR2.

[0141] The size (or planar area) of the first reflective layer RF1 may be larger than the size (or planar area) of the second reflective layer RF2. The width of the first reflective layer RF1 in the first direction DR1 and / or the second direction DR2 may be larger than the width of the second reflective layer RF2 in the first direction DR1 and / or the second direction DR2.

[0142] refer to Figure 7 It can provide a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB.

[0143] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0144] The pixel circuit layer PCL can be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL can include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, the substrate SUB and the pixel circuit layer PCL can include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 can be a sub-pixel circuit SPC included in the first sub-pixel SP1 (see [link to relevant documentation]). Figure 2 One of the transistors in the sub-pixel SP2, the transistor T_SP2 of the second sub-pixel SP2 can be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 can be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. For example... Figure 7 For clarity and conciseness, the diagram shows one transistor for each subpixel, while the rest of the circuitry is omitted.

[0145] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE that may be disposed between the source region SRA and the drain region DRA.

[0146] The source region SRA and drain region DRA can be disposed in the substrate SUB. A well WL formed by an ion implantation process can be disposed in the substrate SUB, and the source region SRA and drain region DRA can be disposed spaced apart from each other within the well WL. The region between the source region SRA and drain region DRA in the well WL can be defined as a channel region. The gate electrode GE overlaps with the channel region between the source region SRA and drain region DRA in a third direction DR3 (e.g., the thickness direction) and can be disposed on the pixel circuit layer PCL. The gate electrode GE can be separated from the well WL or channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE can include a conductive material.

[0147] The pixel circuit layer PCL includes multiple layers comprising insulating layers and conductive patterns disposed between the insulating layers, and the conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 is electrically connected to the drain region DRA through a drain connection portion DRC that penetrates one or more insulating layers. The second conductive pattern CP2 is electrically connected to the source region SRA through a source connection portion SRC that penetrates one or more insulating layers.

[0148] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 can be electrically connected to other circuit elements and / or wires, the transistor T_SP1 of the first sub-pixel SP1 can be provided as one of the transistors of the first sub-pixel SP1.

[0149] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0150] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0151] A via layer (VIAL) can be disposed on the pixel circuit layer (PCL). The VIAL can cover the PCL and can have an overall flat surface. The VIAL can flatten the steps on the PCL. The VIAL can comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x The embodiment may contain at least one of silicon carbide (SiCN) and silicon carbide (SiCN), but the implementation is not limited thereto.

[0152] The light-emitting element layer (LDL) can be disposed on the via layer (VIAL). The light-emitting element layer (LDL) may include a first reflective electrode (RE1) to a third reflective electrode (RE3), a planarization layer (PLNL), a first anode electrode (AE1) to a third anode electrode (AE3), a pixel definition layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0153] The first reflective electrode RE1 to the third reflective electrode RE3 can be respectively disposed in the first sub-pixel SP1 to the third sub-pixel SP3 on the via layer VIAL. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact a circuit element disposed on the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0154] The first reflective electrodes RE1 to the third reflective electrodes RE3 can be used as total reflection mirrors to reflect light emitted from the light-emitting structure EMS toward the display surface (or cover window CW). The first reflective electrodes RE1 to the third reflective electrodes RE3 may include metallic materials suitable for reflecting light. The first reflective electrodes RE1 to the third reflective electrodes RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom, but the embodiments are not limited thereto.

[0155] The connecting electrode can be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode can improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode can have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the implementation is not limited to these. Corresponding reflective electrodes can be disposed between multiple layers of the connecting electrode.

[0156] A buffer pattern BFP can be disposed below at least one of the first reflective electrodes RE1 to the third reflective electrode RE3, and on the via of the through-hole layer VIAL. The buffer pattern BFP can include inorganic materials such as silicon carbon nitride, but the implementation is not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode on the third-direction DR3 can be adjusted. For example, the buffer pattern BFP can be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0157] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a half-reflection mirror. For example, each of the first reflecting electrodes RE1 to the third reflecting electrodes RE3 and the cathode electrode CE can provide a resonant structure in the corresponding sub-pixel. Light emitted from the emissive layer of the light-emitting structure EMS can be amplified by reciprocating between the reflecting electrodes and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. Therefore, the distance between each reflecting electrode and the cathode electrode CE can be understood as the resonant distance for light emitted from the emissive layer of the corresponding light-emitting structure EMS.

[0158] Due to the buffer pattern BFP, the first sub-pixel SP1 can have a shorter resonant distance than other sub-pixels. This resonant distance adjustment allows light within a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first sub-pixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0159] like Figure 7As depicted, the buffer pattern BFP is shown to be provided in the first sub-pixel SP1 and not in the second sub-pixel SP2 and the third sub-pixel SP3, but the implementation is not limited thereto. The buffer pattern may also be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3, allowing adjustment of the resonant distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively; the distance between the first reflective electrode RE1 and the cathode electrode CE in a third direction DR3 (e.g., the thickness direction) may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE; and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0160] To planarize the step between the first reflective electrode RE1 and the third reflective electrode RE3, a planarization layer PLNL can be provided on the via layer VIAL to cover the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL can cover (e.g., completely cover) the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL, and can have a flat surface. The planarization layer PLNL can be omitted.

[0161] First anode electrodes AE1 to third anode electrodes AE3, respectively overlapping with first reflective electrodes RE1 to third reflective electrodes RE3, can be disposed on the planarization layer PLNL. When viewed from a third-party perspective DR3 (or in a plan view), the first anode electrodes AE1 to third anode electrodes AE3 can have... Figure 6 The first light-emitting regions EMA1 to the third light-emitting regions EMA3 have similar shapes. The first anode electrode AE1 to the third anode electrode AE3 can be electrically connected to the first reflective electrode RE1 to the third reflective electrode RE3, respectively. The first anode electrode AE1 can be electrically connected to the first reflective electrode RE1 through a first via VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 can be electrically connected to the second reflective electrode RE2 through a second via VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 can be electrically connected to the third reflective electrode RE3 through a third via VIA3 penetrating the planarization layer PLNL.

[0162] The first anode electrode AE1 to the third anode electrode AE3 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). xIt is at least one of the transparent conductive materials selected from indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1 to the third anode electrode AE3 are not limited thereto. For example, the first anode electrode AE1 to the third anode electrode AE3 may include titanium nitride.

[0163] A pixel-defining layer (PDL) may be disposed on some of the first anode electrodes AE1 to the third anode electrodes AE3 and on the planarization layer PLNL. The PDL has an opening OP that exposes a portion of each of the first anode electrodes AE1 to the third anode electrodes AE3. The region overlapping with the PDL can be understood as the boundary region BDA between adjacent sub-pixels.

[0164] The pixel-defining layer (PDL) may include multiple inorganic insulating layers. Each of the multiple inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. For example, the pixel defining layer PDL may include a first inorganic insulating layer ISL1, a second inorganic insulating layer ISL2, and a third inorganic insulating layer ISL3 stacked sequentially. The first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x However, the implementation is not limited to this. The first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may have a stepped cross-section in the region adjacent to the opening OP.

[0165] The pixel-defined layer (PDL) may include separators (SPRs) in the boundary regions (BDAs) between adjacent sub-pixels. For example, the separators (SPRs) may be set in... Figure 4 In each of the boundary regions between sub-pixels SP.

[0166] The splitter SPR can cause discontinuities in the light-emitting structure EMS within the boundary region BDA. For example, the light-emitting structure EMS can be broken or bent within the boundary region BDA by the splitter SPR. Therefore, the splitter SPR of the pixel definition layer PDL can be used to define the sub-pixels corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Figure 6 The first luminescent region EMA1 to the third luminescent region EMA3.

[0167] The separator SPR can be set in or on the pixel-defined layer (PDL). The pixel-defined layer (PDL) may include one or more trenches TRCH1 and TRCH2 as separator SPRs in the boundary region (BDA). Figure 7As shown, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining layer PDL and partially penetrate the planarization layer PLNL. In other embodiments, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining layer PDL and the planarization layer PLNL, and can partially penetrate the via layer VIAL. In other embodiments, one or more trenches TRCH1 and TRCH2 at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL can be disposed in one or more trenches TRCH1 and TRCH2.

[0168] like Figure 7 As depicted, two trenches TRCH1 and TRCH2 may be provided in the boundary region BDA. However, the implementation is not limited to this. For example, the pixel-defining layer PDL may include one trench in the boundary region BDA. For example, the pixel-defining layer PDL may include three or more trenches in the boundary region BDA.

[0169] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first gap VD1 and the second gap VD2 can be formed in the light-emitting structure EMS within the boundary region BDA. Some of the multiple layers stacked in the light-emitting structure EMS can be broken or bent through the first gap VD1 and the second gap VD2. For example, at least one charge generation layer and at least one hole injection layer included in the light-emitting structure EMS can be broken in the first gap VD1 and the second gap VD2. As described above, due to the first trench TRCH1 and the second trench TRCH2, portions of the light-emitting structure EMS included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated.

[0170] The discontinuities formed in the light-emitting structure EMS can vary depending on the shape of the first trench TRCH1 and the second trench TRCH2.

[0171] The light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing. For example, the same material as the light-emitting structure EMS can be disposed on the bottom surface of the first trench TRCH1 and the second trench TRCH2 adjacent to the via layer VIAL.

[0172] The pixel defining layer (PDL) may include additional separators, allowing the light-emitting structure (EMS) to also include discontinuous portions adjacent to the boundary region BDA. The uppermost of the first inorganic insulating layers (ISL1) to the third inorganic insulating layers (ISL3) of the pixel defining layer (PDL), the third inorganic insulating layer (ISL3), may have a width wider than the second inorganic insulating layer (ISL2) directly below the third inorganic insulating layer (ISL3). For example, the pixel defining layer (PDL) may have a "T"-shaped or "I"-shaped cross-section in the boundary region BDA. Depending on the shape of the pixel defining layer (PDL), the multiple layers included in the light-emitting structure (EMS) may be at least partially broken or bent in the boundary region BDA or in a region adjacent to the boundary region BDA.

[0173] The light-emitting structure EMS can be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel-defining layer PDL. The light-emitting structure EMS can fill the opening OP of the pixel-defining layer PDL and can be disposed across (e.g., completely across) the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the light-emitting structure EMS can be at least partially disconnected or bent in the boundary region BDA by the separator SPR. Therefore, in the case of DP operation of the display panel, the current leakage from each of the first sub-pixel SP1 to the third sub-pixel SP3 to the adjacent sub-pixel through the layer included in the light-emitting structure EMS can be reduced. Therefore, the first light-emitting elements LD1 to the third light-emitting elements LD3 can operate with relatively high reliability.

[0174] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can be provided jointly for the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can function as a semi-reflective mirror that partially transmits and partially reflects light emitted from the light-emitting structure EMS.

[0175] The first anode electrode AE1, the portion of the light-emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 can constitute the first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 can constitute the second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 can constitute the third light-emitting element LD3.

[0176] The TFE encapsulation layer can be disposed on the cathode electrode (CE). The TFE encapsulation layer prevents oxygen and / or moisture from penetrating into the light-emitting element layer (LDL).

[0177] The optical functional layer (OFL) can be disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include the optical layer (OPL) and the color filter layer (CFL).

[0178] The optical layer OPL can be disposed on the encapsulation layer TFE. The optical layer OPL can be disposed (e.g., directly disposed) on the encapsulation layer TFE. The optical layer OPL may include the organic layer OL and the reflective layers RF1 and RF2 in the organic layer OL.

[0179] Each of the reflective layers RF1 and RF2 can control the light emission direction by reflecting the light emitted from the first light-emitting element LD1 to the third light-emitting element LD3 in the expected path, thereby improving light efficiency.

[0180] The organic layer OL can be disposed on the encapsulation layer TFE. The organic layer OL can be disposed (e.g., directly disposed) on the encapsulation layer TFE. The refractive index of the organic layer OL can be different from the refractive index of the encapsulation layer TFE. For example, the refractive index of the organic layer OL can be greater than the refractive index of the encapsulation layer TFE. For example, light emission efficiency can be improved by increasing the amount of light incident on the reflective layers RF1 and RF2.

[0181] The first reflective layer RF1 may be disposed in the organic layer OL. The first reflective layer RF1 may overlap with the pixel-defining layer PDL in the third direction DR3 (e.g., the thickness direction). The first reflective layer RF1 may not overlap with the opening OP of the pixel-defining layer PDL in the third direction DR3 (e.g., the thickness direction), but is not limited thereto.

[0182] The first reflective layer RF1 can be used as a total reflection mirror. Light emitted from the light-emitting structure EMS can be reflected, or at least partially reflected, from the second reflective layer RF2 and incident on the first reflective layer RF1. Light incident on the first reflective layer RF1 can be reflected by the first reflective layer RF1 and emitted in the display direction of the display panel DP (e.g., the front direction or the third direction DR3). Therefore, stray light from the display panel DP can be reduced, and light emission efficiency can be improved.

[0183] The first reflective layer RF1 may include a metallic material. For example, the first reflective layer RF1 may include at least one alloy selected from aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and two or more materials selected therefrom, but the embodiments are not limited thereto. In some embodiments, the first reflective layer RF1 may include a structure in which inorganic films are alternately stacked. For example, the first reflective layer RF1 may include silicon oxide (SiO2) in which silicon oxide (SiO2) is present. x ) and titanium oxide (TiO) x An alternating stacked structure.

[0184] The second reflective layer RF2 can be disposed within the organic layer OL. The second reflective layer RF2 can be disposed on top of the first reflective layer RF1 within the organic layer OL. The second reflective layer RF2 can overlap with the opening OP of the pixel-defining layer PDL in a third direction DR3 (e.g., the thickness direction). The second reflective layer RF2 can overlap with the light-emitting structure EMS in the third direction DR3 (e.g., the thickness direction). For example, the second reflective layer RF2 can overlap with the light-emitting structure EMS disposed in the opening OP of the pixel-defining layer PDL in the third direction DR3 (e.g., the thickness direction). The second reflective layer RF2 can partially overlap with the pixel-defining layer PDL in the third direction DR3 (e.g., the thickness direction), but is not limited thereto.

[0185] The second reflective layer RF2 can be used as a semi-reflective mirror to partially transmit and partially reflect light emitted from the light-emitting structure EMS. Light emitted from the light-emitting structure EMS can be partially reflected by the second reflective layer RF2 and incident on the first reflective layer RF1. Light incident on the first reflective layer RF1 can be reflected by the first reflective layer RF1 and emitted in the display direction of the display panel DP (e.g., the front direction or the third direction DR3). Therefore, stray light from the display panel DP can be reduced, and light emission efficiency can be improved.

[0186] The second reflective layer RF2 may include a metallic material. For example, the second reflective layer RF2 may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the second reflective layer RF2 may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. The second reflective layer RF2 may include the same material as the first reflective layer RF1, but is not limited thereto.

[0187] The first reflective layer RF1 may include a first opening OP1. The second reflective layer RF2 may include a second opening OP2. In a planar view, the size (or diameter) of the first opening OP1 may be larger than the size (or diameter) of the second opening OP2. The width of the first opening OP1 in the first direction DR1 may be larger than the width of the second opening OP2 in the first direction DR1, but is not necessarily limited thereto. In a planar view, the size (or diameter) of the first opening OP1 may be larger than the size (or diameter) of the opening OP of the pixel-defining layer PDL. The width of the first opening OP1 in the first direction DR1 may be larger than the width of the opening OP of the pixel-defining layer PDL in the first direction DR1, but is not necessarily limited thereto. In a planar view, the diameter of the second opening OP2 may be smaller than the diameter of the opening OP of the pixel-defining layer PDL. The width of the second opening OP2 in the first direction DR1 may be smaller than the width of the opening OP of the pixel-defining layer PDL in the first direction DR1, but is not necessarily limited thereto.

[0188] The center of the first opening OP1 can be aligned with or coincide with the center of the opening OP of the pixel-defining layer PDL. For example, in a planar view, the center of the first opening OP1 can overlap with the center of the opening OP of the pixel-defining layer PDL, but is not limited thereto. The center of the second opening OP2 can be aligned with or coincide with the center of the opening OP of the pixel-defining layer PDL. For example, in a planar view, the center of the second opening OP2 can overlap with the center of the opening OP of the pixel-defining layer PDL, but is not limited thereto.

[0189] like Figure 8 As shown, the center of the second opening OP2 can be offset from the center of the opening OP of the pixel-defining layer PDL in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. For example, the center of the second opening OP2 can be offset from the center of the opening OP of the pixel-defining layer PDL in a planar direction. For example, light emitted from the light-emitting structure EMS can be efficiently output in a direction tilted at a predetermined angle relative to the normal direction of the display surface. Figure 8 The embodiment depicted shows an implementation in which the center of the second opening OP2 is offset from the center of the opening OP of the pixel defining layer PDL, but this disclosure is not necessarily limited to this, and considering the light emission direction, the center of the first opening OP1 can be offset from the center of the opening OP of the pixel defining layer PDL.

[0190] like Figure 9 As shown, the second reflective layer RF2 may not include an opening. For example, the second reflective layer RF2 may have a tapered shape in the cross-sectional view. Figure 9The illustration shows an embodiment in which the second reflective layer RF2 does not include an opening, but this disclosure is not limited thereto, and the first reflective layer RF1 may also not include an opening. For example, the first reflective layer RF1 may have a tapered shape in a cross-sectional view.

[0191] Each of the first reflective layer RF1 and / or the second reflective layer RF2 may include a tilted surface. The tilt angle of the tilted surface of the first reflective layer RF1 may differ from the tilt angle of the tilted surface of the second reflective layer RF2. Here, the tilt angle of each tilted surface may refer to the angle formed by each tilted surface relative to the substrate SUB. Considering the light emission path of the light emitted from the light-emitting structure EMS, the tilt angles of the first reflective layer RF1 and / or the second reflective layer RF2 may be varied.

[0192] like Figure 10 and Figure 11 As shown, the first reflective layer RF1 and / or the second reflective layer RF2 may include spherical surfaces. The curvature of the spherical surface of the first reflective layer RF1 may differ from the curvature of the spherical surface of the second reflective layer RF2. Considering the light emission path of the light emitted from the light-emitting structure EMS, the curvature of the first reflective layer RF1 and / or the curvature of the second reflective layer RF2 may be varied.

[0193] In some implementations, one of the first reflective layer RF1 and the second reflective layer RF2 may include a sloping surface, and the other may include a spherical surface.

[0194] like Figure 10 The illustration shows an embodiment in which the first reflective layer RF1 includes a first opening OP1 and the second reflective layer RF2 includes a second opening OP2, but this disclosure is not limited thereto. For example, as Figure 11 As shown, the second reflective layer RF2 may not include an opening. For example, the second reflective layer RF2 may have a semi-circular shape in a cross-sectional view. In some embodiments, the first reflective layer RF1 may not include an opening. For example, the first reflective layer RF1 may have a semi-circular shape in a cross-sectional view.

[0195] refer to Figure 12 The organic layer OL may include a first organic layer OL1, a second organic layer OL2, and / or a third organic layer OL3. The first organic layer OL1 may be disposed on the encapsulation layer TFE. The first organic layer OL1 may be disposed (e.g., directly disposed) on the encapsulation layer TFE. The second organic layer OL2 may be disposed on the first organic layer OL1. The second organic layer OL2 may be disposed (e.g., directly disposed) on the first organic layer OL1. The third organic layer OL3 may be disposed on the second organic layer OL2. The third organic layer OL3 may be disposed (e.g., directly disposed) on the second organic layer OL2.

[0196] The first organic layer OL1, the second organic layer OL2, and / or the third organic layer OL3 may comprise the same material. However, this disclosure is not necessarily limited thereto, and the first organic layer OL1, the second organic layer OL2, and / or the third organic layer OL3 may have different refractive indices. By controlling the refractive indices of the first organic layer OL1, the second organic layer OL2, and / or the third organic layer OL3, the optical layer OPL can be used as a lens.

[0197] The first organic layer OL1, the second organic layer OL2, and / or the third organic layer OL3 may include, but are not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0198] The first organic layer OL1 may include a first inclined surface S1. A first reflective layer RF1 may be disposed on the first inclined surface S1. The first reflective layer RF1 may be disposed between the first organic layer OL1 and the second organic layer OL2. The first reflective layer RF1 may be disposed (e.g., directly disposed) on the first organic layer OL1. The second organic layer OL2 may be disposed (e.g., directly disposed) on the first reflective layer RF1.

[0199] The second organic layer OL2 may include a second inclined surface S2. A second reflective layer RF2 may be disposed on the second inclined surface S2. The second reflective layer RF2 may be disposed between the second organic layer OL2 and the third organic layer OL3. The second reflective layer RF2 may be disposed (e.g., directly disposed) on the second organic layer OL2. The third organic layer OL3 may be disposed (e.g., directly disposed) on the second reflective layer RF2.

[0200] The first organic layer OL1 may be disposed in the first opening OP1 of the first reflective layer RF1. The second organic layer OL2 and / or the third organic layer OL3 may overlap with the first opening OP1 in a third direction DR3 (e.g., the thickness direction), but are not limited thereto.

[0201] The second organic layer OL2 may be disposed in the second opening OP2 of the second reflective layer RF2. In some embodiments, the first organic layer OL1 may also be disposed in the second opening OP2. The third organic layer OL3 may overlap with the second opening OP2 in a third direction DR3 (e.g., the thickness direction), but is not limited thereto.

[0202] In some embodiments, the optical layer OPL may further include a passivation layer PSV. The passivation layer PSV may be disposed on the third organic layer OL3. The passivation layer PSV may be disposed (e.g., directly disposed) on the third organic layer OL3. The passivation layer PSV may include silicon nitride (SiN).x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO) x N y (etc.), but not limited to these.

[0203] According to the above embodiments, by using an organic layer OL and reflective layers RF1 and RF2 to form an optical layer OPL, the light emission efficiency of the display panel DP can be improved.

[0204] See again Figure 7 The color filter layer (CFL) can be disposed on the optical layer (OPL). The CFL can include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) corresponding to the first sub-pixels (SP1) to the third sub-pixels (SP3), respectively. The first color filters (CF1) to the third color filters (CF3) allow light within different wavelength ranges to pass through. For example, the first color filters (CF1) to the third color filters (CF3) can allow red light, green light, and blue light to pass through, respectively.

[0205] The first color filters CF1 to the third color filters CF3 may partially overlap in the boundary region BDA. In other embodiments, the first color filters CF1 to the third color filters CF3 may be spaced apart from each other, and a black matrix may be provided between each of the first color filters CF1 to the third color filters CF3.

[0206] The outer coating OC can be applied to the color filter layer CFL. The outer coating OC protects the underlying layer from foreign matter such as dust and moisture. The cover window CW can be applied to the outer coating OC.

[0207] Figure 13 An example of an embodiment along [the path] is shown. Figure 6 A schematic cross-sectional view taken from line I-I'. Figure 14 It shows Figure 13 An enlarged diagram of region "A".

[0208] refer to Figure 13 The pixel circuit layer PCL and the via layer VIAL can be disposed on the substrate SUB. Figure 13 The substrate SUB, pixel circuit layer PCL, and via layer VIAL can be combined with Figure 7 The substrate SUB, pixel circuit layer PCL, and via layer VIAL are similarly configured. Redundant descriptions will be omitted below.

[0209] The light-emitting element layer LDL' can be disposed on the via layer VIAL. The light-emitting element layer LDL' may include a first reflective electrode RE1' to a third reflective electrode RE3', a first buffer pattern BFP1' and a second buffer pattern BFP2', a first cover pattern CVP1 to a third cover pattern CVP3, a first anode electrode AE1' to a third anode electrode AE3', a pixel defining layer PDL', a light-emitting structure EMS', and a cathode electrode CE.

[0210] The first reflective electrode RE1' to the third reflective electrode RE3' can be respectively disposed in the first sub-pixel SP1 to the third sub-pixel SP3 on the via layer VIAL. Each of the first reflective electrode RE1' to the third reflective electrode RE3' can contact a circuit element disposed on the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0211] The first reflective electrodes RE1' to the third reflective electrodes RE3' can reflect light emitted from the light-emitting structure EMS' toward the display surface (or the cover window CW). The first reflective electrodes RE1' to the third reflective electrodes RE3' may include a metallic material suitable for reflecting light. The first reflective electrodes RE1' to the third reflective electrodes RE3' may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom, but the embodiments are not limited thereto.

[0212] The connecting electrode can also be disposed between each of the first reflective electrode RE1' to the third reflective electrode RE3' and the via layer VIAL. The connecting electrode can improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode can have a multilayer structure. The multilayer structure may include titanium (Ti), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), etc., but the implementation is not limited to these. Corresponding reflective electrodes can be disposed between multiple layers of the connecting electrode.

[0213] A buffer pattern can be provided on at least one of the first reflective electrode RE1' to the third reflective electrode RE3'. The first buffer pattern BFP1' and the second buffer pattern BFP2' can be provided on the first reflective electrode RE1' and the third reflective electrode RE3', respectively. The thicknesses of the first anode electrode AE1' and the third anode electrode AE3' from the upper portion of the via layer VIAL in the third direction DR3 (e.g., the thickness direction) can be adjusted by changing the thicknesses of the first buffer pattern BFP1' and the second buffer pattern BFP2' in the third direction DR3 (e.g., the thickness direction), respectively. The first buffer pattern BFP1' and the second buffer pattern BFP2' can comprise materials such as silicon oxide (SiO2).x ) and silicon nitride (SiN) x ( ) inorganic materials, but the implementation methods are not limited to this.

[0214] First overlay patterns CVP1 to third overlay patterns CVP3 can be respectively disposed on first reflective electrodes RE1' to third reflective electrodes RE3'. In the first sub-pixel SP1, the first overlay pattern CVP1 can be disposed on the first reflective electrode RE1' and the first buffer pattern BFP1'. In the second sub-pixel SP2, the second overlay pattern CVP2 can be disposed on the second reflective electrode RE2'. In the third sub-pixel SP3, the third overlay pattern CVP3 can be disposed on the third reflective electrode RE3' and the second buffer pattern BFP2'. The first overlay patterns CVP1 to third overlay patterns CVP3 can be formed during the manufacturing process after the formation of the first buffer pattern BFP1' and the second buffer pattern BFP2'. The first overlay patterns CVP1 to third overlay patterns CVP3 can include the same material as the first buffer pattern BFP1' and the second buffer pattern BFP2'. For example, the first overlay patterns CVP1 to third overlay patterns CVP3 can include silicon oxide (SiO2). x ) and silicon nitride (SiN) x ( ) inorganic materials, but the implementation methods are not limited to this.

[0215] The first anode electrode AE1' to the third anode electrode AE3' can be respectively disposed on the first cover pattern CVP1 to the third cover pattern CVP3. The first anode electrode AE1' can cover the first cover pattern CVP1, the first buffer pattern BFP1', and the first reflective electrode RE1'. The second anode electrode AE2' can cover the second cover pattern CVP2 and the second reflective electrode RE2'. The third anode electrode AE3' can cover the third cover pattern CVP3, the second buffer pattern BFP2', and the third reflective electrode RE3'.

[0216] The first anode electrode AE1' to the third anode electrode AE3' can be electrically connected to the first reflective electrode RE1' to the third reflective electrode RE3', respectively. For example, each anode electrode can be electrically connected to the end (or edge) of the corresponding reflective electrode. However, the implementation is not limited to this. To improve the electrical connection characteristics between the anode electrode and the reflective electrode, the anode electrode can be electrically connected to the reflective electrode in various ways.

[0217] The first anode electrode AE1' to the third anode electrode AE3' may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). xIt is at least one of the transparent conductive materials selected from indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1' to the third anode electrode AE3' are not limited thereto. For example, the first anode electrode AE1' to the third anode electrode AE3' may include titanium nitride.

[0218] When viewed from a third-party perspective on DR3 (or in a plan view), the first anode electrode AE1' to the third anode electrode AE3' may have the same characteristics as... Figure 6 The first luminous region EMA1 to the third luminous region EMA3 have similar shapes.

[0219] The first anode electrodes AE1' to the third anode electrodes AE3' and the cathode electrode CE can reflect or at least partially reflect the incident light. Light emitted from the light-emitting layer of the light-emitting structure EMS' can be amplified by reciprocating between the anode electrode and the cathode electrode CE, and can be output through the cathode electrode CE. For example, each anode electrode and cathode electrode CE can provide a resonant structure in the corresponding sub-pixel. For example, the distance between each anode electrode and cathode electrode CE can be understood as the resonant distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0220] The first sub-pixel SP1 to the third sub-pixel SP3 can correspond to red, green, and blue, respectively. For example, the thickness of the first anode electrode AE1' and the third anode electrode AE3' in the third direction DR3 (e.g., the thickness direction) can be greater than the thickness of the second anode electrode AE2' by the thickness of the first buffer pattern BFP1' and the second buffer pattern BFP2'. Therefore, due to the first buffer pattern BFP1' and the second buffer pattern BFP2', the first sub-pixel SP1 and the third sub-pixel SP3 can have a shorter resonant distance than the second sub-pixel SP2. For example, the resonant distance of each sub-pixel can be adjusted so that light in the wavelength range of the corresponding color is effectively and efficiently amplified.

[0221] like Figure 14As depicted, the first buffer pattern BFP1' and the second buffer pattern BFP2' are shown as being disposed below the first anode electrode AE1' and the third anode electrode AE3', respectively, but the implementation is not limited thereto. For example, one of the first buffer pattern BFP1' and the second buffer pattern BFP2' may be omitted. As another example, the first buffer pattern BFP1' and the second buffer pattern BFP2' may be omitted. For example, the resonant distance between the corresponding anode electrode and the cathode electrode CE may be the same. As another example, a buffer pattern may be disposed below each of the first anode electrode AE1' to the third anode electrode AE3'. For example, the buffer patterns disposed below the corresponding anode electrode may have different thicknesses, and therefore, the resonant distances between the corresponding anode electrode and the cathode electrode CE may be different from each other. As described above, by providing a buffer pattern for adjusting the height of the anode electrode below at least one of the first anode electrode AE1' to the third anode electrode AE3', the resonant distance in each sub-pixel can be optimized.

[0222] A pixel-defining layer (PDL) may be disposed on portions of the first anode electrode AE1' to the third anode electrode AE3' and on the via layer VIAL. The pixel-defining layer (PDL) has an opening (OP) that exposes a portion of each of the first anode electrode AE1' to the third anode electrode AE3'. The region overlapping with the pixel-defining layer (PDL) can be understood as the boundary region (BDA) between adjacent sub-pixels.

[0223] The pixel-defining layer (PDL) may include a plurality of inorganic insulating layers stacked sequentially. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. However, the implementation is not limited thereto. For example, the pixel defining layer (PDL) may include an organic insulating layer.

[0224] The pixel limiting layer PDL' may include a first inorganic insulating layer ISL1' to a fourth inorganic insulating layer ISL4'. The first inorganic insulating layer ISL1' may cover portions of the first anode electrode AE1' to the third anode electrode AE3' and the via layer VIAL. A second inorganic insulating layer ISL2' may be disposed on the first inorganic insulating layer ISL1', a third inorganic insulating layer ISL3' may be disposed on the second inorganic insulating layer ISL2', and a fourth inorganic insulating layer ISL4' may be disposed on the third inorganic insulating layer ISL3'. The first inorganic insulating layer ISL1' and the third inorganic insulating layer ISL3' may include silicon nitride (SiN). x Furthermore, the second inorganic insulating layer ISL2' and the fourth inorganic insulating layer ISL4' may comprise silicon oxide (SiO2). xHowever, the implementation method is not limited to this. The first inorganic insulating layer ISL1' can be omitted.

[0225] The pixel-defined layer (PDL) may include separators (SPRs) in the boundary regions (BDAs) between adjacent subpixels. The separators (SPRs) may cause discontinuities, such as gaps (VDs), to form in the light-emitting structure (EMS). Due to these discontinuities, at least some of the multiple layers contained in the light-emitting structure (EMS) may be broken or bent.

[0226] The fourth inorganic insulating layer ISL4' may have a width in the first direction DR1 that is wider than that of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'. For example, the side surfaces of the second inorganic insulating layer ISL2' to the fourth inorganic insulating layer ISL4' adjacent to the opening OP' may be provided as separators SPR'.

[0227] refer to Figure 14 as well as Figure 13 The fourth inorganic insulating layer ISL4' may include a first portion P1 to a third portion P3. A second portion P2 may overlap (e.g., completely overlap) the second and third inorganic insulating layers ISL2' and ISL3' in a third direction DR3 (e.g., the thickness direction). The first portion P1 protrudes from the second portion P2 in a direction opposite to the first direction DR1. The third portion P3 protrudes from the second portion P2 in the first direction DR1. Therefore, the width of the fourth inorganic insulating layer ISL4' may be wider than the widths of the second and third inorganic insulating layers ISL2' and ISL3'. For example, during the manufacturing process, the second and third inorganic insulating layers ISL2' and ISL3' may be undercut to exclude portions overlapping with the first and third portions P1 and P3. For example, each of the first and third portions P1 and P3 of the fourth inorganic insulating layer ISL4' may have an eaves shape on the second and third inorganic insulating layers ISL2' and ISL3'.

[0228] In the boundary region BDA, the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have the same width in the first direction DR1. However, the implementation is not limited to this, and the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have different widths. For example, the second inorganic insulating layer ISL2' may have a wider width in the first direction DR1 than the third inorganic insulating layer ISL3'. As another example, the third inorganic insulating layer ISL3' may have a wider width in the first direction DR1 than the second inorganic insulating layer ISL2'.

[0229] In the second sub-pixel SP2, the first portion P1 of the fourth inorganic insulating layer ISL4' and the first side surface SSF1 of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' can be provided as a separator SPR'. Therefore, a first gap VD1' adjacent to the first portion P1 of the fourth inorganic insulating layer ISL4' can be formed in the light-emitting structure EMS'. In the third sub-pixel SP3, the third portion P3 of the fourth inorganic insulating layer ISL4' and the second side surface SSF2 of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' can be provided as another separator SPR'. Therefore, a second gap VD2' adjacent to the third portion P3 of the fourth inorganic insulating layer ISL4' can be formed in the light-emitting structure EMS'.

[0230] Some of the multiple layers stacked in the light-emitting structure EMS' can be disconnected or bent through the first gap VD1' and the second gap VD2'. For example, at least one charge-generating layer and at least one hole-injecting layer included in the light-emitting structure EMS can be disconnected through the first gap VD1' and the second gap VD2'. As described above, due to the separator SPR', the portions of the light-emitting structure EMS' included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated from each other.

[0231] The pixel-defining layer (PDL) may include additional separators, such that the light-emitting structure (EMS) may also include discontinuous portions in the boundary region (BDA). The PDL may include one or more trenches as separators in the boundary region (BDA). The trenches may penetrate one or more of the first inorganic insulating layers (ISL1) to the fourth inorganic insulating layers (ISL4). Due to the trenches, some of the multiple layers stacked in the light-emitting structure (EMS) (e.g., at least one charge-generating layer and at least one hole-injecting layer) may be broken or bent. The EMS may have a structure in which three light-emitting portions, each including a light-emitting layer, are stacked, and two charge-generating layers may be disposed between the three light-emitting portions. The PDL may include one or more trenches in the boundary region (BDA).

[0232] See again Figure 13The light-emitting structure EMS' can be disposed on the anode electrode AE ​​exposed by the opening OP' of the pixel-defining layer PDL'. The light-emitting structure EMS' can fill the opening OP' of the pixel-defining layer PDL' and can be disposed across (e.g., completely across) the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the light-emitting structure EMS' can be disconnected or bent in the boundary region BDA or in the region adjacent to the boundary region BDA by the separator SPR'. Therefore, during the operation of the display panel DP, the current flowing out of each of the first sub-pixel SP1 to the third sub-pixel SP3 through the layer included in the light-emitting structure EMS' can be reduced. Therefore, the first light-emitting element LD1' to the third light-emitting element LD3' can operate with relatively high reliability.

[0233] The light-emitting structure EMS' may include two light-emitting portions stacked sequentially, and each of the light-emitting portions may include a light-emitting layer that generates light according to an applied current. In other embodiments, the light-emitting structure EMS' may include three light-emitting portions stacked sequentially, and each of the light-emitting portions may include a light-emitting layer to generate light according to an applied current. A charge-generating layer may be disposed between the light-emitting portions.

[0234] The light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing.

[0235] The cathode electrode CE can be disposed on the light-emitting structure EMS'. The cathode electrode CE can be provided for the first sub-pixel SP1 to the third sub-pixel SP3.

[0236] The portions of the first anode electrode AE1', the light-emitting structure EMS' overlapping with the first anode electrode AE1' in the third direction DR3 (e.g., the thickness direction), and the portion of the cathode electrode CE overlapping with the first anode electrode AE1' in the third direction DR3 (e.g., the thickness direction) can constitute a first light-emitting element LD1'. The portions of the second anode electrode AE2', the light-emitting structure EMS' overlapping with the second anode electrode AE2' in the third direction DR3 (e.g., the thickness direction), and the portion of the cathode electrode CE overlapping with the second anode electrode AE2' in the third direction DR3 (e.g., the thickness direction) can constitute a second light-emitting element LD2'. The portions of the third anode electrode AE3', the light-emitting structure EMS' overlapping with the third anode electrode AE3' in the third direction DR3 (e.g., the thickness direction), and the portion of the cathode electrode CE overlapping with the third anode electrode AE3' in the third direction DR3 (e.g., the thickness direction) can constitute a third light-emitting element LD3'.

[0237] The encapsulation layer TFE can be disposed on the cathode electrode CE. The encapsulation layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL'.

[0238] The optical functional layer OFL, outer coating OC, and cover window CW can be disposed on the encapsulation layer TFE. The optical functional layer OFL, outer coating OC, and cover window CW can be respectively coupled with… Figure 7 The optical functional layer OFL, outer coating OC, and cover window CW are similarly configured. Repeated descriptions of these are omitted.

[0239] Figure 15 The embodiment shown includes Figures 7 to 11 or Figure 13 A schematic cross-sectional view of a portion of the light-emitting structure in one of the first to third light-emitting elements.

[0240] refer to Figure 15 The light-emitting structure can have a tandem structure in which the first light-emitting portion EU1 and the second light-emitting portion EU2 can be stacked in a third direction DR3 (e.g., the thickness direction). Figure 7 The light-emitting structure of each of the first light-emitting element LD1 to the third light-emitting element LD3 can be substantially the same.

[0241] Each of the first light-emitting portion EU1 and the second light-emitting portion EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting portion EU1 may include a first light-emitting layer EML1, a first electron transport portion ETU1, and a first hole transport portion HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport portion ETU1 and the first hole transport portion HTU1. The second light-emitting portion EU2 may include a second light-emitting layer EML2, a second electron transport portion ETU2, and a second hole transport portion HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport portion ETU2 and the second hole transport portion HTU2.

[0242] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc., as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0243] Each of the first electron transport section ETU1 and the second electron transport section ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer as needed. The first electron transport section ETU1 and the second electron transport section ETU2 may have the same configuration or different configurations.

[0244] A connecting layer, which can be provided in the form of a charge-generating layer CGL, can be disposed between the first light-emitting portion EU1 and the second light-emitting portion EU2 to electrically connect them to each other. The charge-generating layer CGL can have a stacked structure of p-type dopant layers and n-type dopant layers. For example, the p-type dopant layer can include p-type dopants such as HAT-CN, TCNQ, and NDP-9, and the n-type dopant layer can include alkali metals, alkaline earth metals, lanthanides, or combinations thereof. However, the implementation is not limited to this.

[0245] The first emissive layer EML1 and the second emissive layer EML2 can produce light of different colors. Light emitted from each of the first emissive layer EML1 and the second emissive layer EML2 can be mixed to be identified as white light. For example, the first emissive layer EML1 can produce blue light, and the second emissive layer EML2 can produce yellow light. The second emissive layer EML2 may include a structure in which a first sub-emissive layer producing red light and a second sub-emissive layer producing green light can be stacked. Red and green light can be mixed to provide yellow light. For example, an intermediate layer performing hole transport and / or preventing electron transport functions may also be provided between the first and second sub-emissive layers.

[0246] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of the same color.

[0247] The light-emitting structure can be formed by vacuum deposition, inkjet printing, etc., but the implementation method is not limited to these.

[0248] Figure 16 An embodiment according to another embodiment is shown, including Figures 7 to 11 or Figure 13 A schematic cross-sectional view of a portion of the light-emitting structure in one of the first to third light-emitting elements.

[0249] refer to Figure 16 The light-emitting structure can have a series structure in which the first light-emitting portion EU1' to the third light-emitting portion EU3' can be stacked in a third direction DR3 (e.g., the thickness direction). Figure 7 The light-emitting structure of each of the first light-emitting element LD1 to the third light-emitting element LD3 can be substantially the same.

[0250] Each of the first light-emitting portions EU1' to the third light-emitting portions EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting portion EU1' may include a first light-emitting layer EML1', a first electron transport portion ETU1', and a first hole transport portion HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport portion ETU1' and the first hole transport portion HTU1'. The second light-emitting portion EU2' may include a second light-emitting layer EML2', a second electron transport portion ETU2', and a second hole transport portion HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport portion ETU2' and the second hole transport portion HTU2'. The third light-emitting portion EU3' may include a third light-emitting layer EML3', a third electron transport portion ETU3', and a third hole transport portion HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport portion ETU3' and the third hole transport portion HTU3'.

[0251] Each of the first hole transport section HTU1' to the third hole transport section HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc., as needed. The first hole transport section HTU1' to the third hole transport section HTU3' may have the same configuration or different configurations.

[0252] Each of the first electron transport section ETU1' to the third electron transport section ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer as needed. The first electron transport section ETU1' to the third electron transport section ETU3' may have the same configuration or different configurations.

[0253] The first charge generation layer CGL1' can be disposed between the first light-emitting portion EU1' and the second light-emitting portion EU2'. The second charge generation layer CGL2' can be disposed between the second light-emitting portion EU2' and the third light-emitting portion EU3'.

[0254] The first emitting layer EML1' to the third emitting layer EML3' can produce light of different colors. The light emitted by each of the first emitting layer EML1' to the third emitting layer EML3' can be mixed to be considered as white light. For example, the first emitting layer EML1' can produce blue light, the second emitting layer EML2' can produce green light, and the third emitting layer EML3' can produce red light.

[0255] In other embodiments, two or more of the first light-emitting layers EML1' to the third light-emitting layers EML3' can produce light of the same color.

[0256] and Figure 15 and Figure 16 As shown, the light-emitting structure can include a light-emitting portion in each of the first light-emitting elements LD1 to the third light-emitting elements LD3. For example, the light-emitting portions included in the first light-emitting elements LD1 to the third light-emitting elements LD3 can emit light of different colors. For example, the light-emitting portion of the first light-emitting element LD1 can emit red light, the light-emitting portion of the second light-emitting element LD2 can emit green light, and the light-emitting portion of the third light-emitting element LD3 can emit blue light. For example, the light-emitting portions of the first sub-pixel SP1 to the third sub-pixel SP3 can be separated from each other, and each of them can be disposed in the pixel defining layer (see [link to image]). Figure 7 PDL and others Figure 13 The opening of PDL' in (see Figure 7 OP in etc. and Figure 13 In OP').

[0257] For example, at least some of the color filters CF1 to CF3 can be omitted.

[0258] Figure 17 An embodiment according to another embodiment is shown. Figure 5 A schematic top plan view of one of the pixels.

[0259] refer to Figure 17 The first pixel PXL1' may include the first sub-pixel SP1' to the third sub-pixel SP3'.

[0260] The first sub-pixel SP1' may include a first luminous region EMA1' and a non-luminous region NEA' surrounding the first luminous region EMA1'. The second sub-pixel SP2' may include a second luminous region EMA2' and a non-luminous region NEA' surrounding the second luminous region EMA2'. The third sub-pixel SP3' may include a third luminous region EMA3' and a non-luminous region NEA' surrounding the third luminous region EMA3'.

[0261] The first sub-pixel SP1' and the second sub-pixel SP2' can be set on the second direction DR2. The third sub-pixel SP3' can be set on the first direction DR1 relative to each of the first sub-pixel SP1' and the second sub-pixel SP2'. For example, the third sub-pixel SP3' can be set on the first direction DR1 parallel to the first sub-pixel SP1' and the second sub-pixel SP2'.

[0262] In the planar view, the second sub-pixel SP2' can have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' can have a larger area than the second sub-pixel SP2'. Therefore, in the planar view, the second light-emitting region EMA2' can have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' can have a larger area than the second light-emitting region EMA2'. However, the implementation is not limited to this. For example, the first sub-pixel SP1' and the second sub-pixel SP2' can have substantially the same area, and the third sub-pixel SP3' can have an area larger than each of the first and second sub-pixels SP1' and SP2'. Therefore, the areas of the first sub-pixels SP1' to the third sub-pixels SP3' can be varied depending on the implementation.

[0263] The planar shapes of reflective layers RF1 and RF2 can follow the planar shapes of the first light-emitting region EMA1' to the third light-emitting region EMA3'. For example, the planar shapes of reflective layers RF1 and RF2 can be similar to the planar shapes of the first light-emitting region EMA1' to the third light-emitting region EMA3', respectively.

[0264] Figure 18 An embodiment according to another embodiment is shown. Figure 5 A schematic top plan view of one of the pixels.

[0265] refer to Figure 18 The first sub-pixel SP1'' may include a first luminous region EMA1'' and a non-luminous region NEA'' surrounding the first luminous region EMA1''. The second sub-pixel SP2'' may include a second luminous region EMA2'' and a non-luminous region NEA'' surrounding the second luminous region EMA2''. The third sub-pixel SP3'' may include a third luminous region EMA3'' and a non-luminous region NEA'' surrounding the third luminous region EMA3''.

[0266] When viewed from a third-party perspective on DR3 (or in a planar view), the first sub-pixel SP1'' to the third sub-pixel SP3'' can have polygonal shapes. For example, the shapes of the first sub-pixel SP1'' to the third sub-pixel SP3'' can be as follows: Figure 18 The hexagonal shape shown.

[0267] When viewed on a third-party DR3 (or in a plan view), the first luminous region EMA1'' to the third luminous region EMA3'' may have a circular shape. However, the implementation is not limited to this. For example, each of the first luminous region EMA1'' to the third luminous region EMA3'' may have a polygonal shape.

[0268] The first sub-pixel SP1'' and the third sub-pixel SP3'' can be set on the first direction DR1. The second sub-pixel SP2'' can be set relative to the first sub-pixel SP1'' in a direction that is tilted at an acute angle (or diagonal) relative to the second direction DR2.

[0269] The planar shapes of reflective layers RF1 and RF2 can follow the planar shapes of the first light-emitting region EMA1'' to the third light-emitting region EMA3''. For example, the planar shapes of reflective layers RF1 and RF2 can be similar to the planar shapes of the first light-emitting region EMA1'' to the third light-emitting region EMA3'', respectively.

[0270] Figure 6 , Figure 17 and Figure 18 The positions of the sub-pixels shown are merely examples, and the implementation is not limited to them.

[0271] Each pixel may include two or more sub-pixels, which may be set differently. Each sub-pixel may have various shapes, and each of its luminous regions may also have various shapes.

[0272] Figure 19 A schematic block diagram of a display system according to an embodiment is shown.

[0273] refer to Figure 19 The display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0274] Processor 1100 can perform various tasks and calculations. Processor 1100 may include application processors, graphics processors, microprocessors, central processing units (CPUs), etc. Processor 1100 can be electrically connected to other components of display system 1000 via a bus system and enable their stepping.

[0275] like Figure 19 As shown, the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 is electrically connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0276] Through the first channel CH1, the processor 1100 can transmit a first image input IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image input IMG1 and the first control signal CTRL1. The first display device 1210 can be connected to a reference... Figure 1The described display device 100 is similarly configured. For example, the first image input IMG1 and the first control signal CTRL1 can be provided as follows: Figure 1 The input image is IMG and the control signal is CTRL.

[0277] Through the second channel CH2, the processor 1100 can transmit the second image input IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image input IMG2 and the second control signal CTRL2. The second display device 1220 can be connected to a reference... Figure 1 The described display device 100 is similarly configured. For example, a second image input IMG2 and a second control signal CTRL2 can be provided respectively as... Figure 1 The input image is IMG and the control signal is CTRL.

[0278] Display system 1000 may include computing systems that provide image display capabilities, such as portable computers, mobile phones, smartphones, tablet PCs, smartwatches, watch phones, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). Display system 1000 may include at least one of head-mounted display devices (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0279] Figure 20 It shows Figure 19 A schematic 3D diagram illustrating an application example of the display system.

[0280] refer to Figure 20 , Figure 19 The display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device worn on a user's head.

[0281] The head-mounted display device 2000 may include a headband 2100 and a display device housing 2200. The headband 2100 may be connected to the display device housing 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to a user's head. The horizontal strap may surround the side portion of the user's head, and the vertical strap may surround the upper portion of the user's head. However, the implementation is not limited to this. For example, the headband 2100 may be implemented in the form of an eyeglass frame, a helmet, etc.

[0282] The display device housing 2200 can accommodate Figure 19 The first display device 1210 and the second display device 1220. The display device housing 2200 can also accommodate... Figure 19 The processor is 1100.

[0283] Figure 21 It shows the wearable by the user Figure 20 An illustrative head-mounted display device.

[0284] refer to Figure 21 The first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 can be disposed in the head-mounted display device 2000. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0285] In the display device housing 2200, the right eye lens RLNS can be disposed between the first display panel DP1 and the user's right eye. In the display device housing 2200, the left eye lens LLNS can be disposed between the second display panel DP2 and the user's left eye.

[0286] The image output from the first display panel DP1 can be displayed to the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 to guide it to the user's right eye. The right eye lens RLNS can perform optical functions to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0287] The image output from the second display panel DP2 can be displayed to the user's left side via the left eye lens LLNS. The left eye lens LLNS refracts light from the second display panel DP2 to guide it to the user's left eye. The left eye lens LLNS performs optical functions to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0288] Each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens with a pancake-shaped cross-section. Each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens containing sub-regions with different optical properties. For example, each display panel outputs an image corresponding to a sub-region of the multi-channel lens, and the output image can pass through the sub-region and be viewed by the user.

[0289] In other embodiments Figure 19 The display system 1000 shown can be applied to smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, car displays, smart glasses, portable multimedia players (PMPs), navigation systems, ultra-mobile computers (UMPCs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0290] A method for manufacturing a display device according to the above embodiments will then be described.

[0291] Figures 22 to 28 A schematic cross-sectional view of the manufacturing process steps of a display device according to an embodiment is shown. For better understanding and ease of description, the illustrations have been simplified, and redundant descriptions have been omitted.

[0292] refer to Figure 22 A first organic layer OL1 can be formed on the encapsulation layer TFE. The first anode electrode AE1, the light-emitting structure EMS, and / or the cathode electrode CE (including the encapsulation layer TFE) have been referenced. Figures 1 to 21 Detailed descriptions will be provided, therefore redundant descriptions will be omitted.

[0293] The first organic layer OL1 can be formed using acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), but is not necessarily limited to these.

[0294] refer to Figure 23 The first organic layer OL1 can be etched to form a first tilted surface S1. The first tilted surface S1 may overlap with the pixel-defining layer PDL in a third direction DR3 (e.g., the thickness direction). The first tilted surface S1 may not overlap with the opening OP of the pixel-defining layer PDL in a third direction DR3 (e.g., the thickness direction), but is not limited thereto.

[0295] refer to Figure 24 Next, a first reflective layer RF1 can be formed on the first organic layer OL1. The first reflective layer RF1 can be formed (e.g., directly) on the first organic layer OL1. The first reflective layer RF1 can be formed on the first inclined surface S1.

[0296] The first reflective layer RF1 can be formed of a metallic material. For example, the first reflective layer RF1 can be formed of at least one alloy of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and two or more materials selected therefrom, but the embodiments are not limited thereto. In some embodiments, the first reflective layer RF1 can be formed with a structure in which inorganic films can be alternately stacked in a third direction DR3 (e.g., the thickness direction). For example, the first reflective layer RF1 can be formed with silicon oxide (SiO2) in the form of... x ) and titanium oxide (TiO) x A structure that can be stacked alternately in a third direction DR3 (e.g., the thickness direction).

[0297] refer to Figure 25 Then, a second organic layer OL2 can be formed on the first organic layer OL1 and / or the first reflective layer RF1. The second organic layer OL2 can be formed using acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), but is not necessarily limited to these. The second organic layer OL2 can be formed from the same material as the first organic layer OL1, but is not limited to these.

[0298] refer to Figure 26 Then, the second organic layer OL2 can be etched to form the second tilted surface S2. In some embodiments, the first organic layer OL1 can be partially etched during the process of forming the second tilted surface S2. The tilt angle of the second tilted surface S2 can be different from the tilt angle of the first tilted surface S1. For example, the tilt angle of each of the tilted surfaces S1 and S2 can mean the angle formed by each of the tilted surfaces S1 and S2 with respect to the substrate SUB. Taking into account the light emission path of the light emitted from the light-emitting structure EMS, the tilt angle of the first tilted surface S1 and / or the tilt angle of the second tilted surface S2 can be varied.

[0299] The second tilted surface S2 may overlap with the opening OP of the pixel-defining layer PDL in the third direction DR3 (e.g., the thickness direction). The second tilted surface S2 may partially overlap with the pixel-defining layer PDL in the third direction DR3 (e.g., the thickness direction), but is not limited thereto.

[0300] refer to Figure 27 A second reflective layer RF2 can be formed on the second organic layer OL2. The second reflective layer RF2 can be formed (e.g., directly) on the second organic layer OL2. The second reflective layer RF2 can be formed on the second inclined surface S2.

[0301] The second reflective layer RF2 can be made of a metallic material. For example, the second reflective layer RF2 can be made of at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the second reflective layer RF2 can be formed of at least one of silver (Ag), magnesium (Mg), and mixtures thereof.

[0302] refer to Figure 28A third organic layer OL3 may be formed on the second organic layer OL2 and / or the second reflective layer RF2. The third organic layer OL3 may be formed using acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), but is not necessarily limited to these. The third organic layer OL3 may be made of the same material as the first organic layer OL1 and / or the second organic layer OL2, but is not limited to these.

[0303] Subsequently, a passivation layer PSV can be formed on the third organic layer OL3 to form Figure 12 The optical layer OPL. The aforementioned display device can be achieved by forming a color filter layer CFL, an outer coating OC, and / or a cover window CW on the optical layer OPL.

[0304] When using microlenses to form optical layers through injection or etching, defects such as inaccurate microlens alignment or microlens shape deformation may occur. Therefore, by forming the optical layer OPL using the organic layer OL and reflective layers RF1 and RF2 according to the method described above, the process can be simplified, defects caused by microlenses can be improved, and the light output efficiency of the display device can be improved.

[0305] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from the description. Therefore, this disclosure is not limited to these embodiments, but rather to the broader scope of the claims and various apparent modifications and equivalent arrangements.

Claims

1. A display device, characterized by comprising: include: First electrode; A pixel-defining layer is disposed on the first electrode; A light-emitting component is disposed on the first electrode and the pixel defining layer; A second electrode is disposed on the light-emitting component; An organic layer is disposed on the second electrode; A first reflective layer is contained within the organic layer; as well as A second reflective layer is disposed on top of the first reflective layer within the organic layer. In the thickness direction, the first reflective layer overlaps with the pixel defining layer, and the second reflective layer overlaps with the light-emitting component.

2. The display device according to claim 1, characterized in that, The planar area of ​​the first reflective layer is larger than the planar area of ​​the second reflective layer.

3. The display device according to claim 1, characterized in that, The pixel defining layer includes an opening that overlaps with the first electrode in the thickness direction, and The second reflective layer overlaps with the opening in the thickness direction.

4. The display device according to claim 1, characterized in that, The first reflective layer includes a first opening.

5. The display device according to claim 4, characterized in that, The second reflective layer includes a second opening.

6. The display device according to claim 5, characterized in that, The planar dimensions of the first opening are larger than those of the second opening.

7. The display device according to claim 1, characterized in that, The first reflective layer and the second reflective layer include inclined surfaces.

8. The display device according to claim 1, characterized in that, The first reflective layer and the second reflective layer include spherical surfaces.

9. The display device according to claim 1, characterized in that, The pixel definition layer includes a separator, and The light-emitting component is at least partially separated by the separator.

10. An electronic device, comprising: include: Display device, including light-emitting elements disposed on a substrate, The light-emitting element includes: First electrode; A pixel-defining layer is disposed on the first electrode; A light-emitting component is disposed on the first electrode and the pixel defining layer; A second electrode is disposed on the light-emitting component; An organic layer is disposed on the second electrode; A first reflective layer, within the organic layer; and A second reflective layer is disposed on top of the first reflective layer within the organic layer. In the thickness direction, the first reflective layer overlaps with the pixel defining layer, and the second reflective layer overlaps with the light-emitting member.

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