Time-of-flight sensor

Abstract

Some embodiments of the present disclosure disclose a time-of-flight sensor. The time-of-flight sensor includes a bottom die and a top die, wherein the bottom die includes a light emitting diode and a logic region on a semiconductor substrate, and the top die includes an image sensor. The top die is positioned above and electrically connected to the logic region of the bottom die, such that the light emitting diode is adjacent to the image sensor, and an opaque wall is positioned between the light emitting diode and the image sensor to separate the light emitting diode and the image sensor to block a direct light path. The time-of-flight sensor is small in area and height, and has reduced power consumption.

Description

Technical Field

[0001] This disclosure pertains to time-of-flight sensors. Background Technology

[0002] Time-of-flight (ToF) measurements of light emitted by a light source can be used to measure the distance between the light source and the target. This measurement is based on the detection of light rays from the light source, which are reflected back to the detector from the target. Utility Model Content

[0003] According to some embodiments of the present disclosure, a time-of-flight sensor includes a bottom die and a top die, wherein the bottom die includes a semiconductor substrate, a light-emitting diode located on the semiconductor substrate, and a logic region located on the semiconductor substrate, and the top die includes a substrate and an image sensor located in the substrate, and the top die is bonded above the logic region of the bottom die.

[0004] According to some embodiments of this disclosure, a time-of-flight sensor includes a bottom die and a top die, wherein the bottom die includes a light-emitting diode and a logic region located on a semiconductor substrate, and the top die includes an image sensor. The top die is located above and electrically connected to the logic region of the bottom die, and an opaque wall is located between the light-emitting diode and the image sensor.

[0005] According to some embodiments of this disclosure, a time-of-flight sensor includes an image sensor located in a semiconductor substrate, a light-emitting diode located on the semiconductor substrate and adjacent to the image sensor, and a protective layer located on the semiconductor substrate and above the image sensor, wherein the protective layer exposes a central source / drain electrode and peripheral source / drain electrodes of the image sensor. The time-of-flight sensor also includes a dielectric layer located on the semiconductor substrate, and at least one contact extending from the peripheral source / drain electrodes of the image sensor into the dielectric layer. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A This is a cross-sectional view of a first embodiment of a time-of-flight (ToF) sensor according to some embodiments of the present disclosure, wherein the ToF sensor includes a light-emitting diode (LED) and an image sensor; this sensor is a back-side-illuminated (BSI) sensor.

[0008] Figure 1B yes Figure 1A A plan view of the ToF sensor;

[0009] Figure 1C This is a cross-sectional view of a second embodiment of the ToF sensor;

[0010] Figure 1D This is a cross-sectional view of a third embodiment of the ToF sensor;

[0011] Figure 2A This is a cross-sectional view of another embodiment of a ToF sensor according to some embodiments of the present disclosure; this sensor is a front-side-illuminated (FSI) sensor;

[0012] Figure 2B yes Figure 2A A plan view of the ToF sensor;

[0013] Figure 3A and Figure 3B Together, a flowchart is formed to illustrate a first method for manufacturing a ToF sensor according to some embodiments; specifically, this method is used to manufacture a backlight ToF sensor, such as... Figure 1A As shown;

[0014] Figure 4 This is a side cross-sectional view of the bottom grain substrate after n-type wells and p-type wells are formed on the first side of the substrate;

[0015] Figure 5 This is a side cross-sectional view of the bottom die substrate after transistors have been formed in n-type and p-type wells;

[0016] Figure 6 It is a side cross-sectional view of the bottom die substrate after the interconnect layer, including metal wiring and contact vias, has been formed;

[0017] Figure 7 This is a side cross-sectional view of the bottom die substrate after etching the interconnect layer in the LED region;

[0018] Figure 8 This is a side cross-sectional view of the bottom die substrate after light-emitting diode material has been applied to form an LED;

[0019] Figure 9 This is a side cross-sectional view of the top grain substrate after the formation of the first deep well and the first dopant type channel in the substrate.

[0020] Figure 10 This is a side cross-sectional view of the top grain substrate after forming a second deep well of the first dopant type and a first well of the second dopant type at different depths around the channel;

[0021] Figure 11 It is a side cross-sectional view of the top grain substrate after the first doped electrode forming the contact channel and the second doped electrode within the first well of the second doped type;

[0022] Figure 12 It is a side cross-sectional view of the top die substrate after the interconnect layer, including metal wiring and contact vias, has been formed;

[0023] Figure 13 This is a side cross-sectional view of the top grain substrate after the deep trench has been formed;

[0024] Figure 14 This is a side cross-sectional view of the top grain substrate after filling deep trenches to form opaque walls;

[0025] Figure 15 This is a side cross-sectional view of the top grain substrate after the carrier wafer has been applied and the substrate has been ground to expose the first deep well of the first dopant type.

[0026] Figure 16 This is a side cross-sectional view of the top-grain substrate after it has been flipped.

[0027] Figure 17 A flowchart illustrating a second method for manufacturing a ToF sensor is shown according to some embodiments; specifically, this method is used to manufacture a front-illuminated ToF sensor, such as... Figure 2A As shown;

[0028] Figure 18 It is a side cross-sectional view of the substrate after forming a first deep well of the first dopant type, a channel of the first dopant type in the substrate, and forming a second deep well of the first dopant type around the channel at a depth different from that of the first deep well.

[0029] Figure 19 This is a side cross-sectional view of the substrate after the first well of the second dopant type is formed around the channel; one or more wells, a gate dielectric layer and a gate electrode are also formed in the light-emitting diode region;

[0030] Figure 20 It is a side cross-sectional view of the substrate after the source / drain electrodes are formed in one or more wells in the channel, the first well of the second dopant type, and the light-emitting diode region;

[0031] Figure 21 This is a side cross-sectional view of the substrate after a protective layer has been formed over the image sensor; the source / drain electrodes of the image sensor remain exposed.

[0032] Figure 22 It is a side cross-sectional view of the substrate after the dielectric layer and electrical interconnects are formed; at least one contact extends from the peripheral source / drain electrode of the image sensor;

[0033] Figure 23 This is a side cross-sectional view of the substrate after a deep trench has been formed in the dielectric layer between the light-emitting diode region and the image sensor.

[0034] Figure 24 This is a side cross-sectional view of the substrate after filling deep trenches to form opaque walls;

[0035] Figure 25 This is a side cross-sectional view of the substrate after etching the dielectric layer in the LED region;

[0036] Figure 26 A flowchart illustrating a method for measuring distance using a ToF sensor is shown according to some embodiments;

[0037] Figure 27 This is a schematic diagram of an apparatus that includes a ToF sensor and measures the distance to a target, according to some embodiments.

[0038] [Symbol Explanation]

[0039] 101: Sensor

[0040] 102: Second Embodiment

[0041] 103: Third Embodiment

[0042] 104: Sensor System / Sensor

[0043] 110: First grain / bottom grain

[0044] 120:Substrate

[0045] 121: First side / top surface

[0046] 122: Light Emitting Diode Area

[0047] 123: Second side

[0048] 124: Logical Region

[0049] 126: Image sensor area

[0050] 130: Light Emitting Diode

[0051] 131: Length

[0052] 132: Electrical interconnects

[0053] 133: Light Emitting Diode Space

[0054] 134: Color Filter

[0055] 140: Transistor

[0056] 142: Transistor / Active Device

[0057] 144: Transistor / Active Device

[0058] 146: Transistor / Active Device

[0059] 148: Electrical interconnects

[0060] 150: Trap

[0061] 152: Trap

[0062] 154: Trap

[0063] 156: Trap

[0064] 160: Interconnection Layer

[0065] 161: Top surface

[0066] 162: Dielectric materials

[0067] 164: Metal wiring

[0068] 166: Contact element through hole

[0069] 168: Joint gasket

[0070] 170: Opaque wall

[0071] 172: Protective layer

[0072] 174: Dielectric layer

[0073] 175: Top surface

[0074] 176: Contact element

[0075] 180: Gate dielectric layer

[0076] 182: Gate electrode

[0077] 184: Source / Drain Electrode

[0078] 210: Second die package / top die

[0079] 220:Substrate

[0080] 221: First side / first surface

[0081] 223: Second side / second surface

[0082] 230: Image sensor

[0083] 240: First Deep Trap

[0084] 243: Width

[0085] 245: First Depth

[0086] 247: Height / Thickness

[0087] 250: Channel

[0088] 251: Width

[0089] 252: Electrode

[0090] 257: Height / Thickness

[0091] 260: Second deep trap

[0092] 261: Thickness

[0093] 263: Internal width

[0094] 265: External width

[0095] 267: Width

[0096] 270: First Trap

[0097] 271: Thickness

[0098] 273: Internal width

[0099] 275: Second Depth

[0100] 277: Width

[0101] 278: Electrode

[0102] 280: Interconnection Layer

[0103] 281: First side

[0104] 282: Dielectric materials

[0105] 284: Metal wiring

[0106] 286: Contact element through hole

[0107] 288: Joint gasket

[0108] 290: Opaque wall

[0109] 291: Length

[0110] 292: Trench

[0111] 294: Carrier wafer

[0112] 300: Method

[0113] 310,312,314,316,318,320,325,327,329,330,335,337,350,352,354,356,358,360,362,364,366,368,370,372,374: Step 400: Method

[0114] 410,410,412,414,416,418,420,422,424,426,428,430,432,434,436,438,440,442,444: Step 500: Method

[0115] 505, 510, 515: Step 520: Apparatus

[0116] 530: Target

[0117] 540: Arrow

[0118] 550: Arrow

[0119] DNW: Deep n-type well

[0120] HVNW: High-voltage n-type well Detailed Implementation

[0121] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0122] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0123] The numerical values ​​in this disclosure and the claims should be understood to include the same numerical values ​​when reduced to the same number of significant digits, and numerical values ​​that differ from the stated numerical values ​​by less than the experimental error of the conventional measurement techniques used to determine the numerical values ​​as described in this disclosure. All ranges disclosed herein include the stated endpoints.

[0124] The term "about" can be used to include any numerical value that can vary without altering its fundamental function. When used with a range, "about" also indicates a range defined by the absolute values ​​of its two endpoints; for example, "about 2 to about 4" also indicates a range "from 2 to 4". The term "about" can also refer to a number plus or minus 10%.

[0125] This disclosure relates to structures composed of different layers. When the term "on / upon" is used to refer to two different layers (including a substrate), it simply means that one layer is on top of the other. These terms do not require that the two layers be in direct contact with each other and allow other layers to be between the two layers. For example, all layers in the structure can be considered "on" the substrate, even if these layers are not in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other, with no layer between them. Furthermore, when referring to performing process steps on a substrate, it should be interpreted as performing such steps on any layers that may be present on the substrate, depending on the context.

[0126] The terms "annular" or "annulus" refer to a planar shape formed by the region between two concentric shapes with parallel edges. For example, these terms could refer to an annulus defined by two concentric circles, or a shape contained between two squares with a common center and parallel edges.

[0127] As used in this disclosure, the term "die" refers to a combination of one or more integrated circuits (also known as wafers or microwafers) and interconnect layers that allow the integrated circuit(s) to communicate with one or more other dies. Examples of interconnect layers may include redistribution layers (RDLs) or interposers with bonding pads or C4 bumps or pillars. A die may have interconnect layers on only one side or both sides.

[0128] This disclosure relates to various sensors / systems or modules for measuring the distance between two objects, and methods for manufacturing and using such sensors. The systems / modules operate based on time-of-flight (ToF) and are formed from two semiconductor chips. The resulting sensors are significantly smaller than conventional systems, with reduced surface area and reduced height / thickness. The sensors also feature reduced power consumption and do not require the conventionally large housing to separate the light source from the image sensor.

[0129] Figure 1A A side cross-sectional view of a first example of a ToF sensor 101 formed by the hybrid bonding of two semiconductor dies is illustrated according to some embodiments of the present disclosure, and some features are shown. Figure 1B yes Figure 1A A plan view of the sensor. This particular system is a back-side-illuminated (BSI) sensor.

[0130] The sensor 101 includes two semiconductor dies: a first die 110 (or bottom die) and a second die package 210 (or top die). First refer to... Figure 1A The bottom die 110 includes a substrate 120 having a light-emitting diode region 122 and a logic region 124. An interconnect layer 160 is present on a first side or top surface 121 of the substrate. One or more active devices, such as transistors 140, are present in the light-emitting diode region of the substrate. Transistors 140 are electrically connected to light-emitting diodes (LEDs) 130 via electrical interconnects 132. The logic region 124 also includes one or more active devices, such as transistors, in the substrate. Three transistors 142, 144, and 146 are illustrated in this figure. Electrical interconnects 148 extend from the active devices in the logic region to the top surface 161 of the interconnect layer 160.

[0131] Each transistor is formed within a well of either a first dopant type or a second dopant type. The first and second dopant types are different in charge; that is, one is positively charged and the other is negatively charged. If the first dopant type is an n-type dopant, then the second dopant type is a p-type dopant, and vice versa. As shown in the attached figure, the first dopant type is n-type and the second dopant type is p-type.

[0132] As shown in the accompanying drawings, transistors 140, 142, and 146 are located within wells 150, 152, and 156 of the first dopant type, and transistor 144 is located within well 154 of the second dopant type. In the logic region, it should be noted that transistors 142, 144, and 146 alternate, with the second dopant type well 154 located between two first dopant type wells 152 and 156. This may vary depending on whether an n-type metal-oxide-semiconductor (NMOS) or p-type metal-oxide-semiconductor (PMOS) is required. Note that only one transistor 140 is shown in the LED region 122. The well types in the LED region 122 and the logic region 124 can vary as needed, and there is no necessary relationship between their types. For example, transistor 140 in the LED region may be located within a p-type well or an n-type well, while wells 152, 154, and 156 in the logic region need not be changed.

[0133] Next, interconnect layer 160 is formed of dielectric material 162 and includes electrical interconnects in the light-emitting diode region and logic region, including horizontally oriented metal routing 164 and vertically oriented contact vias 166, which are electrically connected to the source / drain electrodes of transistors 142, 144, and 146. Bonding pads 168 are electrically connected to the metal routing and contact vias, and are present on the first surface or top surface 161 of interconnect layer 160.

[0134] The top die 210 includes a substrate 220 and an image sensor 230 formed in the substrate. The substrate has a first side or first surface 221 and a second side or second surface 223 spaced apart from each other, and the first surface 221 and the second surface 223 define the thickness of the substrate.

[0135] Image sensors are avalanche photodiodes, such as single-photon avalanche diodes (SPADs). Avalanche processing can be triggered at very low intensity, down to a single photon. When the reverse-biased pn junction receives additional energy from the incident light, this energy causes charge carriers to separate. At sufficiently high energies, these charge carriers cause further charge carrier separation, generating an avalanche effect that causes current to flow through the diode.

[0136] In this accompanying drawing, the image sensor (such as a SPAD) includes a first deep well 240 of a first dopant type, located at a first depth 245 measured relative to a first side 221 of the substrate, shown in this drawing as along a second side 223 of the substrate 220. A first dopant type channel 250 contacts the first deep well 240 of the first dopant type and extends toward the first side 221. A first dopant type electrode 252 contacts the first dopant type channel 250 and is present along the first side 221 of the substrate.

[0137] refer to Figure 1A and Figure 1B A second deep well 260 of the first dopant type is located around a first deep well 240 of the first dopant type. The second deep well 260 of the first dopant type is located at a second depth 275, different from the first depth 245. The second deep well 260 of the first dopant type is also located around a channel 250 of the first dopant type. A first well 270 of the second dopant type is also located around a first deep well 240 of the first dopant type. The first well 270 of the second dopant type is also located around a channel 250 of the first dopant type. The first well 270 of the second dopant type contacts the second deep well 260 of the first dopant type and is also present on a first side 221 of the substrate. One or more electrodes 278 of the second dopant type are present within the first well 270 of the second dopant type. Two electrodes 278 are shown in this figure.

[0138] like Figure 1B As shown, a first deep well 240 of the first dopant type is surrounded by both a second deep well 260 of the first dopant type and a first well 270 of the second dopant type. The second deep well 260 and the first well 270 of the second dopant type are each formed in a ring around the first deep well 240 of the first dopant type. The first well 270 of the second dopant type has an inner width 273, and the first deep well 240 of the first dopant type has a width 243 smaller than the inner width 273. Metal wiring 284 is shown extending beyond the dimensions of the image sensor 230. Electrodes 278 are also indicated by dashed lines in the figures.

[0139] Next, an interconnect layer 280 exists above the first side 221 of the substrate. The interconnect layer 280 includes a dielectric material 282 having horizontally oriented metal wiring 284 and vertically oriented contact vias 286, the metal wiring 284 and contact vias 286 being electrically connected to electrodes 252 and 278. A bonding pad 288 is electrically connected to the metal wiring and contact vias and is present on the first side 281 of the interconnect layer 280.

[0140] In some embodiments, an opaque wall 290 is present on at least one side of the top grain 210. The opaque wall 290 is located outside the first well 270 of the second dopant type. Figure 1A As shown, the opaque wall 290 extends through both the substrate 220 and the interconnect layer 280. Figure 1B As shown, in some embodiments, the opaque wall 290 may have a length 291 greater than or equal to the length 131 of the light-emitting diode 130. The opaque wall is intended to block any direct light path from the light-emitting diode 130 to the image sensor 230, so that the image sensor 230 only captures light reflected from the target. However, the opaque wall is optional, and in some envisioned embodiments, the opaque wall is not present.

[0141] Subsequently, the first side 281 of the interconnect layer of the top die 210 is bonded to the first surface or top surface 161 of the interconnect layer of the bottom die 110. The top die 210 is located above the logic region 124 of the bottom die. The first doped electrode 252 of the top die is electrically connected to the active device 144 located within the first doped well 154. Similarly, the second doped electrode(s) 278 of the top die are electrically connected to the active devices 142 and 146 located within the second doped wells 152 and 156. It should be noted that the metal wiring 164 and 284 allow the image sensor 230 to be connected to the desired number of active devices, and the image sensor 230 is not necessarily connected only to... Figure 1A The three transistors shown are 142, 144, and 146.

[0142] Figure 1C This is a cross-sectional view of a second embodiment 102 of the ToF sensor. In this figure, the opaque wall 290 is located only within the substrate 220 of the top die and does not extend through the interconnect layer 280. Furthermore, a color filter 134 is present on the light-emitting diode 130. This may be desirable in some applications.

[0143] Figure 1D This is a cross-sectional view of a third embodiment 103 of the ToF sensor. In this figure, an opaque wall 170 also extends through the interconnect layer 160 of the bottom die 110. An opaque wall 290 of the top die extends through the substrate 220 and the interconnect layer 280. The two opaque walls 170 and 290 are aligned with each other to form a single wall extending through the sensor / system.

[0144] Figure 2A This is a cross-sectional view of another embodiment of the ToF sensor system 104 according to some embodiments of the present disclosure. Figure 2B This is a plan view. This particular system is a front-side-illuminated (FSI) sensor.

[0145] The substrate 120 has a light-emitting diode region 122 and an image sensor region 126. Similarly, one or more active devices, such as transistors 140, are present in the light-emitting diode region of the substrate. The transistors 140 are electrically connected to the light-emitting diodes 130 via electrical interconnects 132.

[0146] Continuing on, Figure 2A The image sensor 230 has a connection with Figure 1A A similar structure is described and illustrated in the figure. Similarly, the image sensor includes a first deep well 240 of a first dopant type located at a first depth 245. A first dopant type channel 250 contacts the first deep well 240 of the first dopant type, and as shown in the figure, the channel 250 extends to a first side 121 (or top side) of the substrate. A first dopant type electrode 252 is present within the first dopant type channel 250 and contacts the first side 121 of the substrate. A first dopant type second deep well 260 is located around the first deep well 240 of the first dopant type at a second depth 275 different from the first depth 245. The first dopant type second deep well 260 is also located around the first dopant type channel 250. A second dopant type first well 270 is also located around the first deep well 240 of the first dopant type and contacts the first dopant type second deep well 260, and is also present on the first side 121 of the substrate. One or more second dopant type electrodes 278 are present within the second dopant type first well 270. Two electrodes 278 are illustrated in this figure. The electrode 252 of the first dopant type can also be called the center source / drain electrode, and the electrodes 278 of the second dopant type can also be called the peripheral source / drain electrodes.

[0147] A protective layer 172 is present on the substrate above the image sensor 230. Electrodes 252 and 278 are at least partially exposed, or in other words, the protective layer does not completely cover the electrodes. A dielectric layer 174 is present on the first side 121 of the substrate. The dielectric layer extends over both the light-emitting diode region 122 and the image sensor region 126. At least one contact 176 extends from the peripheral source / drain electrode 278 into the dielectric layer. The contacts(multiple) 176 will collect electrons during SPAD operation.

[0148] An opaque wall 290 exists on the substrate and extends from the top surface 175 through the dielectric layer 174 to a first side 121 of the substrate. The opaque wall 290 is located between the light-emitting diode 130 and the image sensor 230, or between the light-emitting diode region 122 and the image sensor region 126. Similarly, as... Figure 2B As shown, in some embodiments, the opaque wall 290 may have a length 291 that is greater than or equal to the length 131 of the light-emitting diode 130.

[0149] exist Figure 2B In the figure, the long dashed line represents the perimeter of the first well 270 of the second dopant type beneath the protective layer 172. The short dashed line represents the perimeter of the first deep well 240 of the first dopant type. The central electrode 252, the peripheral electrode 278, and the contact 176 are also labeled in the figure.

[0150] Figure 3A and Figure 3B Together, they form a flowchart illustrating a method for manufacturing time-of-flight sensors, more specifically, method 300 for a backlit ToF sensor. Some steps of method 300 are also described in... Figures 4 to 16 The following is an illustration. The method steps are discussed based on the formation of a single sensor, but should also be interpreted broadly as applicable to the simultaneous formation of multiple sensor assemblies. Additional steps may be performed between the steps described herein, and some steps are omitted only for clarity. Not all method steps require obtaining the structure disclosed herein. Furthermore, some steps in the method may be performed simultaneously, or some steps may be performed in a different order than shown or described in this figure. The bottom and top dies can be manufactured separately and then combined. The construction of the bottom die is described first.

[0151] First, refer to Figure 4 The bottom die is formed on and within the substrate 120. The substrate is made of a semiconductor material and is provided in wafer form. Such semiconductor material may include silicon, for example, in crystalline Si form. In alternative embodiments, the substrate may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide, or gallium indium phosphide. In a particular embodiment, the wafer substrate is silicon.

[0152] The substrate 120 of the bottom die has a first side 121 and an opposing second side 123. The substrate 120 of the bottom die includes a light-emitting diode region 122 and a logic region 124. Next, as... Figure 3A As shown in step 310, an active device is formed in the light-emitting diode region 122 and the logic region 124. For example... Figure 3A As shown in step 312 and as Figure 4 As shown, one or more wells of a first dopant type and one or more wells of a second dopant type are formed in the substrate. This is done on the first side 121 of the substrate. Four wells are shown in this figure: three wells 150, 152, and 156 are shown as n-type wells, and one well 154 is shown as a p-type well. For example, this can be accomplished using a separate ion implantation step.

[0153] Implanting various ions into a silicon lattice modifies the conductivity of the lattice at the implantation site, allowing the fabrication of different parts of an optical modulator. An ion implantation machine typically includes an ion source, a beam line, and a process chamber. The ion source generates the desired ions, which act as dopants to alter various properties at desired locations in the substrate. For example, dopants with polarities different from the substrate are used to form positive and negative electrical contacts. Common p-type dopants include boron, gallium, or indium. Common n-type dopants include phosphorus or arsenic. The resulting ion beam enters the beam line, which organizes the ions into a beam with high purity, ion mass, energy, and species. The ion beam is then used to irradiate the wafer substrate in the process chamber.

[0154] For wells 150, 152, 154, and 156, the implantation depth is designed to be the same for both dopant types. However, the dopant energy level will depend on the dopant size and atomic weight, and therefore may vary.

[0155] Next, as Figure 3A As shown in step 314, refer to Figure 5 Transistors 140, 142, 144, and 146 are formed in the well. In step 316, a dielectric layer is formed on the substrate and patterned to form the gate dielectric layer 180 of each transistor. In step 318, gate material is deposited and patterned to form the gate electrode 182 of each transistor. The gate electrode 182 is located on the gate dielectric layer 180 of each transistor. The gate material can be, for example, polysilicon or a conductive metal. These deposition steps can be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Next, in... Figure 3A In step 320, source / drain (S / D) electrodes 184 are formed in wells 150, 152, 154, and 156. It should be noted that p-type electrodes are formed in each n-type well, and n-type electrodes are formed in each p-type well. If necessary, the source / drain electrodes can be formed before forming the gate dielectric layer and the gate electrode. The resulting structure is as follows... Figure 5 As shown. It should be noted that more than one transistor may be formed in the light-emitting diode region 122. In some embodiments, the LED may be driven by 4 to 7 transistors.

[0156] Next, as Figure 3A As shown in step 325 and as Figure 6As shown, an interconnect layer 160 is formed. The interconnect layer 160 includes a dielectric material 162 and conductive components within the dielectric material. The interconnect layer can also be considered a redistribution layer (RDL). As shown in the accompanying figure, the conductive components include metallic wiring 164 and contact vias 166. However, in general, any circuit with any desired structure and composed of any desired components is conceivable. The interconnect layer 160 can be formed in several different steps that build several smaller layers together to form the interconnect layer. For example, a first dielectric layer can be deposited, followed by etching to form openings filled with conductive material, thereby obtaining metallic wiring or contact vias. Non-limiting examples of suitable conductive materials may include metals such as copper, aluminum, gold, tungsten, iron, ruthenium, iridium, and their alloys. This can be repeated to position the conductive components in the desired locations. A bonding pad 168 is also formed on the top surface 161 of the interconnect layer.

[0157] If you wish to manufacture Figure 1D In the embodiments, such as Figure 3A As shown in step 327, a trench can be formed in the interconnect layer between the light-emitting diode region 122 and the logic region 124. This is typically performed by patterning and etching. The trench extends from the top surface 161 of the interconnect layer to the first side 121 of the substrate. Next, in Figure 3A In step 329, the groove is filled with an opaque material to form an opaque wall 170. The opaque material does not allow light to pass through the opaque wall. For example, the opaque material can be a metal such as aluminum or copper.

[0158] Continuing on, such as Figure 3A As shown in step 330 and as Figure 7 As shown, an interconnect layer 160 is etched in the light-emitting diode region 122 to form a light-emitting diode space 133. Next, as... Figure 3A As shown in step 335 and as Figure 8 As shown, a light-emitting diode 130 is formed by filling the space between light-emitting diodes with a light-emitting diode material. In some embodiments, the light-emitting diode material may also be an organic light-emitting diode (OLED) material. The resulting structure corresponds to Figure 1A The bottom grain is 110. If required... Figure 1C The color filter 134 shown is in Figure 3A In optional step 337, a color filter is applied to the light-emitting diode 130. It should be noted that although the opaque wall 170 is described as being formed before the formation of the light-emitting diode 130, the opaque wall may also be formed subsequently.

[0159] The formation of image sensors (such as SPADs) in the top die will now be discussed. (See reference...) Figure 9The top grain is also formed on and within the substrate 220. The substrate may be as described above. The substrate 220 with the top grain also has a first side 221 and an opposing second side 223. Next, as Figure 3B As shown in step 350, an image sensor is formed in the substrate 220. The image sensor may be formed in multiple steps.

[0160] exist Figure 3B In step 352, a first deep well 240 of the first dopant type is formed in the substrate at a first depth 245 relative to the first surface 221. The first deep well of the first dopant type can be considered as being close to the second side 223 of the substrate. Next, in step 354, a channel 250 of the first dopant type is formed in the substrate. The channel contacts the first deep well 240 of the first dopant type at one end and extends toward the first side 221 of the substrate. The first deep well of the first dopant type and the channel can be formed in separate ion implantation steps. It should be noted in particular that it is not necessary to form the channel in one ion implantation step, but rather the channel can be formed in multiple implantation steps (e.g., by varying the implantation energy to allow ions to diffuse at the channel depth).

[0161] As shown in the attached figure, the width 243 of the first deep well of the first dopant type is greater than the width 251 of the channel. Furthermore, the height / thickness 247 of the first deep well of the first dopant type is less than the height / thickness 257 of the channel.

[0162] Continuing on, in Figure 3B In step 356, such as Figure 10 As shown, a second deep well 260 of the first dopant type is formed around a first deep well 240 of the first dopant type at a second depth 275, different from the first depth 245. The second deep well 260 of the first dopant type can also be described as being formed around the channel 250. Next, in step 358, a first well 270 of the second dopant type is formed on a first side 221 of the substrate. In other words, the first well 270 of the second dopant type is exposed on the first side 221 of the substrate. The first well 270 of the second dopant type also contacts the second deep well 260 of the first dopant type. The first well 270 of the second dopant type is also located around the first deep well 240 or the channel 250 of the first dopant type (when viewed from a plan view). The second deep well 260 and the first well 270 of the second dopant type can also be formed using ion implantation.

[0163] In a particular embodiment, the thickness 261 of the second deep well 260 of the first dopant type is approximately equal to the thickness 271 of the first well 270 of the second dopant type. As previously described, both the second deep well 260 of the first dopant type and the first well 270 of the second dopant type have annular shapes. In a particular embodiment, the width 267 of the second deep well 260 and the width 277 of the first well 270 may also be approximately equal to each other. Other values ​​and ranges of these properties are also within the scope of this disclosure.

[0164] As shown in the figure, channel 250 does not extend to the first side 221 of the substrate. Next, as... Figure 3B The optional step 360 is shown and as follows Figure 11 As shown, a source / drain electrode 252 of the first doped type is formed. It can be formed using ion implantation. Such a source / drain electrode can also be considered a center source / drain electrode, and such a source / drain electrode contacts the channel 250. However, in some embodiments, it is conceivable that the channel 250 actually extends to a first side 221 of the substrate, and in such cases, the channel can act as a source / drain electrode. Next, in... Figure 3B In step 362, one or more source / drain electrodes 278 of the second dopant type are formed within the first well 270 of the second dopant type. As a result, an image sensor 230 is formed.

[0165] Next, in Figure 3B In step 364, such as Figure 12 As shown, an interconnect layer 280 is formed on a first side 221 of the substrate. The interconnect layer 280 includes a dielectric material 282 and conductive components within the dielectric material, such as metal wiring 284, contact vias 286, and bonding pads 288. The interconnect layer can be formed by repeated steps of deposition and etching to obtain the desired structure.

[0166] exist Figure 3B In optional step 366 and as follows Figure 13 As shown, trench 292 is formed. This is typically performed by patterning and etching. In this embodiment, trench 292 extends from a first side 281 of the interconnect layer into the substrate, extending at least to a first depth 245 where a first deep well 240 of a first dopant type is located. Trench 292 is formed on at least one side of the image sensor 230, and in some embodiments may surround the entire image sensor. Figure 3B In optional step 368 and as follows Figure 14 As shown, the trench is filled with an opaque material to form an opaque wall 290. Similarly, the opaque material can be a metal such as aluminum or copper, or an opaque dielectric material. If... Figure 1C As shown in the embodiment, if it is desired to form an opaque wall 290 only in the substrate 220, then steps 366 and 368 are performed before step 364 of forming the interconnect layer 280.

[0167] Continuing on, in Figure 3B In step 370 and as Figure 15 As shown, a carrier wafer 294 is applied to the first side 281 of the interconnect layer 280. Next, in step 372, the second side 223 of the substrate 220 is polished to remove excess material until the first deep well 240 of the first dopant type is exposed.

[0168] Figure 16 The top die 210 is shown after the carrier wafer 294 has been flipped and removed. Next, in Figure 3B In step 374, the top die 210 is bonded to the bottom die 110. More specifically, the top die is bonded over the logic region 124 of the bottom die. The top die is aligned such that the opaque wall 290 of the top die is positioned between the light-emitting diode 130 and the image sensor 230. As shown, the bonding pad 288 of the top die is aligned with the bonding pad 168 of the bottom die. Fusion bonding, such as hybrid bonding, can be used to bond the two dies together to obtain a ToF sensor.

[0169] In this regard, hybrid bonding refers to the formation of an interconnect between two dies using both dielectric bonding and metal bonding. Each die includes a dielectric layer containing multiple metal bonding pads. The dielectric layer on each package is activated (typically via plasma) to be hydrophilic. When the metal bonding pads of the two dies are aligned and the dielectric layers of the two dies are joined together, the dielectric layers are bonded together, referred to herein as a hybrid bonding layer. The dual-die system is then annealed, causing the metal pads to bond together, and the metal pads expand and fill any gaps. The resulting sensor 101 is as follows: Figure 1A As shown.

[0170] Figure 17 A flowchart illustrating a method for manufacturing a time-of-flight sensor, more specifically a front-illuminated ToF sensor, is shown. Some steps of the method are also described below. Figures 18 to 25 The following is illustrated in the figure. Similarly, the method steps are discussed below in terms of forming a single sensor, but should be interpreted broadly as applicable to forming multiple sensor components simultaneously. Additional steps may be performed between the steps described herein, and some steps are omitted only for clarity. Not all method steps require the structure disclosed herein. Furthermore, some steps in the method may be performed simultaneously, or some steps may be performed in a different order than shown or described in this figure.

[0171] First refer to Figure 18 The substrate 120 has a first side 121 and an opposite second side 123. The substrate 120 also includes a light-emitting diode region 122 and an image sensor region 126.

[0172] Next, as Figure 17 As shown in step 410, an image sensor (such as a SPAD) is formed in the image sensor region of the substrate. The image sensor can be formed in multiple steps, similar to... Figure 3B The steps for the top grain 210 described in the text.

[0173] exist Figure 17 In step 412, such as Figure 18 As shown, a first deep well 240 of the first dopant type is formed in the substrate at a first depth 245. The first deep well of the first dopant type can be considered as being close to the second side 123 of the substrate. Next, in step 414, a channel 250 of the first dopant type is formed in the substrate. The channel contacts the first deep well 240 of the first dopant type at one end and extends to the first side 121 of the substrate. In other words, the channel is exposed on the first side 121 of the substrate. In step 416, a second deep well 260 of the first dopant type is formed around the first deep well 240 of the first dopant type at a second depth 275 different from the first depth 245. The second deep well 260 of the first dopant type can also be described as being formed around the channel 250. It should be noted that steps 414 and 416 can be performed in any order. These steps can be performed by ion implantation. Similarly, if necessary, multiple implantation steps can be used to form the channel.

[0174] As shown in the accompanying drawings, the second deep well 260 of the first dopant type has an inner width 263 and an outer width 265. The first deep well 240 of the first dopant type may have a width 243 greater than the inner width 263, while in this embodiment, the width 243 is approximately equal to the outer width 265.

[0175] Next, in Figure 17 In step 418 and as Figure 19 As shown, a first well 270 of the second dopant type is formed on the first side 121 of the substrate. Similarly, the first well 270 of the second dopant type is exposed on the first side 121 of the substrate and also contacts the second deep well 260 of the first dopant type. This can be accomplished using ion implantation.

[0176] Continuing on, in Figure 17 In step 420, one or more transistors are formed in the light-emitting diode region in multiple steps. In step 422, one or more wells 150 are formed in the light-emitting diode region. If the well 150 is of a first dopant type, the well 150 may be formed simultaneously with a portion of the channel 250. If the well 150 is of a second dopant type, the well 150 may be formed simultaneously with a first well 270 of the second dopant type. Alternatively, the well 150 may be formed in a separate separate ion implantation step.

[0177] exist Figure 17In step 424, a dielectric layer is formed and patterned on the substrate to form the gate dielectric layer 180 of each transistor. In step 426, gate material is deposited and patterned to form the gate electrode 182 of each transistor. The gate electrode 182 is located on the gate dielectric layer 180. The resulting structure is as follows: Figure 19 As shown.

[0178] exist Figure 17 In step 428 and as Figure 20 As shown, one or more source / drain electrodes of a first dopant type are formed on the substrate. In the image sensor region, a source / drain electrode 252 of the first dopant type contacts the channel 250, or alternatively, is formed within the channel. Such an electrode may also be referred to as the central source / drain electrode of the image sensor, although it is not necessary in some embodiments. As shown, two source / drain electrodes 184 of the first dopant type are also formed within the well 150 in the light-emitting diode region to form a transistor 140.

[0179] exist Figure 17 In step 430, one or more source / drain electrodes of the second dopant type are formed on the substrate. As shown in the accompanying drawings, two source / drain electrodes 278 of the second dopant type are also formed within the first well 270 of the second dopant type in the image sensor. These electrodes may also be referred to as peripheral source / drain electrodes of the image sensor. The resulting structure is as follows. Figure 20 As shown.

[0180] exist Figure 17 In step 432 and as Figure 21 As shown, a protective layer 172 is formed on the substrate 120 and above the image sensor 230. The shape of the protective layer exposes the central source / drain electrode 252 and the peripheral source / drain electrode 278 in the plan view, as shown. Figure 2B As shown. In a particular embodiment, the protective layer is a resist protective oxide (RPO) layer. The RPO layer may be a dielectric material, such as silicon dioxide, silicon oxynitride, or other suitable materials.

[0181] Next, in Figure 17 In step 434 and as Figure 22 As shown, a dielectric layer 174 is formed on a first side 121 of the substrate. Electrical interconnects 132 are also formed within the dielectric layer, for example, in the light-emitting diode region. At least one contact 176 extends from the peripheral source / drain electrode 278 into the dielectric layer. Two contacts 176 are illustrated in this figure. The dielectric layer 174 and at least one contact 176 can be formed by repeated steps of deposition and etching (dielectric material and conductive material) to obtain the desired structure.

[0182] Continuing on, in Figure 17 In optional step 436 and as Figure 23 As shown, a trench 292 is formed in the dielectric layer 174. The trench 292 extends from the top surface 175 of the dielectric layer to a first side 121 of the substrate. The trench 292 is formed between the light-emitting diode region 122 and the image sensor region 126, and in some embodiments may surround the entire image sensor. Figure 17 In optional step 438 and as Figure 24 As shown, the groove is filled with an opaque material to form an opaque wall 290.

[0183] Next, as Figure 17 As shown in step 440 and as Figure 25 As shown, a dielectric layer 174 is etched in the light-emitting diode region 122 to form a light-emitting diode space 133. Next, as... Figure 17 As shown in step 442, the light-emitting diode space is filled with light-emitting diode material to form a light-emitting diode 130. The resulting structure corresponds to... Figure 2A Sensor 104. In optional step 444, a color filter may be applied if necessary.

[0184] The above-described embodiments of the structures and methods of this disclosure pertain to dielectric layers. Such dielectric layers can generally be made of any suitable dielectric material or a combination thereof, but the characteristics of any particular layer can be further defined. Examples of dielectric materials may include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and silicon oxynitride (SiO2). x N y ), Hafnium oxynitride (HfO) x N y Zirconium oxynitride (ZrO) x N y ), Hafnium silicate (HfSi) x O y ), zirconium silicate (ZrSi) x O y ), silicon carbide (SiC) x O y N zAlternatively, it can be hexagonal boron nitride (hBN). Other dielectric materials may include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polycrystalline silicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), and borosilicate glass (BSG). The dielectric layer may be formed by any suitable method, including chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, or other suitable methods.

[0185] It should also be noted that some conventional steps are not explicitly described in the above discussion. For example, a pattern / structure can be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer to form a mask, and then etching through the mask to transfer the pattern to a given layer.

[0186] Generally, photoresist layers can be applied, for example, by spin coating or by spraying, roller coating, dip coating, or extrusion coating. The photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. The photoresist layer is then patterned by exposure to radiation. In a particular embodiment, extreme ultraviolet light with a wavelength of approximately 13.5 nm is used for patterning because the use of extreme ultraviolet light allows for smaller feature sizes. This results in some portions of the photoresist layer being exposed to radiation, while some portions of the photoresist are not exposed. Such exposure causes some portions of the photoresist to dissolve in the developer, while other portions remain insoluble in the developer. The photoresist layer is then developed using a developer. During the development step, the soluble portions of the photoresist layer are dissolved and washed away, leaving the photoresist pattern (i.e., the mask).

[0187] Next, a portion of a given layer beneath the patterned photoresist mask is exposed. An etching step transfers the photoresist pattern to the given layer beneath the patterned photoresist mask. After use, the mask can be removed, for example, using various solvents or by dry etching using oxygen plasma.

[0188] Generally, any etching step described herein may be performed using wet etching, dry etching, plasma etching processes (such as reactive ion etching (RIE) or inductively coupled plasma (ICP)) or combinations thereof, as appropriate. Etching may be anisotropic. Depending on the material, the etchant may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), fluorinated carbon, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), the like, or combinations thereof in various proportions. For example, silicon dioxide can be wet-etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry-etched using various mixtures of CHF3, O2, CF4, and / or H2.

[0189] Figure 26 This is a flowchart illustrating method 500 for measuring distance using a time-of-flight sensor. Method 500 will also refer to... Figure 27 To elaborate.

[0190] First refer to Figure 27 Sensor 101 is illustrated within a suitable device 520, such as a mobile phone, watch, glasses, or a vehicle such as a car. Sensor 101 includes an image sensor 230 and a light source such as a light-emitting diode 130. A target 530 is also included in the illustration, and the distance between the device 520 and the target 530 needs to be measured. It should be noted that such distance measurement can be used, for example, to provide feedback and control the distance between the device and the target, or to change the focus of a camera lens.

[0191] exist Figure 27 In step 505, light is emitted from the LED toward the target. Such a light path is illustrated by arrow 540. In step 510, the light reflected from the target returns toward the image sensor 230 and is captured by the image sensor 230. Such a light path is illustrated by arrow 550. In step 515, the distance is determined. The distance determination can be performed in a logic area or another area of ​​the device.

[0192] At least two techniques can be used to measure time of flight. In the direct method, a start signal is synchronized with the light source, and when reflected light is detected, the detector generates a stop signal. The time difference between the start and stop signals is evaluated to determine the distance. In the indirect method, a continuous sinusoidal light wave is emitted, and the phase difference between the emitted and incident signals is measured. This phase difference is used in a predetermined algorithm to determine the time difference.

[0193] The sensors of the embodiments of this disclosure have several advantages. First, compared to conventional structures without additional process steps or additional masking, the sensors of the embodiments of this disclosure offer better process and quality control. The entire sensor can also be manufactured in a single location. This reduces costs and increases yield. Production cycle time is also shortened. The sensor size is reduced. It is believed that the sensor area can be reduced by more than 50% and the sensor height / thickness by more than 70% compared to conventional sensors. Any housing in which the sensor is placed can be much smaller than conventional housings. The sensor also reduces power consumption. Therefore, the sensor can be used in small devices such as watches, mobile phones, glasses or other small mobile systems, as well as large devices that may be useful for distance measurement, such as vehicles.

[0194] Therefore, some embodiments of this disclosure relate to a method of manufacturing a time-of-flight sensor. A light-emitting diode and a logic region are formed on a semiconductor substrate of a bottom die. An image sensor is formed in a substrate of a top die. The top die is bonded over the logic region of the bottom die. When an opaque wall is present, it is placed between the light-emitting diode and the image sensor to obtain the time-of-flight sensor.

[0195] In some embodiments, the method further includes forming an opaque wall in at least the substrate of the top die, wherein the opaque wall is positioned between the light-emitting diode and the image sensor during the period when the top die is bonded over the logic region.

[0196] Other embodiments disclosed herein relate to a time-of-flight sensor, wherein the time-of-flight sensor includes a bottom die and a top die. The bottom die includes a light-emitting diode and a logic region on a semiconductor substrate. The top die includes an image sensor in the substrate. The top die is located above and electrically connected to the logic region of the bottom die. When an opaque wall is present, the opaque wall is located between the light-emitting diode and the image sensor.

[0197] Top dies that can be used to manufacture time-of-flight sensors are also described in various embodiments herein. Top dies include image sensors and opaque walls in the substrate.

[0198] In some embodiments, the opaque wall is made of metal.

[0199] A method for forming a top grain is also described in various embodiments herein. A first deep well of a first dopant type is formed in a substrate at a first depth. A channel of the first dopant type is formed to contact the first deep well. A second deep well of the first dopant type is formed around the channel in the substrate at a second depth. The first well of the second dopant type is formed on a first side of the substrate, and the first well is located around the channel and contacts the second deep well of the first dopant type. A source / drain electrode of the first dopant type is formed to contact the channel. A source / drain electrode of the second dopant type is formed within the first well of the second dopant type. An interconnect layer is formed on the first side of the substrate, and the interconnect layer includes metal wiring and contact vias. An opaque wall is formed at least in the substrate (and may penetrate the interconnect layer), and the opaque wall is located on at least one side outside the first well of the second dopant type. The opaque wall is completed by etching trenches and then filling the trenches with an opaque material.

[0200] In some embodiments, the first dopant type is an n-type dopant and the second dopant type is a p-type dopant, or the first dopant type is a p-type dopant and the second dopant type is an n-type dopant. In some embodiments, the source / drain electrodes of the first dopant type on the top die are electrically connected to an active device located in a logic region on the bottom die and within a well of the first dopant type, or the source / drain electrodes of the second dopant type on the top die are electrically connected to an active device located in a logic region on the bottom die and within a well of the second dopant type. In some embodiments, the method further includes polishing a second side of the substrate to expose a first deep well of the first dopant type.

[0201] In various embodiments, this disclosure also relates to various embodiments of a bottom die that can be used to manufacture a time-of-flight sensor. The bottom die includes a light-emitting diode (LED) and a logic region on a semiconductor substrate. The logic region includes active devices, such as transistors. An interconnect layer is formed on a first side of the substrate, and the interconnect layer includes metal wiring and contact vias. In certain embodiments, there is an opaque wall that extends through the interconnect layer and may extend into the substrate. The opaque wall is located between the LED and the logic region.

[0202] In some embodiments, the bottom die further includes an interconnect layer on the semiconductor substrate and an opaque wall extending through the interconnect layer between the light-emitting diode and the logic region, wherein the opaque wall of the bottom die is aligned with the opaque wall of the top die. In some embodiments, the image sensor includes an avalanche photodiode. In some embodiments, the time-of-flight sensor further includes a color filter on the light-emitting diode.

[0203] In various embodiments, this disclosure also relates to various embodiments of a method for forming a bottom die. Active devices are formed in the logic region and the light-emitting diode (LED) region of a semiconductor substrate. An interconnect layer is then formed on the substrate, and the interconnect layer includes metal wiring and contact vias. The interconnect layer is etched in the LED region to form LED spaces. The LED spaces are then filled with LED material to form LEDs. Opaque walls are formed by etching trenches and then filling the trenches with an opaque material.

[0204] In various embodiments, this disclosure also relates to various embodiments of other time-of-flight sensors, such as front-illuminated sensors. The time-of-flight sensor includes an image sensor located in a semiconductor substrate. A light-emitting diode (LED) is located on the substrate and adjacent to the image sensor. A protective layer is located on the substrate and above the image sensor, exposing the central source / drain electrode and peripheral source / drain electrode of the image sensor. A dielectric layer is located on the substrate. At least one contact extends from the peripheral source / drain electrode of the image sensor into the dielectric layer. An opaque wall may be present in the dielectric layer, and when present, the opaque wall may be located between the LED and the image sensor.

[0205] In some embodiments, the protective layer is a resistive protective oxide. In some embodiments, the image sensor includes an avalanche photodiode, such as a single-photon avalanche photodiode. In some embodiments, the image sensor includes a first deep well of a first dopant type located at a first depth in a semiconductor substrate, a first dopant type channel contacting the first deep well and extending toward the front side of the semiconductor substrate, a second deep well of the first dopant type located at a second depth in the semiconductor substrate and surrounding the first deep well, a first well of the second dopant type adjacent to the front side of the semiconductor substrate and surrounding the first deep well and contacting the second deep well of the first dopant type, a source / drain electrode of the first dopant type contacting the channel, and a source / drain electrode of the second dopant type located within the first well of the second dopant type.

[0206] A method for manufacturing such a time-of-flight sensor is also described in various embodiments herein. In the image sensor region, a first deep well of a first dopant type is formed at a first depth in a semiconductor substrate. A channel of the first dopant type is formed contacting the first deep well. A second deep well of the first dopant type is formed at a second depth around the channel in the substrate. The first well of the second dopant type is formed on a first side of the substrate, and the first well is located around the channel and contacts the second deep well of the first dopant type. An active device, such as a transistor, is then formed in the light-emitting diode region. In the image sensor region, source / drain electrodes of the first dopant type are formed contacting the channel. Source / drain electrodes of the second dopant type are formed within the first well of the second dopant type. Source / drain electrodes are simultaneously formed for the transistor in the light-emitting diode region. A protective layer is formed over the image sensor. A dielectric layer is formed on a first side of the substrate, and an interconnect layer includes electrical interconnects and at least one contact extending from the peripheral source / drain electrodes. An opaque wall may be formed at least in the dielectric layer between the light-emitting diode region and the image sensor region (possibly through the interconnect layer). Opaque walls can be formed by etching trenches and then filling the trenches with an opaque material. A dielectric layer is etched in the LED region to form LED spaces. These spaces are then filled with LED material to form the LED.

[0207] In various embodiments, this disclosure also relates to various embodiments of other time-of-flight sensors. A time-of-flight sensor includes a bottom die and a top die, wherein the bottom die includes a semiconductor substrate, a light-emitting diode (LED) on the semiconductor substrate, and a logic region on the semiconductor substrate, and the top die includes a substrate and an image sensor located within the substrate, the top die being bonded over the logic region of the bottom die. In some embodiments, the top die further includes a first deep well of a first dopant type at a first depth in the substrate, a channel of a first dopant type located in the substrate and contacting the first deep well, a second deep well of a first dopant type located at a second depth in the substrate and surrounding the channel, a first well of a second dopant type located on a first side of the substrate and surrounding the channel and contacting the second deep well, a source / drain electrode of a first dopant type contacting the channel, a source / drain electrode of a second dopant type located within the first well of the second dopant type, and an interconnect layer located on the first side of the substrate and comprising metal wiring and a plurality of contact vias. In some embodiments, the top die further includes an opaque wall located outside the first well of the second dopant type in the substrate. In some embodiments, the source / drain electrodes of the first dopant type are electrically connected to a first active device located in a logic region and within a well of the first dopant type, or the source / drain electrodes of the second dopant type are electrically connected to a second active device located in a logic region and within a well of the second dopant type.

[0208] Other embodiments disclosed herein relate to devices including the time-of-flight sensor described herein. These devices may be mobile phones, watches, glasses, automobiles, motor-driven or battery-powered vehicles, etc.

[0209] Some further embodiments of this disclosure also relate to methods for measuring the distance between a device and a target using such a time-of-flight sensor. Light is emitted towards the target from a light-emitting diode. The light reflected from the target is captured by an image sensor. Timing information is then used to determine the distance.

[0210] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A time-of-flight sensor, characterized in that, include: A bottom die includes a semiconductor substrate, a light-emitting diode located on the semiconductor substrate, and a logic region located on the semiconductor substrate; and A top die includes a substrate and an image sensor located in the substrate, wherein the top die is bonded above the logic region of the bottom die.

2. The time-of-flight sensor as claimed in claim 1, characterized in that, The top grain further includes: A first deep well of a first dopant type, located at a first depth in the substrate; A channel of the first dopant type is located in the substrate and contacts the first deep well; A second deep well of the first dopant type is located at a second depth in the substrate and is located around the channel; A first well of a second dopant type is located on a first side of the substrate and around the channel, wherein the first well contacts the second deep well of the first dopant type. The first dopant type of source / drain electrode contacts the channel; A source / drain electrode of the second dopant type is located within the first well of the second dopant type; and An interconnect layer is located on the first side of the substrate, wherein the interconnect layer includes metal wiring and a plurality of contact vias.

3. The time-of-flight sensor as described in claim 2, characterized in that, The top grain further includes: An opaque wall is located outside the first well of the second dopant type in the substrate.

4. The time-of-flight sensor as claimed in claim 2, characterized in that, The source / drain electrodes of the first dopant type are electrically connected to a first active device, which is located in the logic region and within a well of the first dopant type; or The source / drain electrode of the second dopant type is electrically connected to a second active device, which is located in the logic region and within a well of the second dopant type.

5. A time-of-flight sensor, characterized in that, include: A bottom die includes a light-emitting diode and a logic region located on a semiconductor substrate; and A top die includes an image sensor. The top die is located above the logic region of the bottom die and is electrically connected to the logic region of the bottom die, and an opaque wall is located between the light-emitting diode and the image sensor.

6. The time-of-flight sensor as claimed in claim 5, characterized in that, The top grain further includes the opaque wall in a substrate.

7. The time-of-flight sensor as claimed in claim 6, characterized in that, The bottom die further includes an interconnect layer located on the semiconductor substrate, and an opaque wall of the interconnect layer extending through the light-emitting diode and the logic region, wherein the opaque wall of the bottom die is aligned with the opaque wall of the top die.

8. The time-of-flight sensor as claimed in claim 5, characterized in that, The image sensor includes an avalanche photodiode.

9. A time-of-flight sensor, characterized in that, include: An image sensor is located in a semiconductor substrate; A light-emitting diode is located on the semiconductor substrate and adjacent to the image sensor; A protective layer is located on the semiconductor substrate and above the image sensor, wherein the protective layer exposes a central source / drain electrode and a peripheral source / drain electrode of the image sensor. A dielectric layer is located on the semiconductor substrate; and At least one contact extends from the peripheral source / drain electrode of the image sensor into the dielectric layer.

10. The time-of-flight sensor as claimed in claim 9, characterized in that, The image sensor includes: A first deep well of a first dopant type, located at a first depth in the semiconductor substrate; A channel of the first dopant type contacts the first deep well and extends toward a front side of the semiconductor substrate; A second deep well of the first dopant type is located at a second depth in the semiconductor substrate and is located around the first deep well; A first well of a second dopant type is adjacent to the front side of the semiconductor substrate, located around the first deep well, and in contact with the second deep well of the first dopant type. The first dopant type of source / drain electrode contacts the channel; and A source / drain electrode of the second dopant type is located within the first well of the second dopant type.

Images