Chip and electrostatic protection circuit for clock signal

Abstract

The application provides a chip and an electrostatic protection circuit of a clock signal. The chip comprises a clock signal sending unit, a clock signal receiving unit, a first protection clamping circuit arranged in the clock signal sending unit, a second protection clamping circuit arranged in the clock signal receiving unit, and an electrostatic protection circuit arranged between the clock signal sending unit and the clock signal receiving unit. The clock signal sending unit is used for generating a clock signal and sending the clock signal to the clock signal receiving unit. The first protection clamping circuit is used for eliminating an overshoot voltage generated by the clock signal in the clock signal sending unit. The second protection clamping circuit is used for eliminating an overshoot voltage generated by the clock signal in the clock signal receiving unit. The electrostatic protection circuit is used for adjusting an overshoot voltage amplitude of the clock signal in a transmission process, so that a back flush voltage amplitude of the clock signal after overshoot is in a preset voltage range.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to an electrostatic discharge protection circuit for a chip and clock signal. Background Technology

[0002] In printed circuit boards, the clock signal serves as the core reference for synchronizing the operation of various circuit modules, and its stability and accuracy directly determine the performance of the entire system. Once the clock signal becomes disordered, it can lead to data processing deviations and transmission errors, or even cause hardware device malfunctions or system-wide crashes. Therefore, the clock signal's anti-interference capability is a key indicator that must be ensured in hardware design.

[0003] Among various interference factors, static electricity has a particularly prominent impact on clock signals: electrostatic interference exhibits typical pulse waveform characteristics, such as... Figure 1 As shown, its frequency can reach up to 500MHz. This frequency range highly overlaps with the operating frequency band of the reference clock in the hardware circuit, making the reference clock extremely susceptible to electrostatic coupling interference. When the electrostatic interference signal is superimposed on the clock signal, it will form... Figure 2 The interference, resembling a superposition of oscillating waves, becomes one of the main causes of hardware circuit failures. However, current solutions for dealing with electrostatic interference in clock signals lack an effective approach that balances interference suppression with cost control, failing to meet users' dual demands for hardware system reliability and economy. Utility Model Content

[0004] To overcome the problems existing in related technologies, this application provides an electrostatic discharge protection circuit for chips and clock signals.

[0005] According to a first aspect of the embodiments of this application, a chip is provided, including: a clock signal transmitting unit, a clock signal receiving unit, a first protective clamping circuit disposed inside the clock signal transmitting unit, a second protective clamping circuit disposed inside the clock signal receiving unit, and an electrostatic discharge protection circuit disposed between the clock signal transmitting unit and the clock signal receiving unit.

[0006] The clock signal transmitting unit is used to generate a clock signal and send it to the clock signal receiving unit;

[0007] The first protective clamping circuit is used to eliminate the overshoot voltage generated by the clock signal inside the clock signal transmitting unit;

[0008] The second protective clamping circuit is used to eliminate the overshoot voltage generated by the clock signal inside the clock signal receiving unit;

[0009] The electrostatic discharge protection circuit is used to adjust the overshoot voltage amplitude of the clock signal during transmission so that the overshoot voltage amplitude of the clock signal is within a preset voltage range.

[0010] According to a second aspect of the present application, an electrostatic discharge protection circuit for a clock signal is provided, disposed between a clock signal transmitting unit and a clock signal receiving unit inside a chip, wherein the clock signal transmitting unit is used to generate a clock signal and send it to the clock signal receiving unit.

[0011] The electrostatic discharge protection circuit includes a first resistor, a signal transmission line, a first capacitor, and a second resistor; the first resistor, the signal transmission line, and the second resistor are connected in series between the signal transmitting unit and the signal receiving unit; one end of the first capacitor is connected to the signal transmission line, and the other end is connected to the ground terminal.

[0012] The first resistor, the first capacitor, and the second resistor are used to adjust the overshoot voltage amplitude of the clock signal during transmission so that the overshoot voltage amplitude of the clock signal is within a preset voltage range.

[0013] The technical solutions provided in this application embodiment may include the following beneficial effects:

[0014] In this embodiment, protective clamping circuits are respectively set inside the clock signal transmitting unit and the receiving unit inside the chip, and an external electrostatic discharge protection circuit is built between the two. This forms a collaborative protection mechanism in which the internal protective clamping circuit eliminates the clock signal overshoot voltage and the external electrostatic discharge protection circuit adjusts the amplitude of the clock signal backflush voltage. This achieves the goal of improving the anti-electrostatic interference capability of the clock signal in a low-cost manner, ensuring that the clock signal can still be transmitted stably in an electrostatic environment and effectively avoiding system failures caused by electrostatic interference.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this application, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] Figure 1 This is a waveform diagram of electrostatic interference according to an exemplary embodiment of this application.

[0018] Figure 2 This is a waveform diagram of a clock signal and its superimposed electrostatic interference, according to an exemplary embodiment of this application.

[0019] Figure 3This is a schematic diagram of the structure of a chip according to an exemplary embodiment of this application.

[0020] Figure 4 This is a waveform diagram of a clock signal superimposed with electrostatic interference, according to an exemplary embodiment of this application.

[0021] Figure 5 This is a schematic diagram of the structure of another chip according to an exemplary embodiment of this application.

[0022] Figure 6 This is a schematic diagram of another electrostatic discharge protection circuit according to an exemplary embodiment of this application. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0024] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0025] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0026] In printed circuit boards, the clock signal serves as the core reference for synchronizing the operation of various circuit modules, and its stability and accuracy directly determine the performance of the entire system. Once the clock signal becomes disordered, it can lead to data processing deviations and transmission errors, or even cause hardware device malfunctions or system-wide crashes. Therefore, the clock signal's anti-interference capability is a key indicator that must be ensured in hardware design.

[0027] Among various interference factors, static electricity has a particularly prominent impact on clock signals: electrostatic interference exhibits typical pulse waveform characteristics, such as... Figure 1 As shown, its frequency can reach up to 500MHz. This frequency range highly overlaps with the operating frequency band of the reference clock in the hardware circuit, making the reference clock extremely susceptible to electrostatic coupling interference. When the electrostatic interference signal is superimposed on the clock signal, it will form... Figure 2 The interference, resembling a superposition of oscillating waves, becomes one of the main causes of hardware failure. However, current solutions for electrostatic interference in clock circuits lack an effective approach that balances interference suppression with cost control, failing to meet users' dual demands for hardware system reliability and economy.

[0028] Based on this, to address the insufficient anti-electrostatic interference (ESI) solutions for clock signals in related technologies, this application provides a chip and an ESI protection circuit for clock signals. This chip establishes protective clamping circuits within both the clock signal transmitting and receiving units, while simultaneously building an external ESI protection circuit between them. This forms a collaborative protection mechanism where the internal protective clamping circuit eliminates clock signal overshoot voltage, and the external ESI protection circuit adjusts the amplitude of clock signal backflash voltage. This achieves the goal of improving the ESI resistance of clock signals at low cost, ensuring stable transmission of clock signals even in ESI environments and effectively preventing system failures caused by ESI.

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0030] Figure 3 This is a schematic diagram of a chip structure according to an exemplary embodiment of this application. Figure 3 As shown, the chip includes: a clock signal transmitting unit 301, a clock signal receiving unit 302, a first protective clamping circuit 303 disposed inside the clock signal transmitting unit 301, a second protective clamping circuit 304 disposed inside the clock signal receiving unit 302, and an electrostatic discharge protection circuit 305 disposed between the clock signal transmitting unit 301 and the clock signal receiving unit 302.

[0031] The clock signal transmitting unit 301, as the source of the clock signal, can generate a stable clock signal through an internal oscillator or an external crystal oscillator, and send the signal along the transmission path to the clock signal receiving unit 302. This provides a precise reference timing for the synchronous operation of the chip's internal logic modules (such as arithmetic units and storage units) and external related circuits (such as peripheral interface circuits). The stability of its output signal directly determines the timing coordination efficiency of the entire hardware system.

[0032] The first protective clamping circuit 303 is integrated inside the clock signal transmitting unit 301, adjacent to the signal output terminal. Its core function is to suppress and eliminate the overshoot voltage generated by the clock signal inside the transmitting unit. When the clock signal generates a momentary high voltage (or low voltage) that exceeds the normal operating range inside the transmitting unit, this circuit can limit the voltage amplitude to within the safe threshold through clamping, so as to avoid damage to the sensitive components inside the transmitting unit by the overshoot voltage, and at the same time ensure the integrity of the initial waveform of the output clock signal.

[0033] The second protective clamping circuit 304 has the same logic as the first protective clamping circuit 303, but it is integrated inside the clock signal receiving unit 302 and close to the signal input terminal. It mainly eliminates the overshoot voltage that may be generated after the clock signal enters the receiving unit, ensuring that the clock signal entering the core logic circuit of the receiving unit is always within a stable voltage range, laying the foundation for subsequent signal analysis and timing judgment.

[0034] The electrostatic discharge protection circuit 305 is connected in series between the output pin of the clock signal transmitting unit 301 and the input pin of the clock signal receiving unit 302. It is a dynamic adjustment barrier during the clock signal transmission process. It does not directly eliminate overshoot, but can adjust the amplitude of the overshoot voltage through impedance matching, filtering and other designs so that the backflip voltage generated by the clock signal after overshoot is stable within the preset voltage range, fundamentally solving the timing abnormality problem caused by backflip.

[0035] In practical applications, electrostatic interference may couple into the clock signal transmission path in the form of high-frequency pulses, causing the originally smooth clock signal to be superimposed with oscillation waves. This leads to four types of problems: overshoot_high, ringback_high, overshoot_low, and ringback_low. For details, please refer to [link to relevant documentation]. Figure 4The signal waveforms are illustrated in the diagram. "Overshoot" refers to the phenomenon where the voltage amplitude of the clock signal exceeds its normal operating threshold after being affected by electrostatic interference: overshoot_high is characterized by a voltage higher than the upper limit of the normal high level of the clock signal (e.g., exceeding the power rail voltage), and overshoot_low is characterized by a voltage lower than the lower limit of the normal low level (e.g., below ground level). If such overshoot voltages persist, they may not only break down sensitive structures such as PN junctions and oxide layers inside the chip, but may also trigger the circuit's false triggering mechanism, leading to incorrect clock signal level judgment and disrupting basic timing logic. "Backshoot" is a derivative problem during the overshoot voltage recovery process. It refers to the phenomenon where, when the overshoot voltage recovers to the normal level, due to factors such as transmission path impedance mismatch and the release of energy from parasitic inductance and capacitance, the voltage fluctuates in the opposite direction again: Ringback_high is when the voltage briefly falls below the effective high-level threshold Vinh of the clock signal during the high-level overshoot recovery; Ringback_low is when the voltage briefly rises above the effective low-level threshold Vinl during the low-level overshoot recovery. Unlike the "hard damage risk" of overshoot, the harm of backshoot is more like a "soft failure". It directly shortens the holding time of the effective level of the clock signal. For example, when Ringback_high is lower than Vinh, the receiving unit may mistakenly identify the high level as a low level. When Ringback_low is higher than Vinh, it may mistakenly identify the low level as a high level, which will eventually lead to communication errors, data transmission errors, and in severe cases, even cause the timing disorder and collapse of the entire system.

[0036] To address the aforementioned issues, this application provides a comprehensive solution through a collaborative protection scheme combining internal clamping and external adjustment. On one hand, the first protection clamping circuit 303 and the second protection clamping circuit 304 respectively eliminate overshoot in the clock signals of the transmitting and receiving units, directly suppressing overshoot_high and overshoot_low caused by occasional electrostatic interference. This typically enables the chip to achieve an electrostatic discharge protection level of 2000V under the Human Body Model (HBM), meeting the basic anti-static requirements of electronic products, without the need for complex filtering circuits integrated within the chip, effectively controlling costs. On the other hand, the electrostatic protection circuit 305 dynamically adjusts the overshoot voltage amplitude during transmission, using a moderate and controllable overshoot to offset the pull-down or rise-up effect of electrostatic oscillation waveforms on the clock signal level. Ultimately, this keeps Ringback_high stably maintained above the high-level effective threshold Vinh, and Ringback_low stably maintained below the low-level effective threshold Vinl. This design avoids the risk of hard damage from overshoot and solves the problem of soft failure from backshoot, achieving the dual goals of low cost and high reliability. It ensures that the chip can still output a stable clock signal in an electrostatic interference environment, providing a guarantee for the long-term stable operation of the hardware system.

[0037] Specifically, in one embodiment, such as Figure 5 As shown, the first protective clamping circuit 303 may include a first transistor 3031, a second transistor 3032, and a third transistor 3033; the positive terminal of the first transistor 3031 is connected to the output pin of the signal transmitting unit 301, and the negative terminal is connected to the power rail ( Figure 5 The positive terminal of the second transistor 3032 is connected to the ground terminal, and the negative terminal is connected to the output pin of the signal transmitting unit 301. The positive terminal of the third transistor 3033 is connected to the power rail, and the negative terminal is connected to the ground terminal, so as to eliminate the overshoot voltage generated by the clock signal inside the clock signal transmitting unit 301 through the power rail and the ground terminal.

[0038] Correspondingly, the second protective clamping circuit 304 may include a fourth transistor 3041, a fifth transistor 3042, and a sixth transistor 3043; the positive terminal of the fourth transistor 3041 is connected to the input pin of the signal receiving unit 302, and the negative terminal is connected to the power rail; the positive terminal of the fifth transistor 3042 is connected to the ground terminal, and the negative terminal is connected to the input pin of the signal receiving unit 302; the positive terminal of the sixth transistor 3043 is connected to the power rail, and the negative terminal is connected to the ground terminal, so as to eliminate the overshoot voltage generated by the clock signal inside the clock signal receiving unit 302 through the power rail and the ground terminal.

[0039] For the first protective clamping circuit 303, under normal operating conditions, the voltage across the first transistor 3031 is the difference between the high level of the clock signal and the power rail voltage, which does not reach the forward conduction threshold of the device. Therefore, the first transistor 3031 remains in the off state and will not affect the normal transmission of the clock signal. When electrostatic interference couples into the transmitting unit, causing an overshoot_high (high-level overshoot) at the output pin, the pin voltage rises instantaneously and exceeds the power rail voltage, causing the voltage across the first transistor 3031 to reach the forward conduction threshold. At this time, the device quickly conducts, and the excess energy generated by the overshoot flows into the common power rail along the path of "positive terminal → negative terminal of the first transistor 3031". It is then absorbed by the third transistor 3033 connected between the power rail and the ground terminal and further discharged to the ground terminal, forming a complete discharge loop of "pin → power rail → ground". This stabilizes and clamps the high-level overshoot voltage within the safe range of the circuit, preventing damage to internal sensitive components caused by excessive voltage.

[0040] If electrostatic interference causes an overshoot_low (low-level overshoot) at the output pin of the transmitting unit, meaning the pin voltage is lower than the ground level, the two ends of the second transistor 3032 will be forward biased. When the voltage difference between the two ends reaches the conduction threshold, the second transistor 3032 will conduct in the forward direction, and the overshoot energy can be directly discharged through the ground terminal, effectively preventing circuit malfunctions caused by abnormal low-level pull-down and ensuring the stability of the low-level clock signal.

[0041] The working principle of the second protection clamping circuit 304 is similar to that of the first protection clamping circuit 303: when overshoot_high occurs at the input pin of the receiving unit, the fourth transistor 3041 is forward-biased and discharges the overshoot energy through the power rail; when overshoot_low occurs, the fifth transistor 3042 is forward-biased and discharges the energy through the ground terminal; the sixth transistor 3043 serves as the common rail discharge channel on the receiving side, and together with the third transistor 3033, it forms a global electrostatic discharge protection network covering both the transmitting and receiving ends, thereby achieving comprehensive suppression of overshoot of the internal clock signal of the chip.

[0042] This design utilizes a synergistic mechanism of local clamping guidance and global common rail discharge. It can achieve precise overshoot suppression at the pin level by leveraging the fast response characteristics of the front-end transistors (transistors 1, 2, 4, and 5), and can also achieve aggregated discharge of large-energy static electricity through the common rail layout of the back-end transistors (transistors 3 and 6). This effectively prevents the spread of static energy inside the chip, ensuring the waveform integrity of the clock signal during transmission and reception. At the same time, it eliminates the need for complex internal integration design, balancing protection effectiveness and cost control.

[0043] Among them, the first transistor 3031, the second transistor 3032, the fourth transistor 3041, and the fifth transistor 3042 can preferably be Zener diodes because they have a clear and stable conduction threshold, can respond quickly when the voltage is abnormal, can accurately clamp local overshoot at the pin, and are small in size and low in cost, making them suitable for internal chip integration; while the third transistor 3033 and the sixth transistor 3043 can preferably be TVS diodes or silicon controlled rectifiers, both of which have large current carrying capacity and energy absorption capacity, can efficiently cope with the large energy electrostatic shocks accumulated on the common rail, avoid power rail voltage fluctuations, and further improve protection reliability.

[0044] Furthermore, such as Figure 5As shown, the electrostatic discharge protection circuit 305 may include a first resistor 3051, a signal transmission line 3052, a first capacitor 3053, and a second resistor 3054. The first resistor 3051, the signal transmission line 3052, and the second resistor 3054 are connected in series between the output pin of the clock signal transmitting unit 301 and the input pin of the clock signal receiving unit 302, forming the main transmission path of the clock signal. One end of the first capacitor 3053 is connected to the signal transmission line 3052, and the other end is connected to the ground terminal, forming a filtering branch on the transmission line.

[0045] In terms of parameter selection, considering the clock signal transmission characteristics and anti-static requirements, the resistance value of the first resistor 3051 is preferably in the range of 0 to 50Ω. This parameter range can flexibly adapt to the output impedance of different transmitting units, achieving impedance matching between the transmitting end and the transmission line, and reducing overshoot caused by signal reflection. The characteristic impedance of the signal transmission line 3052 is preferably 50Ω. This value matches the impedance design of mainstream high-speed signal transmission systems, which can reduce signal attenuation and distortion during transmission. The capacitance value of the first capacitor 3053 is preferably in the range of 6.8 to 33pF, mainly used to filter out high-frequency components introduced by electrostatic interference and suppress the steepness of overshoot voltage. The resistance value of the second resistor 3054 is preferably in the range of 10 to 100Ω. As a matching resistor at the receiving end, it can further absorb the reflected signal at the end of the transmission line, stabilize the clock signal level at the receiving end, and reduce the risk of backflash.

[0046] In practice, the optimal parameters of the first resistor 3051, the first capacitor 3053, and the second resistor 3054 can be determined through the following process: First, apply standard electrostatic interference (such as HBM). Simulate and test the clock signal waveform after passing through signal transmission line 3052 (2000V), focusing on the voltage amplitudes of Ringback_high and Ringback_low. If the overshoot value exceeds the preset safety range (i.e., Ringback_high is lower than Vinh or Ringback_low is higher than Vinl), adjust the parameters of the first resistor 3051, the first capacitor 3053, or the second resistor 3054. For example, increasing the first resistor 3051 can reduce the overshoot amplitude, adjusting the first capacitor 3053 can change the high-frequency filtering effect, and optimizing the second resistor 3054 can improve the impedance matching at the receiving end. After each parameter adjustment, recheck whether the overshoot value falls within the safety range, and verify the integrity of the clock signal (such as whether the rise time and duty cycle meet the design requirements). If the overshoot value meets the standard and the signal integrity is not affected, determine that the current parameter combination is the optimal choice. If it does not meet the standard, repeat the above adjustment process until both the anti-static requirements and signal transmission performance are met.

[0047] This external electrostatic discharge (ESD) protection circuit 305, through a dual mechanism of impedance matching and filtering adjustment, can precisely control the overshoot amplitude of the clock signal during transmission, thereby stabilizing the backflip voltage within a preset safe range. It complements the internal first protection clamping circuit 303 and second protection clamping circuit 304: the internal circuit eliminates direct overshoot at the chip pins, while the external circuit specifically addresses backflip issues during transmission. Their combined effect avoids hardware damage caused by ESD interference and eliminates the risk of soft failures caused by abnormal signal timing. Furthermore, through adjustable parameter design, this circuit can adapt to different ESD environments in various application scenarios, effectively controlling hardware costs while ensuring protection effectiveness, making it particularly suitable for electronic devices with high cost-effectiveness requirements.

[0048] On the other hand, this application also provides an electrostatic discharge protection circuit for clock signals. This circuit can be independently applied to the transmission link of chip clock signals to specifically solve the backflush problem caused by electrostatic interference during the transmission of clock signals, thus ensuring the timing stability of the hardware system.

[0049] Figure 6 This is a schematic diagram illustrating the structure of an electrostatic discharge (ESD) protection circuit according to an exemplary embodiment of this application. Figure 6 As shown, the electrostatic discharge protection circuit is located between the clock signal transmitting unit and the clock signal receiving unit inside the chip. It is used to adjust the overshoot voltage amplitude of the clock signal during transmission so that the feedback voltage amplitude after the clock signal overshoots is within a preset voltage range.

[0050] The clock signal transmitting unit is used to generate a clock signal and send it to the clock signal receiving unit.

[0051] The electrostatic discharge protection circuit includes a first resistor 601, a signal transmission line 602, a first capacitor 603, and a second resistor 604. The first resistor 601, the signal transmission line 602, and the second resistor 604 are connected in series between the output pin of the clock signal transmitting unit and the input pin of the clock signal receiving unit. One end of the first capacitor 604 is connected to the signal transmission line 602, and the other end is connected to the ground terminal.

[0052] Specifically, the resistance value of the first resistor 601 is preferably in the range of 0 to 50 Ω; the characteristic impedance of the signal transmission line 602 is preferably 50 Ω; the capacitance value of the first capacitor 603 is preferably in the range of 6.8 to 33 pF; and the resistance value of the second resistor 605 is preferably in the range of 10 to 100 Ω.

[0053] The specific functions and implementation processes of each device in the above electrostatic discharge protection circuit are consistent with the description of the corresponding device in the electrostatic discharge protection circuit 305 in the aforementioned chip embodiment. Please refer to the previous content for details, which will not be repeated here.

[0054] This independent electrostatic discharge (ESD) protection circuit allows for cost-effective improvement of the clock signal's anti-ESD interference capability without complex modifications to the chip's internal structure, making it particularly suitable for upgrading the ESD performance of existing hardware systems.

[0055] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the utility model applied herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the foregoing claims.

[0056] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0057] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A chip, characterized in that, include: A clock signal transmitting unit, a clock signal receiving unit, a first protective clamping circuit disposed inside the clock signal transmitting unit, a second protective clamping circuit disposed inside the clock signal receiving unit, and an electrostatic discharge protection circuit disposed between the clock signal transmitting unit and the clock signal receiving unit; The clock signal transmitting unit is used to generate a clock signal and send it to the clock signal receiving unit; The first protective clamping circuit is used to eliminate the overshoot voltage generated by the clock signal inside the clock signal transmitting unit; The second protective clamping circuit is used to eliminate the overshoot voltage generated by the clock signal inside the clock signal receiving unit; The electrostatic discharge protection circuit is used to adjust the overshoot voltage amplitude of the clock signal during transmission so that the overshoot voltage amplitude of the clock signal is within a preset voltage range.

2. The chip according to claim 1, characterized in that, The first protective clamping circuit includes a first transistor, a second transistor, and a third transistor; The positive terminal of the first transistor is connected to the output pin of the signal transmitting unit, and the negative terminal is connected to the power rail; The positive terminal of the second transistor is connected to the ground terminal, and the negative terminal is connected to the output pin of the signal transmitting unit; The positive terminal of the third transistor is connected to the power rail, and the negative terminal is connected to the ground terminal, so as to eliminate the overshoot voltage generated by the clock signal inside the clock signal transmitting unit through the power rail and the ground terminal. And / or, The second protective clamping circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; The positive terminal of the fourth transistor is connected to the input pin of the signal receiving unit, and the negative terminal is connected to the power rail. The positive terminal of the fifth transistor is connected to the ground terminal, and the negative terminal is connected to the input pin of the signal receiving unit. The positive terminal of the sixth transistor is connected to the power rail, and the negative terminal of the sixth transistor is connected to the ground terminal, so as to eliminate the overshoot voltage generated by the clock signal inside the clock signal receiving unit through the power rail and the ground terminal.

3. The chip according to claim 1, characterized in that, The electrostatic discharge protection circuit includes a first resistor, a signal transmission line, a first capacitor, and a second resistor; the first resistor, the signal transmission line, and the second resistor are connected in series between the output pin of the clock signal transmitting unit and the input pin of the clock signal receiving unit; one end of the first capacitor is connected to the signal transmission line, and the other end is connected to the ground terminal.

4. The chip according to claim 2, characterized in that, The first transistor, the second transistor, the fourth transistor, and the fifth transistor are Zener diodes, and the third transistor and the sixth transistor are TVS diodes or silicon controlled rectifiers.

5. The chip according to claim 3, characterized in that, The resistance value of the first resistor is in the range of 0~50Ω.

6. The chip according to claim 3, characterized in that, The characteristic impedance of the signal transmission line is 50Ω.

7. The chip according to claim 3, characterized in that, The capacitance of the first capacitor ranges from 6.8 to 33 pF, and the resistance of the second resistor ranges from 10 to 100 Ω.

8. An electrostatic discharge protection circuit for a clock signal, characterized in that, The clock signal transmitting unit is disposed between the clock signal transmitting unit and the clock signal receiving unit inside the chip according to any one of claims 1-7, wherein the clock signal transmitting unit is used to generate a clock signal and send it to the clock signal receiving unit. The electrostatic discharge protection circuit includes a first resistor, a signal transmission line, a first capacitor, and a second resistor; the first resistor, the signal transmission line, and the second resistor are connected in series between the output pin of the clock signal transmitting unit and the input pin of the clock signal receiving unit; one end of the first capacitor is connected to the signal transmission line, and the other end is connected to the ground terminal; The first resistor, the first capacitor, and the second resistor are used to adjust the overshoot voltage amplitude of the clock signal during transmission so that the overshoot voltage amplitude of the clock signal is within a preset voltage range.

9. The circuit according to claim 8, characterized in that, The resistance value of the first resistor is in the range of 0~50Ω; And / or, the characteristic impedance of the signal transmission line is 50Ω; And / or, the capacitance of the first capacitor is in the range of 6.8~33pF, and the resistance of the second resistor is in the range of 10~100Ω.

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