A three-phase interleaved half-bridge LLC converter circuit

Abstract

This utility model belongs to the field of converter technology and discloses a three-phase interleaved half-bridge LLC converter circuit, including a current sampling section. One side of the current sampling section is connected to the half-bridge LLC circuit, and the other side is connected to pins 1 and 3 of rectifier bridge D13. Pin 2 of rectifier bridge D13 is connected to one end of resistor R1 and pin 5 of comparator U2. Pin 4 of rectifier bridge D13 is connected to the other end of resistor R1, pin 2 of comparator U2 and one end of resistor R2. Pin 3 of comparator U2 is connected to port V_REF. The other end of resistor R2 is connected to one end of capacitor C6 and port 1 of controller U3. The other end of capacitor C6 is connected to port GND. The beneficial effects of this utility model are: fewer circuit components, simple structure, ability to achieve hardware overcurrent protection and software overcurrent protection, and significant reduction of the risk of instantaneous high current damage to power transistors.

Description

Technical Field

[0001] This utility model relates to the field of converter technology, and in particular to a three-phase interleaved half-bridge LLC converter circuit. Background Technology

[0002] With the advent of third-generation power semiconductors SiC MOSFETs at 1200V and above, the DC topology of high-power charging modules can directly draw power from the PFC bus capacitor. The most commonly used topologies are the LLC full-bridge structure and the three-phase half-bridge interleaved LLC structure. These topologies use fewer semiconductor switching transistors and have minimal dynamic losses during operation, which can greatly improve the overall efficiency. However, SiC MOSFETs generally have poor surge current resistance. Under some extreme operating conditions, their topology is prone to breakdown of the third-generation power semiconductor due to instantaneous large currents, such as load short circuits or large currents generated by switching multiple modules.

[0003] Therefore, it is necessary to provide a three-phase interleaved half-bridge LLC converter circuit to solve the problem of power transistor breakdown caused by instantaneous large current during operation under sudden conditions. Utility Model Content

[0004] This utility model discloses a three-phase interleaved half-bridge LLC converter circuit, belonging to the field of switching power supplies, and relating to three-phase interleaved LLC technology and the protection circuit of the LLC converter, which can effectively solve the technical problems involved in the background art.

[0005] To achieve the above objectives, the technical solution of this utility model is as follows:

[0006] A three-phase interleaved half-bridge LLC converter circuit includes a protection circuit. The protection circuit includes a current sampling section. One side of the current sampling section is connected to the half-bridge LLC circuit, and the other side is connected to pins 1 and 3 of rectifier bridge D13. Pin 2 of rectifier bridge D13 is connected to one end of resistor R1 and pin 5 of comparator U2. Pin 4 of rectifier bridge D13 is connected to the other end of resistor R1, pin 2 of comparator U2, and one end of resistor R2. Pin 3 of comparator U2 is connected to port V_REF. The other end of resistor R2 is connected to one end of capacitor C6 and port 1 of controller U3. The other end of capacitor C6 is connected to port GND. Pin 5 of comparator U2 is connected to port 2 and port GND of controller U3. Pin 6 of comparator U2 is connected to port 3 of controller U3.

[0007] The three-phase interleaved LLC converter uses a Y-connection on both the primary and secondary sides. Because the charging module has a wide output voltage range, the secondary side requires two-way series-parallel switching to achieve high-voltage, high-current output. During operation, the transformer current passes through a current sampling circuit. This circuit can be a separate current transformer or a winding of the transformer. The current sampling circuit converts the current signal into a voltage signal after passing through a resistor. This circuit has two protection modes: the first is to RC-filter the abnormal voltage signal and send it to the MCU AD port for internal OCP protection; the second is to use an external comparator chip. This chip compares the voltage signal with V_REF, and outputs a high level to the MCU TZ pin in case of an abnormality, enabling fast shutdown protection.

[0008] As a preferred improvement of this utility model: the controller U3 is connected to the switching transistor of the half-bridge LLC circuit.

[0009] As a preferred improvement of this utility model, the port V_REF is connected to a reference voltage source.

[0010] As a preferred improvement of this utility model: the comparator U2 is NSI22C12-DSWVR, and the controller U3 is TMS320F280023PMSR.

[0011] As a preferred improvement of this utility model: port one of the controller U3 is the OCP pin, port two of the controller U3 is the GND pin, and port three of the controller U3 is the TZ pin.

[0012] As a preferred improvement of this utility model: the current sampling section includes a current transformer U1, pins 1 and 2 of the current transformer U1 are connected to a half-bridge LLC circuit, pin 3 of the current transformer U1 is connected to pin 1 of the rectifier bridge D13, and pin 4 of the current transformer U1 is connected to pin 3 of the rectifier bridge D13.

[0013] As a preferred improvement of this utility model, the current transformer U1 is ZHTM104B.

[0014] As a preferred improvement of this utility model: the half-bridge LLC circuit includes port PFC+ and port PFC-. Port PFC+ is connected to the drain of MOSFET Q1, the drain of MOSFET Q3, and the drain of MOSFET Q5. Port PFC- is connected to the source of MOSFET Q2, the source of MOSFET Q4, and the source of MOSFET Q6. The source of MOSFET Q1 is connected to the drain of MOSFET Q2 and one end of capacitor C1. The source of MOSFET Q3 is connected to the drain of MOSFET Q4 and one end of capacitor C2. The source of transistor Q5 is connected to the drain of MOSFET Q6 and one end of capacitor C3. The other end of capacitor C1 is connected to one end of inductor L1. The other end of inductor L1 is connected to pin 1 of transformer T1. The other end of capacitor C2 is connected to one end of inductor L2. The other end of inductor L2 is connected to pin 1 of transformer T2. The other end of capacitor C3 is connected to one end of inductor L3. The other end of inductor L3 is connected to pin 1 of transformer T3. Pin 8 of transformer T1 is connected to pin 8 of transformer T2 and pin 8 of transformer T3.

[0015] Pin 3 of transformer T1 is connected to pin 3 of transformer T2 and pin 4 of transformer T3. Pin 4 of transformer T1 is connected to pin 4 of transformer T2 and pin 4 of transformer T3. Pin 6 of transformer T1 is connected to the positive terminal of diode D1 and the negative terminal of diode D4. Pin 6 of transformer T2 is connected to the positive terminal of diode D2 and the negative terminal of diode D5. Pin 6 of transformer T3 is connected to the positive terminal of diode D3 and the negative terminal of diode D6. The negative terminal of diode D1 is connected to the negative terminal of diode D2, the negative terminal of diode D3, one end of capacitor C4, and port DC1+. The positive terminal of diode D4 is connected to the positive terminal of diode D5, the positive terminal of diode D6, the other end of capacitor C4, and port DC1-.

[0016] Pin 5 of transformer T1 is connected to the positive terminal of diode D9 and the negative terminal of diode D12. Pin 5 of transformer T2 is connected to the positive terminal of diode D8 and the negative terminal of diode D11. Pin 5 of transformer T3 is connected to the current sampling section. The current sampling section is connected to the positive terminal of diode D7 and the negative terminal of diode D10. The negative terminal of diode D7 is connected to the negative terminals of diode D8, diode D9, one end of capacitor C5, and port DC2+. The positive terminal of diode D10 is connected to the positive terminals of diode D11, diode D12, the other end of capacitor C5, and port DC2-.

[0017] As a preferred improvement of this utility model: pins 1 and 8 of the transformer T1 share a common coil, pins 3 and 6 of the transformer T1 share a common coil, and pins 4 and 5 of the transformer T1 share a common coil.

[0018] As a preferred improvement of this utility model, the load is connected in parallel or in series between the ports DC1+ and DC2+.

[0019] The beneficial effects of this utility model are as follows:

[0020] The advantages of this utility model circuit are that it has fewer circuit components and a simpler structure, and it can realize both hardware and software overcurrent protection, significantly reducing the risk of damage to the power transistor due to instantaneous high current. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0022] Figure 1 This is a schematic diagram of a three-phase interleaved half-bridge LLC converter circuit according to the present invention;

[0023] Figure 2 This is a schematic diagram of the half-bridge LLC circuit structure of this utility model;

[0024] Figure 3 This is a schematic diagram of the protection circuit structure of this utility model;

[0025] Figure 4 This is a schematic diagram of the comparator pinout of this utility model. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0028] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0029] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0031] Please see Figure 1 As shown, this utility model provides a three-phase interleaved half-bridge LLC converter circuit, including a protection circuit and a half-bridge LLC circuit. The half-bridge LLC circuit is connected to the PFC bus and the output to perform voltage conversion, and the protection circuit protects the half-bridge LLC circuit.

[0032] Please see Figure 2As shown, the half-bridge LLC circuit includes port PFC+ and port PFC-. Port PFC+ is connected to the drain of MOSFET Q1, the drain of MOSFET Q3, and the drain of MOSFET Q5. Port PFC- is connected to the source of MOSFET Q2, the source of MOSFET Q4, and the source of MOSFET Q6. The source of MOSFET Q1 is connected to the drain of MOSFET Q2 and one end of capacitor C1. The source of MOSFET Q3 is connected to the drain of MOSFET Q4 and one end of capacitor C2. The source of MOSFET Q5 is connected to the drain of MOSFET Q6 and one end of capacitor C3. The capacitor C1... The other end of capacitor C2 is connected to one end of inductor L1, and the other end of inductor L1 is connected to pin 1 of transformer T1. The other end of capacitor C2 is connected to one end of inductor L2, and the other end of inductor L2 is connected to pin 1 of transformer T2. The other end of capacitor C3 is connected to one end of inductor L3, and the other end of inductor L3 is connected to pin 1 of transformer T3. Pin 8 of transformer T1 is connected to pin 8 of transformer T2 and pin 8 of transformer T3. Pin 3 of transformer T1 is connected to pin 3 of transformer T2 and pin 3 of transformer T3. Pin 4 of transformer T1 is connected to pin 4 of transformer T2. Pin 4 of transformer T1 is connected to pin 4 of transformer T2 and pin 4 of transformer T3. Pin 6 of transformer T1 is connected to the positive terminal of diode D1 and the negative terminal of diode D4. Pin 6 of transformer T2 is connected to the positive terminal of diode D2 and the negative terminal of diode D5. Pin 6 of transformer T3 is connected to the positive terminal of diode D3 and the negative terminal of diode D6. The negative terminal of diode D1 is connected to the negative terminals of diode D2, diode D3, one end of capacitor C4, and port DC1+. The positive terminal of diode D4 is connected to the positive terminals of diode D5, diode D6, the other end of capacitor C4, and port DC1-. Pin 5 of transformer T1 is connected to the positive terminal of diode D9 and the negative terminal of diode D12. Pin 5 of transformer T2 is connected to the positive terminal of diode D8 and the negative terminal of diode D11. Pin 5 of transformer T3 is connected to the current sampling section, which is connected to the positive terminal of diode D7 and the negative terminal of diode D10. The negative terminal of diode D7 is connected to the negative terminals of diode D8, diode D9, one end of capacitor C5, and port DC2+. The positive terminal of diode D10 is connected to the positive terminals of diode D11, diode D12, the other end of capacitor C5, and port DC2-. Pins 1 and 8 of transformer T1 share a coil, pins 3 and 6 of transformer T1 share a coil, and pins 4 and 5 of transformer T1 share a coil. Pins 1 and 8 of transformer T2 share a coil, pins 3 and 6 of transformer T2 share a coil, and pins 4 and 5 of transformer T2 share a coil.The transformer T3 has a shared coil between pins 1 and 8, a shared coil between pins 3 and 6, and a shared coil between pins 4 and 5. The load is connected in parallel or in series between ports DC1+ and DC2+.

[0033] Please see Figure 3 As shown, the protection circuit includes a current sampling section. One side of the current sampling section is connected to a half-bridge LLC circuit, and the other side is connected to pins 1 and 3 of rectifier bridge D13. Pin 2 of rectifier bridge D13 is connected to one end of resistor R1 and pin 5 of comparator U2. Pin 4 of rectifier bridge D13 is connected to the other end of resistor R1, pin 2 of comparator U2, and one end of resistor R2. Pin 3 of comparator U2 is connected to port V_REF. The other end of resistor R2 is connected to one end of capacitor C6 and port one of controller U3. The other end of capacitor C6 is connected to port GND. Pin 5 of comparator U2 is connected to port two and port GND of controller U3. Pin 6 of comparator U2 is connected to port three of controller U3. Controller U3 is connected to the switching transistor of the half-bridge LLC circuit, and port V_REF is connected to a reference voltage source. Comparator U2 is an NSI22C12-DSWVR, and controller U3 is a TMS320F280023PMSR. The controller U3 has three ports: port 1 is the OCP pin, port 2 is the GND pin, and port 3 is the TZ pin. The current sampling section includes a current transformer U1. Pins 1 and 2 of the current transformer U1 are connected to a half-bridge LLC circuit. Pin 3 of the current transformer U1 is connected to pin 1 of the rectifier bridge D13, and pin 4 of the current transformer U1 is connected to pin 3 of the rectifier bridge D13. The current transformer U1 is a ZHTM104B.

[0034] When a three-phase half-bridge interleaved LLC circuit malfunctions, an abnormal current in any phase will induce a current in the sampling current transformer U1 due to the zero vector sum of the three-phase currents caused by the Y-connection. This induced current is rectified by the full-bridge rectifier D13 into a single positive current, which then flows through R1, generating a voltage drop and becoming a voltage signal. This voltage signal is sent to two parts: one part is filtered by R2 and C6 using a low-pass RC filter and then sent to the OCP sampling port of MCU U3. After software processing, if the voltage exceeds a certain threshold, software overcurrent shutdown protection is implemented. The other part is sent to the IN pin of U2. U2 is an external comparator chip with an externally set trigger reference voltage on the REF pin. When the voltage sampling signal is greater than V_REF, the OUTA pin of U2 will output a 3.3V high level to the TZ pin of U3. After U3 recognizes the high level on the TZ pin, it can directly disable the PWM output without software algorithm processing, thus quickly implementing hardware overcurrent protection. This circuit design allows for the setting of different gradient current protections, effectively identifying the magnitude of abnormal currents and thus adaptively adjusting the overcurrent protection response speed. It should be further noted that any other components used to achieve the above effects should fall within the inventive concept of this utility model and should be protected within its scope.

[0035] Although the embodiments of this utility model have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for this utility model. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, this utility model is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A three-phase interleaved half-bridge LLC converter circuit, characterized in that: The system includes a protection circuit, which comprises a current sampling section. One side of the current sampling section is connected to a half-bridge LLC circuit, and the other side is connected to pins 1 and 3 of a rectifier bridge D13. Pin 2 of the rectifier bridge D13 is connected to one end of a resistor R1 and pin 5 of a comparator U2. Pin 4 of the rectifier bridge D13 is connected to the other end of the resistor R1, pin 2 of the comparator U2, and one end of the resistor R2. Pin 3 of the comparator U2 is connected to port V_REF. The other end of the resistor R2 is connected to one end of a capacitor C6 and port 1 of the controller U3. The other end of the capacitor C6 is connected to port GND. Pin 5 of the comparator U2 is connected to port 2 and port GND of the controller U3. Pin 6 of the comparator U2 is connected to port 3 of the controller U3.

2. The three-phase interleaved half-bridge LLC converter circuit according to claim 1, characterized in that: The controller U3 is connected to the switching transistor of the half-bridge LLC circuit.

3. The three-phase interleaved half-bridge LLC converter circuit according to claim 1, characterized in that: The port V_REF is connected to a reference voltage source.

4. A three-phase interleaved half-bridge LLC converter circuit according to claim 1, characterized in that: The comparator U2 is an NSI22C12-DSWVR, and the controller U3 is a TMS320F280023PMSR.

5. A three-phase interleaved half-bridge LLC converter circuit according to claim 4, characterized in that: The controller U3 has three ports: port 1 is the OCP pin, port 2 is the GND pin, and port 3 is the TZ pin.

6. A three-phase interleaved half-bridge LLC converter circuit according to claim 1, characterized in that: The current sampling section includes a current transformer U1. Pins 1 and 2 of the current transformer U1 are connected to a half-bridge LLC circuit. Pin 3 of the current transformer U1 is connected to pin 1 of the rectifier bridge D13. Pin 4 of the current transformer U1 is connected to pin 3 of the rectifier bridge D13.

7. A three-phase interleaved half-bridge LLC converter circuit according to claim 6, characterized in that: The current transformer U1 is a ZHTM104B.

8. A three-phase interleaved half-bridge LLC converter circuit according to claim 1, characterized in that: The half-bridge LLC circuit includes port PFC+ and port PFC-. Port PFC+ is connected to the drain of MOSFET Q1, the drain of MOSFET Q3, and the drain of MOSFET Q5. Port PFC- is connected to the source of MOSFET Q2, the source of MOSFET Q4, and the source of MOSFET Q6. The source of MOSFET Q1 is connected to the drain of MOSFET Q2 and one end of capacitor C1. The source of MOSFET Q3 is connected to the drain of MOSFET Q4 and one end of capacitor C2. The source of MOSFET Q5 is connected to... The drain of the MOSFET Q6 is connected to one end of the capacitor C3. The other end of the capacitor C1 is connected to one end of the inductor L1. The other end of the inductor L1 is connected to pin 1 of the transformer T1. The other end of the capacitor C2 is connected to one end of the inductor L2. The other end of the inductor L2 is connected to pin 1 of the transformer T2. The other end of the capacitor C3 is connected to one end of the inductor L3. The other end of the inductor L3 is connected to pin 1 of the transformer T3. Pin 8 of the transformer T1 is connected to pin 8 of the transformer T2 and pin 8 of the transformer T3. Pin 3 of transformer T1 is connected to pin 3 of transformer T2 and pin 4 of transformer T3. Pin 4 of transformer T1 is connected to pin 4 of transformer T2 and pin 4 of transformer T3. Pin 6 of transformer T1 is connected to the positive terminal of diode D1 and the negative terminal of diode D4. Pin 6 of transformer T2 is connected to the positive terminal of diode D2 and the negative terminal of diode D5. Pin 6 of transformer T3 is connected to the positive terminal of diode D3 and the negative terminal of diode D6. The negative terminal of diode D1 is connected to the negative terminal of diode D2, the negative terminal of diode D3, one end of capacitor C4, and port DC1+. The positive terminal of diode D4 is connected to the positive terminal of diode D5, the positive terminal of diode D6, the other end of capacitor C4, and port DC1-. Pin 5 of transformer T1 is connected to the positive terminal of diode D9 and the negative terminal of diode D12. Pin 5 of transformer T2 is connected to the positive terminal of diode D8 and the negative terminal of diode D11. Pin 5 of transformer T3 is connected to the current sampling section. The current sampling section is connected to the positive terminal of diode D7 and the negative terminal of diode D10. The negative terminal of diode D7 is connected to the negative terminals of diode D8, diode D9, one end of capacitor C5, and port DC2+. The positive terminal of diode D10 is connected to the positive terminals of diode D11, diode D12, the other end of capacitor C5, and port DC2-.

9. A three-phase interleaved half-bridge LLC converter circuit according to claim 8, characterized in that: The transformer T1 has a shared coil between pin 1 and pin 8, a shared coil between pin 3 and pin 6, and a shared coil between pin 4 and pin 5.

10. A three-phase interleaved half-bridge LLC converter circuit according to claim 8, characterized in that: The load is connected in parallel or in series at ports DC1+ and DC2+.

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