Test device and test system
Patent Information
- Application Number
- CN202522018307.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-19
- Publication Date
- 2026-09-29
- Estimated Expiration
- 2035-09-19
AI Technical Summary
当对SOC芯片进行掉电重启测试时，相关技术中要么对整个PCB进行循环掉电重启测试时，此时需要独立部署一套软硬件控制系统，来控制PCB板的上下电动作，成本高且相对比较复杂
[0003]本申请实施例的主要目的在于提出一种测试装置及测试系统，能在对SOC芯片进行掉电重启测试时兼顾测试成本和测试的准确性。
Smart Images
Figure CN224816463U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and in particular to a testing device and testing system. Background Technology
[0002] When testing System-on-Chips (SoCs), the SoC is typically mounted on a PCB, with integrated test circuitry. Multiple tests (such as voltage tests) are then performed on the SoC using this PCB-based circuitry. However, when performing power-down / reboot tests on the SoC, existing technologies either cyclically test the entire PCB, requiring a separate hardware and software control system to manage the PCB's power-on and power-off actions, which is costly and relatively complex. While some technologies utilize a Power Management Integrated Circuit (PMIC) on the PCB for power-down / reboot testing, this method only de-energizes a portion of the PMIC's power supply channels (i.e., the SoC's power supply is cut off), resulting in low accuracy. Therefore, current power-down / reboot testing methods for SoCs struggle to balance testing cost and accuracy. Summary of the Invention
[0003] The main objective of this application is to provide a testing device and system that can balance testing cost and testing accuracy when performing power-down restart tests on SOC chips.
[0004] To achieve the above objectives, a first aspect of this application provides a testing apparatus, the testing apparatus comprising:
[0005] The PCB board integrates a power conversion circuit, a power management integrated circuit (PMIC), and a restart control circuit.
[0006] The voltage output terminal of the power conversion circuit is connected to the voltage input terminal of the PMIC; the voltage output terminal of the PMIC is used to connect to the power supply terminal of the SOC chip under test.
[0007] The output terminal of the restart control circuit is connected to the enable control terminal of the power conversion circuit; the control input terminal of the restart control circuit is connected to the signal control terminal of the SOC chip under test; the restart control circuit is used to continuously send an enable control signal to the enable control terminal within a preset time according to the restart signal of the signal control terminal, so that the power conversion circuit stops supplying power to the PMIC for the preset time according to the enable control signal.
[0008] The testing apparatus of the above embodiments of this application has at least the following beneficial effects: The restart signal from the signal control terminal of the SOC chip under test causes the restart control circuit to control the power conversion circuit to stop supplying power to the PMIC. When the power conversion circuit does not receive an enable control signal, it resumes supplying power to the PMIC. Thus, the restart control circuit can achieve a method of automatically powering on the PMIC after a certain time interval, and the power-on process does not require software control and can achieve a complete power-off of the PCB board. Therefore, compared with related technologies, the embodiments of this application can achieve a complete power-off of the PCB board at a lower cost, balancing testing cost and accuracy during the power-off restart test of the SOC chip.
[0009] According to some embodiments of the test apparatus of the first aspect of this application, the restart control circuit includes a first switch control sub-circuit, a first capacitor, a first resistor, and a first MOSFET. The control terminal of the first switch control sub-circuit is connected to the signal control terminal of the SOC chip under test. The voltage input terminal of the first switch control sub-circuit is used to connect to a preset power supply. The second terminals of the first capacitor and the first resistor are grounded. The first terminals of the first capacitor and the first resistor are connected to the gate of the first MOSFET and the voltage output terminal of the first switch control sub-circuit, and the first capacitor and the first resistor are located between the gate of the first MOSFET and the first switch control sub-circuit. The first capacitor and the first resistor are used to control the conduction time of the first MOSFET. The first switch control sub-circuit is used to disconnect or connect the voltage input terminal and the voltage output terminal of the first switch control sub-circuit according to the restart signal of the signal control terminal. The drain of the first MOSFET is grounded, and the source of the first MOSFET is connected to the enable control terminal of the power conversion circuit.
[0010] According to some embodiments of the test apparatus of the first aspect of this application, the first switch control sub-circuit includes a second MOS transistor and a third MOS transistor. The gate of the second MOS transistor is connected to the signal control terminal of the SOC chip under test. The drain of the second MOS transistor is grounded. The source of the second MOS transistor is connected to the gate of the third MOS transistor. The drain of the third MOS transistor is connected to the first terminal of the first capacitor and the first resistor. The source of the third MOS transistor is connected to the preset power supply.
[0011] According to some embodiments of the test apparatus of the first aspect of this application, the first switch control sub-circuit further includes a second resistor, the two ends of the second resistor being respectively connected to the source of the second MOS transistor and the source of the third MOS transistor, and the gate of the third MOS transistor being connected to the junction of the second resistor and the source of the second MOS transistor.
[0012] According to some embodiments of the test apparatus of the first aspect of this application, the first switch control sub-circuit further includes a third resistor, the first end of the third resistor being connected to the gate of the second MOS transistor, and the third resistor being connected to the drain of the second MOS transistor.
[0013] According to some embodiments of the test apparatus of the first aspect of this application, the first switch control sub-circuit further includes a fourth resistor, which is connected in series between the third MOS transistor and the first capacitor and is also connected in series between the third MOS transistor and the first resistor.
[0014] According to some embodiments of the first aspect of this application, the power conversion circuit of the test apparatus includes a DC-DC chip.
[0015] To achieve the above objectives, a second aspect of this application provides a testing system, the testing system comprising:
[0016] The test apparatus as described in any of the first aspects;
[0017] The SOC chip under test is connected to the power supply terminal of the PMIC and the signal control terminal of the SOC chip under test is connected to the control input terminal of the restart control circuit.
[0018] According to some embodiments of the testing apparatus of the second aspect of this application, the SOC chip under test is disposed on the PCB board, and the SOC chip under test is detachably connected to the PCB board. Attached Figure Description
[0019] Figure 1 This is one embodiment of testing SOC chips in the prior art;
[0020] Figure 2 This is another embodiment of testing SOC chips in the prior art;
[0021] Figure 3 This is a schematic diagram of a module of a test system for which the test apparatus provided in this application is applied;
[0022] Figure 4 This is a schematic diagram of the restart control circuit in the test device provided in this application. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0024] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0026] When testing a System-on-Chip (SoC), the SoC is typically mounted on a PCB, with test circuitry integrated on the PCB. Multiple tests (such as voltage tests) are then performed on the SoC using this PCB-based test circuitry. When performing a power-down / reboot test on the SoC, refer to... Figure 1 As shown, the power-on and power-off actions of the PCB board can be controlled by deploying a separate hardware and software control system to perform cyclic power-down and restart tests on the entire PCB. However, this control method is costly and relatively complex. In other cases, refer to... Figure 2 As shown, a power management integrated circuit (PMIC) integrated on the PCB board can also be used for power-down restart testing. However, this method can only power down the power supply section of the SOC chip. Since the PMIC is always connected to the power supply Vin, some circuits on the PMIC are always in a conducting state, which can easily interfere with the SOC chip, resulting in low accuracy of the power-down restart test. Therefore, in the prior art, the method of power-down restart testing of SOC chips is difficult to balance test cost and test accuracy. Based on this, the embodiments of this application provide a test device and test system that can balance test cost and test accuracy when performing power-down restart testing on SOC chips.
[0027] Understandably, referring to Figure 3 As shown, a testing apparatus according to an embodiment of this application includes:
[0028] The PCB board integrates a power conversion circuit, a power management integrated circuit (PMIC), and a restart control circuit.
[0029] The voltage output terminal of the power conversion circuit is connected to the voltage input terminal of the PMIC; the voltage output terminal of the PMIC is used to connect to the power supply terminal of the SOC chip under test.
[0030] The restart control circuit's output is connected to the enable control terminal of the power conversion circuit; the restart control circuit's control input is connected to the signal control terminal of the SOC chip under test; the restart control circuit is used to continuously send an enable control signal to the enable control terminal within a preset time according to the restart signal from the signal control terminal, so that the power conversion circuit stops supplying power to the PMIC for a preset time according to the enable control signal.
[0031] Therefore, by sending a restart signal to the signal control terminal of the SOC chip under test, the restart control circuit controls the power conversion circuit to stop supplying power to the PMIC. When the power conversion circuit does not receive an enable control signal, it resumes supplying power to the PMIC. This allows the restart control circuit to automatically power on the PMIC at a set time, without requiring software control, and enables a complete PCB board power-off. Therefore, this embodiment can achieve a lower cost for the entire PCB board, balancing testing cost and accuracy during SOC chip power-down restart testing.
[0032] A Power Management Component (PMIC) is a core chip in electronic devices responsible for the unified management, distribution, conversion, and monitoring of power. It integrates traditional discrete power management components (such as voltage regulators, chargers, and voltage monitors) into a single chip, enabling efficient control over various power requirements of the device. This application does not limit the specific circuit configuration of the PMIC; those skilled in the art can choose to configure it accordingly.
[0033] The power conversion circuit is used to convert external power into the voltage required by the PMIC. This application does not limit the structure of the power conversion circuit. In some embodiments, the power conversion circuit can be configured as an integrated chip (such as a DC-DC converter), while in other embodiments, it can be configured as a circuit composed of electronic components. Those skilled in the art can selectively configure it according to the actual situation.
[0034] The embodiments of this application do not limit the structure of the restart control circuit. Those skilled in the art can set up a circuit that uses a MOS transistor to output the enable control signal.
[0035] Understandably, referring to Figure 4As shown, the restart control circuit includes a first switch control sub-circuit, a first capacitor, a first resistor, and a first MOSFET. The control terminal of the first switch control sub-circuit is connected to the signal control terminal of the SOC chip under test. The voltage input terminal of the first switch control sub-circuit is used to connect to a preset power supply. The second terminals of the first capacitor and the first resistor are grounded. The first terminals of the first capacitor and the first resistor are connected to the gate of the first MOSFET and the voltage output terminal of the first switch control sub-circuit, and the first capacitor and the first resistor are located between the gate of the first MOSFET and the first switch control sub-circuit. The first capacitor and the first resistor are used to control the conduction time of the first MOSFET. The first switch control sub-circuit is used to disconnect or connect the voltage input terminal and the voltage output terminal of the first switch control sub-circuit according to the restart signal of the signal control terminal. The drain of the first MOSFET is grounded, and the source of the first MOSFET is connected to the enable control terminal of the power conversion circuit.
[0036] The embodiments of this application do not limit the specific circuit structure of the first switch control sub-circuit. Those skilled in the art can use a switch circuit composed of MOS transistors or a switch circuit composed of transistors. In this regard, those skilled in the art can selectively set according to actual needs.
[0037] For example, such as Figure 4 As shown, under normal operating conditions, since the first resistor R200 and the first capacitor C329 are connected in parallel, the first capacitor C329 is charging. When a restart is required and power is lost, the first switch control sub-circuit is disconnected, and the first capacitor C329 discharges, thereby turning on the first MOSFET Q8. The power conversion circuit receives the enable control signal, thus disconnecting the power conversion circuit from the PMIC. When the first capacitor C329 has fully discharged its charge, the first MOSFET Q8 turns off, stops sending the enable control signal to the power conversion circuit, and the power conversion circuit resumes supplying power to the PMIC.
[0038] Understandably, referring to Figure 4 As shown, the first switch control sub-circuit includes a second MOSFET and a third MOSFET. The gate of the second MOSFET is connected to the signal control terminal of the SOC chip under test. The drain of the second MOSFET is grounded. The source of the second MOSFET is connected to the gate of the third MOSFET. The drain of the third MOSFET is connected to the first terminal of the first capacitor and the first resistor. The source of the third MOSFET is connected to a preset power supply.
[0039] For example, refer to Figure 4 As shown, the second MOSFET is Q13, the third MOSFET is Q14, the source of Q13 and the drain of Q14 are connected, the drain of Q13 is grounded, and the gate of Q13 is connected to the signal control terminal of the SOC chip under test.
[0040] Understandably, referring to Figure 4As shown, the first switch control sub-circuit also includes a second resistor, the two ends of which are respectively connected to the source of the second MOS transistor and the source of the third MOS transistor, and the gate of the third MOS transistor is connected to the junction of the second resistor and the source of the second MOS transistor.
[0041] For example, such as Figure 4 As shown, the source of the second MOSFET Q13 is connected to the source of the third MOSFET Q14 through the second resistor R199.
[0042] Understandably, referring to Figure 4 As shown, the first switch control sub-circuit also includes a third resistor, the first end of which is connected to the gate of the second MOS transistor, and the third resistor is connected to the drain of the second MOS transistor.
[0043] For example, such as Figure 4 As shown, the third resistor is R201. The first end of the third resistor R201 is grounded, and the second end of the third resistor R201 is connected to the gate of the second MOS transistor.
[0044] Understandably, the first switch control sub-circuit also includes a fourth resistor, which is connected in series between the third MOSFET and the first capacitor, and is also connected in series between the third MOSFET and the first resistor.
[0045] For example, such as Figure 4 As shown, the third MOSFET Q14 and the fourth resistor R126 are connected in series, and the first capacitor C329 and the first resistor R200 are connected in parallel. The parallel terminals of the fourth resistor R126, the first capacitor C329, and the first resistor R200 are connected in series.
[0046] Understandably, the power conversion circuit includes a DC-DC chip.
[0047] Understandably, referring to Figure 3 As shown in the embodiment of this application, a testing system is provided, the testing system comprising:
[0048] Such as any of the test devices in the first aspect;
[0049] The SOC chip under test is connected to the power supply terminal of the SOC chip and the voltage output terminal of the PMIC. The signal control terminal of the SOC chip under test is connected to the control input terminal of the restart control circuit.
[0050] Understandably, the SOC chip under test is mounted on the PCB board, and the SOC chip under test is detachably connected to the PCB board.
[0051] This application does not limit how the SOC chip under test and the PCB board are detachably connected. In some embodiments, a clamping seat can be provided on the PCB board to clamp and fix the SOC chip under test and to electrically connect the SOC chip under test through the PIN pins on the clamping seat.
[0052] For example, refer to Figure 3 and Figure 4 The test system described in this application, taking a DC-DC power conversion circuit as an example, firstly places the power supply at the front end of the power input of the test board. The test board integrates three MOSFETs. The control input pin "RSET_C" can be connected to any I / O of the SOC chip under test, and the enable control pin "DC-EN" is connected to the EN pin of the DC-DC chip. When power-down is required, the SOC under test outputs a high level on RESET_C, turning on MOSFET Q8, which in turn triggers the shutdown of the DC-DC chip, resulting in a power-down of the entire board. After power-down, due to the effect of resistor R200 and capacitor C328, Q8 will remain in a conducting state. The conduction time is determined by R200 and C328, and the set time can range from milliseconds to tens of seconds (based on the capacitor discharge principle). There is no need to deploy a separate power control system to control the power supply's on / off state; this optimizes the original PMIC power-down method, making the system power-down more thorough.
[0053] The terms “comprising” and “having”, and any variations thereof, in the specification and accompanying drawings of this application are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are expressly listed, but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or apparatus.
[0054] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.
Claims
1. A testing device, characterized in that, The testing apparatus includes: The PCB board integrates a power conversion circuit, a power management integrated circuit (PMIC), and a restart control circuit. The voltage output terminal of the power conversion circuit is connected to the voltage input terminal of the PMIC; the voltage output terminal of the PMIC is used to connect to the power supply terminal of the SOC chip under test. The output terminal of the restart control circuit is connected to the enable control terminal of the power conversion circuit; the control input terminal of the restart control circuit is connected to the signal control terminal of the SOC chip under test; the restart control circuit is used to continuously send an enable control signal to the enable control terminal within a preset time according to the restart signal of the signal control terminal, so that the power conversion circuit stops supplying power to the PMIC for the preset time according to the enable control signal.
2. The testing apparatus according to claim 1, characterized in that, The restart control circuit includes a first switch control sub-circuit, a first capacitor, a first resistor, and a first MOSFET. The control terminal of the first switch control sub-circuit is connected to the signal control terminal of the SOC chip under test. The voltage input terminal of the first switch control sub-circuit is used to connect to a preset power supply. The second terminals of the first capacitor and the first resistor are grounded. The first terminals of the first capacitor and the first resistor are connected to the gate of the first MOSFET and the voltage output terminal of the first switch control sub-circuit, and the first capacitor and the first resistor are located between the gate of the first MOSFET and the first switch control sub-circuit. The first capacitor and the first resistor are used to control the conduction time of the first MOSFET. The first switch control sub-circuit is used to disconnect or connect the voltage input terminal and the voltage output terminal of the first switch control sub-circuit according to the restart signal of the signal control terminal. The drain of the first MOSFET is grounded, and the source of the first MOSFET is connected to the enable control terminal of the power conversion circuit.
3. The testing apparatus according to claim 2, characterized in that, The first switch control sub-circuit includes a second MOSFET and a third MOSFET. The gate of the second MOSFET is connected to the signal control terminal of the SOC chip under test. The drain of the second MOSFET is grounded. The source of the second MOSFET is connected to the gate of the third MOSFET. The drain of the third MOSFET is connected to the first terminal of the first capacitor and the first resistor. The source of the third MOSFET is connected to the preset power supply.
4. The testing apparatus according to claim 3, characterized in that, The first switch control sub-circuit further includes a second resistor, the two ends of which are respectively connected to the source of the second MOS transistor and the source of the third MOS transistor, and the gate of the third MOS transistor is connected to the junction of the second resistor and the source of the second MOS transistor.
5. The testing apparatus according to claim 3, characterized in that, The first switch control sub-circuit further includes a third resistor, the first end of which is connected to the gate of the second MOS transistor, and the third resistor is connected to the drain of the second MOS transistor.
6. The testing apparatus according to claim 3, characterized in that, The first switch control sub-circuit further includes a fourth resistor, which is connected in series between the third MOS transistor and the first capacitor, and also connected in series between the third MOS transistor and the first resistor.
7. The testing apparatus according to claim 3, characterized in that, The power conversion circuit includes a DC-DC chip.
8. A testing system, characterized in that, The testing system includes: The test apparatus as described in any one of claims 1 to 7; The SOC chip under test is connected to the power supply terminal of the PMIC and the signal control terminal of the SOC chip under test is connected to the control input terminal of the restart control circuit.
9. The testing system according to claim 8, characterized in that, The SOC chip under test is mounted on the PCB board, and the SOC chip under test is detachably connected to the PCB board.