A multi-power supply power-on timing control circuit and electronic equipment

Abstract

The utility model relates to electronic circuit technical field discloses a kind of multi-power power-on timing control circuit and electronic equipment, the circuit includes self-locking circuit module, primary power module, at least one secondary power module, self-locking circuit controls primary power start and self-locking, the PG signal of primary power is input comparator after RC delay, and the output enable signal control secondary power after comparing with reference voltage;The PG signal of secondary power is similarly processed by RC delay and comparator, realizes the cascade control of multiple power supply. Circuit is completely made of simulator, without MCU / CPLD and firmware dependence, power-on moment autonomous work, timing accuracy is high, reliability is strong, BOM cost is low, applicable to the multi-power timing control of complex electronic system such as server, communication equipment.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a multi-power supply power-on timing control circuit and electronic equipment. Background Technology

[0002] In complex electronic circuits such as server motherboards, communication equipment, high-end industrial control equipment, and medical instruments, there are often multiple power rails with different voltage levels. Each power rail must meet specific power-on timing requirements. For example, voltage A must reach a stable output value before voltage B, and there must be a preset delay between them. If this timing cannot be strictly controlled, it can easily lead to system latch-up, overcurrent, logic confusion, or even damage to core components. Therefore, accurately controlling the power-on sequence and timing parameters of multiple power supplies is a key prerequisite for ensuring stable system startup.

[0003] However, current mainstream multi-rail power-on timing control schemes all have significant technical shortcomings and are difficult to adapt to actual application requirements, as follows: Option 1: Discrete RC delay circuit. This option uses resistors (R), capacitors (C), and transistors (such as MOSFETs) to build a simple delay-on circuit. Its control logic is as follows: the PG (Power Good) signal from the previous stage power supply is delayed by the RC network and then directly applied to the enable terminal of the next stage power supply, thus achieving basic timing control for the delayed triggering of the next stage after the previous stage starts. The overall topology of this option is shown in Figure 1, and the actual application circuit is shown in Figure 2. Although this option has the advantage of low hardware cost, it has a key technical defect: the voltage rise rate of the RC network is slow, which can easily lead to the problem of the next stage power supply being falsely triggered before the voltage reaches the high-level threshold. This directly results in timing accuracy deviations and cannot meet the high-precision timing control requirements of complex systems.

[0004] Option 2: Programmable control based on MCU / CPLD / FPGA. This option monitors the PG status of each power supply through a microcontroller (MCU) or complex programmable logic device (CPLD / FPGA), and controls the output of the enable signal of each power supply according to the preset program logic. Its overall topology is shown in Figure 3. Although this option has the advantage of flexible configuration of timing parameters, it has significant cost and complexity issues. It requires additional MCU / CPLD / FPGA chips and the design of peripheral circuits such as clock, reset, and memory, which not only directly increases the system BOM (Bill of Materials) cost, but also further increases the complexity and cost of the overall design and subsequent maintenance due to the need to develop and debug firmware / software and perform long-term compatibility maintenance.

[0005] In summary, both of the current mainstream solutions have irreconcilable technical shortcomings and cannot simultaneously meet the core requirements of complex electronic systems for high precision, high reliability, low cost, and low complexity in multi-power supply timing control. Utility Model Content

[0006] This invention provides a multi-power-on timing control circuit and electronic device to solve the problems of poor accuracy and easy false triggering of existing discrete RC solutions, as well as high cost and software dependence of MCU / CPLD solutions.

[0007] In a first aspect, this utility model provides a multi-power-supply timing control circuit, the circuit comprising: a self-locking circuit module, a primary power supply module, and at least one subsequent power supply module, each subsequent power supply module including a power supply unit, a delay unit, and a comparator unit, wherein... The input terminal of the self-locking circuit module is connected to a level signal, the output terminal of the self-locking circuit module is connected to the enable terminal of the primary power supply module, the input terminal of the primary power supply module is connected to a DC power supply, the output terminal of the primary power supply module is connected to the device to be powered, and the power normal signal output terminal of the primary power supply module is connected to the input terminal of the first-stage RC delay unit, which is the delay unit in the first-stage subsequent power supply module. The first input terminal of the first-stage comparator unit is connected to the output terminal of the first-stage RC delay unit. The second input terminal of the first-stage comparator unit is connected to a reference voltage. The output terminal of the first-stage comparator unit is connected to the enable terminal of the first-stage power supply unit. The input terminal of the first-stage power supply unit is connected to a DC power supply. The output terminal of the first-stage power supply unit is connected to the device to be powered. The first-stage comparator unit is the comparator unit in the first-stage power supply module. The first-stage power supply unit is the power supply unit in the first-stage power supply module. If there are multiple stages of power supply modules, the normal power signal output terminal of the previous stage power supply unit is electrically connected to the input terminal of the next stage RC delay unit, the output terminal of the next stage RC delay unit is electrically connected to the first input terminal of the next stage comparator unit, and the output terminal of the next stage comparator unit is electrically connected to the enable terminal of the next stage power supply unit, thus forming cascaded control.

[0008] This invention provides a multi-power-on timing control circuit that cleverly utilizes the self-locking circuit principle. By precisely controlling the enable terminal of the primary power module, it achieves convenient startup and stable maintenance of the first-stage power supply, effectively avoiding power-on failure caused by trigger signal interruption. The design of adding a comparator after the RC delay unit completely avoids the defect of false triggering when the voltage of the traditional discrete RC circuit does not reach the stable threshold. Furthermore, the delay duration can be flexibly configured by adjusting the resistance and capacitance values ​​of the RC components, thereby precisely adjusting the startup interval sequence of different subsequent power supplies. The circuit is built entirely with analog devices, without relying on programmable devices such as MCUs, CPLDs, and FPGAs, or firmware programs. It can operate autonomously instantly upon power-on, without software initialization, ensuring both deterministic and reliable timing control and completely eliminating timing blind spots during software initialization. Simultaneously, relying on the inherent stability of the hardware logic, this circuit significantly reduces the system BOM cost compared to MCU / CPLD programmable solutions and some dedicated IC solutions.

[0009] In one optional embodiment, the self-locking circuit module includes: a first controllable switch, a second controllable switch, a third controllable switch, a first resistor, a second resistor, and a Zener diode, wherein, The control terminal of the first controllable switch is connected to an electrical level signal. The first terminal of the first controllable switch is connected to the first terminal of the second controllable switch and one terminal of the second resistor, respectively. The second terminal of the first controllable switch is grounded. The control terminal of the third controllable switch is connected to one end of the first resistor and the other end of the second resistor, respectively. The first terminal of the third controllable switch is connected to the other end of the first resistor and the DC power supply, respectively. The second terminal of the third controllable switch is connected to the enable terminal of the primary power module and the anode of the Zener diode, respectively. The control terminal of the second controllable switch is connected to the cathode of the Zener diode, and the second terminal of the second controllable switch is grounded.

[0010] In one optional embodiment, the self-locking circuit module further includes a third resistor connected in series between the control terminal and the second terminal of the first controllable switch.

[0011] In one optional implementation, the first controllable switch and the second controllable switch are both NPN transistors, and the third controllable switch is a PMOS transistor.

[0012] In one optional implementation, the comparator unit includes: a comparator, a fourth resistor, and a fifth resistor, wherein, The first input terminal of the comparator is connected to the output terminal of the same stage RC delay unit. The second input terminal of the comparator is connected to one end of the fourth resistor and one end of the fifth resistor, respectively. The output terminal of the comparator is connected to the enable terminal of the same stage power supply unit. The other end of the fourth resistor is connected to the DC voltage, and the other end of the fifth resistor is grounded.

[0013] In one optional implementation, the delay unit includes a sixth resistor and a first capacitor, wherein, One end of the sixth resistor is connected to a DC power supply, and the other end of the sixth resistor is connected to one end of the first capacitor and the normal power signal output terminal of the same level power supply unit, respectively. The other end of the first capacitor is grounded.

[0014] In one optional implementation, the primary power module includes a primary power unit, wherein the primary power unit and the power units in each subsequent power module are DC-DC power modules.

[0015] Secondly, the present invention provides an electronic device, which includes a multi-power-on timing control circuit of the first aspect or any corresponding embodiment described above.

[0016] The electronic device provided by this utility model, due to its integrated timing control circuit, can avoid faults caused by timing disorder upon power-up, ensuring stable startup; it has no software dependency, ensuring reliable long-term operation; it can adjust RC parameters to adapt to different scenarios, and also reduces BOM costs and simplifies maintenance. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is the overall topology diagram of the existing scheme 1; Figure 2 This is the actual application circuit diagram of the existing scheme 1; Figure 3 This is the overall topology diagram of the existing scheme 2; Figure 4 This is a block diagram of the multi-power supply power-on timing control circuit according to an embodiment of the present utility model; Figure 5 This is a circuit diagram of a self-locking circuit module according to an embodiment of the present utility model; Figure 6This is a circuit diagram of the power supply unit according to an embodiment of the present utility model; Figure 7 This is a circuit diagram of a comparator unit according to an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0020] It is understood that before using the technical solutions disclosed in the various embodiments of this utility model, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this utility model in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0021] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.

[0022] In complex electronic systems, the power-on timing of multiple power rails directly determines system reliability. Existing technologies mainly employ two approaches, both of which have significant drawbacks: Option 1: Discrete RC delay circuit, see [link / reference] Figure 1 and Figure 2 This scheme uses resistors (R), capacitors (C), and transistors (such as MOSFETs) to build a simple delayed-on circuit. The PG (Power Good) signal of the first-stage power supply is delayed by the RC network before turning on the enable terminal of the next-stage power supply.

[0023] While this solution boasts the advantage of low cost, it suffers from multiple shortcomings and struggles to meet the needs of complex systems: 1) Extremely low timing accuracy: The RC time constant is highly sensitive to ambient temperature and component tolerance (especially capacitor tolerance), which can easily lead to significant delay fluctuations and make it unsuitable for high-precision timing scenarios. 2) Poor long-term reliability: It directly relies on the delay characteristics of the RC network. Component aging during long-term use will further aggravate timing drift. It is also highly dependent on the threshold voltage and response speed of the front-end power supply PG signal. Any parameter deviation may destroy the timing logic. 3) Weak functional scalability: It can only realize simple timing relationships of single-level triggering, and cannot meet the complex timing control requirements such as cross-dependency between multiple power supplies and multi-level cascading; 4) High risk of false triggering: The voltage rise rate of the RC network is slow. If the PG signal of the preceding stage has not reached the stable high level threshold and is only in the rising process when the next stage power supply is enabled, it will directly cause the subsequent power supply to start falsely, resulting in timing disorder.

[0024] Option 2: Programmable control based on MCU / CPLD / FPGA, see [link / reference] Figure 3 This solution uses a microcontroller (MCU) or complex programmable logic device (CPLD / FPGA) to monitor the PG status of each power supply and control the output of the power supply enable signal according to the preset program logic.

[0025] While this solution offers the flexibility of timing programmability, it suffers from several issues, including cost, reliability, and power consumption. 1) Significantly increased hardware costs: Additional MCU / CPLD / FPGA chips are required, along with peripheral components such as clock circuits, reset circuits, and memory circuits, which directly increases the system BOM cost; 2) High design and maintenance complexity: Firmware / software development, debugging, flashing and long-term compatibility verification are required, which not only extends the project design cycle, but also requires program modification and verification if timing logic needs to be adjusted later, resulting in high maintenance costs. 3) Startup logic contradiction: In the initial stage of system power-on, the MCU / CPLD / FPGA itself must complete the power supply stabilization, clock initialization and program loading process before it can work. There is a contradiction that the control unit must be started before other power supplies can be controlled to start, which can easily lead to timing control startup delay or direct failure. 4) Program execution risks: In actual working conditions, factors such as electromagnetic interference and voltage fluctuations may cause the program to crash, resulting in disorder of timing control logic, and in severe cases, system crash. 5) Additional power consumption: MCU / CPLD / FPGA will continuously consume static power and dynamic power, which does not meet the design requirements of low power systems.

[0026] To address this, the present invention provides a multi-power-on timing control circuit, comprising: a self-locking circuit module, a primary power supply module, and at least one subsequent power supply module. Each subsequent power supply module includes a power supply unit, a delay unit, and a comparator unit. The specific number of subsequent power supply modules is not fixed, but is determined by the actual number of power rails at different voltage levels in the system. Figure 4 illustrates an application scenario with two subsequent power supply modules to clearly demonstrate the cascaded control logic of the multi-power-on timing.

[0027] The input terminal of the self-locking circuit module is connected to an electrical level signal, and the output terminal of the self-locking circuit module is connected to the enable terminal of the primary power supply module. Specifically, the self-locking circuit module receives an external electrical level signal, triggers the primary power supply module to start through hardware self-locking logic, and continuously outputs a stable enable signal to ensure that the primary power supply will not be interrupted due to the disappearance of the trigger signal after startup.

[0028] The primary power module's input is connected to a DC power supply, its output is connected to the device to be powered, and its power normal signal output is connected to the input of the first-stage RC delay unit, which is the delay unit in the first-stage power supply module. Specifically, driven by the enable signal output from the self-locking circuit module, the primary power module converts the externally input DC power supply into a stable first-stage output voltage, which directly provides power to the device in the system. Simultaneously, the primary power module outputs a power normal signal (PG signal, Power Good). This PG signal serves as a critical startup command, specifically used to trigger the startup process of the next-stage power supply module, and is the core trigger signal for achieving multi-power supply cascade timing control. The first-stage RC delay unit receives the PG signal from the previous stage power supply (primary power supply) and, through the charging and discharging characteristics of resistors and capacitors, delays the PG signal by a preset time before outputting it. The delay time can be flexibly configured by adjusting the RC component parameters to meet the timing interval requirements of different power rails.

[0029] The first input terminal of the first-stage comparator unit is connected to the output terminal of the first-stage RC delay unit. The second input terminal of the first-stage comparator unit is connected to a reference voltage. The output terminal of the first-stage comparator unit is connected to the enable terminal of the first-stage power supply unit. The first-stage comparator unit is the comparator unit in the first-stage power supply module, and the first-stage power supply unit is the power supply unit in the first-stage power supply module. Specifically, the first-stage comparator unit acts as a filter for the delayed signal. By comparing it with a fixed reference voltage, it ensures that a high-level enable signal is output to trigger the power supply unit only when the delayed PG signal reaches a stable high level (exceeding the reference voltage). This completely solves the problem of false triggering when the voltage of the traditional discrete RC circuit does not reach the threshold. Driven by the enable signal of the first-stage comparator unit, the first-stage power supply unit converts the input voltage into a stable output voltage and outputs its own PG signal to provide a trigger signal for the next-stage power supply module.

[0030] If multiple power supply modules exist, the normal power signal output of the previous stage power supply unit is electrically connected to the input of the next stage RC delay unit, the output of the next stage RC delay unit is electrically connected to the first input of the next stage comparator unit, and the output of the next stage comparator unit is electrically connected to the enable terminal of the next stage power supply unit, forming a cascaded control. Specifically, if the system has multiple voltage levels of power rails (e.g., requiring four voltage levels: P5V / P3V3 / P1V5 / P1V1), the number of stages in the subsequent power supply module must match the number of power rails excluding the primary stage. The cascading logic is as follows: The PG signal output by the primary power module is first transmitted to the RC delay unit in the first-stage power supply module. After the RC delay unit completes the preset delay processing, the signal is further transmitted to the comparator unit in the first-stage power supply module. The comparator unit compares the delayed PG signal with the reference voltage. When the signal meets the trigger condition, it outputs an enable signal and transmits it to the first-stage power supply unit, which ultimately drives the first-stage power supply unit to start and output the P1V5 voltage.

[0031] After the first-stage power supply unit stabilizes, its output PG signal is transmitted to the RC delay unit in the second-stage power supply module. After the RC delay unit completes the preset delay processing, the signal is transmitted to the comparator unit in the second-stage power supply module. The comparator unit compares the delayed PG signal with the reference voltage. When the trigger condition is met, it outputs an enable signal to drive the second-stage power supply unit to start and output the P1V1 voltage.

[0032] Similarly, for power modules with more stages in the system, the same startup process is followed: the PG signal output by the previous stage power module is first transmitted to the RC delay unit of the next stage power module, and after delay processing, it is transmitted to the current stage comparator unit. The enable signal output by the comparator unit then drives the current stage power module to start. Through this pattern, all power rails in the system are finally powered on in a preset order and with a delay time.

[0033] This invention provides a multi-power-on timing control circuit that cleverly utilizes the self-locking circuit principle. By precisely controlling the enable terminal of the primary power module, it achieves convenient startup and stable maintenance of the first-stage power supply, effectively avoiding power-on failure caused by trigger signal interruption. The design of adding a comparator after the RC delay unit completely avoids the defect of false triggering when the voltage of the traditional discrete RC circuit does not reach the stable threshold. Furthermore, the delay duration can be flexibly configured by adjusting the resistance and capacitance values ​​of the RC components, thereby precisely adjusting the startup interval sequence of different subsequent power supplies. The circuit is built entirely with analog devices, without relying on programmable devices such as MCUs, CPLDs, and FPGAs, or firmware programs. It can operate autonomously instantly upon power-on, without software initialization, ensuring both deterministic and reliable timing control and completely eliminating timing blind spots during software initialization. Simultaneously, relying on the inherent stability of the hardware logic, this circuit significantly reduces the system BOM cost compared to MCU / CPLD programmable solutions and some dedicated IC solutions.

[0034] In one alternative implementation, such as Figure 5 As shown, the self-locking circuit module includes: a first controllable switch Q1, a second controllable switch Q2, a third controllable switch PQ1, a first resistor R10, a second resistor R14, and a Zener diode D1. The control terminal of the first controllable switch Q1 is connected to a voltage level signal. The first terminal of the first controllable switch Q1 is connected to the first terminal of the second controllable switch Q2 and one terminal of the second resistor R14, respectively. The second terminal of the first controllable switch Q1 is grounded. The control terminal of the third controllable switch PQ1 is connected to one terminal of the first resistor R10 and the other terminal of the second resistor R14, respectively. The first terminal of the third controllable switch PQ1 is connected to the other terminal of the first resistor R10 and a DC power supply, respectively. The second terminal of the third controllable switch PQ1 is connected to the enable terminal of the primary power supply module and the anode of the Zener diode D1, respectively. The control terminal of the second controllable switch Q2 is connected to the cathode of the Zener diode D1, and the second terminal of the second controllable switch Q2 is grounded. Both the first and second controllable switches Q1 and Q2 are NPN transistors. The third controllable switch PQ1 is a PMOS transistor.

[0035] Specifically, this application cleverly utilizes the self-locking circuit principle to achieve core control over the power-on sequence of the entire system. Its detailed working process and component functions are as follows: In the self-locking circuit shown in Figure 5, the POWER_ON_SW network is connected to the trigger button, which is configured to be active high by default. When the button is pressed, the high-level signal is transmitted to the base of the first controllable switch Q1 through the current-limiting resistor R16, turning on the first controllable switch Q1. After the first controllable switch Q1 is turned on, its collector and emitter form a path, and since the emitter of the first controllable switch Q1 is grounded, the gate of the third controllable switch PQ1, which is connected to the collector of the first controllable switch Q1, is pulled to ground potential. When the gate of the third controllable switch PQ1 is grounded, the third controllable switch PQ1 is turned on, and the P5V DC power supply is transmitted to the P5V_EN network through the third controllable switch PQ1. At this time, the enable terminal (P5V_EN) of the primary power module obtains an effective voltage, preparing to start the primary power supply.

[0036] When the P5V_EN network is powered on, the voltage of P5V_EN is applied to the anode of Zener diode D1. When the voltage reaches the reverse breakdown voltage of Zener diode D1, Zener diode D1 breaks down in reverse and forms a stable current. The current after the breakdown of Zener diode D1 is transmitted to the base of the second controllable switch Q2 through the current-limiting resistor R18, satisfying the conduction condition of the second controllable switch Q2, making the collector and emitter of the second controllable switch Q2 conduct. After the second controllable switch Q2 conducts, its collector is connected to the collector of the first controllable switch Q1 and the gate of the third controllable switch PQ1. Therefore, the gate of the third controllable switch PQ1 is continuously grounded through the second controllable switch Q2, ensuring that the third controllable switch PQ1 always maintains a source-drain conduction state. Even if the POWER_ON_SW button is released at this time, the gate of the third controllable switch PQ1 is still grounded through the second controllable switch Q2, and the P5V_EN network continues to be energized, forming a self-locking loop in the entire circuit.

[0037] Furthermore, one end of the first resistor R10 is connected to P5V, and the other end is connected to the gate of the third controllable switch PQ1. Together with the second resistor R14, it stabilizes the potential of the gate of the third controllable switch PQ1, optimizes the conduction threshold of the third controllable switch PQ1, and ensures that the third controllable switch PQ1 can reliably conduct when the gate is grounded.

[0038] In one alternative implementation, such as Figure 5 As shown, the self-locking circuit module also includes a third resistor R17, which is connected in series between the control terminal and the second terminal of the first controllable switch Q1.

[0039] Specifically, in the self-locking circuit, each auxiliary component, through precise functional design, provides crucial support for stable circuit operation, prevention of accidental triggering, and component protection. Their specific functions are as follows: The third resistor R17 acts as a pull-down resistor, stabilizing the base potential of the first controllable switch Q1 to ground, preventing external interference signals from causing the first controllable switch Q1 to mis-turn on when the button is not pressed, thus avoiding accidental system power-on. Resistor R16 limits the input current to the base of the first controllable switch Q1, preventing excessive current from burning it out. Resistor R18 limits the current flowing to the base of the second controllable switch Q2 after Zener diode D1 breaks down, protecting both the second controllable switch Q2 and Zener diode D1. Filter capacitors C1~C4 filter out the ripple of the P5V power supply, providing a stable DC input for the entire circuit; filter capacitor C6 filters out voltage fluctuations in the P5V_EN network, ensuring a stable enable signal for the primary power module and preventing accidental primary power supply startup or interruption.

[0040] In one optional implementation, the primary power module includes a primary power unit, wherein the primary power unit and the power units in each subsequent power module are DC-DC power modules.

[0041] Specifically, the primary power module and the power supply units in each subsequent power module all uniformly adopt the DC-DC power module shown in Figure 6. Figure 6 takes the primary power supply unit of the primary power module as an example to illustrate its circuit structure and working logic in detail, as explained below: The startup of the primary power supply unit is directly controlled by the self-locking circuit module. The P5V_EN signal output by the self-locking circuit is the enable signal for the primary power supply unit to output a 3.3V voltage. The primary power supply unit will only start working when the P5V_EN signal is valid. Driven by the P5V_EN enable signal, the primary power supply unit can stably convert the externally input P5V DC power supply into a primary output voltage of 3.3V, providing continuous and stable power to the equipment to be powered. At the same time, the primary power supply unit will synchronously output a power good signal (PG signal, Power Good). This PG signal is the key instruction to trigger the startup of the next stage power supply module and is also the core trigger signal for realizing the timing control of multi-power rail cascading, ensuring that the subsequent power supply only starts after the primary power supply has stabilized.

[0042] Furthermore, the DC-DC power module selected in this application is not limited to the SGM61032 model. This model is only an application example in actual project development. In actual design, other standardized DC-DC modules of other specifications can be flexibly adapted according to the system's requirements for input voltage range, output voltage accuracy, output power, etc. In this embodiment of the utility model, the DC-DC module can be a PWR9 module. The PWR9 module is a mature standardized DC-DC power module, which has pre-integrated the core components required for DC-DC conversion, such as inductors, input and output filter capacitors, and control chips. Integrating and packaging these components simplifies the schematic diagram of the external circuit. On the other hand, relying on the standardized module manufacturing process, it can further ensure the matching and stability of components such as inductors and capacitors, avoiding problems such as low conversion efficiency and large output ripple caused by component parameter mismatch in discrete design.

[0043] Furthermore, in the primary power supply unit circuit shown in Figure 6, the current-limiting resistor R12 is connected in series in the enable signal path to limit the current flowing into the enable terminal of the DC-DC module, preventing damage to the module due to excessive current and ensuring stable transmission of the enable signal. R13 and R15 form a feedback network, directly connected to the feedback terminal (FB) of the DC-DC module, for precise configuration of the module's output voltage. The output voltage is calculated using the formula VOUT = 0.6V × (1 + R13 / R15). By adjusting the resistance ratio of R13 and R15, the output voltage of the DC-DC module can be flexibly set.

[0044] In one alternative implementation, such as Figure 6 As shown, the delay unit includes a sixth resistor R11 and a first capacitor C5. One end of the sixth resistor R11 is connected to the DC power supply, and the other end of the sixth resistor R11 is connected to one end of the first capacitor C5 and the power supply normal signal output terminal of the same stage power supply unit. The other end of the first capacitor C5 is grounded.

[0045] Specifically, the delay unit in each stage of the power supply module uniformly adopts the RC delay circuit structure shown in Figure 6. Figure 6 uses the first-stage delay unit in the first stage power supply module as an example to illustrate its circuit structure and working logic in detail, as explained below: The core of this delay unit is an RC delay network consisting of the sixth resistor R11 and the first capacitor C5. Its input is directly connected to the PG signal (normal power signal) output of the primary power supply unit. When the primary power supply unit outputs the original PG signal, the RC network performs a preset delay on the signal, ultimately outputting the P3V3_PG signal (i.e., the delayed PG signal). This delayed signal is transmitted as a precise delayed trigger signal to the comparator unit in the same stage. By strictly controlling the signal triggering timing, the problem of erroneous triggering of subsequent circuits before the signal reaches a stable high-level threshold, as seen in traditional discrete RC circuits, is effectively avoided. This provides a crucial guarantee for the accuracy of multi-power supply timing control.

[0046] In one alternative implementation, such as Figure 7 As shown, the comparator unit includes: comparator U1A, a fourth resistor R22, and a fifth resistor R27. The first input terminal of comparator U1A is connected to the output terminal of the same-stage RC delay unit. The second input terminal of comparator U1A is connected to one end of the fourth resistor R22 and one end of the fifth resistor R27, respectively. The output terminal of comparator U1A is connected to the enable terminal of the same-stage power supply unit. The other end of the fourth resistor R22 is connected to a DC voltage, and the other end of the fifth resistor R27 is grounded.

[0047] Specifically, the comparator unit in each subsequent power supply module uniformly adopts the hardware structure shown in Figure 7. Figure 7 uses the first-stage comparator unit in the first subsequent power supply module as an example to illustrate its circuit structure and operating logic in detail, as explained below: The P3V3_PG signal (the delayed PG signal) output by the pre-stage RC delay network, while achieving basic timing delay, is susceptible to environmental factors such as temperature and component parameter drift, resulting in insufficient stability and a risk of false triggering. Therefore, this solution adds a comparator after the RC delay network to ensure reliable signal triggering through precise voltage threshold judgment.

[0048] The comparator's reference threshold is generated by a voltage divider network consisting of the fourth resistor R22 and the fifth resistor R27. These two resistors are connected in series and then connected to the system reference voltage (e.g., P3V3). Through resistor value matching, a stable 2.75V reference voltage is finally output, serving as the threshold for the comparator to determine the validity of the P3V3_PG signal. The comparator acquires the P3V3_PG signal output from the RC delay network in real time and compares it with the 2.75V reference threshold. When the P3V3_PG signal voltage is higher than 2.75V, it indicates that the preceding power supply has stabilized and the delay signal has reached a valid state. The comparator then outputs a high-level P3V3_PG_OUT signal, which directly acts on the enable terminal of the same-stage power supply unit, driving the same-stage power supply to start. If the P3V3_PG signal does not reach the 2.75V threshold, the comparator maintains a low-level output, and the same-stage power supply does not start temporarily.

[0049] In addition, the resistor R23 added to the circuit is a pull-up resistor. One end of it is connected to the system reference voltage, and the other end is connected to the comparator output. Its core function is to ensure that when the comparator is not triggered (output low level), the output will not be misjudged due to level floating, and will always maintain a stable low level state, further improving the reliability of the circuit operation.

[0050] This application specifically optimizes the power-on timing of multi-power supply systems, ultimately achieving the core effect of stable and highly reliable overall power-on timing. This effect is not only difficult to achieve with traditional discrete RC solutions, but also has significant advantages in terms of faster response and higher reliability compared to solutions that rely solely on software monitoring. The solution cleverly utilizes a comparator in power-on timing control. Its key innovation lies in the fact that the comparator does not directly monitor the power supply voltage itself, but instead specifically monitors the ramp voltage generated by the local RC delay network driven by the front-end control signal or the PG signal (power normal signal). By judging this ramp voltage, the timing delay rhythm can be accurately controlled, and the problem of being susceptible to ripple interference when directly monitoring the power supply voltage can be avoided, further improving the stability of timing control. Furthermore, by using a precision comparator and a stable Vref, combined with a high-quality RC, a much higher timing accuracy and temperature stability than traditional discrete solutions are achieved.

[0051] The entire timing control circuit is composed entirely of analog devices (comparators, resistors, capacitors) and basic logic circuits. The entire control process does not depend on any clock signal, processor instructions, or programmable logic. It completely avoids the risks of software / firmware initialization delays and operational instability, providing the highest level of power-on timing determinism and reliability. Circuit behavior is determined solely by hardware connections and component parameters, exhibiting consistent performance under all power-on conditions and unaffected by software states. It avoids traditional hardware RC delay schemes.

[0052] This utility model provides a multi-power supply power-on sequence control circuit. It cleverly utilizes the self-locking circuit principle to design a primary power supply whose enable terminal is controlled by a self-locking circuit, allowing for one-button startup of the first-stage power supply. The second and third-stage power supplies are connected to a comparator after the output of the PG pin of the previous stage and an RC delay. Based on a pure hardware logic chain using a precision voltage comparator and configurable delay units, multi-power supply power-on sequence control is achieved. This avoids the false triggering of traditional RC circuits and allows for flexible adjustment of the startup sequence. Furthermore, the circuit does not rely on any MCU, CPLD, FPGA, or firmware program, and operates autonomously from the moment of power-on, ensuring deterministic and reliable control, avoiding timing blind spots caused by software initialization, and allowing for flexible configuration of the startup order among multiple power supplies. Compared to MCU / CPLD solutions and some dedicated IC solutions, it reduces BOM cost and design complexity, and simplifies debugging and configuration.

[0053] This utility model provides an electronic device, including Figures 4-7 The multi-power supply power-on sequence control circuit shown is shown.

[0054] Specifically, the electronic device of this invention mainly addresses complex scenarios requiring stable power supply from multiple power rails, including but not limited to: server motherboards, communication base station equipment, high-end industrial control devices, and medical diagnostic instruments. These devices share a common requirement: they contain multiple power rails of different voltage levels (e.g., P5V, P3V3, P1V5, P1V1), and each power rail must adhere to strict power-on sequence and delay requirements (e.g., P5V stabilizes first, P3V3 starts after a 10ms delay, and P1V5 starts after a 5ms delay). Otherwise, latch-up, overcurrent, logic corruption, or even damage to the core chip can easily occur. The timing control circuit shown in Figures 4-7 precisely addresses the power supply pain points of these devices. Through self-locking start-up, RC delay, and pure hardware logic using a precision comparator, it achieves high-precision, high-reliability timing control of multiple power rails, perfectly meeting the core requirements of the aforementioned electronic devices.

[0055] The electronic device provided by this utility model, due to its integrated timing control circuit, can avoid faults caused by timing disorder upon power-up, ensuring stable startup; it has no software dependency, ensuring reliable long-term operation; it can adjust RC parameters to adapt to different scenarios, and also reduces BOM costs and simplifies maintenance.

[0056] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A multi-power-supply power-on timing control circuit, characterized in that, The circuit includes: a self-locking circuit module, a primary power supply module, and at least one subsequent power supply module. Each subsequent power supply module includes a power supply unit, a delay unit, and a comparator unit. The input terminal of the self-locking circuit module is connected to a level signal, the output terminal of the self-locking circuit module is connected to the enable terminal of the primary power supply module, the input terminal of the primary power supply module is connected to a DC power supply, the output terminal of the primary power supply module is connected to the device to be powered, and the power normal signal output terminal of the primary power supply module is connected to the input terminal of the first-stage RC delay unit, which is the delay unit in the first-stage subsequent power supply module. The first input terminal of the first-stage comparator unit is connected to the output terminal of the first-stage RC delay unit. The second input terminal of the first-stage comparator unit is connected to a reference voltage. The output terminal of the first-stage comparator unit is connected to the enable terminal of the first-stage power supply unit. The input terminal of the first-stage power supply unit is connected to a DC power supply. The output terminal of the first-stage power supply unit is connected to the device to be powered. The first-stage comparator unit is the comparator unit in the first-stage power supply module. The first-stage power supply unit is the power supply unit in the first-stage power supply module. If there are multiple stages of power supply modules, the normal power signal output terminal of the previous stage power supply unit is electrically connected to the input terminal of the next stage RC delay unit, the output terminal of the next stage RC delay unit is electrically connected to the first input terminal of the next stage comparator unit, and the output terminal of the next stage comparator unit is electrically connected to the enable terminal of the next stage power supply unit, thus forming a cascaded control.

2. The multi-power supply power-on timing control circuit according to claim 1, characterized in that, The self-locking circuit module includes: a first controllable switch, a second controllable switch, a third controllable switch, a first resistor, a second resistor, and a Zener diode, wherein... The control terminal of the first controllable switch is connected to an electrical level signal. The first terminal of the first controllable switch is connected to the first terminal of the second controllable switch and one terminal of the second resistor, respectively. The second terminal of the first controllable switch is grounded. The control terminal of the third controllable switch is connected to one end of the first resistor and the other end of the second resistor, respectively. The first terminal of the third controllable switch is connected to the other end of the first resistor and the DC power supply, respectively. The second terminal of the third controllable switch is connected to the enable terminal of the primary power module and the anode of the Zener diode, respectively. The control terminal of the second controllable switch is connected to the cathode of the Zener diode, and the second terminal of the second controllable switch is grounded.

3. The multi-power-on timing control circuit according to claim 2, characterized in that, The self-locking circuit module further includes a third resistor, which is connected in series between the control terminal and the second terminal of the first controllable switch.

4. The multi-power supply power-on timing control circuit according to claim 2, characterized in that, The first and second controllable switches are both NPN transistors, and the third controllable switch is a PMOS transistor.

5. The multi-power-on timing control circuit according to claim 1, characterized in that, The comparator unit includes: a comparator, a fourth resistor, and a fifth resistor, wherein, The first input terminal of the comparator is connected to the output terminal of the same stage RC delay unit. The second input terminal of the comparator is connected to one end of the fourth resistor and one end of the fifth resistor, respectively. The output terminal of the comparator is connected to the enable terminal of the same stage power supply unit. The other end of the fourth resistor is connected to the DC voltage, and the other end of the fifth resistor is grounded.

6. The multi-power supply power-on timing control circuit according to claim 1, characterized in that, The delay unit includes a sixth resistor and a first capacitor, wherein, One end of the sixth resistor is connected to a DC power supply, and the other end of the sixth resistor is connected to one end of the first capacitor and the normal power signal output terminal of the same level power supply unit, respectively. The other end of the first capacitor is grounded.

7. The multi-power supply power-on timing control circuit according to claim 1, characterized in that, The primary power module includes a primary power unit, and the power units in the primary power unit and each subsequent power module adopt a DC-DC power module.

8. An electronic device, characterized in that, The electronic device includes the multi-power-on timing control circuit according to any one of claims 1-7.

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