A power module with front and back cascaded protection circuit and its heat dissipation shell

Abstract

The utility model relates to power module technical field provides a power module with front and rear cascade action protection circuit and its heat dissipation casing, through the overvoltage and undervoltage state of control chip detection input voltage in front stage protection circuit, and based on overvoltage or undervoltage state drive MOSFET conduction or shut off, thereby control the power supply to the rear stage circuit. Meanwhile, the EN pin of buck chip U1 is linked with the PGD pin of the control chip U2, which realizes rapid response relying on hardware, avoids abnormal voltage acting on the rear chip, prevents device damage, does not need software intervention, simplifies the control link, reduces the software failure risk, ensures the front and rear stage cooperative action, and improves the protection timeliness.

Description

Technical Field

[0001] This utility model relates to the field of power module technology, and more specifically, to a power module with a front-to-back stage linkage protection circuit and its heat dissipation housing. Background Technology

[0002] The content in this section only provides background information related to this utility model and may not constitute prior art.

[0003] In applications requiring highly reliable power supplies, such as servers, communication base stations, and industrial control equipment, it is often necessary to convert high DC input voltages (e.g., 724V, 48V, or 760V via-hole) into stable low-voltage DC outputs. Existing technologies typically employ a front-end hot-swappable controller in conjunction with a rear-end 7-channel DC / DC step-down chip to achieve this function: the front-end handles overvoltage, undervoltage, and overcurrent protection on the input side, while the rear-end reduces the input voltage to the target output voltage. However, existing solutions have some shortcomings in practical applications.

[0004] First, the pre-amplifier and power-up circuits are controlled independently. When an abnormal input voltage occurs (overvoltage or undervoltage), the pre-amplifier controller may cut off the input, but the power-up buck circuit, lacking a linkage signal, may continue to attempt operation, posing a risk of overvoltage damage to components. Second, most systems require manual restart or a microcontroller unit (MCU) command to resume operation after a fault is resolved, resulting in low automation and impacting system reliability.

[0005] Therefore, there is an urgent need for an improved power module design that enables the front-end protection and the back-end buck converter to be linked for control and automatic recovery. Summary of the Invention

[0006] To address the aforementioned technical problems, the present invention aims to provide a power module and its heat dissipation housing with a front-to-back stage linkage protection circuit. The front-to-back protection circuit uses a control chip to detect overvoltage and undervoltage states of the input voltage and drives the MOSFET to turn on or off based on these states. This is achieved through linkage between the EN pin of the buck chip U1 and the PGD pin of the control chip U2, enabling rapid hardware response, preventing abnormal voltage from acting on the downstream chips, and preventing device damage. Furthermore, it eliminates the need for software intervention, simplifying the control chain and reducing the risk of software failure.

[0007] The objective of this utility model is achieved through the following technical solution: In a first aspect, this utility model provides a power supply module with a front-to-back stage linkage protection circuit, comprising: The pre-stage protection circuit includes an overvoltage divider sampling module, an undervoltage divider sampling module, and a control chip U2 for detecting the overvoltage and undervoltage states of the input voltage. The input terminals of the overvoltage divider sampling module and the undervoltage divider sampling module are connected to the power supply, and the output terminals of the overvoltage divider sampling module and the undervoltage divider sampling module are connected to the control chip U2. An external power MOSFET module is powered by a power supply and is connected to the control chip U2. In response to the drive signal of the control chip U2, the external power MOSFET module performs to turn on or off. The subsequent step-down circuit includes a step-down chip U1 and a voltage divider module. The EN pin of the step-down chip U1 is connected to the PGD pin of the control chip U2. When the external power MOSFET module is turned off, the step-down chip U1 is turned off synchronously. When the external power MOSFET module is turned on, the PGD signal of the control chip U2 automatically rises and restarts the step-down circuit. The voltage divider module is connected to the FB pin of the step-down chip U1.

[0008] Furthermore, the connection between the EN pin of the aforementioned step-down chip U1 and the PGD pin of the aforementioned control chip U2 can be achieved by one of the following methods: direct connection with a resistor, connection via optocoupler isolation, or connection through a logic circuit.

[0009] Furthermore, it also includes the aforementioned delay module, which includes a resistor R and a capacitor C. One end of the resistor R is connected to the EN pin of the step-down chip U1, and the other end of the resistor R is connected to the PGD pin of the control chip U2. One end of the capacitor C is connected to the EN pin of the step-down chip U1, and the other end of the capacitor C is grounded.

[0010] Furthermore, the aforementioned external power MOSFET module includes a diode D4, a capacitor C24, and a MOSFET Q2. The cathode of the diode D4 is connected to the gate of the MOSFET Q2 and the GATE pin of the control chip U2, respectively. The anode of the diode D4 is connected to the drain of the MOSFET Q2, and the source of the MOSFET Q2 is connected to the OUT pin of the control chip U2 and the VIN pin of the buck chip U1, respectively. The capacitor C24 is connected in parallel with the diode D4.

[0011] Furthermore, the voltage divider module includes multiple voltage divider units and resistor R32. Each voltage divider unit includes a voltage divider resistor and a switch connected in series. Multiple voltage divider units are arranged in parallel. In any voltage divider unit, the end of the voltage divider resistor away from the switch is connected to the FB pin of the buck chip U1. The FB pin of the buck chip U1 is connected to the target voltage output terminal through the resistor R32.

[0012] Furthermore, it also includes a current limiting module, which includes a Schottky diode D2, a resistor R12, a capacitor C18, and a capacitor C22. The cathode of the Schottky diode D2, the resistor R12, and the SEN pin of the control chip U2 are connected in sequence; the anode of the Schottky diode D2 is grounded; and the capacitors C18 and C22 are connected in parallel with the Schottky diode D2.

[0013] Furthermore, it also includes a loop compensation module, which includes a resistor R24, a capacitor C2, and a capacitor C23 connected in sequence to form a loop. The end of the resistor R24 ​​away from the capacitor C2 is connected to the COMP pin of the step-down chip U1, and the end of the capacitor C2 away from the resistor R24 ​​is grounded.

[0014] Furthermore, it also includes a capacitor C1 and an inductor L1 connected in series. The end of the capacitor C1 away from the inductor L1 is connected to the BOOT pin of the step-down chip U1, the end of the capacitor C1 close to the inductor L1 is connected to the SW pin of the step-down chip U1, and the end of the inductor L1 away from the capacitor C1 is connected to the target voltage output terminal.

[0015] Secondly, this utility model provides a heat dissipation housing, including: an upper housing, a lower housing, and a circuit board equipped with a power module having a front-to-back linkage protection circuit as described in the first aspect; the upper housing and the lower housing are combined to form a cavity adapted to the shape of the circuit board, the circuit board is disposed in the cavity and contacts the upper housing and the lower housing respectively; multiple sets of heat dissipation fins are provided on the outer walls of the upper housing and the lower housing, any one of the heat dissipation fins is perpendicular to the circuit board, and there is a gap between adjacent heat dissipation fins.

[0016] Furthermore, several through holes are evenly provided on the side walls of the upper and lower housings. These through holes serve both as airflow and heat dissipation holes and as mounting and positioning holes.

[0017] In summary, the technical solution of this utility model embodiment has at least the following advantages and beneficial effects: This invention utilizes an external power MOSFET module to receive drive signals from the pre-stage control chip. The PGD pin of the pre-stage control chip is directly connected to the EN pin of the subsequent buck converter chip. When the pre-stage MOSFET module is off, the power supply normal pin outputs a low level, causing the subsequent buck converter chip to shut down synchronously. When the MOSFET module is on and the input is normal, the power supply normal pin outputs a high level, activating the subsequent buck converter chip. This hardware-based rapid response prevents abnormal voltage from affecting the subsequent chips, thus preventing device damage. Furthermore, it eliminates the need for software intervention, simplifying the control chain, reducing the risk of software failures, and ensuring coordinated operation between the pre-stage and subsequent stages, improving timely protection. Attached Figure Description

[0018] Figure 1 A schematic diagram of the structure of a power module with a front-to-back linkage protection circuit provided by this utility model; Figure 2 This is a circuit diagram of the overvoltage divider sampling module in this utility model; Figure 3 This is a circuit diagram of the undervoltage divider sampling module in this utility model; Figure 4 This is a pin diagram of the control chip U2 in this utility model; Figure 5 This is a circuit diagram of the external power MOSFET module in this utility model; Figure 6 This is the circuit diagram of the subsequent step-down circuit in this utility model; Figure 7 This is the circuit schematic diagram of the current limiting module in this utility model; Figure 8 This is the circuit schematic diagram of the delay module in this utility model; Figure 9 This is a schematic diagram of the structure of a heat dissipation shell provided by this utility model.

[0019] Icons: 1. Pre-amplifier protection circuit; 11. Overvoltage divider sampling module; 12. Undervoltage divider sampling module; 2. External power MOSFET module; 3. Post-amplifier step-down circuit; 31. Voltage divider module; 4. Upper housing; 5. Lower housing; 6. Heat sink; 7. Through hole. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Example 1:

[0022] like Figure 1 As shown in the figure, the power supply module with a front-to-back linkage protection circuit proposed in this utility model embodiment includes a front-end protection circuit 1. The front-end protection circuit 1 includes an overvoltage divider sampling module 11, an undervoltage divider sampling module 12, and a control chip U2 for detecting the overvoltage and undervoltage states of the input voltage. The input terminals of the overvoltage divider sampling module 11 and the undervoltage divider sampling module 12 are connected to the power supply, and the output terminals of the overvoltage divider sampling module 11 and the undervoltage divider sampling module 12 are connected to the control chip U2.

[0023] Specifically, the front-end protection circuit 1 is the core protection and control unit on the input side of the power module. Its function is to monitor the voltage status of the high-voltage DC power supply (such as 24V, 48V or 60V, adapting to the power supply needs of servers, communication base stations, industrial control equipment and other scenarios) input to the power module in real time, and realize accurate overvoltage and undervoltage protection logic based on preset thresholds. At the same time, it provides a basis for linkage control for the start and stop of the subsequent circuits through status signal output, so as to avoid damage to the power module and downstream loads caused by abnormal input voltage from the source, and ensure the reliability and safety of the entire power supply system.

[0024] Among them, the control chip U2, such as Figure 4 As shown, this is the decision-making center of the entire front-end protection circuit 1. It integrates a voltage comparator, drive logic unit, and status monitoring unit, enabling it to detect overvoltage and undervoltage conditions of the input voltage, for example, using an LM5069MM-2 / NOPB. Specifically, the control chip U2 receives the voltage signal transmitted from the external voltage divider sampling module and compares it with the preset voltage threshold inside the chip to determine whether the input voltage is within the legal operating range. Simultaneously, the control chip U2 can output corresponding control signals based on the determination result (used to drive the external power MOSFET module 2; although this module is not part of the front-end protection circuit 1 itself, it is an execution link of the front-end protection logic). It also provides feedback on its own operating status and the legality of the input voltage through its PGD (Power-Good) pin, providing crucial signal support for the coordinated control of the front-end protection circuit 1 and the subsequent buck circuit 3, ensuring that the front and rear circuits can act collaboratively when there is an input abnormality, thus improving the timeliness and reliability of the overall protection.

[0025] Among them, such as Figure 2As shown, the overvoltage divider sampling module 11 includes resistors R29 and R30 connected in series. The end of resistor R29 furthest from resistor R30 is directly connected to the input power supply, and the end of resistor R30 furthest from resistor R29 is grounded. The connection point between resistors R29 and R30 is electrically connected to the OVLO (Over-Voltage Lockout) pin of the control chip U2. Since the input power supply is usually high-voltage DC, its voltage value far exceeds the tolerance range of the control chip U2 pin (the chip pin can generally only withstand low-voltage signals). Therefore, it is necessary to use the voltage divider network formed by resistors R29 and R30 to reduce the input high voltage by a fixed ratio, so that the voltage signal transmitted to the OVLO pin is within the detection range of the control chip U2, thus preventing the chip pin from being damaged by overvoltage. When the input power supply voltage rises above the preset overvoltage threshold (for example, for a 48V nominal input system, the overvoltage threshold can be set to 60V; the specific threshold can be adjusted according to the actual application scenario), the voltage value transmitted to the OVLO pin by the voltage divider network will rise synchronously until it reaches the action threshold of the voltage comparator inside the control chip U2. At this time, the control chip U2 immediately determines that the input is in an overvoltage state and triggers protection logic (such as controlling the external power MOSFET module 2 to turn off), thereby cutting off the power supply to the subsequent circuit and preventing the overvoltage input from damaging the subsequent step-down chip U1 or causing damage to downstream load components. The beneficial effect of this overvoltage divider sampling module 11 is that its voltage division ratio can be flexibly set by adjusting the resistance ratio of resistors R29 and R30, thereby realizing the configuration of different overvoltage thresholds. This allows the front-end protection circuit 1 to adapt to systems with multiple input voltage levels such as 24V, 48V, and 60V, improving the versatility and applicability of the circuit. It eliminates the need to design separate protection circuits for different input voltage scenarios, reducing design costs and complexity.

[0026] Correspondingly, the pre-stage protection circuit 1 is also equipped with an undervoltage divider sampling module 12, such as... Figure 3As shown, this module, used for detecting undervoltage input, consists of resistors R31 and R15 connected in series. The end of resistor R31 furthest from resistor R15 is connected to the input power supply, while the end of resistor R15 furthest from resistor R31 is grounded. The connection point between resistors R31 and R15 is electrically connected to the UVLO (Under-Voltage Lockout) pin of the control chip U2. Consistent with the design logic of the overvoltage divider sampling module 11, the undervoltage divider sampling module 12 also uses the voltage divider effect of resistors R31 and R15 to reduce the input high voltage and transmit it to the UVLO pin, providing the control chip U2 with an undervoltage detection sampling signal. When the input power supply voltage drops below a preset undervoltage threshold (for example, for a 48V nominal input system, the undervoltage threshold can be set to 36V), the voltage value transmitted to the UVLO pin by the voltage divider network will decrease synchronously, falling below the undervoltage action threshold of the voltage comparator inside the control chip U2. At this point, the control chip U2 determines that the input is in an undervoltage state. The reason for needing undervoltage protection is that when the input voltage is too low, the subsequent step-down circuit 3 may experience unstable output voltage or even abnormal operating current due to insufficient input energy, causing overheating of the subsequent chips or malfunction of the load. Therefore, the control chip U2 triggers the undervoltage protection logic to prevent the subsequent circuit from forcing operation under insufficient input voltage and causing failure. The beneficial effect of this undervoltage divider sampling module 12 is that it can also set different undervoltage thresholds by adjusting the resistance ratio of resistors R31 and R15. For example, for a 24V nominal input system, the undervoltage threshold can be adjusted to 18V, further enhancing the adaptability of the front-end protection circuit 1 to different input voltage scenarios and meeting diverse application needs.

[0027] External power MOSFET module 2, such as Figure 4 As shown, the external power MOSFET module 2 is powered by a power supply and is connected to the control chip U2. In response to the drive signal of the control chip U2, the external power MOSFET module 2 performs to turn on or off.

[0028] Among them, the external power MOSFET module 2 is the core execution unit connecting the front-end protection circuit 1 and the rear-end buck circuit 3. By receiving the control signal from the front-end protection circuit 1, it realizes the control of the power supply path of the rear-end buck circuit 3 to turn on and off, which is a key link in the implementation of the front-end protection logic.

[0029] Specifically, the external power MOSFET module 2 consists of diode D4, capacitor C24 and MOSFET Q2. The connection relationship and functional coordination of each component are designed to ensure that the module can work stably and reliably under different operating conditions. In this circuit, the cathode of diode D4 is electrically connected to the gate of MOSFET Q2 and the GATE pin of control chip U2, while the anode of diode D4 is electrically connected to the drain of MOSFET Q2. This connection allows diode D4 to form a reverse protection path for the gate of MOSFET Q2. Since a reverse potential may be generated between the gate and drain of MOSFET Q2 due to transient voltage fluctuations in the front-end bus (such as input-side surges or reverse induced voltages in subsequent circuits), diode D4 can quickly discharge this reverse potential to the drain through its unidirectional conductivity, preventing the gate from being broken down due to reverse overvoltage and ensuring the safety of the gate drive circuit of MOSFET Q2. At the same time, during the turn-off process of MOSFET Q2, diode D4 can also accelerate the release of gate charge, shorten the turn-off delay of MOSFET Q2, improve the response speed of the front-end protection circuit 1 to abnormal inputs, and ensure that the power supply to the subsequent stage can be quickly cut off when input overvoltage, undervoltage, or other faults occur.

[0030] Furthermore, capacitor C24 and diode D4 are connected in parallel. Their core function is to filter and compensate the charge of the GATE drive signal output by control chip U2. The drive signal output from the GATE pin of control chip U2 is used to control the turn-on / turn-off of the external MOSFET. This signal may generate high-frequency ripple due to internal logic switching. Capacitor C24 can absorb this high-frequency ripple through its charging and discharging characteristics, making the drive voltage transmitted to the gate of MOSFET Q2 more stable. This avoids MOSFET Q2 operating in an unstable linear region due to drive voltage fluctuations, reducing the switching losses and heat generation of MOSFET Q2. In addition, at the moment MOSFET Q2 turns on, the gate needs to quickly acquire sufficient drive charge to achieve saturation conduction. Capacitor C24 can pre-store some charge and quickly release it to the gate at the moment of turn-on to replenish the drive current, ensuring that MOSFET Q2 can quickly switch from the off state to the on state, reducing dynamic losses during the conduction process.

[0031] MOSFET Q2, as the core switching element of the external power MOSFET module 2, has its drain not directly connected to the input power supply (VIN of the front stage), but indirectly connected to the relevant power supply circuit of the control chip U2 through the bus of the front stage protection circuit 1. Its source is electrically connected to the OUT pin of the control chip U2 and the VIN pin of the buck chip U1, forming the main power supply path from the front stage bus to the rear stage buck circuit 3. The operating state of MOSFET Q2 is completely controlled by the drive signal output from the GATE pin of the control chip U2: when the control chip U2 detects that the input voltage is within the normal range (such as the 36V~60V range of a 48V nominal input system) through the overvoltage divider sampling module 11 (resistors R29, R30) and the undervoltage divider sampling module 12 (resistors R31, R15), the GATE pin of the control chip U2 outputs a gradually increasing drive voltage (this gradually increasing characteristic is achieved by the gradually increasing capacitor connected to the TIMER pin of the control chip U2). The implementation, namely the "pre-stage soft-start / limited slope" design, involves filtering the drive voltage through diode D4 and transmitting it to the gate of MOSFET Q2, causing the gate-source voltage of MOSFET Q2 to gradually increase. MOSFET Q2 slowly transitions from the off state to the on state, which is the "soft-start" control of the pre-stage protection circuit 1. By controlling the conduction slope of MOSFET Q2, the circuit avoids the large current surge generated when the pre-stage bus is directly "hard-closed" to the subsequent step-down circuit 3, preventing the surge current from impacting the components of the subsequent step-down circuit 3 and reducing stress damage to the components.

[0032] In practical implementation, when control chip U2 detects an abnormal input voltage (such as a voltage below the 36V undervoltage threshold or above the 60V overvoltage threshold), the GATE pin of control chip U2 immediately stops outputting the drive voltage and rapidly discharges the gate charge through an internal discharge circuit. This causes the gate-source voltage of MOSFET Q2 to quickly drop below the conduction threshold, and MOSFET Q2 quickly turns off the main power supply path, disconnecting the connection between the front-end bus and the rear-end buck circuit 3. This prevents abnormal voltage from directly acting on buck chip U1, preventing buck chip U1 from being damaged by overvoltage or by unstable output voltage due to undervoltage, thus damaging downstream components. The load; at the same time, the source of MOSFET Q2 is connected to the OUT pin of control chip U2, so that control chip U2 can monitor the voltage and current signal of the source of MOSFET Q2 in real time. Combined with the external sampling resistor connected to the SENSE pin of control chip U2, it can determine whether there is an overcurrent fault in MOSFET Q2 (such as a short circuit in the subsequent step-down circuit 3 causing a sudden increase in input current). If an overcurrent occurs, control chip U2 can immediately turn off the GATE drive signal to realize overcurrent protection for MOSFET Q2 and prevent MOSFET Q2 from burning out due to overcurrent and overheating. This is consistent with the "coarse protection" function of the front-end protection circuit 1.

[0033] Post-stage step-down circuit 3, such as Figure 6As shown, the subsequent step-down circuit 3 includes a step-down chip U1 and a voltage divider module 31. The EN pin of the step-down chip U1 is connected to the PGD pin of the control chip U2. When the external power MOSFET module 2 is turned off, the step-down chip U1 is turned off synchronously. When the external power MOSFET module 2 is turned on, the PGD signal of the control chip U2 automatically rises and restarts the step-down circuit. The voltage divider module 31 is connected to the FB pin of the step-down chip U1.

[0034] Specifically, the post-stage step-down circuit 3 is the core functional unit in the power module of this utility model that realizes voltage conversion and stable output. Its core components include a step-down chip U1 and a voltage divider module 31. At the same time, it needs to form a close linkage with the pre-stage protection circuit 1 to ensure that the target voltage is stably output when the input voltage is normal and stops working synchronously when the input is abnormal, so as to ensure the overall reliability of the circuit. In this circuit, the EN pin (enable control terminal) of the buck converter U1 is directly electrically connected to the PGD pin (Power-Good, power normal indicator terminal) of the control chip U2 in the front-end protection circuit 1. This connection is crucial for achieving coordinated control between the front and rear stages: when abnormal conditions such as overvoltage or undervoltage occur in the input voltage, the external power MOSFET module 2 (composed of diode D4, capacitor C24, and MOSFET Q2) in the front-end protection circuit 1 is turned off in response to the drive signal of the control chip U2. Simultaneously, the PGD pin of the control chip U2 outputs a low-level signal. This low-level signal, transmitted to the EN pin of the buck converter U1, immediately triggers the turn-off logic of the buck converter U1, causing the subsequent buck converter circuit 3 to stop working synchronously. This prevents abnormal input voltage from directly affecting the buck converter U1 or downstream load, preventing device failures such as output instability due to overvoltage breakdown or undervoltage. When the input voltage returns to the preset value... Within the normal range (e.g., 36V~60V for a 48V nominal input system), when the external power MOSFET module 2 in the pre-stage protection circuit 1 is turned on again under the drive of the control chip U2, the control chip U2 will determine through its internal monitoring unit that the input voltage is valid and the MOSFET module has been reliably turned on. At this time, the PGD pin will automatically output a high-level signal. After this high-level signal is transmitted to the EN pin of the buck chip U1, it will release the buck chip U1 from its off state, drive it to restart and execute the internal soft-start program, so that the output voltage slowly rises to the target value according to the preset ramp, avoiding the voltage overshoot at the moment of startup from impacting the downstream load. This linkage logic is entirely hardware-based and does not require the intervention of a microcontroller unit (MCU). The response speed can reach the microsecond level. Compared with the traditional control scheme that relies on the MCU, it simplifies the control link, reduces the risk of software failure, and improves the timeliness of abnormal response and recovery.

[0035] The voltage divider module 31 includes multiple voltage divider units and resistor R32. Each voltage divider unit consists of a voltage divider resistor and a switch connected in series. The multiple voltage divider units are arranged in parallel. This design allows for flexible switching of the switching states of different voltage divider units to achieve multi-level adjustment of the output voltage, adapting to the voltage requirements of different downstream loads (such as the 5V, 8.4V, 12V, and 24V output levels mentioned in the document). In terms of specific connections, in any voltage divider unit, the end of the voltage divider resistor furthest from the switch is electrically connected to the FB pin (feedback pin) of the buck chip U1. At the same time, the FB pin of the buck chip U1 is electrically connected to the target voltage output terminal (VOUT) of the subsequent buck circuit 3 through resistor R32, forming a complete voltage feedback loop. Its working principle is as follows: The voltage signal at the target voltage output terminal is transmitted to the FB pin via resistor R32. At the same time, each parallel voltage divider unit connects a voltage divider resistor of different values ​​to the feedback loop according to the on / off state of the switch. By adjusting the resistance ratio of the voltage divider resistor to resistor R32, the feedback voltage value transmitted to the FB pin is changed. The error amplifier integrated inside the buck chip U1 compares the feedback voltage value with the preset reference voltage value inside the chip (such as the common 0.8V reference voltage) in real time. If the feedback voltage is lower than the reference voltage, the error amplifier will output a control signal to increase the conduction time of the power transistor inside the buck chip and increase the output voltage. If the feedback voltage is higher than the reference voltage, the conduction time will be reduced and the output voltage will be reduced. Through this closed-loop regulation mechanism, the output voltage is ensured to be stable at the target value set by the voltage divider ratio, thus achieving high-precision voltage regulation. For example, when a 12V output is required, the voltage divider unit switch corresponding to the voltage divider ratio can be closed, so that the voltage divider resistor of the voltage divider unit is connected to the feedback loop. Through the synergistic effect of resistor R32 and the voltage divider resistor, the feedback voltage of the FB pin is stabilized at the reference voltage, thereby enabling the output terminal to stably output 12V. If it is necessary to switch to 5V output, simply disconnect the original voltage divider unit switch and close the voltage divider unit switch corresponding to the 5V voltage divider ratio. There is no need to replace the step-down chip or reconstruct the circuit, which greatly improves the versatility and flexibility of the circuit.

[0036] In addition, regarding the connection method between the PGD pin of the front-end control chip U2 and the EN pin of the back-end buck chip U1, besides the above-mentioned direct resistor connection, in practical applications, the connection can also be made via optocoupler isolation or through logic circuits, depending on the specific scenario requirements. Specifically, when using optocoupler isolation connection, the electrical isolation characteristics of optocouplers can be utilized to achieve isolation between the high-voltage side of the front stage and the low-voltage side of the rear stage, avoiding mutual influence between the two circuits due to common ground interference, voltage fluctuations, and other issues. This improves the circuit's anti-interference capability in complex electromagnetic environments, making it particularly suitable for scenarios such as medical equipment and industrial automation control where high electrical isolation is required. When using logic circuit connection (such as through AND gates, OR gates, and other logic devices), additional control signals (such as system enable signals, load status signals, etc.) can be introduced to achieve multi-condition linkage control. For example, the rear-stage step-down chip U1 is only allowed to start when the front-stage PGD signal is high and the system enable signal is high, further improving the flexibility and safety of circuit control. The above different connection methods are all equivalent implementations of this utility model and can be flexibly selected according to the needs of actual application scenarios. All of them can achieve reliable linkage between the front and rear stage circuits and ensure the stable operation of the power module.

[0037] In addition, such as Figure 8 As shown, this embodiment also includes a delay module between the PGD and EN pins. The delay module includes a resistor R and a capacitor C. One end of the resistor R is connected to the EN pin of the step-down chip U1, and the other end of the resistor R is connected to the PGD pin of the control chip U2. One end of the capacitor C is connected to the EN pin of the step-down chip U1, and the other end of the capacitor C is grounded. The principle is that when the output of the current stage protection circuit 1 stabilizes and the PG signal transitions from low to high, the delay circuit begins charging. After a preset time constant, the delay circuit outputs a high level to the EN pin of the subsequent stage. This ensures that the subsequent power supply only starts after the previous stage is fully stable, achieving orderly power-on of multiple power supplies. This delay can be set according to RC parameters or comparator thresholds to adapt to different startup timing requirements. This prevents undervoltage, surges, or logic anomalies caused by chaotic startup timing in multi-stage power supply systems; it achieves automatic timing control of power supply cascading without the need for an external MCU or timing control chip.

[0038] Furthermore, it also includes a rate limiting module, such as... Figure 7 As shown, the current limiting module includes a Schottky diode D2, a resistor R12, a capacitor C18, and a capacitor C22. The cathode of the Schottky diode D2, the resistor R12, and the SEN pin of the control chip U2 are connected in sequence; the anode of the Schottky diode D2 is grounded; and the capacitors C18 and C22 are connected in parallel with the Schottky diode D2.

[0039] Specifically, in terms of component connections, the cathode of Schottky diode D2 is electrically connected to one end of sampling resistor R12, while the other end of sampling resistor R12 is directly connected to the SEN pin of control chip U2, forming a transmission path for the current detection signal. The anode of Schottky diode D2 is directly grounded, putting the diode in a reverse bias state, and it only conducts under specific operating conditions to achieve the protection function. At the same time, capacitors C18 and C22 are connected in parallel across Schottky diode D2, with one end of each capacitor connected to the cathode of Schottky diode D2 and the other end connected to the anode (ground terminal) of Schottky diode D2, forming a filtering network for the detection signal.

[0040] From a working principle perspective, the core logic of the current limiting module is based on a closed-loop mechanism of "current sampling - signal conversion - threshold comparison - protection triggering". When the MOSFET Q2 in the external power MOSFET module 2 is turned on, and the front-end bus supplies power to the subsequent step-down circuit, the current in the power supply circuit flows through the sampling resistor R12. According to Ohm's law, the current will generate a voltage drop (i.e., the sampling voltage signal) across the sampling resistor R12 that is proportional to the magnitude of the current. This sampling voltage signal is transmitted to the two ends of the Schottky diode D2 through the cathode. Since the Schottky diode D2 is in a reverse bias state at this time (anode grounded, cathode potential higher than anode), its forward conduction characteristic does not play a role, but only serves as part of the signal path to stably transmit the sampling voltage signal to the SEN pin of the control chip U2. The control chip U2 integrates a highly sensitive voltage comparator, which compares the sampled voltage signal received by the SEN pin with the chip's internally preset overcurrent protection threshold (this threshold can be configured by the chip or fine-tuned by external circuitry to adapt to different power supply requirements) in real time. When the subsequent buck circuit 3 is operating normally and the supply current is within the rated range, the voltage across the sampling resistor R12 drops below the overcurrent protection threshold. The control chip U2 determines that the current is not abnormal and maintains the drive signal output of the GATE pin, ensuring that the MOSFET Q2 remains stably turned on and guaranteeing a normal power supply path. However, when the subsequent buck circuit 3 experiences a short circuit, overload, or other faults, causing a sudden increase in supply current, the voltage drop across the sampling resistor R12 will rise synchronously. When this voltage drop exceeds the overcurrent protection threshold inside the control chip U2, the current will be released. The control chip U2 immediately determines that an overcurrent fault has occurred and quickly triggers the overcurrent protection logic. On the one hand, it rapidly discharges the charge on the gate of the MOSFET Q2 through the internal discharge circuit, causing the GATE pin drive voltage to drop sharply. The MOSFET Q2 is quickly turned off, cutting off the power supply path between the front-end bus and the rear-end buck circuit 3. This prevents excessive current from continuously flowing through the rear-end buck chip U1 (such as SCT2650) and the external power MOSFET module 2, preventing components from burning out due to overcurrent and overheating. On the other hand, the control chip U2 will synchronously pull down the output level of the PGD pin, feeding back the overcurrent fault status to the rear-end buck circuit 3. This causes the EN pin of the buck chip U1 to receive a low-level signal and then synchronously stop working, forming a dual protection of "abnormal current - front-end shutdown - rear-end linkage shutdown", further enhancing the timeliness and reliability of fault handling.

[0041] Furthermore, Schottky diode D2, with its low forward voltage drop and fast switching speed, not only serves as part of the sampling signal transmission path but also rapidly conducts forward when a reverse induced voltage is generated across sampling resistor R12 due to a sudden current change (such as a sudden current drop caused by the sudden turn-off of MOSFET Q2). This discharges the reverse induced voltage through the anode-to-ground loop, preventing a high reverse voltage from impacting the SEN pin of control chip U2, protecting the internal detection circuit of the chip from damage, and shortening the duration of the reverse voltage, thus reducing interference with the accuracy of the sampling signal detection. As a core component of the current-to-voltage conversion, the resistance value of sampling resistor R12 must be precisely selected based on the rated current of the preceding protection circuit 1 and the overcurrent threshold of control chip U2 to ensure that the sampling voltage generated under rated current is within the linear range of chip detection. To ensure both detection sensitivity and avoid power loss due to excessive voltage drop during normal operation, high-precision alloy resistors with low temperature coefficients are typically selected to reduce the impact of temperature changes on sampling accuracy and ensure the stability of the overcurrent protection threshold. Capacitors C18 and C22 form a two-stage filtering network. Capacitor C18 is usually a high-frequency ceramic capacitor (such as 100nF), mainly used to absorb high-frequency ripple in the sampling voltage signal (such as high-frequency noise generated by the switching action of MOSFET Q2). Capacitor C22 can be a slightly larger capacitor (such as 1μF) to filter out low-frequency interference signals. The two work together to make the sampling voltage signal transmitted to the SEN pin of the control chip U2 more stable, avoiding misjudgment of overcurrent faults by the control chip U2 due to signal fluctuations, and improving the accuracy and reliability of overcurrent protection.

[0042] Furthermore, it also includes a loop compensation module, which includes a resistor R24, a capacitor C2, and a capacitor C23 connected in sequence to form a loop. The end of the resistor R24 ​​away from the capacitor C2 is connected to the COMP pin of the step-down chip U1, and the end of the capacitor C2 away from the resistor R24 ​​is grounded.

[0043] Specifically, the subsequent buck circuit 3 forms a voltage feedback loop with the FB pin (feedback pin) of the buck chip U1 through the voltage divider module 31. This loop transmits the output voltage change signal to the error amplifier inside the buck chip U1. The error amplifier outputs the difference signal between the feedback voltage and the internal reference voltage to the COMP pin. The loop compensation module, through its connection with the COMP pin, performs phase compensation and amplitude adjustment on this error signal to solve the phase lag problem that may occur in the closed-loop control of the buck circuit. That is, because there are energy storage components such as inductors and capacitors in the subsequent buck circuit 3, these components will cause a phase difference between the voltage feedback signal and the output signal of the error amplifier. When the phase difference accumulates to a certain extent, it may cause closed-loop oscillation of the circuit, resulting in unstable output voltage. Resistor R24 ​​can provide phase lead compensation to offset part of the phase lag. Capacitors C2 and C23 absorb high-frequency components in the error signal and suppress high-frequency noise, further stabilizing the output signal of the error amplifier, ensuring that the error signal can accurately reflect the change in output voltage, so that the buck chip U1 can accurately adjust the switching action of the internal power transistor according to the signal and avoid circuit oscillation.

[0044] Furthermore, it also includes a capacitor C1 and an inductor L1 connected in series. The end of the capacitor C1 away from the inductor L1 is connected to the BOOT pin of the buck chip U1, the end of the capacitor C1 near the inductor L1 is connected to the SW pin of the buck chip U1, and the end of the inductor L1 away from the capacitor C1 is connected to the target voltage output terminal.

[0045] Specifically, capacitor C1 acts as the bootstrap capacitor for buck converter U1, providing sufficient drive voltage to the gate drive circuit of the high-side power transistor inside buck converter U1. Since buck converter U1 typically employs a synchronous or asynchronous buck topology, it contains two power transistors, one on the high-side and one on the low-side. When the high-side power transistor is turned on, the potential of the SW pin increases synchronously with the input voltage of the preceding stage. However, the BOOT pin needs to provide a higher voltage than the SW pin to ensure reliable conduction of the high-side power transistor. During the conduction of the low-side power transistor, capacitor C1 obtains charge from the power supply through the bootstrap diode inside buck converter U1 and completes its charging. When the high-side power transistor is about to turn on, capacitor C1 releases the stored charge, providing the required voltage to the gate drive circuit of the high-side power transistor. This prevents insufficient conduction of the high-side power transistor due to insufficient drive voltage, thereby reducing the conduction loss of the power transistor, ensuring the conversion efficiency of buck converter U1, and forming a crucial foundation for the subsequent buck circuit 3 to stably handle high-voltage input and achieve efficient voltage conversion. The inductor L1, connected in series with capacitor C1, is an energy storage and filtering element in the subsequent step-down circuit 3. It stores and releases energy through the principle of electromagnetic induction, thereby converting the pulse voltage output from the SW pin of the step-down chip U1 into a stable DC voltage. This effectively suppresses the fluctuation of the pulse voltage at the SW pin, making the voltage output to the target voltage output terminal more stable and preventing the pulse voltage from directly acting on the downstream load and causing abnormal load operation.

[0046] In this embodiment of the invention, an external power MOSFET module 2 receives drive signals from the front-end control chip and operates by forming a gate reverse protection path with a diode, which can discharge transient reverse potential and accelerate turn-off. A capacitor connected in parallel with the diode filters high-frequency ripple in the drive signal and replenishes gate charge at the moment of conduction. Furthermore, the front-end control chip enables soft start-up and controls the conduction slope. This protects the MOSFET gate from breakdown, stabilizes the drive signal to reduce switching losses, prevents power surges from impacting the subsequent stage, and quickly shuts off the power supply path and disconnects the front and subsequent stages in case of input abnormalities. Simultaneously, the PGD pin of the front-end control chip is directly connected to the EN pin of the subsequent buck chip. When the front-end MOSFET module is turned off, the power supply normal pin outputs a low level, causing the subsequent buck chip to turn off synchronously; when the MOSFET module is turned on and the input is normal, the power supply normal pin outputs a high level, starting the subsequent buck chip. This achieves rapid response through hardware, avoids abnormal voltage acting on the subsequent chip, prevents device damage, simplifies the control chain without software intervention, reduces the risk of software failure, and ensures coordinated operation between the front and rear stages, improving protection timeliness.

[0047] Example 2:

[0048] like Figure 9As shown in the figure, a heat dissipation housing proposed in this embodiment of the present invention includes: an upper housing 4, a lower housing 5, and a circuit board equipped with a power module having a front-to-back linkage protection circuit as in Embodiment 1; the upper housing 4 and the lower housing 5 are combined to form a cavity adapted to the shape of the circuit board, the circuit board is disposed in the cavity and contacts the upper housing 4 and the lower housing 5 respectively; multiple sets of heat dissipation fins 6 are provided on the outer walls of the upper housing 4 and the lower housing 5, any heat dissipation fin 6 is perpendicular to the circuit board, and there is a gap between adjacent heat dissipation fins 6.

[0049] The circuit board provides a stable mounting platform for the power module and also serves as an intermediate link in heat conduction, absorbing the heat generated during circuit operation. The upper housing 4 and lower housing 5 are made of a highly thermally conductive metal material (such as aluminum alloy). When combined, they form a cavity that conforms to the shape of the circuit board. This cavity's shape-fitting design prevents the circuit board from shifting within the housing due to vibration or installation misalignment, preventing damage from collisions between circuit components and the housing. Simultaneously, it ensures that the circuit board fits tightly against the inner walls of the upper and lower housings 4 and 5. This direct contact method creates an efficient heat conduction path, allowing the heat generated by the heat-generating components on the circuit board (such as the power MOSFETs in the front-end and the SCT2650 chip in the back-end) to be quickly transferred to the upper and lower housings 5, preventing heat accumulation on the circuit board and thus avoiding impacts on circuit performance. To further improve heat dissipation efficiency, multiple sets of heat sinks 6 are provided on the outer walls of both the upper housing 4 and the lower housing 5. These heat sinks 6 increase the contact area between the housing and the outside air, accelerating the dissipation of heat absorbed by the housing. Furthermore, each heat sink 6 is perpendicular to the circuit board. This vertical design conforms to the laws of natural convection—when the circuit board is installed horizontally, the vertical heat sinks 6 follow the upward flow of hot air, reducing airflow resistance and allowing hot air to smoothly escape from the heat sinks 6, preventing heat from accumulating between them. In addition, gaps are provided between adjacent heat sinks 6, providing necessary channels for airflow. This allows cool air to continuously enter between the heat sinks 6, exchange heat with the high-temperature heat sinks 6, and then carry away the heat, further ensuring effective heat dissipation.

[0050] Furthermore, several through holes 7 are evenly provided on the side walls of the upper housing 4 and the lower housing 5. These through holes 7 are used for air circulation and heat dissipation, and also serve as mounting and positioning holes.

[0051] The above are merely preferred embodiments of this utility model and are not intended to limit the scope of this utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A power supply module with a front-to-back stage linkage protection circuit, characterized in that, include: The pre-stage protection circuit includes an overvoltage divider sampling module, an undervoltage divider sampling module, and a control chip U2 for detecting the overvoltage and undervoltage states of the input voltage; the input terminals of the overvoltage divider sampling module and the undervoltage divider sampling module are connected to the power supply, and the output terminals of the overvoltage divider sampling module and the undervoltage divider sampling module are connected to the control chip U2. An external power MOSFET module is powered by a power supply and is connected to the control chip U2 via a signal. In response to the drive signal of the control chip U2, the external power MOSFET module performs turn-on or turn-off. The subsequent step-down circuit includes a step-down chip U1 and a voltage divider module. The EN pin of the step-down chip U1 is connected to the PGD pin of the control chip U2. When the external power MOSFET module is turned off, the step-down chip U1 is simultaneously turned off. When the external power MOSFET module is turned on, the PGD signal of the control chip U2 automatically rises and restarts the step-down circuit. The voltage divider module is connected to the FB pin of the step-down chip U1.

2. A power module with a front-to-back stage linkage protection circuit according to claim 1, characterized in that, The connection between the EN pin of the step-down chip U1 and the PGD pin of the control chip U2 can be achieved by one of the following methods: direct connection with a resistor, connection via optocoupler isolation, or connection through a logic circuit.

3. A power module with a front-to-back stage linkage protection circuit according to claim 1, characterized in that, It also includes a delay module, which includes a resistor R and a capacitor C. One end of the resistor R is connected to the EN pin of the step-down chip U1, and the other end of the resistor R is connected to the PGD pin of the control chip U2. One end of the capacitor C is connected to the EN pin of the step-down chip U1, and the other end of the capacitor C is grounded.

4. A power supply module with a front-to-back stage linkage protection circuit according to any one of claims 1 to 3, characterized in that, The external power MOSFET module includes a diode D4, a capacitor C24, and a MOSFET Q2. The cathode of the diode D4 is connected to the gate of the MOSFET Q2 and the GATE pin of the control chip U2, respectively. The anode of the diode D4 is connected to the drain of the MOSFET Q2, and the source of the MOSFET Q2 is connected to the OUT pin of the control chip U2 and the VIN pin of the buck chip U1, respectively. The capacitor C24 is connected in parallel with the diode D4.

5. A power module with a front-to-back stage linkage protection circuit according to claim 4, characterized in that, The voltage divider module includes multiple voltage divider units and resistor R32. Each voltage divider unit includes a voltage divider resistor connected in series and a switch. Multiple voltage divider units are arranged in parallel. In any voltage divider unit, the end of the voltage divider resistor away from the switch is connected to the FB pin of the buck chip U1. The FB pin of the buck chip U1 is connected to the target voltage output terminal through the resistor R32.

6. A power module with a front-to-back stage linkage protection circuit according to claim 5, characterized in that, It also includes a current limiting module, which includes a Schottky diode D2, a resistor R12, a capacitor C18, and a capacitor C22. The cathode of the Schottky diode D2, the resistor R12, and the SEN pin of the control chip U2 are connected in sequence. The anode of the Schottky diode D2 is grounded. The capacitors C18 and C22 are connected in parallel with the Schottky diode D2.

7. A power module with a front-to-back stage linkage protection circuit according to claim 5, characterized in that, It also includes a loop compensation module, which includes a resistor R24, a capacitor C2 and a capacitor C23 connected in sequence to form a loop. The end of the resistor R24 ​​away from the capacitor C2 is connected to the COMP pin of the step-down chip U1, and the end of the capacitor C2 away from the resistor R24 ​​is grounded.

8. A power module with a front-to-back stage linkage protection circuit according to claim 5, characterized in that, It also includes a capacitor C1 and an inductor L1 connected in series. The end of the capacitor C1 away from the inductor L1 is connected to the BOOT pin of the step-down chip U1, the end of the capacitor C1 close to the inductor L1 is connected to the SW pin of the step-down chip U1, and the end of the inductor L1 away from the capacitor C1 is connected to the target voltage output terminal.

9. A heat dissipation housing, characterized in that, include: The upper housing, the lower housing, and the circuit board equipped with a power module having a front-to-back linkage protection circuit as described in any one of claims 1 to 8; The upper housing and the lower housing together form a cavity adapted to the shape of the circuit board. The circuit board is disposed in the cavity and contacts the upper housing and the lower housing respectively. Multiple sets of heat sinks are provided on the outer walls of the upper housing and the lower housing. Each heat sink is perpendicular to the circuit board, and there is a gap between adjacent heat sinks.

10. A heat dissipation housing according to claim 9, characterized in that, The upper housing and the lower housing have several through holes evenly distributed on their side walls. These through holes serve both as airflow and heat dissipation holes and as mounting and positioning holes.

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