Semiconductor package device

Abstract

The application provides a semiconductor packaging device, comprising: a first electronic element and a second electronic element arranged side by side; a lower redistribution layer arranged below the first electronic element and the second electronic element, comprising a lower bridge circuit for electrically connecting the first electronic element and the second electronic element, and further comprising a functional circuit; and an upper redistribution layer arranged above the first electronic element and the second electronic element, comprising an upper bridge circuit for electrically connecting the first electronic element and the second electronic element, and further comprising a dummy circuit symmetrically arranged with the functional circuit. The application increases the wiring area of the bridge circuit, can realize higher density and more stable interconnection, and does not have to further reduce the line width / line spacing of the bridge circuit, thereby being beneficial to improving signal integrity, improving heat dissipation and reliability, reducing manufacturing cost, and improving manufacturing yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more specifically to a semiconductor packaging device. Background Technology

[0002] With the rapid development of artificial intelligence (AI) and high-performance computing (HPC) technologies, the demand for data transmission between application-specific integrated circuits (ASICs) and high-bandwidth memory (HBM) is constantly increasing. To meet this demand for high-speed, high-density data exchange, packaging technology must provide higher interconnect density.

[0003] However, in traditional packaging technologies, such as fan-out board-on-chip (FOCoS), the interconnect between the ASIC and HBM is mainly achieved through a redistribution layer (RDL) on the package substrate. But as the demand for interconnect density increases, the line width / spacing of the RDL needs to be continuously reduced. When the line width / spacing is reduced to below 2 / 2 μm, problems such as decreased signal integrity, reduced heat dissipation and reliability, and increased manufacturing difficulty are encountered, which are explained in detail below.

[0004] (1) Decreased signal integrity: To increase interconnect density, if the line spacing is reduced from 5 / 5μm to 2 / 2μm, crosstalk between adjacent lines will increase by 20-30%, resistance will increase by about 2.5 times, and capacitance effect will be aggravated. For high-speed data transmission, this will cause a decrease in signal integrity, which in turn will affect the signal transmission speed and increase power consumption.

[0005] (2) Decreased heat dissipation and reliability: High-density interconnects generate more heat, and inadequate heat dissipation design can affect component lifespan and long-term reliability. These issues are particularly critical in AI and high-performance computing applications, where data transmission speed and stability requirements are extremely high. High-density interconnects increase local heat density, potentially raising temperatures by 5-10°C. Poor thermal management will significantly impact component lifespan and reliability.

[0006] (3) Increased Manufacturing Difficulty: Under existing etching processes, reducing the linewidth / spacing to 2 / 2 μm requires higher precision equipment and stricter process control, significantly increasing manufacturing costs and limiting mass production possibilities due to decreased yield. Furthermore, to address signal integrity issues, designers need to introduce more complex routing strategies and verification processes, which increases development time and overall costs. If further reduced to 1 / 1 μm, the yield may fall below 70%. Utility Model Content

[0007] This application provides a semiconductor packaging device, which aims to overcome the bottlenecks of traditional technologies and achieve higher density and more stable interconnection.

[0008] This application discloses a semiconductor packaging device, comprising: a first electronic component and a second electronic component, arranged side by side; a lower redistribution layer disposed below the first electronic component and the second electronic component, including a lower bridging line for electrically connecting the first electronic component and the second electronic component, and further including functional lines; and an upper redistribution layer disposed above the first electronic component and the second electronic component, including an upper bridging line for electrically connecting the first electronic component and the second electronic component, and further including dummy lines symmetrically arranged with respect to the functional lines.

[0009] In some alternative embodiments, it further includes: a molding layer covering the first electronic component and the second electronic component; wherein the upper redistribution layer extends above the molding layer.

[0010] In some alternative implementations, the sides of the upper redistribution layer, the lower redistribution layer, and the molding layer are substantially flush.

[0011] In some alternative embodiments, the upper surface of the molding layer is substantially flush with the upper surfaces of the first electronic component and the second electronic component, and the lower surface of the molding layer is substantially flush with the lower surfaces of the first electronic component and the second electronic component.

[0012] In some alternative embodiments, the molding layer fills the gap between the first electronic component and the second electronic component.

[0013] In some alternative implementations, the vertical projection of the upper redistribution layer covers both the first and second electronic components.

[0014] In some alternative implementations, the dummy line is exposed on the upper surface of the upper redistribution layer.

[0015] In some alternative implementations, it further includes a heat sink disposed above the upper redistribution layer and in contact with the dummy line.

[0016] In some alternative embodiments, in a top view, at least one of the first electronic components and at least one of the second electronic components are arranged side-by-side, forming a square overall.

[0017] In some alternative implementations, it further includes: a dummy element disposed between at least two of the second electronic elements.

[0018] In order to address the numerous problems arising from the increasing interconnect density requirements of interconnection circuit structures between chips such as ASICs and HBMs, this application proposes a semiconductor packaging device. By providing a lower redistribution layer including lower bridging lines below the two electronic components and an upper redistribution layer including upper bridging lines above the two electronic components, the wiring area of ​​the bridging lines is increased, enabling higher density and more stable interconnections without further reducing the linewidth / spacing of the bridging lines. This is beneficial for improving signal integrity, heat dissipation and reliability, reducing manufacturing costs, and increasing manufacturing yield. Attached Figure Description

[0019] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0020] Figure 1 This is a longitudinal cross-sectional structural schematic diagram of a semiconductor packaging device 1a according to an embodiment of this application;

[0021] Figure 2 This is a top view of a semiconductor packaging device 1a according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging device 3a according to an embodiment of this application;

[0023] Figure 4 This is a longitudinal cross-sectional structural schematic diagram of a semiconductor packaging device 4a according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging device 5a according to an embodiment of this application;

[0025] Figure 6 This is a top view of a semiconductor packaging device 5a according to another embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging device 7a according to an embodiment of this application;

[0027] Figure 8 This is a top view of a semiconductor packaging apparatus according to an embodiment of this application;

[0028] Figure 9 These are schematic diagrams illustrating the manufacturing steps of a semiconductor packaging apparatus according to an embodiment of this application;

[0029] Figures 10 to 11 This is a schematic diagram of the manufacturing steps of a semiconductor packaging apparatus according to another embodiment of this application.

[0030] Explanation of reference numerals / symbols in the attached diagram:

[0031] 11: First electronic component; 111: Metal pillar; 112: Solder pad; 113: Metal block; 12: Second electronic component; 13: Lower redistribution layer; 131: Lower bridging line; 132: Lower functional line; 14: Upper redistribution layer; 141: Upper bridging line; 142: Dummy line; 143: Upper functional line; 15: Mold layer; 16: Heat sink; 17: Dummy component; 18: Bridge chip; 181: Bridge line; 182: Through-Silicon Via (TSV). Detailed Implementation

[0032] The specific embodiments of this application will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this application and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0033] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0034] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0035] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0036] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0037] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0038] It should also be noted that the longitudinal section corresponding to the embodiment of this application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0039] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] refer to Figure 1 and Figure 2 , Figure 1 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 1a according to an embodiment of this application. Figure 2 This is a top view schematic diagram of a semiconductor packaging device 1a according to an embodiment of this application. Figure 1 and Figure 2 As shown, the semiconductor packaging device 1a of this application includes:

[0041] The first electronic component 11 and the second electronic component 12 are arranged side by side;

[0042] The lower redundancy layer 13 is disposed below the first electronic component 11 and the second electronic component 12. It includes a lower bridging line 131 for electrically connecting the first electronic component 11 and the second electronic component 12, and also includes a lower functional line 132.

[0043] The upper redundancy layer 14 is disposed above the first electronic component 11 and the second electronic component 12. It includes an upper bridging line 141 for electrically connecting the first electronic component 11 and the second electronic component 12, and also includes a dummy line 142 symmetrically arranged with the lower functional line 132.

[0044] Here, the first electronic component 11 and the second electronic component 12 can be various chips, such as logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, micro-electro-mechanical system (MEMS) chips, radio frequency chips, die or chip-scale packages, interposers, or combinations thereof. For example, the first electronic component 11 can be an application-specific integrated circuit (ASIC), and the second electronic component 12 can be a high-bandwidth memory (HBM).

[0045] Here, the lower redistribution layer 13 and the upper redistribution layer 14 can be composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies; this application does not specifically limit this. For example, redistribution layers can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0046] Here, the lower functional line 132 can be a line used to implement electrical functions, such as a line used to transmit signals or power. Here, the dummy line 142 is a fake line that does not implement electrical functions.

[0047] This application increases the wiring area of ​​the bridging lines by providing a lower redistribution layer 13 including a lower bridging line 131 below the two electronic components and an upper redistribution layer 14 including an upper bridging line 141 above the two electronic components, thereby achieving higher density and more stable interconnection.

[0048] This application improves the overall symmetry of the device by further setting up a dummy line 142 in the upper redistribution layer 14 and symmetrically arranging it with the lower functional line 132, which helps to suppress warping.

[0049] In some alternative implementations, the upper redistribution layer 14 may also include upper functional lines 143 for implementing electrical functions.

[0050] In some optional embodiments, the semiconductor packaging device 1a of this application further includes: a molding layer 15 covering the first electronic component 11 and the second electronic component 12. Here, the molding layer 15 can be formed of various molding compounds. Exemplarily, molding materials may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. Exemplarily, the molding layer 15 can be an epoxy molding compound (EMC epoxy molding compound).

[0051] In some alternative implementations, the lower redistribution layer 13 extends below the molding layer 15 to carry the first electronic component 11, the second electronic component 12, and the molding layer 15.

[0052] In some alternative implementations, the upper redistribution layer 14 extends above the molding layer 15. In other words, the upper redistribution layer 14 covers the entire layer and is symmetrically arranged with the lower redistribution layer 13 below, thereby further improving the symmetry of the device and thus further suppressing warping.

[0053] In some alternative implementations, the sides of the upper redistribution layer 14, the lower redistribution layer 13, and the molding layer 15 are substantially flush.

[0054] In some alternative embodiments, the upper surface of the molding layer 15 is substantially flush with the upper surfaces of the first electronic component 11 and the second electronic component 12, and the lower surface of the molding layer 15 is substantially flush with the lower surfaces of the first electronic component 11 and the second electronic component 12.

[0055] In some alternative embodiments, the molding layer 15 fills the gap between the first electronic component 11 and the second electronic component 12. This ensures that the molding layer 15 covers and protects the electronic components.

[0056] In some alternative implementations, the vertical projection of the upper redistribution layer 14 may cover the first electronic component 11 and the second electronic component 12. This ensures that the upper redistribution layer 14 covers a larger area, improving its ability to suppress warping.

[0057] In some alternative implementations, the vertical projection of the upper redundancy layer 14 substantially overlaps with that of the lower redundancy layer 13. This ensures structural symmetry between the upper redundancy layer 14 and the lower redundancy layer 13, improving the ability to suppress warping.

[0058] In some alternative implementations, the thickness of the upper redistribution layer 14 and the lower redistribution layer 13 are substantially the same. This ensures structural symmetry between the upper redistribution layer 14 and the lower redistribution layer 13, improving the ability to suppress warping.

[0059] In some alternative implementations, the linewidth of the upper bridging line 141 and the lower bridging line 131 is greater than 2 micrometers, and the line spacing is greater than 2 micrometers. Alternatively, the linewidth and line spacing of the upper bridging line 141 and the lower bridging line 131 can both be greater than 3 micrometers, 4 micrometers, or 5 micrometers. Here, since the linewidth and line spacing do not need to be excessively reduced, the manufacturing difficulty can be reduced and the process yield can be improved.

[0060] In some alternative embodiments, in a top view, at least one first electronic component 11 and at least one second electronic component 12 are arranged side-by-side, forming a square overall. This results in a more compact structure and a smaller package area.

[0061] In some optional embodiments, the semiconductor packaging apparatus 1a of this application further includes a dummy element 17 disposed between at least two second electronic components 12. The dummy element 17 is a component without electrical function, and its material can be the same as or similar to that of electronic components such as chips, for example, silicon. Here, by providing the dummy element 17, the structural strength can be enhanced, and package warping can be suppressed.

[0062] The semiconductor packaging apparatus 1a of this application has been described above. This application increases the wiring area of ​​the bridging lines without further reducing the line width / spacing of the bridging lines, enabling higher density and more stable interconnections. This is beneficial for improving signal integrity, heat dissipation and reliability, reducing manufacturing costs, and increasing manufacturing yield.

[0063] The upper redistribution layer 14 can cover a large area, thus being symmetrically arranged with the lower redistribution layer 13, which can improve symmetry. Furthermore, dummy lines 142 can be made on the upper redistribution layer 14, which are symmetrically arranged with the lower functional lines 132 in the lower redistribution layer 13, further improving symmetry. This helps to balance the possible warping of the first electronic component 11, the second electronic component 12, and the lower redistribution layer 13, and has the effect of suppressing warping.

[0064] Compared to traditional technologies that only utilize the lower redundancy layer 13, the upper redundancy layer 14 in this application provides additional wiring area, doubling the available wiring area for connections. Therefore, the RDL lines of the bridging circuits do not need excessively reduced line width and spacing; instead, both line width and spacing can be maintained at approximately 5 micrometers or more. Furthermore, more mature process technologies can be used, reducing reliance on high-precision equipment and avoiding manufacturing difficulties and yield issues. This allows for customized designs based on different application requirements, providing greater scalability and adaptability. Further, vertical vias can be designed in the upper redundancy layer 14 to connect the first electronic component 11 and the second electronic component 12. Vertical connections shorten the signal transmission path, reducing crosstalk and delay, and improving signal integrity for high-speed data transmission. In summary, this application utilizes space expansion and vertical connections to achieve higher interconnect density and excellent signal integrity, making it particularly suitable for AI and high-performance computing applications. Moreover, this application has a significant cost advantage compared to other solutions such as CoWoS (Chip on Wafer on Substrate).

[0065] refer to Figure 3 , Figure 3 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 3a according to an embodiment of this application. Figure 3 The semiconductor packaging device 3a shown is similar to Figure 1 The semiconductor packaging device 1a shown differs in that:

[0066] In the semiconductor packaging device 3a, the dummy line 142 is exposed on the upper surface of the upper redistribution layer 14.

[0067] In some alternative embodiments, the semiconductor packaging device 3a of this application further includes: a heat sink 16 disposed above the upper redistribution layer 14 and in contact with the dummy line 142.

[0068] Here, by exposing the dummy line 142 to the upper redundancy layer 14, the heat dissipation performance of the device can be improved. By further removing the heat sink 16 from the dummy line 142, the heat dissipation performance of the device can be further improved.

[0069] Here, there is no limitation on the type of heat sink 16; for example, it can be an air-cooled heat sink that includes heat dissipation fins.

[0070] refer to Figure 4 , Figure 4 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 4a according to an embodiment of this application. Figure 4 The semiconductor packaging device 4a shown is similar to Figure 1 The semiconductor packaging device 1a shown differs in that:

[0071] In the semiconductor packaging device 4a, no dummy lines 142 are provided in the upper redistribution layer 14. This simplifies the manufacturing process and reduces costs.

[0072] refer to Figure 5 and Figure 6 , Figure 5 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 5a according to an embodiment of this application. Figure 6 This is a top view of a semiconductor packaging device 5a according to an embodiment of this application. Figure 5 and Figure 6 The semiconductor packaging device 5a shown is similar to Figure 1 and Figure 2 The semiconductor packaging device 1a shown differs in that:

[0073] In the semiconductor packaging device 5a, the upper redistribution layer 14 does not cover the entire layer. Its vertical projection only covers the area where the first electronic component 11 and the second electronic component 12 need to be interconnected, and does not completely cover the first electronic component 11 and the second electronic component 12.

[0074] This reduces the area required for the upper wiring layer 14, thus lowering costs.

[0075] refer to Figure 7 and Figure 8 , Figure 7 This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device 7a according to an embodiment of this application. Figure 8 This is a top view of a semiconductor packaging device 7a according to an embodiment of this application. Figure 7 and Figure 8 The semiconductor packaging device 5a shown is similar to Figure 5 and Figure 6 The semiconductor packaging device 5a shown differs in that:

[0076] In the semiconductor packaging device 7a, a skybridge die 18 is included, which is disposed above the first electronic component 11 and the second electronic component 12. The skybridge die 18 contains a skybridge line 181 and through-silicon vias (TSVs) 182. The skybridge die 18 can be vertically connected to the first electronic component 11 and the second electronic component 12 via different TSVs 182, and horizontally connected via the skybridge line 181, thereby achieving electrical connection between the first electronic component 11 and the second electronic component 12.

[0077] Here, a bridge chip 18 is used to replace the upper redistribution layer 14 to achieve the same electrical function. The vertical connection of the through-silicon via 182 shortens the signal transmission path, reduces crosstalk and delay, and can improve the signal integrity of high-speed information transmission.

[0078] Here, bridge chip 18 is a bridge chip used to implement bridging function. It is called bridge chip 18 because it is placed above two electronic components.

[0079] refer to Figure 9 , Figure 9 These are schematic diagrams illustrating the manufacturing steps of a semiconductor packaging apparatus according to an embodiment of this application. Figure 9 As shown, the manufacturing process of the semiconductor packaging apparatus in this application includes the following steps:

[0080] Steps A1 to A3: Provide a first electronic component 11 and a second electronic component 12. The first electronic component 11 may include metal pillars 111. The first electronic component 11 can be thinned through a grinding step, exposing the metal pillars 111 on its upper surface. Then, solder pads 112 can be fabricated at the exposed location of the metal pillars 111 (e.g., method 1-1 in step A3), or the metal pillars 111 can be heightened by fabricating metal blocks 113 (e.g., method 1-2 in step A), thereby enabling the upper surface of the first electronic component 11 to be used for external electrical connection. Similarly, the second electronic component 12 can be treated in the same way to enable its upper surface to be used for external electrical connection.

[0081] Step A4: Provide a lower redistribution layer 13 with a lower bridging line 131, bond the first electronic component 11 and the second electronic component 12 to the lower redistribution layer 13, and electrically connect the first electronic component 11 and the second electronic component 12 through the lower bridging line 131.

[0082] Step A5: Perform molding to form a molding layer 15 covering the first electronic component 11 and the second electronic component 12.

[0083] Step A6: Perform grinding to thin the molding layer 15 so that the upper surfaces of the first electronic component 11 and the second electronic component 12 are exposed in the molding layer 15.

[0084] Step A7: An upper redistribution layer 14 including an upper bridging line 141 is formed above the first electronic component 11 and the second electronic component 12, so that the first electronic component 11 and the second electronic component 12 are electrically connected through the upper bridging line 141.

[0085] At this point, it is possible to produce something like... Figure 1 The semiconductor packaging device 1a shown.

[0086] refer to Figures 10 to 11, Figures 10 to 11 This is a schematic diagram illustrating the manufacturing steps of a semiconductor packaging apparatus according to another embodiment of this application. Figures 10 to 11 As shown, the manufacturing process of the semiconductor packaging device in this application embodiment may include the following steps:

[0087] Steps B1 to B6: Refer to steps A1 to A6 described above; they will not be repeated here.

[0088] Step B7: Bond the bridge chip 18 above the first electronic component 11 and the second electronic component 12, so that the first electronic component 11 and the second electronic component 12 can be electrically connected through the bridge circuit 181 inside the bridge chip 18.

[0089] Step B8: Perform a second molding process to thicken the molding layer 15 to cover the bridge chip 18.

[0090] Step B9: Perform grinding to thin the mold sealing layer 15 and expose the bridge chip 18.

[0091] At this point, it is possible to produce something like... Figure 7 The semiconductor packaging device 7a shown.

[0092] Although this application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this application and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this application. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this application.

Claims

1. A semiconductor packaging device, characterized in that, include: The first electronic component and the second electronic component are arranged side by side; The lower redistribution layer is disposed below the first electronic component and the second electronic component, and includes a lower bridging line for electrically connecting the first electronic component and the second electronic component, as well as functional lines; The upper redistribution layer is disposed above the first electronic component and the second electronic component, and includes an upper bridging line for electrically connecting the first electronic component and the second electronic component, and also includes a dummy line symmetrically arranged with the functional line, the dummy line being exposed on the upper surface of the upper redistribution layer.

2. The semiconductor packaging apparatus according to claim 1, characterized in that, Further includes: A molding layer covers the first electronic component and the second electronic component; The upper redistribution layer extends above the molding layer.

3. The semiconductor packaging apparatus according to claim 2, characterized in that, The sides of the upper redistribution layer, the lower redistribution layer, and the molding layer are substantially flush.

4. The semiconductor packaging apparatus according to claim 2, characterized in that, The upper surface of the molding layer is substantially flush with the upper surfaces of the first electronic component and the second electronic component, and the lower surface of the molding layer is substantially flush with the lower surfaces of the first electronic component and the second electronic component.

5. The semiconductor packaging apparatus according to claim 2, characterized in that, The molding layer fills the gap between the first electronic component and the second electronic component.

6. The semiconductor packaging apparatus according to claim 1, characterized in that, The vertical projection of the upper redistribution layer covers the first electronic component and the second electronic component.

7. The semiconductor packaging apparatus according to claim 1, characterized in that, Further includes: The heat sink is disposed above the upper redundancy layer and contacts the dummy circuit.

8. The semiconductor packaging apparatus according to claim 1, characterized in that, Viewed from above, at least one of the first electronic components and at least one of the second electronic components are arranged side-by-side, forming a square overall.

9. The semiconductor packaging apparatus according to claim 1, characterized in that, Further includes: A dummy element is disposed between at least two of the second electronic elements.

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