Abnormality detection device for vehicle microcomputer

Abstract

An abnormality detection device for a vehicle microcomputer, which monitors a function of a microcomputer (1) controlling an on-board device and has a plurality of abnormality detection circuits (4a, 4b) that output an abnormality detection signal to an external part when a pattern of test data input from the microcomputer (1) does not correspond to a predetermined pattern, comprising: a self-diagnosis circuit (17) that monitors the function of the plurality of abnormality detection circuits (4a, 4b) and outputs self-diagnosis data having a pattern identical to the test data to each of the abnormality detection circuits (4a, 4b); a plurality of data selection circuits (9a, 9b) that select either the test data or the self-diagnosis data and output the selected data to each of the abnormality detection circuits (4a, 4b); a data or signal selection circuit (10),which selects the abnormality detection signal output from a second abnormality detection circuit (4b) or the self-diagnosis data, and outputs either the selected abnormality detection signal output from a second abnormality detection circuit (4b) or the selected self-diagnosis data to a first abnormality detection circuit (4a), wherein the plurality of abnormality detection circuits (4a, 4b) comprises at least the first abnormality detection circuit (4a) and the second abnormality detection circuit (4b); anda plurality of comparison circuits (8a, 8b) which compare a value expected to be output from each of the abnormality detection circuits (4a, 4b) with data actually output from each of the abnormality detection circuits (4a, 4b) when the self-diagnosis circuit (17) connects the data selection circuits (9a,9b) and controls the data or signal selection circuit (10) to output the self-diagnosis data to the plurality of abnormality detection circuits (4a, 4b), wherein a first comparison circuit (8a) of the comparison circuits (8a, 8b) is associated with the first abnormality detection circuit (4a), a second comparison circuit (8b) of the comparison circuits (8a, 8b) is associated with the second abnormality detection circuit (4b), and the second comparison circuit (8b) receives either the selected abnormality detection signal output by the second abnormality detection circuit (4b) or the selected self-diagnosis data through the data or signal selection circuit (10).

Description

[0001] The present invention relates to an abnormality detection device which monitors the function of a microcomputer controlling an on-board device.

[0002] For example, with respect to a microcomputer having a control function for controlling an on-board actuator and a monitoring function for monitoring whether the microcomputer is functioning properly, JP 2007-002760 A discloses that a monitoring module monitors whether the monitoring function of the microcomputer is functioning properly. According to JP 2007-002760 A, the microcomputer has a module monitoring section to improve reliability, and the module monitoring section of the microcomputer monitors whether the monitoring module is functioning properly.

[0003] JP 2001-304025 A discloses performing a run-on test to verify a self-diagnosis function. JP 2011-126327 A discloses an in-vehicle control device that reduces the arithmetic processing load associated with vehicle control and ensures safety. JP 2011-012594 A discloses an economical running control device and a control method thereof, wherein execution of economical running control using a failed starter drive means is prevented even at the time of a voltage drop. JP H09-280101 A discloses a drive control of an engine, the execution of which is prevented in the presence of abnormalities at the time of restart. JP 2010-179712 A discloses fault diagnosis of a sensor or device installed in the exhaust system of an internal combustion engine.

[0004] The function of the monitoring module of JP 2007-002760 A can be configured differently according to the system specification. Accordingly, the configuration for monitoring the monitoring module can be varied in various ways. For example, if the monitoring module has multiple abnormality detection circuits and a detection result from one of the multiple abnormality detection circuits is input to another abnormality detection circuit, an input part of an abnormality detection circuit may require a selection circuit (equivalent to a multiplexer) for switching a signal. In this case, it may be necessary to confirm whether the selection circuit switches the signal normally. Therefore, the configuration and method for confirming each function can be very complicated.

[0005] An object of the present invention is to provide an abnormality detection device for a vehicle microcomputer which effectively and efficiently performs each function confirmation even when a plurality of abnormality detection circuits are provided.

[0006] The abnormality detection device for a vehicle microcomputer according to the present invention has a plurality of abnormality detection circuits. Each of the plurality of abnormality detection circuits outputs an abnormality detection signal to an external part when a pattern of test data input from the microcomputer does not match a predetermined pattern. A self-diagnosis circuit outputs self-diagnosis data having the identical pattern to the test data to each of the abnormality detection circuits and monitors the operation of the abnormality detection circuits. Switching between the test data and the self-diagnosis data input to each of the abnormality detection circuits is performed by a data selection circuit associated with each of the abnormality detection circuits.

[0007] A first abnormality detection circuit performs abnormality detection by considering the state of an abnormality detection signal output from a second abnormality detection circuit when the first abnormality detection circuit receives the test data from the microcomputer. The first abnormality detection circuit receives the abnormality detection signal output from the second abnormality detection circuit through a data or signal selection circuit.

[0008] The first abnormality detection circuit is associated with an object of a first BIST, and the second abnormality detection circuit is associated with an object of a second BIST.

[0009] The self-diagnosis circuit controls each selection circuit and outputs the self-diagnosis data to the multiple abnormality detection circuits. In this case, a comparison circuit compares an expected value of the data that each of the abnormality detection circuits should output with the data that each of the abnormality detection circuits actually outputs. The comparison circuit associated with the second abnormality detection circuit receives the data output by the data or signal selection circuit.

[0010] According to this configuration, when the self-diagnosis circuit outputs the self-diagnosis data to the second abnormality detection circuit, the abnormality detection signal output from the second abnormality detection circuit is input to the corresponding comparison circuit through the data or signal selection circuit. Therefore, when a comparison result is relayed by the comparison circuit, it is possible to confirm whether the second abnormality detection circuit is functioning normally and to confirm whether the data or signal selection circuit is functioning normally. It is possible to simplify the configuration of the abnormality detection device and to complete self-diagnosis in a shorter time.

[0011] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings: Is Fig. 1 is a block diagram showing a configuration of a monitoring module in a prior art reference example; Is Fig. 2 is a drawing showing a method of BIST operation in the reference example; Is Fig. 3 is a drawing showing a first processing method in a microcomputer in the reference example; Is Fig. 4 is a drawing showing a second processing method in the microcomputer; Is Fig. 5 is a drawing showing a third processing method in the microcomputer; Is Fig. 6 is a drawing showing a fourth processing method in the microcomputer; Is Fig. 7 is a drawing showing a fifth processing method in the microcomputer; Is Fig. 8 is a drawing showing a sixth processing method in the microcomputer; Is Fig. 9 is a flowchart showing a procedure of a BIST operation; Is Fig. 10 is a flowchart showing a process in the microcomputer; Is Fig. 11 is a block diagram showing a configuration of a monitoring module in a first embodiment; Is Fig. 12 is a flowchart showing a procedure of a BIST operation in the first embodiment; Is Fig. 13 is a flowchart showing a process in the microcomputer in the first embodiment; Is Fig. 14 is a drawing showing an operation timing table; Is Fig. 15 is a drawing showing an operation timing table in a second embodiment; Is Fig. 16 is a flowchart showing a procedure of a BIST operation; Is Fig. 17 is a drawing showing an operation timing table in a third embodiment; and Is Fig. 18 is a flowchart showing a procedure of BIST operation. Reference example

[0012] A reference example is explained below. In this reference example, it is assumed that an abnormality detection signal from one abnormality detection circuit is input to another abnormality detection circuit, and the other abnormality detection circuit incorporates the abnormality detection signal as an abnormality detection factor. A microcomputer 1 performs drive control of an onboard actuator such as a motor or the like through a drive circuit such as an inverter circuit or the like.

[0013] A monitoring module 2 (also referred to as a monitoring IC) performs serial communication through the microcomputer 1 and a communication section 3. The monitoring module 2 includes a first abnormality detection circuit 4a and a second abnormality detection circuit 4b. The first abnormality detection circuit 4a and the second abnormality detection circuit 4b are collectively referred to as an abnormality detection circuit 4. The abnormality detection circuit 4 receives test data from the microcomputer 1 through the communication section 3. The abnormality detection circuit 4 outputs an abnormality detection signal (Error_Out 1, 2) to an external part when the pattern of the input test data does not conform to a predetermined pattern. The abnormality detection signal indicates an abnormality in the function of the microcomputer 1.

[0014] The predetermined pattern may be stored, for example, in the abnormality detection circuit 4.

[0015] A power supply controller 5 receives a power supply of approximately 14 volts from a vehicle battery. The power supply of approximately 14 volts is reduced to 5 volts by the power supply controller 5. The power supply controller 5 generates an operating power supply for the monitoring module 2. The power supply controller 5 outputs a power-on-reset (POR) signal to the microcomputer 1 when battery power is supplied by an ignition switch (not shown here).

[0016] A BIST is a built-in self-test (BIST). A BIST controller 6 controls each section and detects whether the abnormality detection circuit 4 inside the monitoring module 2 is functioning normally. A first BIST section 7a, a result comparator 8a (corresponding to a first comparison circuit), and a first selector 9A are associated with the first abnormality detection circuit 4a.

[0017] A second BIST section 7b, a second result comparator 8b corresponding to a second comparison circuit, and a second selector 9b are associated with the second abnormality detection circuit 4b. The first result comparator 8a and the second result comparator 8b are collectively referred to as a result comparator 8.

[0018] Information regarding the power supply is transmitted from the power supply controller 5 to the BIST controller 6.

[0019] The first abnormality detection circuit 4a and the second abnormality detection circuit 4b are collectively referred to as the abnormality detection circuit 4. Similarly, the first BIST section 7a and the second BIST section 7b are collectively referred to as the BIST section 7. The first result comparator 8a and the second result comparator 8b are collectively referred to as a result comparator 8. The first selector 9a and the second selector 9b are collectively referred to as selector 9.

[0020] One of the input terminals of each of the selectors 9 is connected to an input / output terminal of the communication section 3, and a signal (ON / OFF SIGNAL 1, 2) is exchanged. This one of the input terminals of the selector 9 receives the test data output from the microcomputer 1.

[0021] The other input terminal of each of the selectors 9 is connected to an output terminal of each of the BIST sections 7. The BIST sections 7 perform selection and switching from an input of the selectors 9 by a signal (SEL_IN 1, 2). An output terminal of the selector 9 is connected to an input / output terminal of the associated abnormality detection circuit 4.

[0022] The first BIST section 7a outputs self-diagnosis data (TEST_IN 1a) to the first abnormality detection circuit 4a through the first selector 9a. The second BIST section 7b outputs self-diagnosis data (TEST_IN 2) to the second abnormality detection circuit 4b through the second selector 9b. The first BIST section 7a outputs self-diagnosis data (TEST_IN 1b) to the first abnormality detection circuit 4a through the selector 10. That is, one of the input terminals of the selector 10 is connected to the first BIST section 7a. The self-diagnosis data is identical to the test data output by the microcomputer.

[0023] The abnormality detection circuit 4 communicates with the microcomputer 1 through the communication section 3 with a signal (ON / OFF SIGNAL 1, 2), and the function of the microcomputer is checked when the monitoring module 2 is operating normally. The other of the input terminals of the selector 10 is connected to an output terminal of the second abnormality detection circuit 4b. The first abnormality detection circuit 4a performs abnormality detection by incorporating an abnormality detection result of the second abnormality detection circuit 4b.

[0024] An output terminal of the abnormality detection circuit 4 is connected to an external part through the first selector 11a or the second selector 11b. The first selector 11a and the second selector 11b are collectively referred to as selector 11. In addition, the output terminal of the first abnormality detection circuit 4a and the second abnormality detection circuit 4b are connected to the first result comparator 8a and the second result comparator 8b, respectively. Therefore, a signal ERROR_OUT 1 is output from the output terminal of the first abnormality detection circuit 4a to the external part and is input to the first result comparator 8a as a signal BIST_OUT 1. A signal ERROR_OUT 2 is output from the output terminal of the second abnormality detection circuit 4b to the external part and is input to the second result comparator 8b as a signal BIST_OUT 2.The external part may correspond to a drive circuit to which the microcomputer 1 outputs the control signal for performing drive control of a control object. The control object corresponds, for example, to an on-board actuator. The drive circuit performs a protective operation or safety operation when the drive circuit receives the abnormality detection signal (FAULT_OFF 1, 2). The protective operation or safety operation may, for example, cause a stop of the load operation.

[0025] The BIST controller 6 performs switching control of the first selector circuit 11a and the second selector circuit 11b by a signal (SEL_ON 3). A fixed value set inside the selector 11 is selected when one side of the output terminal of the abnormality detection circuit 4 is not selected in the connected selector 11. The set value corresponds to data indicating that the drive circuit is operating on the safety side when the drive circuit receives the set value.

[0026] The result comparator 8a receives an expected data value from the first BIST section 7a. The second result comparator 8b receives an expected data value from the second BIST section 7b. An expected data value is a data value corresponding to the data represented by the output signal (ERROR_OUT 1, 2) when the BIST section 7 outputs the self-diagnosis data (TEST_IN 1, IN 2) to the abnormality detection circuit 4 and the operation of the abnormality detection circuit is normal. The abnormality detection circuit 4 outputs the output signal (ERROR_OUT 1, 2) as described above. The result comparator 8 compares the input output signal (ERROR_OUT 1, 2) and the corresponding expected value and detects whether the operation of the abnormality detection circuit 4 is normal or not.The detection result is output to the communication section 3 as a signal (BIST 1_ERROR_OFF, BIST 2_ERROR_OFF) and stored in a BIST execution result register 12 formed within the communication section 3.

[0027] The BIST controller 6 issues an execution instruction to the BIST section 7 and issues an execution instruction to the communication section 3 for communication with the microcomputer 1. The BIST controller 6 outputs switching control signals (SEL_ON 1, 2, 3) to the selector 9, the selector 10, and the selector 11. The first selector 9a and the second selector 9b correspond to a data selection circuit. The BIST controller 6 receives a completion signal from the BIST section 7. The completion signal indicates that the BIST section 7 has completed the BIST operation. In other words, the completion signal represents execution completion.

[0028] The first abnormality detection circuit 4a includes two registers 13 (corresponding to a first register 13a and a second register 13b). The second abnormality detection circuit 4b includes a register 14, an error detection section 15, and an error counter 16. The error detection section 15 detects whether data input to the second abnormality detection circuit 4b is appropriate or correct or not. The microcomputer 1 repeatedly compares the pattern of the test data and the predetermined pattern several times when the microcomputer itself performs the function confirmation. The error counter 16 counts the number of times the error detection section 15 detects an error and converts the output signal (ERROR_OFF 2) to an active state when the number exceeds a predetermined threshold. The first register 13a and the second register 13b are collectively referred to as the register 13.

[0029] Register 13 and register 14 store the detection result in the event that the abnormality detection circuit 4 detects an error. The microcomputer 1 is accessible to the first register 13a, the second register 13b, and the register 14 through the communication section 13, allowing data to be read and written. Additionally, the microcomputer is accessible to the error counter 16, allowing a threshold value for error detection to be written and set.

[0030] The first abnormality detection circuit 4a also includes a configuration corresponding to the error detection section 15 and the error counter 16 in the second abnormality detection circuit 4b. This configuration is not required for the following explanation. Therefore, this configuration is omitted from the drawings. The BIST controller 6 and the BIST section 7 correspond to a self-diagnosis circuit 17.

[0031] Fig. 9 shows a flow of a BIST operation. As in Fig. As shown in Figure 9, when the vehicle's ignition switch is turned on, the power supply controller 5 is supplied with power from the battery (S1). The BIST controller 6 determines whether the supply voltage output from the power supply controller 5 reaches an operating voltage (S2). In other words, the BIST controller 6 detects whether the supplied voltage reaches a voltage for BIST operation based on power supply information received from the power supply controller. The power supply controller 5 performs a power-on-reset (POR) of the microcomputer 1. If the detection in step S2 is OK (Yes), the BIST controller 6 causes the selector 11 to select the set value (S3). The BIST controller 6 outputs the BIST execution instruction to the first BIST section 7a and executes a first BIST (S4).

[0032] The first BIST section 7a outputs the switching control signal (SEL_ON) to the first selector 9a and the selector 10. The input terminals of the first selector 9a and the selector 10 are switched to one side of self-diagnosis data. The first BIST section 7a outputs the self-diagnosis data (TEST_ON 1A, B). The first selector 9a receives the self-diagnosis data (TEST_ON 1A), and the selector 10 receives the self-diagnosis data (TEST_ON 1B). The first abnormality detection circuit 4a outputs the signal (BIST_OFF 1) corresponding to the input data. The first result comparator 8a compares the signal (BIST_OFF 1) and the expected value. The first result comparator 8a outputs a comparison result (BIST 1_ERROR_OFF) to the communication section 3. A first BIST execution result register 12a stores the comparison result (BIST 1_ERROR_OFF).The first BIST section 7a transmits the completion signal to the BIST controller 6 after the first BIST (S5). Fig. 1 corresponds to the execution state described above.

[0033] The input terminal of the first selector 9a is switched to one side of the communication section 3 and the input terminal of the selector 10 is switched to one side of the second abnormality detection circuit 4b by the switching control signal (SEL_ON 1) when the first BIST section 7a completes the BIST operation.

[0034] In Fig. 1, the first BIST completion signal is switched from an off state to an on state.

[0035] The BIST controller 6 outputs the BIST execution instruction to the second BIST section 7b and executes the second BIST (S6). The second BIST section 7b outputs the switching control signal (SEL_ON 2) to the second selector 9b. The input terminal of the second selector 9b is switched to a self-diagnosis data side and connects to the second BIST section 7b. The second BIST section 7b outputs the self-diagnosis data (TEST_ON 2) to the second selector 9b. The second abnormality detection circuit 4b outputs the signal (BIST_OFF 2) corresponding to the data input to the second result comparator 8b. The second result comparator 8b compares the signal (BIST_OFF 2) and the expected value and outputs a comparison result (BIST_ERROR_OFF) to the communication section 3. A second BIST execution result register 12b stores the comparison result corresponding to an execution result of the second BIST.The second BIST section 7b sends the completion signal to the BIST controller 6 after the completion of the second BIST (S7 with reference to . Fig. 2). The first BIST execution result register 12a and the second BIST execution result register 12b are collectively referred to as the BIST execution result register 12. In Fig. 2-8, the first BIST completion signal and the second BIST completion signal are switched from an off state to an on state.

[0036] As in Fig. As described in Figure 3, the input terminal of the second selector 9b is switched to one side of the communication section 3 by switching the control signal (SEL_ON1) at a time when the completion signal is transmitted. The BIST controller 6 switches the input terminal of the selector 11 to one side of the abnormality detection circuit 4 by switching the control signal (SEL_ON3) (S8). The power supply controller 5 enables the power-on reset of the microcomputer 1 after a predetermined period of time has elapsed (S9 with reference to Fig. 3).

[0037] The software processing by microcomputer 1 is described. The software processing confirms a function of selector 9 and selector 10 of monitoring module 2. Fig. 10 shows a flow of a software inspection. As in Fig. As described in Figure 10, the microcomputer 1 performs an initial check of the microcomputer 1 and starts an initial check of the monitoring module 2 (S10). The microcomputer 1 writes data into the register 14, reads the data from the register 14 immediately after writing, and checks whether the written data is appropriately read out by the communication section 3 and the second selector 9b through the ON / OFF SIGNAL 2 (S11 with reference to Fig. 4).

[0038] This makes it possible to confirm that the second selector 9b is properly switched according to the switching control signal (SEL_IN 2) when the data is properly read out. That is, it is possible to confirm that the function of the second selector 9b is normal. In other words, it is possible to confirm that the second selector 9b is functioning properly.

[0039] Then, the microcomputer 1 writes data into the first register 13a, reads the data from the first register 13a immediately after writing, and checks whether the written data is read out appropriately or correctly by the ON / OFF_SIGNAL 1 (S12 with reference to Fig. 5). It is possible to confirm that the function of the first selector 9a is normal if the data is read correctly. That is, it is possible to confirm that the function of the first selector 9a is normal. That is, it is confirmed whether the selector 9 is functioning normally.

[0040] The microcomputer 1 accesses the second abnormality detection circuit 4b and decreases the threshold value of the error counter 16. For example, if the threshold value is set to 3 during normal operation, the threshold value is decreased to 1 by the ON / OFF SIGNAL 2 (S13). The microcomputer 1 intentionally transmits a data pattern (corresponding to the error information and the microcomputer abnormality information), which the second abnormality detection circuit 4b detects as an error by the ON / OFF SIGNAL 2 (S14 with reference to Fig. 6). Accordingly, when the second abnormality detection circuit 4b detects the error (S15), the detection result is input to the first abnormality detection circuit 4a through the selector 10. The second register 13b stores the detection result (S16 with reference to Fig. 7).

[0041] Then, the microcomputer 1 accesses the second register 13b, reads the data, and detects whether the data corresponds to an expected data value (S17 with reference to Fig. 8). It is possible to confirm that the function of the selector 10 is normal when the microcomputer 1 reads the expected data value.

[0042] As described above, hard logic of the monitoring module 2 confirms the function of the abnormality detection circuit 4 through the BIST operation (S1 to S9), and then, in the microcomputer 1, software is executed to confirm whether the input selection function of the selector 9 and the selector 10 is normal by performing the processing steps from S10 to S17. The software processing load on the microcomputer 1 can be large. Confirming all the functions of the monitoring module 2 can take a long time. First embodiment

[0043] Based on the above-mentioned reference example, a configuration will be described as a first embodiment, which reduces the load of the software processing of the microcomputer 1. As shown in Fig. As described in Figure 1, a monitoring module 21 (corresponding to an abnormality detection apparatus) is provided in the first embodiment by slightly modifying the configuration of the monitoring module in the reference example. In the monitoring module 2, the output terminal of the second abnormality detection circuit 4b is directly connected to the input terminal of the second result comparator 8b. In the monitoring module 21, instead of this connection, the output terminal of the selector 10 is connected to the input terminal of the second result comparator 8b.

[0044] At the beginning, as in Fig. 11, the first BIST completion signal is switched from an off state to an on state.

[0045] The operational flow diagram of the monitoring module 21 as shown in Fig. 12, corresponds essentially to the flow chart as shown in Fig. 9. A step number (in Fig. 12) corresponds to the step number in Fig. 9. When a power supply voltage with which the BIST controller 6 (corresponding to a self-diagnosis circuit) reaches the operating voltage (S12: Yes), the process moves to a BIST mode (S22). The BIST controller 6 causes the selector 1 to select the set value (S23). The BIST controller 6 gives the BIST execution instruction to the first BIST section 7a (S24). The step numbers of the process of the Fig. 12 and the Fig. 13 correspond to the step numbers which are shown in a time flow diagram of the Fig. 14 are shown.

[0046] When the first BIST section 7a performs the first BIST operation and completes the BIST operation (S25: Yes), the first BIST section 7a switches a first BIST completion signal to an on-state and sends the first BIST completion signal to the BIST controller 6 (S26). The register 13 stores the comparison result of the first BIST operation (S27). The first BIST operation corresponds to the BIST operation by the first BIST section 7a. Here, the timing when the first BIST section 7a switches the BIST completion signal to the on-state substantially corresponds to the timing when the first result comparator 8a outputs the comparison result to the communication section 3.

[0047] When the BIST controller 6 issues the BIST execution instruction to the second BIST section 7b (S28), the second BIST section 7b executes the second BIST operation. When the second BIST operation is executed, the second abnormality detection circuit 4b outputs the signal (BIST_OUT 2) to the second result comparator 8b through the selector 10. That is, the signal (BIST_OUT 2) is not directly output to the second result comparator 8b. The signal (BIST_OUT 2) is output as a result of the second abnormality detection circuit 4b receiving the self-diagnosis data (TEST_IN 2). When the second BIST operation is completed (S29: Yes), the second BIST section 7b switches the second BIST completion signal to the on state and sends the second BIST completion signal to the BIST controller 6 (S13). Register 14 stores the comparison result of the second BIST operation (S31).The BIST controller 6 switches the input terminal of the selector 11 to the abnormality detection circuit 4 side (S32). When the BIST mode is completed (S33), the power supply controller 5 initiates the power-on reset of the microcomputer 1.

[0048] The execution result (BIST_OUT 2) of the second BIST operation input to the second result comparator 8b is input through the selector 10. Therefore, it is possible to determine whether the function of the selector 10 is normal when the execution result corresponds to the expected value.

[0049] Fig. Fig. 13 illustrates a process corresponding to steps S41 to S47 performed by the microcomputer. The process of steps S41 to S47 corresponds to the process of steps S10 to S12 in Fig. 10. The process of steps S13 to S17 in Fig. 10 is performed to determine whether the selector 10 is functioning normally or not. As described above, in the first embodiment, whether the selector 10 is functioning normally or not is determined in process step S29, which is performed by the monitoring module 21. Therefore, it is unnecessary for the microcomputer 1 to perform the process corresponding to steps S13 to S17. In other words, the process in Fig. 13 the procedure in Fig. 10 without the process steps S13 to S17 in Fig. 10 correspond.

[0050] According to the first embodiment, the monitoring module 21 has two abnormality detection circuits 4 (corresponding to the first abnormality detection circuit 4a and the second abnormality detection circuit 4b). The abnormality detection circuit 4 outputs the abnormality detection signal (ERROR_OFF 1, 2) to the external part when the pattern of the data input from the microcomputer 1 does not match the predetermined pattern. As described above, the BIST controller 6 and the BIST section 7 correspond to the self-diagnosis circuit 17. The self-diagnosis circuit 17 outputs self-diagnosis data having an identical pattern to the test data of the abnormality detection circuit 4 and monitors the function of the abnormality detection circuit 4.

[0051] The first abnormality detection circuit 4a performs abnormality detection by considering a state of the abnormality detection signal output from the second abnormality detection circuit 4b when the abnormality detection circuit 4a receives the test data from the microcomputer 1. The first abnormality detection circuit 4a receives the abnormality detection signal (BIST_OFF 2) output from the second abnormality detection circuit 4b through the selector 10.

[0052] This is based on the assumption that the self-diagnosis circuit 17 controls the selector 9 and the selector 10 to output the self-diagnosis data to the abnormality detection circuits 4. In this case, the result comparator 8 compares the expected value of the data that should be output by the abnormality detection circuit 4 and the data that has actually been output by the abnormality detection circuit 4. The second result comparator 8b, which corresponds to the second abnormality detection circuit 4b, receives the data through the selector 10.

[0053] Therefore, it is possible to determine whether the function of the second abnormality detection circuit 4b is normal and to determine whether the function of the selector 10 is normal by referring to the comparison result of the second result comparator 8b. Therefore, it is possible to simplify the configuration of the monitoring module 21. It is therefore possible to perform self-diagnosis in a shorter time. Second embodiment

[0054] If the operating power supply voltage supplied to the monitoring module 21 is unstable during a period in which the monitoring module 21 performs the BIST operation, the reliability of the BIST operation result may be reduced. For example, in a vehicle having an idle reduction function, when a starter motor is driven to restart an engine that temporarily stops during driving, a battery voltage may be temporarily reduced, and the operating power supply voltage may be unstable.

[0055] In the second embodiment, as shown in Fig. 15, if a drop in the operating power supply voltage is detected during a period in which the BIST operation is being executed, the execution result data acquired up to that point is discarded, and the BIST operation is restarted from the beginning. As described in Fig. As described in Figure 16, the BIST controller 6 monitors whether the operating power supply voltage of 5 volts has an abnormality during a period from the start of the first BIST operation in step S24 to the completion of the first BIST operation in step S25 and during a period from the start of the second BIST operation in step S28 to the completion of the second BIST operation in step S29 (S34, S35). The BIST controller 6 corresponds to a voltage abnormality detection section in the present disclosure.

[0056] Specifically, a lower limit of the operating voltage of the monitoring module 21 is set as a threshold. The BIST controller 6 monitors whether the operating power supply voltage is below this threshold. If the operating power supply voltage falls below this threshold (S34, S35: No), the execution result data acquired up to that point is discarded. The process moves to step S24 in the case of the first BIST operation, and the first BIST operation is again performed from the beginning. Similarly, the process moves to step S28 in the case of a second BIST operation, and the second BIST operation is again performed from the beginning.

[0057] According to the second embodiment, when the BIST controller 6 detects an abnormality in the operating power supply voltage during a period in which the self-diagnosis data is output to the abnormality detection circuit 4, the BIST controller 6 stops outputting the self-diagnosis data, and the data output operation is performed again from the beginning. Therefore, even if the operating power supply voltage becomes temporarily unstable, it is possible to maintain the reliability of the diagnosis result data. Third embodiment

[0058] For example, assume that a CR oscillator circuit or the like is used to provide timing in the monitoring module 21. In this case, an operation time of the BIST operation may be longer if a timing frequency is changed in accordance with an ambient temperature or the like, and especially if the timing frequency is reduced. For example, if the function of the BIST section 7 is abnormal and a BIST operation sequence stops midway, the completion signal may not be switched to the on state. In this case, the reliability of the BIST operation result may be reduced.

[0059] In the third embodiment, the BIST controller 6 monitors the execution time of the BIST operation. In the third embodiment, it is assumed that the BIST controller 6 receives a clock signal from a high-precision oscillation circuit including a crystal oscillator, which the crystal oscillator supplies and drives. The third embodiment performs the following function in addition to the function described in the second embodiment.

[0060] As in Fig. As described in Figure 13, when the BIST section 7 initiates the BIST operation, the BIST controller 6 measures the execution time with a counter, stopwatch, or the like (corresponding to a self-diagnosis time measuring circuit). In the third embodiment, when the operating power supply voltage is unstable and the BIST operation is performed again as in the second embodiment, the BIST controller 6 again measures the execution time from a starting time of execution. A threshold time value T1 of the execution time is set. The threshold time value T1 corresponds to a predetermined time. A result of the BIST operation is considered abnormal if the execution time exceeds the threshold time value T1 (in other words, if the execution time has elapsed).

[0061] As in Fig.As described in Figure 18, if the process in step S25 is No, the BIST controller 6 determines whether the execution time (corresponding to a first elapse time) of the first BIST operation exceeds the threshold time value T1 (S36). At step S36, the process moves to step S32, and the BIST operation is completed if the first elapse time exceeds the threshold time value T1 (S36: Yes). If the process in step S29 is No, the BIST controller 6 determines whether a value obtained by adding an execution time (corresponding to a second elapse time) of the second BIST operation to the execution time of the first BIST operation exceeds the threshold time value T1 (S37). If the value exceeds the threshold time value T1 (S37: Yes), the process moves to step S32.

[0062] According to the abnormality detection device of the third embodiment, the BIST controller 6 measures a time that begins to run when the abnormality detection circuit 4 receives the self-diagnosis data. When the measured time reaches the predetermined time and the result comparator 8 corresponding to the abnormality detection circuit 4 does not output a comparison completion signal, the self-diagnosis is completed. Therefore, it is possible to maintain the reliability of the result of the BIST operation by removing the execution result in a case where the BIST operation is not performed normally.

[0063] The present invention is not limited to the embodiments described above or depicted in the figures. The following modifications or extensions are possible within the scope of the present disclosure.

[0064] The abnormality detection circuit may consist of three or four circuits. Additionally, two or more pairs may be provided, each pair corresponding to a first abnormality detection circuit and a second abnormality detection circuit.

[0065] The function corresponding to the second embodiment can be removed from the third embodiment.

[0066] The result comparator 8 corresponds to a comparison unit. The first selector 9a and the second selector 9b correspond to a data selection circuit. The selector 10 corresponds to a data or signal selection circuit. The monitoring module 21 corresponds to an abnormality detection device.

[0067] Although the present invention has been described with reference to preferred embodiments, this disclosure is not limited to the preferred embodiments and constructions. The present disclosure is intended to cover various modifications and equivalent constructions. Furthermore, in addition to the various combinations and configurations that are preferred, other combinations and configurations including more, fewer, or even a single element are also within the scope of the present invention and utilize the teachings of the present invention.

Claims

[1] An abnormality detection device for a vehicle microcomputer, which monitors a function of a microcomputer (1) controlling an on-board device and has a plurality of abnormality detection circuits (4a, 4b) which output an abnormality detection signal to an external part when a pattern of test data input from the microcomputer (1) does not correspond to a predetermined pattern, comprising: a self-diagnosis circuit (17) which monitors the function of the plurality of abnormality detection circuits (4a, 4b) and outputs to each of the abnormality detection circuits (4a, 4b) self-diagnosis data having a pattern identical to the test data; a plurality of data selection circuits (9a, 9b) which select either the test data or the self-diagnosis data and output the selected data to each of the abnormality detection circuits (4a, 4b); a data or signal selection circuit (10) which selects the abnormality detection signal output from a second abnormality detection circuit (4b) or the self-diagnosis data, and outputs either the selected abnormality detection signal output from a second abnormality detection circuit (4b) or the selected self-diagnosis data to a first abnormality detection circuit (4a), wherein the plurality of abnormality detection circuits (4a, 4b) comprises at least the first abnormality detection circuit (4a) and the second abnormality detection circuit (4b); and a plurality of comparison circuits (8a, 8b) which compare a value expected to be output by each of the abnormality detection circuits (4a, 4b) with data actually output by each of the abnormality detection circuits (4a, 4b) when the self-diagnosis circuit (17) controls the data selection circuits (9a, 9b) and the data or signal selection circuit (10) to output the self-diagnosis data to the plurality of abnormality detection circuits (4a, 4b), wherein a first comparison circuit (8a) of the comparison circuits (8a, 8b) is associated with the first abnormality detection circuit (4a), a second comparison circuit (8b) of the comparison circuits (8a, 8b) is associated with the second abnormality detection circuit (4b), and the second comparison circuit (8b) receives either the selected abnormality detection signal output from the second abnormality detection circuit (4b) or the selected self-diagnosis data through the data or signal selection circuit (10). [2] An abnormality detecting device for the vehicle microcomputer according to claim 1, further comprising: a BIST controller (6) configured as a voltage abnormality detection section, which detects an abnormality of an operating power supply voltage during a period in which a BIST operation is carried out, wherein the self-diagnosis circuit (17) comprising the BIST controller (6) and BIST sections (7a, 7b) stops outputting the self-diagnosis data and outputs the self-diagnosis data again from the beginning when the BIST controller (6) of the self-diagnosis circuit (17) detects the abnormality of the operating power supply voltage during a period in which the self-diagnosis circuit (17) outputs the self-diagnosis data to each abnormality detection circuit (4a, 4b). [3] An abnormality detecting device for the vehicle microcomputer according to claim 1, wherein the self-diagnosis circuit (17) includes a BIST controller (6) designed as a self-diagnosis time measuring circuit, which measures a time from a time when the self-diagnosis circuit (17) starts outputting the self-diagnosis data to each of the abnormality detection circuits (4a, 4b), the comparison circuit (8a, 8b) associated with each of the abnormality detection circuits (4a, 4b) outputs a signal representing comparison completion when the comparison circuit (8a, 8b) completes a comparison between the expected value and the data actually output by each of the abnormality detection circuits (4a, 4b), and the self-diagnosis circuit (17) completes a self-diagnosis when the time measured by the self-diagnosis time measuring circuit reaches a predetermined time and the comparison circuit (8a, 8b) associated with each of the abnormality detection circuits (4a, 4b) does not output the comparison completion signal.

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