PERFORMANCE MANAGEMENT FOR DATA CENTER PERFORMANCE ARCHITECTURES

Abstract

Method for managing resource utilization for a system board (100) which has: multiple processors (102), memory allocated to each of the processors (102), several voltage regulators (106) designed to regulate voltages applied to the processors (102) and memory, and a board manager (108) trained to manage resources of the system board (100), the method comprising: Transmitting an operating status information from the board manager (108) to controllers (107) of the voltage regulators (106) independently of the processors (102), which also communicate with the controllers (107), wherein the operating status information received by each controller (107) specifies a computational load for the processor (102) which is controlled by the voltage regulator (106) controlled by the controller (107), and Controlling the voltage regulators (106) based on the operating state information to set the power limit of the voltage regulators (106) according to the processing load specified by the operating state information transmitted by the board manager (108) to the controllers (107) for each processor (102), and the procedure also features: Receiving telemetry information from the voltage regulators (106) by the board manager (108), wherein the telemetry information indicates an efficiency of the voltage regulators (106) for different power modes of the respective processors (102), and Generating an efficiency profile by the board manager (108) based on the telemetry information.

Description

[0001] The present invention relates to performance management schemes for data center performance architectures and in particular relates to a dynamic scaling of performance components in a data center for optimal performance efficiency.

[0002] Data center power architectures feature multiple conversion stages to transform the main AC power supply into the lower DC voltage required by the CPU (central processing unit), memory, and other electronic components within the system, such as storage, graphics logic, I / O (input / output), and so on. A data center typically has multiple racks, and each rack contains multiple server boards. In one example, a 48V distribution voltage is stepped down to 12V on each board, which is then further reduced to the low voltage required by the digital circuitry using voltage regulators (SRs) and point-of-load converters (POLs). Each board typically contains N CPUs (where N could be, for example, 2 or 4) and 2 or more memory banks per CPU.Optimal efficiency at each power conversion stage is highly desirable, as the total required input power is a function of the product of the efficiencies of all stages. Furthermore, a significant portion of the energy consumed by data centers is used for thermal management of fans and air conditioning. Inefficient use of computing resources can lead to inefficient operation of the power converters, which in turn places additional strain on the cooling systems. Therefore, small improvements to the power management scheme at the individual CPU level can result in dramatic performance efficiencies at the data center level.

[0003] German patent DE 10 2007 021 258 A1 describes an information processing system with modular processing resources, each comprising a main processor, system memory, and preferably a service processor resource. A management resource evaluates a system power budget and allocates power to a processing resource by indicating a critical power level. The processing resource determines a warning power level based on the critical power level and monitors its current power consumption. If the current power consumption exceeds the critical power level, the processing resource is shut down. If the current power consumption exceeds the warning power level, the processing resource throttles its performance to conserve power and requests an increase in power allocation.If the current power consumption is below the warning power level, the processing resource can request a reduction in the allocated power.

[0004] DE 10 2007 046 002 A1 describes a method for controlling power supplies in an information processing system. The method comprises measuring the power consumption of each of several electrical devices in the information processing system and adjusting a number of operating power supplies at least partially based on the measured power consumption of the electrical devices.

[0005] WO 2013 / 158116 A1 discloses a processor power management system and a corresponding method. The system comprises a control system that communicates with each of several processors. The voltage regulator control system generates a processor voltage that is made available to each of the processors and controls the level of the processor voltage based on power management request signals provided by each of the processors.

[0006] One embodiment of the invention relates to a method according to claim 1 for managing resource utilization for a system board.

[0007] Another embodiment relates to a system board according to claim 14.

[0008] Another embodiment relates to a data center according to claim 21.

[0009] Experts will recognize further features and advantages when reading the following detailed description and examining the accompanying drawings.

[0010] The elements in the drawings are not necessarily to scale. Identical reference numerals denote corresponding similar parts. The features of the various illustrated embodiments can be combined, provided they are not mutually exclusive. Embodiments are shown in the drawings and described in detail in the following description. Fig. Figure 1 illustrates, according to one embodiment, a block diagram of a system board which includes a board power manager configured to manage resources of the system board. Fig. Figure 2 illustrates, according to one embodiment, a flowchart of a method for managing resource utilization for a system board. Fig. Figure 3 illustrates, according to one embodiment, a block diagram of a rack comprising multiple system boards and a rack-level power manager associated with the system boards, configured to manage rack resources. Fig. Figure 4 illustrates, according to one embodiment, a block diagram of a data center which has multiple racks and a data center-level power manager associated with the racks, which is trained to manage data center resources.

[0011] In the embodiments described here, power managers are used to generate a power efficiency profile of the components in a data center and to control the use of these components based on the defined power efficiency profile. At the board level of the data center, a board manager has a direct data transmission link to the voltage regulator controllers. The controllers manage the operation of the voltage regulators so that the voltage applied to the processors is efficiently regulated and have the ability to switch between different power modes. The board manager thus has a direct data transmission link to the voltage regulator controllers that is independent of the processors exchanging data with the controllers. The board manager receives telemetry information (e.g.,Input power of the voltage regulators), which indicate the power efficiency of the voltage regulators assigned to each processor. Using this telemetry information, the board manager can generate an efficiency profile that specifies which processors on the board should be used for optimal power efficiency under which conditions.

[0012] The implementations described here offer significant advantages compared to conventional data center power management methods. Traditionally, each processor communicates directly with its voltage regulator controller, adjusting power levels up or down based on various factors. However, the processors are unaware of the power efficiency or the use of other processor-voltage regulator pairs within the system. For various reasons, certain voltage regulators on each board may be more or less efficient under given power settings. These reasons can include, for example, process variations in the components and their physical distance from one another.The board manager assigns workloads to the processor-voltage regulator pairs that are most efficient under given conditions, utilizing less efficient pairs only when necessary. The board manager can also override the power state of the voltage regulators. Processors remain free to adjust their respective voltages, and the corresponding voltage regulator responds accordingly. This avoids unnecessary transitions between power modes. This concept can be implemented at any hierarchical level within the system. For example, at the rack level, where multiple boards are located per rack, each rack can have a power manager that assigns workloads to individual boards within its respective racks using a similar priority scheme.The power manager of each rack can also control cooling settings such as fan speed and temperature within the rack. The same concept can be applied at the data center level, using a single power manager to control multiple racks.

[0013] Fig. Figure 1 shows a representative block diagram of a system board 100, configured to manage resource utilization, according to one embodiment. The system board 100 has a plurality (e.g., two, three, four, etc.) of processors 102 (e.g., CPUs). The system board 100 also has at least one memory 104, which is assigned to each of the processors 102. For example, as shown in Fig. Figure 1 shows two memory units 104 coupled to each of the processors 102. The system board 100 further comprises several voltage regulators (SRs) 106 configured to regulate voltages applied to the processors 102 and the memory units 104. According to one embodiment, the voltage regulators 106 are multiphase voltage regulators 106 comprising two or more power stages 109, each power stage 109 providing one phase of the multiphase voltage regulator and configured to supply current to the CPU. In the case of a multiphase buck converter, each power stage 109 of the multiphase buck converter comprises a high-side transistor and a low-side transistor for coupling this phase to the corresponding processor 102 via an inductor.

[0014] As the CPU's power requirements change, the voltage regulators 106 can dynamically activate or deactivate the phases. Furthermore, during periods of low utilization, the voltage regulator 106 can select a subset of the power phases and deactivate the other power phase(s). This is commonly referred to as phase shedding. Each voltage regulator 106 also includes a controller 107 for managing the operation of the respective voltage regulators. While the voltage regulators are logically illustrated as individual units, they can be implemented as a collection of separate components, such as power transistor dies, controller dies, capacitors, inductors, and so on.

[0015] The system further comprises a board manager 108, which exchanges data with each of the processors 102, each of the memory units 104, and each of the voltage regulators 106. For this purpose, the system has a first data transmission link 110 between the board manager 108 and the voltage regulators 106, and a second data transmission link 112 between the board manager 108 and the voltage regulators 106. The first and second data transmission links 110 and 112 can, for example, be provided by means of a serial bus. According to one embodiment, the first and second data transmission links 110 and 112 are independent of each other. The board manager 108 can have direct two-way data exchange with the voltage regulators 106 (and in particular with the controllers 107 assigned to each voltage regulator 106) without using the data transmission link between the processors 102 and the voltage regulators 106.

[0016] The board manager 108 is configured to manage the resource utilization of the system board 100 as follows. The board manager 108 transmits an operating state information from the board manager 108 to the controllers 107 of the voltage regulators 106. The operating state information specifies a processor workload to the SR controllers 107. When the board manager 108 transmits the operating state information to the SR controllers 107, it is transmitting a current or power. The voltage regulators 106 do not have the knowledge or the ability to translate an actual processor workload into an operating state. Instead, the board manager 108 performs this function. In one embodiment, the board manager 108 proactively transmits a limit of the electrical load to the SR controllers 107. For example, the board manager translates a processor workload into, say, a certain amount of current or power.MIPS (millions of instructions per second) in current or power. In a second embodiment, the board manager 108 does not translate processor workload, but instead notifies the SR controller 107 that the electrical load will not increase.

[0017] The operating status information is transmitted by the board manager 108 to the controllers 107 of the voltage regulators 106 independently of the processors 102, which also communicate with the SR controllers 107. This independent data exchange can be achieved by the second data transmission link 112, as already discussed.

[0018] The board manager 108 is configured to control the voltage regulators 106 based on operating state information. The board manager 108 controls the voltage regulators 106 in accordance with the computational load specified by the operating state information transmitted by the board manager 108 to the SR controllers 107 assigned to each processor 102. This means that the board manager 108 can set the power limit of the voltage regulators 106 based on the operating state information. The processors 102 are permitted to control their respective voltages, while the board manager 108 sets the respective power limits. Each power limit set by the board manager 108 takes into account the dynamic voltage set by the corresponding processor 102.

[0019] One way in which the board manager 108 can optimize the power efficiency of the system board 100 involves using telemetry information to allocate processing load to the most efficient pairings of processors 102 and voltage regulators 106. According to one embodiment, the board manager 108 receives telemetry information from the voltage regulators 106 connected to the board manager 108. The telemetry information can be any information that provides an indication of the efficiency of the voltage regulators 106. The telemetry information can include the activity levels of each processor 102, the input voltage, current, and / or power of each voltage regulator 106, the output voltage, current, and / or power of each voltage regulator 106, the voltage of each processor 102, the current of each processor 102, the temperature of each processor 102, the temperature of each regulator 106, and so on.The telemetry information can, for example, be transmitted to the second data transmission connection 112.

[0020] The board manager 108 is trained to prioritize the use of the processors 102 based on the efficiencies of the voltage regulators 106 for the different power modes. That is, the board manager 108 can use telemetry information to determine which processor 102 / voltage regulator 106 pairings should be given a higher priority and which should be given a lower priority. Although each processor 102 / voltage regulator 106 pairing might nominally operate at the same efficiency under the same conditions, there are various reasons why the processor 102 / voltage regulator 106 pairings might not behave as nominally. For example, one or more components of each voltage regulator 106, such as output inductors, output capacitors, input capacitors, etc., might vary due to process variation.Furthermore, the physical arrangement of the processors 102, memory 104, and voltage regulators 106 can result in certain data transmission paths being faster than others. According to one embodiment, the board manager 108 generates a profile of the input power of each voltage regulator 106 as a function of a processing level of the respective processors 102 for the different power modes. That is, the board manager 108 collects data on which pairs of processors 102 and voltage regulators 106 perform better than others at a given power setting and maps this data to a priority scheme.

[0021] The board manager 108 routes incoming board data to the processors 102 based on prioritized usage, so that the incoming board data is first routed to the processors 102 whose voltage regulators 106 are more efficient, and subsequently to the processors 102 whose voltage regulators 106 are less efficient. This prioritization occurs only when additional processing resources are needed to process the incoming board data. That is, the board manager 108 only reacts to load conditions that involve a change in the voltage regulation of at least one processor 102 and where a priority scheme would therefore be advantageous, specifying which pairs of processors 102 and voltage regulators 106 should be used first.

[0022] According to one embodiment, the incoming board data is routed to the processors 102 by means of the board manager 108 based on the generated profiles, such that the incoming board data is first routed to the processors 102 whose voltage regulators 106 have a lower input power-to-computing-level profile, and subsequently routed to the processors 102 whose voltage regulators 106 have a higher input power-to-computing-level profile only when additional processing resources are needed to process the incoming board data. A working example of this fixed resource allocation will now be discussed for illustrative purposes. The profile generated by the board manager 108 may indicate that the two processors 102 on the system board 100 operating at 80% of a peak power consumption are more efficient than four of the processors 102 operating at 40% of a peak power consumption.Based on this knowledge, the board manager 108 directs the incoming board data to the two more efficient processors 102, so that these processors 102 perform the calculation, and so that the two less efficient processors 102 can be deactivated or only used when additional processing resources are needed to handle the incoming data.

[0023] In addition to the resource allocation priority management scheme described above, the board manager 108 can be used to control the voltage regulators 106 independently of the respective processors 102. If the board manager 108 and the second data transmission link 112 between the board manager 108 and the voltage regulators 106 are not present, the voltage regulators 106 can only be controlled externally by the processors 106. In this case, the power mode of the voltage regulators 106 is controlled directly by the processor 102, without regard to the efficiency of the processor 102 and the voltage regulator 106, and without regard to the likely allocation of future processing requirements on the system board 100.The system overcomes this disadvantage by using the second data transmission link 112 between the board manager 108 and the voltage regulators 106 to speed up the process of instructing the voltage regulators 106 to change power states and / or to eliminate unnecessary transitions of the voltage regulators 106 between power states.

[0024] According to one embodiment, the operating state information (e.g., a specification of a computational load for processor 102) is proactively transmitted by the board manager 108 to a first of the SR controllers 107 before processor 102, to which the first SR controller 107 is assigned, enters a restricted power range. The proactively transmitted operating state information indicates that processor 102, to which the first SR controller 107 is assigned, is expected to eventually enter the restricted power range and remain there for a predetermined period. Based on this information, a reduced-power operating state is determined for the voltage regulator 106, which is controlled by the first SR controller 107.According to another embodiment, the board manager 108 transmits the operating state information to a first SR controller 107 after the processor 102, to which the first SR controller 107 is assigned, has entered a restricted power range. In this case, the operating state information indicates that the processor 102, to which the first SR controller 107 is assigned, has entered the restricted power range and will remain in the restricted power range for a predetermined period. In each case, the voltage regulator 106, which is controlled by the first SR controller 107, is operated in the reduced power state based on the direct transmission of the operating state information between the board manager 108 and the first SR controller 107.The first SR controller 107 can be instructed to remain in the reduced-power operating state until the board manager 108 specifies otherwise. In this way, the board manager 108 can override any instructions that the processors 102 might issue to the controllers 107 of the voltage regulators 106 assigned to these processors 102.

[0025] The system can also use the operating state information to accelerate the transition of the voltage regulators 106 from different power states using the board manager 108. For example, according to one embodiment, the board manager 108 proactively forces the voltage regulator 106, controlled by the first SR controller 107, to exit the reduced-power operating state. This can occur, for example, if the operating state information indicates to the board manager 108 that an increase in the computational load imposed on the processor 102 is imminent. The voltage regulator 106 is forced to exit the reduced-power operating state before the processor 102, to which the first SR controller 107 is assigned, issues a command to the voltage regulator 106 indicating that the voltage regulator 106 should exit the reduced-power operating state.Advantageously, since the board manager 108 has generated a profile of the input power of each voltage regulator 106 as a function of a computing level of the respective processors 102 for the different power modes, the board manager 108 can determine which of the processors 102 will leave the reduced-power operating state and which of the processors 102 will remain in the reduced-power operating state, and accordingly only initiate a transition of the voltage regulators 106 assigned to these processors 102 to the operating state with suitable power.

[0026] The system can also use the operating state information to prevent the processor 102 from adjusting the power state of the voltage regulator 106 in response to a dynamic event, such as a sudden increase or decrease in the computational load of one of the processors 102. For example, according to one embodiment, the operating state information is transmitted by the board manager 108 to a first of the SR controllers 107 in response to a dynamic event at the processor 102 to which the first SR controller 107 is assigned. In this case, the operating state information indicates that a dynamic event has occurred at the processor 102. The voltage regulator 106 controlled by the first SR controller 107 is prevented from entering a reduced-power state in response to receiving this operating state information at the first SR controller 107.In other words, the operating state information is used to indicate to the voltage regulator 106 that a large computation event is imminent, so that the voltage regulator 106 remains at optimal efficiency and / or optimal performance.

[0027] Fig. Figure 2 shows a flowchart of a procedure for managing resource utilization on a system board. According to a first step 200 in the procedure, operating state information, e.g., as one or more instructions, is transmitted from the board manager 108 to the controllers 107 of the voltage regulators 106, independently of the processors, which also communicate with the SR controllers 107. The operating state information is received by each SR controller 107 and specifies a workload for the processor 102, which is controlled by the voltage regulator 106 controlled by that controller. The operating state information can specify certain current or power limits.

[0028] According to a second step 202 in the procedure, the voltage regulators 106 are controlled based on the operating state information to set the power limit of the voltage regulators 106 according to the processing load specified by the operating state information transmitted by the board manager 108 to the SR controllers 107. The individual processors 102 are allowed to control their respective voltages, but the board manager 108 sets the power limit by sending the operating state information, e.g., in the form of one or more commands, to the corresponding SR controllers 107 via the second data transmission link 112. Each power limit set by the board manager 108 takes into account the dynamic voltage set by the corresponding processor 102.The dynamic voltage telemetry information for the processors 102 is transmitted from the processor 102 to the board manager 108 via the first data transmission link 110.

[0029] Fig. Figure 3 shows that the system board consists of 100 components. Fig. 1 was integrated into a frame 300 (e.g., a server frame). The frame 300 also has several additional system boards 100, which are essentially similar to or identical with the system board 100 from Fig. The rack 300 has a rack manager 302, which is configured to manage the resources of the rack 300. The rack manager 302 has a direct data transmission link 304 to each of the board managers 108 of each system board 100.

[0030] The Frame Manager 302 is trained to use a similar performance efficiency management scheme from a frame level perspective as the one related to Fig. 1. Board Manager 108 is discussed from the perspective of a board level. In particular, the operating state information is transmitted from each of the board managers 108 to the rack manager 302, using the direct data transmission link 304 between the two. The operating state information transmitted by each of the board managers 108 represents a computational load for the system board- The rack manager 302 prioritizes the use of system boards 100 based on the operating status information transmitted by the board managers 108. Based on this prioritization, the rack manager 302 routes incoming rack data to the system boards 100, first to those with higher operating status information and then to those with lower operating status information. This prioritization occurs only when additional processing resources are needed to handle the incoming rack data.This means that the rack manager 302 only reacts to load conditions that involve a change in the voltage regulation of at least one board 100 and where a priority scheme would therefore be advantageous as to which boards 100 should be used first.

[0031] The rack manager 302 is also trained to adjust the cooling system of the rack 300 based on its knowledge of the performance requirements of the individual circuit boards 100. As in Fig. As shown in Figure 3, the rack manager board 302 receives telemetry from the board managers 108 of each board. Examples of telemetry from the board managers 108 include: processor 102 temperature, processor 102 input voltage (applied by the voltage regulators 106), processor 102 input current, and processor 102 input power. The rack manager 302 also receives telemetry from the rack 300 cooling system via a direct data transmission path between the rack manager 302 and the cooling system. Examples of telemetry from the cooling system include: rack 300 ambient temperature, fan input voltage, fan input current, and fan input power. The rack manager 302 aggregates this telemetry and adjusts the rack 300 cooling system accordingly.For example, according to one embodiment, the rack manager 302 adjusts the temperature and airflow in the rack 300 based on the operating status information transmitted by the board managers 108.

[0032] Fig. Figure 4 shows a Data Center 400, which houses a variety of the components related to Fig. The system comprises three described racks 300. Each rack 300 has a rack manager 302, which is trained to manage the resources of that rack 300, e.g., those relating to Fig. 3. The data center 400 has a data center manager 402 trained to manage the resources of the data center 400. The rack manager 302 has a direct data transmission link 404 to each of the board managers 108 of each system board 100. From a data center level perspective, the data center 400 employs a similar resource utilization and efficiency scheme as that described in Fig. 1 discussed circuit board manager 108 and the based on Fig. Three rack managers 302 were discussed. In particular, each rack manager 302 is configured to transmit an operational status information to the data center manager 402. The operational status information transmitted by each rack manager 302 indicates a workload for the rack 300 assigned to that rack manager 302. The data center manager 402 is configured to prioritize the use of racks 300 based on the operational status information transmitted by the rack managers 302. The data center manager 402 is configured to route incoming data center data to the racks based on the prioritized use, such that the incoming data center data is first routed to racks 300 whose operational status information indicates higher efficiency, and subsequently to racks 300 whose operational status information indicates lower efficiency.This prioritized usage only occurs when additional processing resources are needed to handle incoming data center data. That is, data center 400 only responds to load conditions that require a change in the voltage regulation of at least one processor 102, and where a priority scheme for which voltage regulators 106 should be used first would therefore be advantageous.

[0033] The Data Center Manager 402 is also trained to adjust the cooling mechanisms of the Data Center Manager 402 based on its knowledge of the performance requirements of each rack. As in Fig.As shown in Figure 4, the data center manager 402 receives telemetry from the rack managers 302 of each rack 300. Examples of telemetry from the rack managers 302 include: aggregated rack telemetry (e.g., rack temperature, rack output voltage, rack output current, rack output power, compute load (in MIPS, FLOPS, etc.)); data center-level telemetry (e.g., data center input power, data center input current, data center input power); and data center cooling system information (e.g., data center HVAC system temperature setting, active HVAC units, etc.). The data center 400 aggregates this telemetry and adjusts the data center cooling system accordingly. For example, according to one embodiment, the data center manager 402 is configured to adjust the temperature and airflow in the data center 400 based on the operating status information transmitted by the rack managers 302.

[0034] Although a Data Center 400 is used as an example, the implementations described here are equally applicable to microservers and cloud computing architectures.

[0035] It is understood that the features of the various embodiments described here can be combined with one another, unless expressly stated otherwise.

Claims

[1] Method for managing resource utilization for a system board (100) comprising: multiple processors (102), memory allocated to each of the processors (102), several voltage regulators (106) designed to regulate voltages applied to the processors (102) and memory, and a board manager (108) trained to manage resources of the system board (100), the method comprising: Transmitting an operating status information from the board manager (108) to controllers (107) of the voltage regulators (106) independently of the processors (102), which also communicate with the controllers (107), wherein the operating status information received by each controller (107) specifies a computational load for the processor (102) which is controlled by the voltage regulator (106) controlled by the controller (107), and Controlling the voltage regulators (106) based on the operating state information to set the power limit of the voltage regulators (106) according to the processing load specified by the operating state information transmitted by the board manager (108) to the controllers (107) for each processor (102), and the procedure also features: Receiving telemetry information from the voltage regulators (106) by the board manager (108), wherein the telemetry information indicates an efficiency of the voltage regulators (106) for different power modes of the respective processors (102), and Generating an efficiency profile by the board manager (108) based on the telemetry information. [2] The method of claim 1, further comprising: Prioritizing processor usage (102) using the board manager (108) based on the efficiency profile for the different power modes and Directing incoming board data to the processors (102) based on prioritized usage, such that the incoming board data is first directed to the processors (102) whose voltage regulators (106) are more efficient, and subsequently directed to the processors (102) whose voltage regulators (106) are less efficient only when additional processing resources are needed to process the incoming board data. [3] The method of claim 2, wherein: the telemetry information includes an input power of the voltage regulators (106); a use of the processors (102) by generating a profile of the input power of each voltage regulator (106) as a function of a computation level of the respective processors (102) is prioritized for the different power modes and The incoming board data is directed to the processors (102) based on the profiles, such that the incoming board data is first directed to the processors (102) whose voltage regulators (106) have a lower input power-to-computing level profile, and is then directed to the processors (102) whose voltage regulators (106) have a higher input power-to-computing level profile only if additional processing resources are needed to process the incoming board data. [4] A method according to any of the preceding claims, further comprising: preventive transmission of the operating state information from the board manager (108) to a first of the controllers (107) before the processor (102) assigned to the first controller enters a restricted power range, wherein the preventively transmitted operating state information indicates that the processor (102) assigned to the first controller is expected to eventually enter the restricted power range and remain in the restricted power range for a specified period of time; Setting a reduced-power operating state for the voltage regulator (106) controlled by the first controller based on the proactively transmitted operating state information and Operating in reduced power mode. [5] The method of claim 4, further comprising: preventively forcing the voltage regulator (106) controlled by the first controller to exit the reduced-power operating state before the processor (102) associated with the first controller issues an instruction to the voltage regulator (106) indicating that the voltage regulator (106) should exit the reduced-power operating state. [6] Method according to claim 4 or 5, wherein the first controller remains in the reduced-power operating state until the board manager (108) indicates otherwise. [7] A method according to any of the preceding claims, further comprising: Transmitting the operating state information from the board manager (108) to a first of the controllers (107) after the processor (102) assigned to the first controller has entered a restricted power range, wherein the operating state information indicates that the processor (102) assigned to the first controller has entered the restricted power range and will remain in the restricted power range for a specified period of time; Setting a reduced-power operating state for the voltage regulator (106) controlled by the first controller based on the operating state information and Operating the voltage regulator (106) controlled by the first controller in the reduced power operating state. [8] Method according to claim 7, wherein the first controller remains in the reduced-power operating state until the board manager (108) indicates otherwise. [9] A method according to any of the preceding claims, further comprising: Transmitting the operating state information from the board manager (108) to a first of the controllers (107) in response to a dynamic event on the processor (102) assigned to the first controller, wherein the operating state information indicates that the dynamic event has occurred on the processor (102), and Prevent the voltage regulator (106) controlled by the first controller from entering a reduced power state in response to the first controller receiving operating state information. [10] A method according to any of the preceding claims, wherein the system board (100) is arranged in a frame (300) which further comprises several additional system boards (100) and a frame manager (302) configured to manage resources of the frame (300), each of the additional system boards (100) comprising several processors (102), memory assigned to each of the processors (102), several voltage regulators (106) configured to regulate voltages applied to the processors (102) and memory, and the board manager (108) according to claim 1, which serves to manage resources of the additional system boards (100), the method further comprising: Transmitting an operating status information from each of the board managers (108) to the rack manager (302), wherein the operating status information transmitted by each of the board managers (108) specifies a computational load for the corresponding system board; Prioritizing the use of the system boards (100) using the rack manager (302) based on the operating status information transmitted by the board managers (108) and Routing incoming rack data to the system boards (100) based on prioritized usage, such that the incoming rack data is first routed to the system boards (100) whose operating state information indicates a higher efficiency, and subsequently routed to the system boards (100) whose operating state information indicates a lower efficiency only if additional processing resources are needed to process the incoming rack data. [11] The method of claim 10, further comprising: Adjusting the temperature and airflow in the racks (300) based on the operating status information transmitted by the board managers (108). [12] Method according to claim 10 or 11, wherein the rack (300) is arranged in a data center (400) which further comprises several additional racks (300) and a data center manager (402) configured to manage resources of the data center (400), each of the additional racks comprising the rack manager (302) according to claim 10 for managing resources of the additional racks, the method further comprising: Transmitting operational status information from each of the rack managers (302) to the data center manager (402), wherein the operational status information transmitted by each of the rack managers (302) indicates a compute load for the corresponding rack; Prioritizing rack usage (300) using the data center manager (402) based on operational status information transmitted by the rack managers (302) and Route incoming data center data to racks (300) based on prioritized usage, such that incoming data center data is first routed to racks (300) whose operational status information indicates higher efficiency, and subsequently routed to racks (300) whose operational status information indicates lower efficiency only if additional processing resources are needed to process the incoming data center data. [13] The method of claim 12, further comprising: Adjusting the temperature and airflow in the data center (400) based on the operational status information transmitted by the rack managers (302). [14] System board which features: multiple processors (102); memory allocated to each of the processors (102); several voltage regulators (106) designed to regulate voltages applied to the processors (102) and memory, and a circuit board manager (108) who is trained to: to transmit operating status information to controllers (107) of the voltage regulators (106) independently of the processors (102), which also communicate data with the controllers (107), wherein the operating status information received by each controller (107) specifies a computational load for the processor (102) that is controlled by the voltage regulator (106) that is controlled by that controller (107), to control the voltage regulators (106) using the respective controllers based on the operating state information in order to set the power limit of the voltage regulators (106) according to the processing load specified by the operating state information transmitted by the board manager (108) to the controllers (107) for each processor (102), and to receive telemetry information from the voltage regulators (106), wherein the telemetry information specifies an efficiency of the voltage regulators (106) for different power modes of the respective processors (102), and to generate an efficiency profile based on the telemetry information. [15] System board (100) according to claim 14, wherein the board manager (108) is further configured to: to prioritize the use of the processors (102) based on the efficiency profile for the different performance modes, and to direct incoming board data to the processors (102) based on prioritized usage, such that the incoming board data is first directed to the processors (102) whose voltage regulators (106) are more efficient, and subsequently directed to the processors (102) whose voltage regulators (106) are less efficient only when additional processing resources are needed to process the incoming board data. [16] System board (100) according to claim 15, wherein the telemetry information has an input power of the voltage regulators (106), and wherein the board manager (108) is configured to: to generate a profile of the input power of each voltage regulator (106) as a function of a computing level of the respective processors (102) for the different power modes and to direct the incoming board data to the processors (102) based on the profiles, such that the incoming board data is first directed to the processors (102) whose voltage regulators (106) have a lower input power-to-computing level profile, and is then only directed to the processors (102) whose voltage regulators (106) have a higher input power-to-computing level profile if additional processing resources are needed to process the incoming board data. [17] System board (100) according to one of claims 14 to 16, wherein the board manager (108) is configured to: to proactively transmit an operating state information to a first of the controllers (107) before the processor (102) assigned to the first controller enters a restricted power range, wherein the proactively transmitted operating state information indicates that the processor (102) assigned to the first controller is expected to eventually enter the restricted power range and remain in the restricted power range for a specified period of time; to determine a reduced power operating state for the voltage regulator (106) controlled by the first controller based on the proactively transmitted operating state information and to force the voltage regulator (106) controlled by the first controller to operate in the reduced power operating state. [18] System board (100) according to claim 17, wherein the board manager (108) is configured to: to preventively force the voltage regulator (106) controlled by the first controller to leave the reduced-power operating state before the processor (102) associated with the first controller issues an instruction to the voltage regulator (106) indicating that the voltage regulator (106) should leave the reduced-power operating state. [19] System board (100) according to one of claims 14 to 18, wherein the board manager (108) is configured to: to transmit the operating state information to a first of the controllers (107) after the processor (102) assigned to the first controller has entered a restricted power range, wherein the operating state information indicates that the processor (102) assigned to the first controller has entered the restricted power range and will remain in the restricted power range for a specified period of time; to determine a reduced power operating state for the voltage regulator (106) controlled by the first controller based on the operating state information and to force the voltage regulator (106) controlled by the first controller to operate in the reduced power operating state. [20] System board (100) according to one of claims 14 to 19, wherein the board manager (108) is configured to: to transmit an operating state information to a first of the controllers (107) in response to a dynamic event on the processor (102) assigned to the first controller, wherein the operating state information indicates that a dynamic event has occurred on the processor (102), and to prevent the voltage regulator (106) controlled by the first controller from entering a reduced power state in response to receiving operating state information at the first controller. [21] Data center (400), which features: several racks (300), each rack (300) having a rack manager (302) trained to manage resources of that rack (300); several system boards (100), each configured according to one of claims 14 to 20; and a data center manager (402) who is trained to manage data center resources (400). [22] Data center (400) according to claim 21, wherein: Each of the board managers (108) is trained to transmit an operating status information to the rack manager (302) assigned to this board manager (108), wherein the operating status information transmitted by each of the board managers (108) specifies a computational load for the system board (100) assigned to this board manager (108); each of the rack managers (302) is trained to prioritize the use of the system boards (100) assigned to this rack manager (302) based on the operational status information transmitted by the board managers (108) assigned to this rack manager (302), and Each of the rack managers (302) is trained to direct incoming rack data to the system boards (100) assigned to that rack manager (302) based on prioritized usage, such that the incoming rack data is first directed to the system boards (100) whose operating state information indicates a higher efficiency, and subsequently directed to the system boards (100) whose operating state information indicates a lower efficiency only if additional processing resources are needed to process the incoming rack data. [23] Data center (400) according to claim 22, wherein each of the rack managers (302) is configured to adjust a temperature and an airflow in the rack (300) assigned to this rack manager (302) on the basis of the operating status information transmitted by the board managers (108) assigned to this rack manager (302). [24] Data center (400) according to one of claims 21 to 23, wherein: Each of the rack managers (302) is trained to transmit an operational status information to the data center manager (402), wherein the operational status information transmitted by each of the rack managers (302) specifies a compute load for the rack (300) assigned to that rack manager (302); the data center manager (402) is trained to prioritize the use of the racks (300) based on the operational status information transmitted by the rack managers (302), and The data center manager (402) is trained to route incoming data center data to racks (300) based on prioritized usage, such that incoming data center data is first routed to racks (300) whose operational state information indicates higher efficiency, and subsequently routed to racks (300) whose operational state information indicates lower efficiency only when additional processing resources are needed to process the incoming data center data. [25] Data center (400) according to claim 24, wherein the data center manager (402) is configured to adjust a temperature and airflow in the data center (400) based on the operating status information transmitted by the rack managers (302).

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