PARALLELIZATION METHOD AND PARALLELIZATION TOOL

Abstract

Parallelization methods for parallelizing a single program with a multitude of parallelizable processes (T1 to T14) for a single-core microcomputer, in the form of a first and a second parallelized process of the parallelized program for a multi-core microcomputer, (A.1) wherein the single program of the single-core microcomputer comprises a first, a second and a third processing block (T1, T8, T3), wherein the second processing block (T8) is to be processed by the single-core microcomputer after the first processing block (T1) and before the third processing block (T3), (A.2) wherein a first and a second process of the parallelized program are each assigned to different cores (21c, 21d) of the multi-core microcomputer for execution, (A.3) wherein the first process of the parallelized program is configured to execute the first processing block (T1) before the third processing block (T3), (A.4) wherein the second process of the parallelized program is configured to execute the second processing block (T8), (A.5) where a first state flag (A1) can be written by the first process of the parallelized program and read by the second process of the parallelized program, (A.6) wherein a second state flag (B8) can be written by the second process of the parallelized program and read by the first process of the parallelized program, wherein the parallelization procedure comprises the following steps: (A.7) Inserting into the first process of the parallelized program a storage processing step (F1) that causes the first process, after execution of the first processing block (T1), to set the first state flag (A1) that is unset at that time, (A.8) Inserting into the first process of the parallelized program a waiting processing step (W1) which causes the first state flag (A1), which may have been cleared in the meantime (tm12) by a random disturbance, to be set again in a waiting loop before the execution of the third processing block (T3) following the processing of the first processing block (T1), then checking whether the second state flag (B8) is set, and, if the check shows that the second state flag (B8) is set (tm16), exiting the waiting loop; (A.9) Inserting into the second process of the parallelized program a waiting processing step (W6) which causes a check to be performed in a wait loop before the execution of the second processing block (T8) to see if the first state flag (A1) is not set, and, if the check shows that the first state flag (A1) is set, to exit the wait loop. (A.10) Inserting into the second process of the parallelized program a storage processing step (F5) that causes the second state flag (B8), which is unset at that time, to be set after the execution of the second processing block (T8).

Description

[0001] The present invention relates to a parallelization method and a parallelization tool for generating a program for a multi-core microcomputer from a program for a single-core microcomputer.

[0002] Until now, as an example of a parallelization method for generating the program for the multi-core microcomputer from the program for the single-core microcomputer, there is a parallelization compilation method disclosed in JP 2015 - 1 807 A.

[0003] In the parallelization compilation method, after a sequential program of an embedded system, which is to be executed by a single-processor system, is divided into several macrotasks, the macrotasks that have a control dependency are combined into a single macrotask. The parallelization compilation method then extracts parallelizable macrotasks based on data dependency, and static scheduling is performed to generate a parallel program.

[0004] Furthermore, in the parallelization method, it is conceivable to assign a normal process to each core and insert a synchronization process to maintain the order of operations after parallelization has been analyzed. The synchronization process includes a state setting process for setting a variable indicating that the normal process has ended, and a wait process for waiting for the variable to be set in another core and transitioning to the normal process of the respective core.

[0005] However, it is conceivable that the variable is inadvertently changed due to noise. If the variable is changed for this reason, a problem arises that the waiting process continues into a deadlock state, in which the normal process cannot be executed on at least one core in the multi-core microcomputer.

[0006] It is an object of the present invention to provide a parallelization method and a parallelization tool capable of accelerating recovery from a deadlock. This object is achieved by a parallelization method and a parallelization tool having the features of the independent claims. The dependent claims are directed to advantageous developments of the invention.

[0007] According to a first aspect of the present invention, a parallelization method generates a parallelized parallel program for a multi-core microcomputer having a plurality of cores from a plurality of parallelizable processes in a single program for a single-core microcomputer having one core. The plurality of processes includes a preceding process to be executed early and a following process to be executed after the preceding process is completed. The preceding process and the following process are each assigned to different cores.The parallelization method includes: inserting a storage process having a completion state into the parallel program to maintain an execution order of the different cores when the preceding process is completed; inserting a wait process for waiting for the completion state to be saved and switching to execution of the following process under a condition that the completion state is saved into the parallel program to maintain the execution order of the different cores; and inserting a re-storage process (a re-storage process) for controlling the core that executed the storage process to execute the storage process again when another process is executed after the preceding process is completed into the parallel program.

[0008] As described above, according to the present invention, the saving process of the completion state is inserted into the parallel program when the preceding process has been executed, and the waiting process for transitioning to the execution of the following process under a condition where the completion state has been saved is inserted into the parallel program. Therefore, the present invention can generate the parallel program that can maintain the execution order of the preceding process and the following process assigned to the different cores.

[0009] Furthermore, according to the present invention, because the re-storage process for re-executing the storage process is incorporated into the parallel program, the parallel program that can save the termination state can be re-provisioned even if the termination state has inadvertently disappeared. Therefore, according to the present invention, when the termination state has inadvertently disappeared into a deadlock that cannot transition to the execution of the next process, the parallel program that can quickly return from the deadlock can be generated.

[0010] According to a second aspect of the present invention, a parallelization tool generates a parallelized parallel program for a multi-core microcomputer having a plurality of cores from a plurality of parallelizable processes in a single program for a single-core microcomputer having one core. The plurality of processes includes a preceding process to be executed early and a following process to be executed after the preceding process is completed. The preceding process and the following process are each assigned to different cores.The parallelization tool includes: inserting a save process having a completion state into the parallel program to maintain an execution order of the different cores when the preceding process is completed; inserting a wait process for waiting for the completion state to be saved and switching to execution of the following process under a condition that the completion state is saved into the parallel program to maintain the execution order of the different cores; and inserting a re-save process for controlling the core that executed the save process to re-execute the save process when another process is executed after the preceding process is completed into the parallel program.

[0011] As a result, as in the above embodiment, the parallel program which can quickly return from the deadlock can be generated.

[0012] According to a third aspect of the present invention, a vehicle-mounted device comprises: a multi-core microcomputer that operates on a parallel program. The parallel program is parallelized for the multi-core computer having a plurality of cores from a plurality of parallelizable processes into a single program for a single-core microcomputer having one core. The plurality of processes includes a preceding process to be executed early and a following process to be executed after the preceding process is completed. The preceding process and the following process are respectively assigned to different cores.The multi-core microcomputer executes: a storage process for storing a completion state to maintain an execution order of the different cores when the preceding process is executed; a wait process for waiting for the completion state to be stored and switching to execution of the following process under a condition that the completion state is stored to maintain the execution order of the different cores; and a re-storage process for re-executing the storage process to be executed by the core that executed the storage process when another process is executed after the preceding process is completed.

[0013] With the above configuration, the execution order of the various cores can be maintained because the vehicle-mounted device saves the completion state when the previous process has been executed and proceeds to the execution of the following process under the condition that the completion state has been saved after waiting for the completion state to be saved. Furthermore, even in the case where the completion state has inadvertently disappeared, the completion state can be saved again because the vehicle-mounted device again executes the saving process to be performed by the core that executed the saving process when another process executed after the previous process has finished.For this reason, the vehicle-mounted device can quickly return from the deadlock even if the termination state has inadvertently disappeared into the deadlock, which cannot proceed to the execution of the following process.

[0014] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings: Fig. 1 is a block diagram illustrating a general configuration of a parallelization tool according to an embodiment; Fig. 2 is a block diagram illustrating a general configuration of a vehicle-mounted device according to the embodiment; Fig. 3 is a flowchart illustrating a processing operation of a computer according to the embodiment; Fig. 4 is a diagram illustrating a processing execution order and synchronization logic according to the embodiment; Fig. 5 is a flowchart illustrating a state setting process of the vehicle-mounted device according to the embodiment; Fig. 6 is a flowchart illustrating a waiting process of the vehicle-mounted device according to the embodiment; Fig. 7 is a flowchart illustrating a processing operation in a normal state of the vehicle-mounted device according to the embodiment; Fig. 8 is a flowchart illustrating the processing operation in a noise-generated state of the vehicle-mounted device according to the embodiment; Fig. 9 is a flowchart illustrating a processing operation in a noise-generated state of a vehicle-mounted device according to a comparative example; Fig. 10 is a flowchart illustrating a processing operation of a vehicle-mounted device according to a modification 1; and Fig. 11 is a diagram illustrating a processing execution order and synchronization logic according to a modification 2.

[0015] Hereinafter, several aspects for embodying the present invention will be described with reference to the drawings. In the respective embodiments, a part corresponding to a matter described in a previous embodiment may be assigned the same reference numeral, and redundant explanation for the part may be omitted. When only a part of an embodiment is described in the respective embodiments, another previous embodiment may be applied to the other parts of the embodiment.

[0016] The present embodiment shows an example of generating a parallel program 21a1 in which a plurality of parallelizable processes (T1 to T14) of a single program for a single-core microcomputer having one core are parallelized for a multi-core microcomputer having a first core 21c and a second core 21d. In generating the parallel program 21a1, as disclosed in JP-A-2015-1807, a process of analyzing a single program and assigning a plurality of processes to the first core 21c and the second core 21d is performed. Reference is made to JP-A-2015-1807 in this regard.

[0017] Hereinafter, the processes are also called “process blocks.” In the present embodiment, as shown in Fig. 4, a first processing block (process block) T1 to a fourteenth processing block (process block) T14 are employed as the plurality of processing blocks. The plurality of processing blocks T1 to T14 include a preceding process to be executed earlier in the execution order and a following process to be executed after the preceding process is executed, which are assigned to different cores. The following process is a process affected by the preceding process, which is a process that uses data whose contents are expected to be updated in the preceding process. For example, in the first processing block T1 and the eighth processing block T8, the first processing block T1 is the preceding process, and the eighth processing block T8 is the following process.In the third processing block T3 and the eighth processing block T8, the eighth processing block T8 is the preceding process and the third processing block T3 is the following process.

[0018] First, embodiments of a computer 10 and a vehicle-mounted device 20 will be described. The computer 10 corresponds to a parallelization tool that executes a parallelization procedure. As shown in Fig. As shown in Figure 1, the computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, and a reading unit 17. The computer 10 can read memory contents stored in a storage medium 18. HDD is an abbreviation for hard disk drive. CPU is an abbreviation for central processing unit. ROM is an abbreviation for read-only memory. RAM is an abbreviation for random access memory. For the configurations of the computer 10 and the storage medium 18, see a workstation computer 100 and a storage medium 180 disclosed in JP-A-2015-1807.

[0019] An automatic parallelization compiler 1 corresponds to a parallelization method. In other words, the automatic parallelization compiler 1 is a program in which the parallelization method is described. The automatic parallelization compiler 1 includes a procedure of inserting a state setting process, a procedure of inserting a wait process, and a procedure of inserting a state resetting process, in addition to the disclosure of JP-A-2015-1807.

[0020] The procedure of inserting the state setting processes is a procedure of inserting state setting processes F1 to F9 for saving a termination state into the parallel program 21a1 when the previous process has been executed in order to maintain an execution order of the cores 21c and 21d. In other words, the procedure of inserting the state setting processes is to allow the cores 21c and 21d to execute the state setting processes when the cores 21c and 21d have executed the previous process.

[0021] In this example, a method for storing the completion state uses state flags A1, A3, A4, A13, B1, B10, B11, B12, and B14. Each of the state flags indicates the completion state when the state flag is set to 1, and indicates no completion state when the state flag is not set to 1, that is, when the state flag is set to 0. For this reason, the vehicle-mounted device 20 is configured to set the state flags according to the respective preceding processes. The procedure of inserting the state setting processes corresponds to a storage process insertion procedure. The state setting process corresponds to a storage process of the completion state.

[0022] The procedure of inserting the wait processes is a procedure of inserting wait processes W1 to W9 for waiting for the status flag to be set and for transitioning to the execution of the next process under a condition that the status flag has been set into the parallel program 21a1 in order to maintain the execution order of the cores 21c and 21d. Therefore, the procedure of inserting the wait processes W1 to W9 is a procedure of inserting the wait processes W1 to W9 for waiting for the previous process to complete and for transitioning to the execution of the next process under a condition that the previous process has been completed.In other words, the procedure for inserting the wait processes W1 to W9 is to wait for the status flag to be set and to proceed to the execution of the next process under the condition that the status flag has been set, with respect to the cores 21c and 21d. The procedure of inserting the wait processes W1 to W9 corresponds to a wait process insertion procedure.

[0023] The state re-setting process insertion procedure is a procedure for inserting the state re-setting processes W1 to W9 into the parallel program 21a1 to allow the cores 21c and 21d that have executed the state setting process to re-execute the state setting process when another processing block executed after the previous process has been completed. In other words, the state re-setting process insertion procedure is for allowing the cores 21c and 21d that have executed the state setting process to re-execute the state setting process when another processing block executed after the previous process has been completed. The state re-setting process insertion procedure corresponds to a storage process re-insertion procedure.

[0024] In the present embodiment, a synchronization process for terminating the processes of all cores at the same time uses the automatic parallelization compiler 1, which has a procedure for inserting the state setting process and the waiting process at an end of the parallel program 21a1. As an example, as shown in Fig. As shown in Figure 4, the automatic parallelization compiler 1 includes a procedure for inserting the state setting process F4 and the waiting process W5, and the state setting process F9 and the waiting process W9. With the above configuration, the automatic parallelization compiler 1 can generate the parallel program 21a1 that enables the first core 21c and the second core 21d to complete processing at the same time.

[0025] The present embodiment shows an example in which the wait processes W1 to W9 are executed after the cores 21c and 21d that executed the state setting processes have completed other process blocks. Furthermore, the present embodiment uses the procedure for inserting the re-state setting processes to insert the re-state setting processes to be executed during the wait processes W1 to W9 by the cores 21c and 21d that executed the state setting processes. Thus, in the present embodiment, the same symbols W1 to W9 are assigned to the wait processes and the re-state setting processes. However, the present invention is not limited to this configuration.The parallelization method may be the procedure for inserting the re-state setting processes for inserting the re-state setting processes to be executed after the state setting processes F1 to F9.

[0026] As in Fig. As shown in FIG. 2, the vehicle-mounted device 20 includes a multi-core processor 21, a ROM 21a, a RAM 21b, the first core 21c, the second core 21d, a communication unit 22, a sensor unit 23, and an input / output port 24. The vehicle-mounted device 20 can be applied to an internal combustion engine control device or a hybrid control device mounted in an automobile. In this example, an example in which the vehicle-mounted device 20 is applied to the internal combustion engine control device is used. In this case, the parallel program 21a1 can be regarded as an automobile control program such as an internal combustion engine controller. The multi-core processor corresponds to a multi-core microcomputer. The cores may also be called "processor elements."

[0027] Regarding the RAM 21b, the communication unit 22, the sensor unit 23, and the input / output port 24, reference is made to a RAM 420, a communication unit 430, a sensor unit 450, and an input / output port 460 disclosed in JP-A-2015-1807.

[0028] The parallel program 21a1 generated by the parallelization process is stored in the ROM 21a. The first core 21c and the second core 21d execute the parallel program 21a1 to control an internal combustion engine.

[0029] Next, a processing operation of the computer 10 with respect to Fig. 3 and Fig. 4. When an execution instruction for the insertion process is given by the input device 16, the CPU 13 executes a Fig. 3. The CPU 13 executes the automatic parallelization compiler 1 to generate the parallel program 21a1 from a single program. The CPU 13 executes the following steps S11 to S13 in generating the parallel program 21a1 according to a procedure disclosed in JP-A-2015-1807.

[0030] In step S11, a state setting process insertion step is performed (storage process insertion step). The CPU 13 executes the procedure of inserting the state setting process in the automatic parallelization compiler 1. In other words, the CPU 13 inserts the state setting processes F1 to F9 into the parallel program 21a1. In the present embodiment, as shown in Fig. 4, for example, the state setting process F1 is inserted after the first processing block T1, and the state setting process F8 is inserted after the eighth processing block T8. As described above, step S11 is a process for executing the procedure for inserting the state setting process and is therefore also called the "storage process insertion procedure."

[0031] In step S12, a wait process insertion step is performed (wait process insertion step). The CPU 13 executes the wait process insertion procedure in the automatic parallelization compiler 1. In other words, the CPU 13 inserts the wait processes W1 to W9 into the parallel program 21a1. In the present embodiment, as shown in Fig. 4, for example, the wait process W6 is inserted before the eighth processing block T8, and the wait process W1 is inserted before the third processing block T3. As described above, step S12 is a process for executing the wait process insertion procedure and is therefore also called the "wait process insertion procedure."

[0032] In step S13, a state resetting process insertion step is performed (re-storage process insertion step). The CPU 13 executes the state resetting process insertion procedure in the automatic parallelization compiler 1. In other words, the CPU 13 inserts the state resetting process into the parallel program 21a1. As described above, step S13 is a process for executing the state resetting process insertion procedure and is therefore also called the "re-storage process insertion procedure."

[0033] In the present embodiment, as the synchronization processing for completing the processing of all cores at the same time, the computer 10 inserts the state setting process and the waiting process at the end of the parallel program 21a1. As an example, inserts, as shown in Fig. As shown in Figure 4, the computer 10 initiates the state setting process F4 and the waiting process W5, and the state setting process F9 and the waiting process W9. With the above process, the computer 10 can generate the parallel program 21a1 that enables the first core 21c and the second core 21d to complete processing at the same time.

[0034] In the present embodiment, an example of inserting the re-state setting process to be executed during the waiting process is used. For this reason, in the present embodiment, as shown in Fig. 4, for example, the waiting process W6, which includes the re-state setting process, is inserted before the eighth processing block T8, and the waiting process W1, which includes the re-state setting process, is inserted before the third processing block T3. In the present embodiment, for example, as with "do{A1=1}while(B8=0)" ("tue{A1 =1}solange(B8=0)") before the third processing block in Fig. 4, the wait process including the state resetting process is expressed by a do-while statement. In this case, the first core 21c sets the state flag A1 to 1 after waiting for a state flag B8 to be set to 1 during a state in which the state flag B8 is 0, and proceeds to the execution of the third processing block T3 under a condition that the state flag B8 is set to 1. As described above, because the computer 10 inserts the state resetting process to be executed during the wait processes W1 to W9 into the parallel program 21a1, the computer 10 can generate the parallel program 21a1, which enables an overhead caused by the state resetting process to be reduced. The parallelization method according to the present embodiment can achieve the same advantages.

[0035] The present invention is not limited to the above embodiment. The computer 10 may insert the re-state setting process to be executed after the state setting processes F1 to F9.

[0036] As described above, in the present embodiment, the computer 10 executes step S13 in addition to the parallelization method disclosed in JP-A-2015-1807, thereby generating the parallel program 21a1. However, the present invention is not limited to this configuration. A worker may execute step S13 in addition to the parallelization method disclosed in JP-A-2015-1807, thereby generating the parallel program 21a1.

[0037] An example of the parallel program 21a1 generated as described above is shown in Fig. 4. In this example, the first processing block T1 to the sixth processing block T6 and the thirteenth processing block T13 are assigned to the first core 21c, and the seventh processing block T7 to the twelfth processing block T12 and the fourteenth processing block T14 are assigned to the second core 21d. Furthermore, the parallel program 21a1 inserts the state setting processes F1 and F5 after the first processing block T1 and the eighth processing block T8. Furthermore, the wait processes W1 and W6, including the state resetting process, are inserted before the third processing block T3 and the eighth processing block T8.

[0038] As described above, the computer 10 inserts the state setting process into the parallel program 21a1 when the previous process has been executed, and inserts the wait process for transitioning to the execution of the following process under the condition that 1 has been stored in the state flag into the parallel program 21a1. Therefore, the computer 10 can generate the parallel program 21a1 that maintains the execution order of the previous process and the following process assigned to the first core 21c and the second core 21d.

[0039] Furthermore, according to the present invention, even if a value of the status flag has inadvertently disappeared, the computer 10 can provide the parallel program that can again set the status flag to 1 because the computer 10 inserts the re-status setting process for re-executing the status setting process into the parallel program 21a1. For this reason, if the value of the status flag has inadvertently disappeared into the deadlock, which cannot proceed to the execution of the following process, the computer 10 can generate the parallel program 21a1 that can quickly return from the deadlock.

[0040] Furthermore, because the computer 10 inserts the state resetting process into the parallel program 21a1 to be executed during the wait process, the computer 10 can generate the parallel program, which makes it possible to reduce the overhead caused by the state resetting process. The automatic parallelization compiler 1 can achieve the same advantages as those of the computer 10.

[0041] Next, the processing operation of the first core 21c and the second core 21d will be described with reference to Fig. 5 to 9 in addition to Fig. 4 are described.

[0042] The first core 21c and the second core 21d execute the processes assigned to the respective cores in the parallel program 21a1 of Fig. 4 in order from the top while executing the processes in synchronization to maintain the order of the respective cores. In other words, the first core 21c executes the processes in order from the first processing block T1 in response to a processing execution trigger. On the other hand, the second core 21d executes the processes in order from the seventh processing block T7 in response to the processing execution trigger.

[0043] As in Fig. As shown in Figure 5, the first core 21c and the second core 21d set the status flag when executing the status setting process after the processing blocks have been executed (step S21). In other words, the first core 21c and the second core 21d set the status flag to 1 to record that the processing blocks have been executed. As shown in Fig. 4 and Fig. For example, as shown in FIG. 7, the first core 21c executes the state setting process F1 at time tm1 and sets the state flag A1 to 1 when the first processing block T1 has been executed. When the eighth processing block T8 has been executed, the second core 21d executes the state setting process F5 at time tm4 and sets the state flag B8 to 1. The respective processing blocks and the respective state flags have a one-to-one correspondence relationship. Thus, the first core 21c and the second core 21d store which of the plurality of processing blocks T1 to T14 have been executed.

[0044] The state setting processes F1 to F9 are processes for maintaining the execution order of the first core 21c and the second core 21d. In other words, the state setting processes F1 to F9 are blocks for recording that the processing blocks have been executed, for synchronization between the first core 21c and the second core 21d.

[0045] Thus, the first core 21c and the second core 21d store the completion state of the previous process when the previous process has been executed, for the purpose of maintaining the execution order between the first core 21c and the second core 21d. The first core 21c executes the state setting process so that the next process assigned to the second core 21d is executed after the previous process assigned to the first core 21d. In addition, the first core 21c executes the state setting process to notify the second core 21d to which the next process has been assigned of the fact that the previous process assigned to the first core 21c has been executed. For example, the first core 21c executes the state setting process F1 so that the eighth processing block T8 assigned to the second core 21d is executed after the first processing block T1 assigned to the first core 21c.

[0046] Similarly, the second core 21d executes the state setting process so that the next process assigned to the first core 21c is executed after the previous process assigned to the second core 21d. Furthermore, the second core 21d executes the state setting process to notify the first core 21c, to which the next process has been assigned, that the previous process assigned to the second core 21d has been executed. For example, the second core 21d executes the state setting process F5 so that the third processing block T3 assigned to the first core 21c is executed after the eighth processing block T8 assigned to the second core 21d.

[0047] The first core 21c and the second core 21d introduce a Fig. 6 when executing the wait process. In step S32, it is determined whether the status flag of the previous process is 0 or not. If it is determined that the status flag of the previous process is 0, the first core 21c and the second core 21d proceed to step S31, and if it is determined that the status flag of the previous process is 1, the first core 21c and the second core 21d terminate the processing of Fig. 6.

[0048] If it is determined that the status flag of the previous process is 1, the first core 21c and the second core 21d proceed to the execution of a next processing block. In other words, the first core 21c and the second core 21d wait for the status flag of the previous process to become 1 and proceed to the execution of the following process. As shown in Fig. 4 and Fig. 7, for example, in the wait process W6, the second core 21d proceeds to the execution of the eighth processing block T8 when it is determined that the status flag A1 is set to 1 at a time tm2. In the wait process W1, when it is determined from a time tm3 whether the status flag B8 is 0 or not and it is determined that the status flag B8 is set to 1 at a time tm4, the first core 21c proceeds to the execution of the third processing block T3.

[0049] Confirming whether the status flag of the preceding process is 1 or not, that is, whether the counter-core processing block has been executed, is also called "polling" below. Waiting for the execution of the preceding process to complete and transitioning to the execution of the following process is also called "waiting." The process of confirming whether the counter-core processing block has been executed can be performed by a method other than polling if the status flag is periodically reset.

[0050] In step S31, the own state flag is reset. The first core 21c and the second core 21d again set their own state flags to 1 and proceed to step S32. In this way, during a period in which the flag of the previous process is 0, the first core 21c and the second core 21d wait for the state flag to be set to 1 and set the state flags set by the respective cores to 1. In the waiting process W1, for example, the first core 21c sets the state flag A1 to 1 between times tm3 and tm4 where the state flag B8 is 0.

[0051] The status flag A1 in the example of Fig. 7 is maintained at 1 without becoming 0 after being set to 1 at time tm1. In other words, Fig. 7 shows the state flag A1 in a normal state. In this way, when the state flag is normal, the first core 21c and the second core 21d again set the state flag set to 1 to 1 in step S31.

[0052] However, the value of the state flag may be changed due to noise. In other words, the termination state of the state flag, ie, 1, may have inadvertently disappeared to 0. This phenomenon will be explained with reference to Fig. 9. A parallel program in a comparative example is identical to that of the present embodiment except for no insertion of the process in step S31.

[0053] A first core executing the parallel program in the comparative example sets the state flag A1 to 1 at a time tm21. However, the 1 of the state flag A1 inadvertently disappears to 0 due to noise at a time tm22.

[0054] For this reason, the second core cannot execute the eighth processing block T8 even if polling is started at time tm23 because the state flag A1 is maintained at 0. In other words, in the second core, polling continues into a deadlock state. Furthermore, in the comparative example, the state flag B8 is not set to 1 because the second core cannot execute the eighth processing block T8. For this reason, in the first core, the third processing block T3 cannot be executed even if polling is started at time tm24 because the state flag B8 is maintained at 0. In other words, in the first core, polling continues into the deadlock state.

[0055] The processing operation of the first core 21c and the second core 21d when the value of the status flag has changed unintentionally is described with reference to Fig. 8. The parallel program 21a1 has wait processes W1 to W9, including a state resetting process. The first core 21c and the second core 21d wait for the state flag to be set to 1 during a period in which the state flag of the previous process is 0, and set the state flags set by the respective cores to 1 to execute the parallel program as described above.

[0056] The first core 21c sets the state flag A1 to 1 at a time tm11. However, the 1 of the state flag A1 inadvertently disappears to 0 at a time tm12 due to noise. On the other hand, in the second core 21d, polling is started at a time tm13.

[0057] In this case, in the first core 21c, polling is started at time tm14. The first core 21c sets the state flag A1 to 1 after time tm15 because the state flag B8 is 0. As a result, the first core 21c can restore the state flag A1, which has become 0 due to noise, to 1. Therefore, the second core 21d can proceed to the execution of the eighth processing block T8 after time tm15.

[0058] As described above, in the vehicle-mounted device 20, the first core 21c and the second core 21d set the status flags to 1 when the previous process has been executed, wait for the status flags to be set to 1, and proceed to the execution of the following process under a condition where the status flag has been set to 1. For this reason, the vehicle-mounted device 20 can maintain the execution order of the first core 21c and the second core 21d.

[0059] Furthermore, the first core 21c and the second core 21d in the vehicle-mounted device 20 again execute the state setting process, which is a process to be performed by the core that executed the state setting process after executing another processing block executed after the previous process. For this reason, the first core 21c and the second core 21d in the vehicle-mounted device 20 can again set the state flags to 1 even if the value of the state flags has inadvertently disappeared. For this reason, the vehicle-mounted device 20 can quickly recover from the deadlock even if the value of the state flag has inadvertently disappeared into the deadlock, which cannot proceed to the execution of the following process.

[0060] Because the first core 21c and the second core 21d in the vehicle-mounted device 20 execute the wait processes W1 to W9 including the state resetting process, an overhead caused by the state resetting process can be reduced.

[0061] In other words, the overhead caused by the state resetting process can be reduced because the first core 21c and the second core 21d in the vehicle-mounted device 20 perform the state resetting process while waiting for the execution of the previous process, that is, while actual calculation in the engine controller is not performed.

[0062] The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-mentioned embodiment and can be variously modified without departing from the spirit of the present invention. Modifications 1 and 2 of the embodiment according to the present invention will be described below. The above embodiment and modifications 1 and 2 can be implemented independently, but can also be implemented in an appropriate combination. The present invention is not limited to the combination described in the embodiment, but can be realized by various combinations. (Modification 1)

[0063] An automatic parallelization compiler 1 according to Modification 1 may include an abnormality detection process insertion procedure for inserting an abnormality detection process into a parallel program 21a1. A computer 10 according to Modification 1 may include an abnormality detection process insertion step for inserting the abnormality detection process into the parallel program 21a1. Thus, in Modification 1, a first core 21c and a second core 21d execute the abnormality detection process. The abnormality detection process corresponds to a detection process.

[0064] The abnormality determination process according to Modification 1 is a process for determining whether an abnormality occurs in a state flag, depending on whether the state flag is 0 or not, during a state resetting operation. In other words, the abnormality determination process compares the value of the state flag during the state resetting operation with the value of the state flag before the state resetting operation, and determines an abnormality during the state resetting operation when both of these values ​​are different from each other. The abnormality determination process is different from the abnormality determination process in the above embodiment. In this example, the same symbols as those in the above embodiment are used for descriptive purposes.

[0065] The first core 21c and the second core 21d in modification 1 introduce a Fig. 10 when they execute a wait process.

[0066] In step S40, it is determined whether any state flag is 0 or not. If it is determined that any state flag is 0, the first core 21c and the second core 21d proceed to step S41, and if it is determined that no state flag is 0, the first core 21c and the second core 21d proceed to step S42. For example, in the case of executing a wait process W2, if it is determined that any of the state flags A1, A3, and A4 is 0, the first core 21c proceeds to step S41. The state flags A1, A3, and A4 are set to 1 during the state resetting operation. Thus, if any of the state flags A1, A3, and A4 is 0, memory contents during the state resetting operation are different from memory contents before the state resetting operation.

[0067] Furthermore, the first core 21c proceeds to step S42 when it is determined that all of the status flags A1, A3, and A4 are 1. In the case of executing a wait process W1, the first core 21c determines whether the status flag A1 is 0 or not. Therefore, there are cases where the number of status flags determined in step S40 is one or more.

[0068] In step S41, an abnormality flag is set. The first core 21c and the second core 21d set the abnormality flag to 1 to record that the state flag is abnormal. The abnormality flag indicates an abnormal state when the abnormality flag is set to 1, and indicates no abnormal state when the abnormality flag is not set to 1, that is, set to 0.

[0069] Step S42 is the same as step S31 above. Step S43 is the same as step S32 above.

[0070] As described above, with the automatic parallelization compiler 1 and the computer 10 in modification 1, the parallel program that can determine whether the value of the status flag has disappeared accidentally or not can be generated because the determination process is incorporated into the parallel program 21a1. The first core 21c and the second core 21d in modification 1 can determine whether the value of the status flag has disappeared accidentally or not, that is, whether an abnormality occurs in the status flag or not.

[0071] Furthermore, in the automatic parallelization compiler 1 and the computer 10 in Modification 1, the parallel program that can record that the abnormality occurs in the condition flag can be generated because the process of setting the abnormality flag when the abnormality is detected is incorporated into the parallel program 21a1. Furthermore, in the first core 21c and the second core 21d in Modification 1, the abnormality occurrence can be recorded in the condition flag because the abnormality flag is set when the abnormality is detected. (Modification 2)

[0072] In Modification 2, contents of store processes R1 to R9, contents of a wait process, and contents of a re-store process are different from those in the above embodiment. Thus, an automatic parallelization compiler 1 according to Modification 2 includes procedures for inserting each of a store process, a wait process, and a re-store process in Modification 2 into a parallel program. In addition, a computer 10 includes steps for inserting each of the store process, the wait process, and the re-store process in Modification 2 into a parallel program. Further, a first core 21c and a second core 21d operate according to the parallel program having the store process, the wait process, and the re-store process in Modification 2.In this example, the same symbols as those in the above embodiment are used for descriptive purposes.

[0073] The storage processes R1 to R9 in the modification 2 store a completion state by increasing (incrementing) state values ​​A and B in a RAM when a previous process has been executed in order to maintain an execution order of the first core 21c and the second core 21d. As shown in Fig. 11, for example, the first core 21c increments the state value A in the storage process R1 when a first processing block T1 has been executed, and further increments the state value A in the storage process R2 when a third processing block T3 has been executed. For example, the second core 21d increments the state value B in the storage process R5 when an eighth processing block T8 has been executed, and further increments the state value B in the storage process R6 when a tenth processing block T10 has been executed. The first core 21c and the second core 21d write initial values ​​to the respective state values ​​A and B of the RAM before executing a first processing block. For example, the state values ​​A and B are 0 as initial values ​​and are updated to 1, 2, and 3 with each increment made.A method for updating the state values ​​A and B can be performed not by incrementing but by writing a value.

[0074] Waiting processes WR1 to WR9 in Modification 2 wait for the state values ​​A and B to be incremented, and proceed to the execution of subsequent processes, respectively, under the condition that the state values ​​A and B have been incremented to maintain an execution order of the first core 21c and the second core 21d. The re-store process in Modification 2 allows the first core 21c and the second core 21d, which have executed the store process, to re-execute the store process when another processing block executed after the previous process has ended. In the re-store process of Modification 2, a previous value is written as the state value when the store process is executed again. In this example, the waiting processes WR1 to WR9, which include the re-store process, are employed.

[0075] For example, the waiting process WR1 waits for Fig.11, the first core 21c waits for 1 to be written, and writes a previous value 1 as the state value A as long as the state value B is less than 1, and proceeds to the execution of the third processing block T3 under the condition that the state value B has become 1 or more. Similarly, in the wait process WR2, the first core 21c waits for 2 to be written, and writes a previous value 3 as the state value A as long as the state value B is less than 2, and proceeds to the execution of a fifth processing block T5 under the condition that the state value B has become 2 or more.Furthermore, in the waiting process WR7, the second core 21d waits for 2 to be written, and writes a previous value 1 as the state value B as long as the state value A is less than 2, and proceeds to the execution of the tenth processing block T10 under the condition that the state value A has become 2 or more.

[0076] The automatic parallelization compiler 1 according to Modification 2 may include an abnormality detection process insertion procedure for inserting an abnormality detection process into a parallel program 21a1. The computer 10 according to Modification 2 may include an abnormality detection process insertion step for inserting the abnormality detection process into the parallel program 21a1. Therefore, in Modification 2, the first core 21c and the second core 21d execute the abnormality detection process.

[0077] The abnormality detection process according to Modification 2 is a process for detecting whether or not an abnormality occurs in the state value, depending on whether or not the state value during the re-storage process is the same as the state value before the re-storage process. For example, the first core 21c detects an abnormality when the state value A of a RAM 21b is not 3 when writing 3 as the state value A in the wait process WR3. The first core 21c sets the abnormality flag to 1 when the abnormality is detected.

[0078] In the present modification, as in the above embodiment, a synchronization process uses the automatic parallelization compiler 1, which has a procedure for inserting the state setting process and the wait process at one end of the parallel program 21a1. In the present modification, the computer 10, which inserts the state setting process and the wait process at one end of the parallel program 21a1, is used as the synchronization process. The synchronization process includes the storage process R4, the wait process WR5, the storage process R9, and the wait process WR9.

[0079] The automatic parallelization compiler 1 and the computer 10 according to the modification 2 can achieve the same advantages as those of the modification 1. The first core 21c and the second core 21d according to the modification 2 can achieve the same advantages as those of the modification 1.

[0080] It is noted that a flowchart or the processing of the flowchart in the present application includes sections (also referred to as steps), each of which is represented, for example, as S11. Furthermore, each section may be divided into multiple subsections, while multiple sections may be combined into a single section. Furthermore, each of the sections thus configured may also be referred to as a device, a module, or a means.

[0081] While the present invention has been described with reference to exemplary embodiments thereof, it should be understood that the invention is not limited to the exemplary embodiments and embodiments. The present invention is intended to cover various modifications and equivalent arrangements. Furthermore, in addition to the various combinations and embodiments, other combinations and embodiments including more, fewer, or only a single element are also within the spirit and scope of the present invention.

Claims

[1] Parallelization method for parallelizing from a single program with a plurality of parallelizable processes (T1 to T14) for a single-core microcomputer, in the form of a first and a second parallelized process of the parallelized program for a multi-core microcomputer, (A.1) wherein the single program of the single-core microcomputer comprises a first, a second and a third processing block (T1, T8, T3), wherein the second processing block (T8) is to be processed by the single-core microcomputer after the first processing block (T1) and before the third processing block (T3), (A.2) wherein a first and a second process of the parallelized program are respectively assigned to different cores (21c, 21d) of the multi-core microcomputer for execution, (A.3) wherein the first process of the parallelized program is configured to execute the first processing block (T1) before the third processing block (T3), (A.4) wherein the second process of the parallelized program is configured to execute the second processing block (T8), (A.5) wherein a first status flag (A1) can be written by the first process of the parallelized program and read by the second process of the parallelized program, (A.6) wherein a second status flag (B8) can be written by the second process of the parallelized program and read by the first process of the parallelized program, the parallelization method comprising the following steps: (A.7) Inserting into the first process of the parallelized program a processing step of storing (F1) which causes the first process, after execution of the first processing block (T1), to set the first status flag (A1) which is unset at that time, (A.8) Inserting into the first process of the parallelized program a processing step of waiting (W1) which causes, before the execution of the third processing block (T3) following the processing of the first processing block (T1), in a waiting loop the first status flag (A1), which could have been cleared in the meantime (tm12) by a random disturbance, to be set again, then checking whether the second status flag (B8) is set, and, if the check shows that the second status flag (B8) is set (tm16), exiting the waiting loop; (A.9) Inserting into the second process of the parallelized program a processing step of waiting (W6), which causes a check to be carried out in a waiting loop before the execution of the second processing block (T8) to determine whether the first status flag (A1) is not set, and if the check shows that the first status flag (A1) is set, the waiting loop is exited, (A.10) Inserting into the second process of the parallelized program a processing step of storing (F5) which causes, after the execution of the second processing block (T8), the second status flag (B8), which is unset at that time, to be set. [2] The parallelization method according to claim 1, wherein the parallelization method is applied to an internal combustion engine control device or a hybrid control device mounted in an automobile, wherein control of the automobile is performed based on input and output from a sensor unit via an input / output port, [3] Parallelization tool for generating a parallel program starting from a single program with a plurality of parallelizable processes (T1 to T14) for a single-core microcomputer in the form of a first and a second parallelized process of the parallelized program for a multi-core microcomputer, wherein the parallelization tool is designed to carry out the method according to claim 1 or 2.

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