semiconductor chip

Abstract

Semiconductor chip (100) with a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material, wherein the semiconductor layer sequence (10) includes a p-type semiconductor region (4) and an n-type semiconductor region (2), and an active layer (3) arranged between the p-type semiconductor region (4) and the n-type semiconductor region (2), wherein - the n-type semiconductor region (2) comprises a superlattice structure (20) to improve current expansion, wherein the superlattice structure (20) has a periodic arrangement of semiconductor layers (21, 22, 23, 24), - a period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and one doped second semiconductor layer (22), wherein an electronic band gap E2 of the doped second semiconductor layer (22) is larger than an electronic band gap E1 of the undoped first semiconductor layer (21), and - the undoped first semiconductor layer (21) in the superlattice structure (20) is arranged between an undoped first intermediate layer (23) and an undoped second intermediate layer (24), and - the doped second semiconductor layer (22) is between 10 nm and 200 nm thick.

Description

[0001] The invention relates to a semiconductor chip, in particular a semiconductor chip based on a phosphide compound semiconductor material or an arsenide compound semiconductor material.

[0002] In electronic or optoelectronic semiconductor chips, such as light-emitting diode chips, a relatively thick current expansion layer made of a semiconductor material with good electrical conductivity is usually placed between the electrical contact and the light-emitting semiconductor layer sequence in order to achieve the most uniform current flow possible through the active layer.

[0003] It has been found that while relatively thick AlGaAs current expansion layers achieve good current expansion, they also absorb a significant proportion of the emitted radiation. The absorption of a thick current expansion layer is particularly noticeable when the emitted radiation is short-wave and / or the aluminum content in the current expansion layer is low.

[0004] The publication US 2014 / 0 077 157 A1 describes a nitride semiconductor device.

[0005] Publication DE 10 2008 032 318 A1 deals with an optoelectronic semiconductor chip.

[0006] The invention is based on the objective of providing a semiconductor chip that is characterized by improved current expansion, particularly with comparatively low absorption in the current expansion layer.

[0007] This problem is solved by a semiconductor chip according to claim 1. Advantageous embodiments and further developments of the invention are the subject of the dependent claims.

[0008] According to at least one embodiment, the semiconductor chip comprises a semiconductor layer sequence based on a phosphide compound semiconductor material or on an arsenide compound semiconductor material. In this context, "based on a phosphide compound semiconductor material" means that one or more layers of the semiconductor layer sequence comprise a III-phosphide compound semiconductor material, in particular In x Al y Ga 1-x-y P with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1, preferably In 0,5 Al x Ga 0,5-x P with 0 ≤ x ≤ 0.5, or Al n Ga 1-n As 1-m P mwith 0 ≤ n ≤ 1 and 0 < m ≤ 1. Accordingly, “based on an arsenide compound semiconductor material” in the present context means that one or more layers of the semiconductor layer sequence are a III arsenide compound semiconductor material, in particular In x Al y Ga 1-x-y As with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1, preferably Al y Ga 1-y The formula includes As, where 0 ≤ y ≤ 1. The material in question does not necessarily have to have a mathematically exact composition according to the formula above. Rather, it may contain one or more dopants as well as additional components. For the sake of simplicity, however, the formulas above only include the essential components of the crystal lattice (In, Al, Ga, P, As), even though these may be partially replaced by small amounts of other substances.

[0009] The semiconductor layer sequence includes, in particular, a p-type semiconductor region and an n-type semiconductor region. In the case of an optoelectronic semiconductor chip, the semiconductor chip contains an active layer arranged between the p-type semiconductor region and the n-type semiconductor region. The active layer is specifically designed for the emission of electromagnetic radiation. The optoelectronic semiconductor chip can, in particular, be an LED chip, preferably suitable for emitting light in the visible or infrared spectral range. Alternatively, it is also possible that the active layer is a radiation-receiving layer and the optoelectronic semiconductor chip is a detector.

[0010] The active layer can be configured, for example, as a pn junction, a double heterostructure, a single quantum well structure, or a multiple quantum well structure. The term quantum well structure encompasses any structure in which charge carriers undergo quantization of their energy states through confinement. In particular, the term quantum well structure does not specify the dimensionality of the quantization. It therefore includes, among other things, quantum wells, quantum wires, quantum dots, and any combination of these structures.

[0011] According to at least one embodiment, the n-type semiconductor region has a superlattice structure to improve current expansion. The superlattice structure has a periodic arrangement of semiconductor layers, meaning that the arrangement of semiconductor layers in the superlattice structure is repeated at least once, or preferably several times. Each period of the superlattice structure comprises at least one undoped first semiconductor layer and one doped second semiconductor layer. Here and in the following, an undoped layer is understood to be a nominally undoped layer, i.e., a layer that is not actively doped during fabrication. This does not preclude the possibility that small amounts of foreign atoms may unintentionally enter the undoped layer during fabrication and / or through diffusion in the semiconductor layer sequence.

[0012] Advantageously, the electronic band gap E2 of the doped second semiconductor layer is larger than the electronic band gap E1 of the undoped first semiconductor layer. The superlattice structure thus advantageously contains alternating undoped first semiconductor layers with a smaller electronic band gap E1 and doped second semiconductor layers with a larger electronic band gap E2.

[0013] It has been found that in such a periodic arrangement of undoped first semiconductor layers and doped second semiconductor layers, a two-dimensional electron gas advantageously forms in the undoped first semiconductor layers. This two-dimensional electron gas advantageously increases the conductivity of the superlattice structure. In particular, the specific resistance of the superlattice structure is reduced, resulting in increased transverse conductivity. Therefore, using the superlattice structure described here in the n-type semiconductor region, a particularly homogeneous current induction into the semiconductor chip, especially into the active layer of an optoelectronic semiconductor chip, can be achieved.

[0014] In a preferred embodiment, the undopted first semiconductor layer In 0,5 Al x1 Ga 0,5-x1 P with 0 ≤ x1 ≤ 0.27 or Al y1 Ga 1-y1As with 0 ≤ y1 < 0.4. The doped second semiconductor layer preferably exhibits In 0,5 Al x2 Ga 0,5-x2 P with 0 ≤ x2 ≤ 0.5 and x1 < x2 or Al y2 Ga 1-y2 As with 0 < y2 ≤ 1 and y1 < y2. In this configuration, the doped second semiconductor layer has a higher aluminum content than the undoped first semiconductor layer. In arsenide and phosphide compound semiconductors, the electronic band gap increases with increasing aluminum content. The higher aluminum content makes it possible, in particular, to achieve a larger electronic band gap in the doped second semiconductor layer than in the undoped first semiconductor layer.

[0015] The doped second semiconductor layer is advantageously n-doped and preferably comprises Te or Si as the dopant. Preferably, the dopant concentration in the doped second semiconductor layer is at least 1 × 10⁻⁶. 16 cm -3In particular, the dopant concentration in the doped second semiconductor layer can have a value between 1 * 10 16 cm -3 and 1 * 10 20 cm -3 preferably between 1 * 10 17 cm -3 and 1 * 10 19 cm -3 , for example, about 1 * 10 18 cm -3 exhibit.

[0016] In one embodiment, the thickness of the undoped first semiconductor layer is between 1 nm and 30 nm, preferably between 3 nm and 15 nm, and particularly preferably between 5 nm and 10 nm. The doped second semiconductor layer is, for example, between 5 nm and 200 nm thick, preferably between 20 nm and 30 nm.

[0017] In a preferred embodiment of the semiconductor chip, the undoped first semiconductor layer in the superlattice structure is arranged between an undoped first intermediate layer and an undoped second intermediate layer. In this embodiment, one period of the superlattice structure advantageously consists of four layers, with the undoped first intermediate layer, the undoped first semiconductor layer, the undoped second intermediate layer, and the doped second semiconductor layer following each other in one period. The undoped intermediate layers in the superlattice structure ensure that the undoped first semiconductor layer and the doped second semiconductor layer are not directly adjacent to each other in each period of the superlattice structure.In this way, scattering of electrons at the interfaces between the undoped first semiconductor layers and the doped second semiconductor layers in the superlattice structure is reduced.

[0018] In a preferred embodiment, the first undoped intermediate layer and the second undoped intermediate layer each comprise the same semiconductor material as the doped second semiconductor layer. In particular, the first undoped intermediate layer and the second undoped intermediate layer can have substantially the same electronic band gap as the doped second semiconductor layer.

[0019] The first undoped intermediate layer and the second undoped intermediate layer are preferably each between 0.5 nm and 20 nm thick.

[0020] According to at least one embodiment, the superlattice structure has between 5 and 100 periods, preferably between 30 and 50 periods. A high electrical conductivity can be achieved with a number of periods in this range, while the overall thickness of the superlattice structure can still be advantageously kept small.

[0021] In a preferred embodiment, the specific resistance of the superlattice structure is less than 0.05 Ωcm, e.g. 0.01 Ωcm.

[0022] In a preferred embodiment, the semiconductor chip is an optoelectronic semiconductor chip comprising an active layer. The active layer of the optoelectronic semiconductor chip is preferably configured as a single or multiple quantum well structure, comprising at least one quantum well layer and at least one barrier layer. In this embodiment, the undoped first semiconductor layers of the superlattice structure advantageously exhibit a larger electronic band gap in the current-expansion layer than the at least one quantum well layer of the quantum well structure.

[0023] The invention is described below with reference to exemplary embodiments in connection with the Fig. 1, Fig. 2, Fig. 3 to Fig. 4 explained in more detail.

[0024] They show: Fig. 1 a schematic representation of a cross-section through an optoelectronic semiconductor chip according to a first embodiment, Fig. 2 a schematic graphical representation of the electron density n e in the superlattice structure in one embodiment depending on a spatial coordinate z running perpendicular to the layer planes, Fig. 3 a schematic graphical representation of the electronic band structure in the superlattice structure in an exemplary embodiment, and Fig. 4 a schematic representation of a cross-section through an optoelectronic semiconductor chip according to a second embodiment.

[0025] Identical or similarly functioning elements in the figures are marked with the same reference symbols. The sizes of the individual elements and their relative sizes are not to be considered to scale.

[0026] The in Fig. The optoelectronic semiconductor chip 100 shown in Figure 1 contains a semiconductor layer sequence 10, comprising an n-type semiconductor region 2 and a p-type semiconductor region 4. An active layer 3 is arranged between the n-type semiconductor region 2 and the p-type semiconductor region 4.

[0027] The semiconductor layer sequence 10 is preferably based on a phosphide compound semiconductor, i.e., one or more semiconductor layers contained in the semiconductor layer sequence 10 have in particular In x Ga y Al 1-x-y P with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1, preferably In 0,5 Al x Ga 0,5-xP with 0 ≤ x ≤ 0.5. In particular, one or more layers of the n-type semiconductor region 2, the active layer 3, and the p-type semiconductor region 4 are formed from phosphide compound semiconductor materials. However, it is not excluded that the semiconductor layer sequence 10 contains one or more layers of another III-V compound semiconductor material, for example, one or more arsenide compound semiconductor layers or arsenide-phosphide compound semiconductor layers.

[0028] In this embodiment, the active layer 3 is configured as a quantum well structure 31, 32, preferably as a multiple quantum well structure. The quantum well structure, for example, has a periodic arrangement of alternating quantum well layers 31 and barrier layers 32. The quantum well structure has a number P periods, where P is, for example, between 1 and 120.

[0029] The quantum well layers 31 intended for radiation generation have an electronic band gap E QW on, which is smaller than an electronic band gap E B of the barrier layers 32.

[0030] The p-type semiconductor region 4 can contain one or more p-doped semiconductor layers. However, it is not excluded that the p-type semiconductor region 4 contains one or more undoped layers. Similarly, the n-type semiconductor region 2 can contain one or more n-doped layers and one or more undoped layers.

[0031] In the optoelectronic semiconductor chip 100, the n-type semiconductor region 2 has a superlattice structure 20 that functions as a current-expansion layer. In addition to the superlattice structure 20, the n-type semiconductor region 2 can also include further semiconductor layers 25, 26. The superlattice structure 20 has a periodic sequence of semiconductor layers 21, 22, with a period N. Increasing the number of periods increases the electrical conductivity, but conversely, absorption can increase due to the increasing overall thickness. Advantageously, the number N of periods is between 5 and 70.

[0032] Preferably, the number N of periods is between 30 and 50. This makes it possible to achieve good electrical conductivity with no or only moderate absorption. Each period of the superlattice structure 20 comprises an undoped first semiconductor layer 21 and a doped second semiconductor layer 22. The doped semiconductor layers 22 each have an electronic band gap E2 that is larger than the electronic band gap E1 of the undoped first semiconductor layers 21.

[0033] The undoped first semiconductor layers 21 form potential wells between the doped second semiconductor layers 22 in the superlattice structure. The band gap E1 of the undoped first semiconductor layers 21, which form the potential wells, is larger than the band gap E QWThe quantum well layers 31 in the multiple quantum well structure function as the active layer 3. In contrast to the quantum well layers 31, the potential wells formed by the undoped first semiconductor layers 21 do not serve for radiation generation.

[0034] To achieve the larger electronic band gap E2, it is advantageous if the doped second semiconductor layers 22 have a higher aluminum content than the undoped first semiconductor layers 21. The undoped first semiconductor layers 21 can, in particular, be made of aluminum. 0,5 Al x1 Ga 0,5-x1 P with 0 ≤ x1 ≤ 0.27 or Al y1 Ga 1-y1 As with 0 ≤ y1 < 0.4. The doped second semiconductor layers 22 can in particular In 0,5 Al x1 Ga 0,5-x1 P with 0 < x2 ≤ 0.5 and x2 > x1 or Al y2 Ga 1-y2 As with y2 > y1.

[0035] For example, the undoped first semiconductor layer has 21 In0,5 Al 0,1 Ga 0,4 P and the doped second semiconductor layer 22 In 0,5 Al 0,28 Ga 0,22 P. The doped second semiconductor layer 22 is preferably doped with Si or Te and has a dopant concentration of, for example, 1*10 18 cm -3 on.

[0036] For example, the thickness of the undoped first semiconductor layer 21 is about 7 nm and the thickness of the doped second semiconductor layer 22 is about 30 nm.

[0037] In the undoped first semiconductor layers 21, which are arranged between the doped second semiconductor layers 22 in the superlattice structure 20, a two-dimensional electron gas advantageously forms, thereby increasing the electrical conductivity. In particular, the superlattice structure 20 makes it possible to achieve a resistivity of no more than 0.05 Ωcm. The optoelectronic semiconductor chip 100 is therefore characterized by good current expansion, which leads to particularly homogeneous radiation emission across the surface of the optoelectronic semiconductor chip 100. The superlattice structure 20 has the particular advantage that good current expansion can be achieved with a comparatively thin n-type semiconductor region 2.The superlattice structure in the n-type semiconductor region 2 allows, in particular, the conductivity to be increased without increasing the overall thickness of the n-type semiconductor region 2, or, for a given conductivity, the overall thickness to be reduced compared to a homogeneous current-expansion layer.

[0038] The embodiment of the optoelectronic semiconductor chip 100 shown here is a so-called thin-film LED, in which the semiconductor layer sequence 10 has been detached from its original growth substrate. The original growth substrate has been detached by the n-type semiconductor region 2, which in this embodiment is located on the radiation-emitting side of the optoelectronic semiconductor chip 100. On the side opposite the original growth substrate, the optoelectronic semiconductor chip 100 is deposited onto a support substrate 1 with at least one interconnection layer 7, such as a solder layer. Thus, from the perspective of the active layer 3, the p-type semiconductor region 4 faces the support substrate 1. The support substrate 1 is different from the growth substrate used for the epitaxial growth of the semiconductor layer sequence 10.The support substrate 1 can, for example, consist of a semiconductor material such as silicon, germanium or molybdenum, or a ceramic.

[0039] The p-type semiconductor region 4 borders a reflective layer 6 in certain areas. The reflective layer 6 is designed to reflect the radiation emitted from the active zone 3 towards the substrate 1 to the opposite radiation exit surface on the surface of the n-type semiconductor region 2. The reflective layer 6 can, in particular, comprise or consist of silver or gold. Silver and gold are characterized by high reflectivity.

[0040] In the embodiment shown here, a dielectric layer 5, which can be a silicon oxide layer in particular, is arranged in certain areas between the p-type semiconductor region 4 and the mirror layer 6. Due to the comparatively low refractive index of the dielectric material of the dielectric layer 5, for example SiO2, the dielectric layer 5 can cause total internal reflection of a portion of the radiation emitted towards the substrate 1 to the radiation emission surface. The reflective effect of the metallic mirror layer 6 is therefore advantageously further enhanced by the dielectric layer 5. Since the dielectric layer 5 is not electrically conductive, the mirror layer 6 is connected to the p-type semiconductor region 4 by one or more openings in the dielectric layer 5.

[0041] For electrical contacting the optoelectronic semiconductor chip 100, an n-terminal layer 8 and a p-terminal layer 9 are provided. The n-terminal layer 8 for electrical contacting from the n-side can, for example, be arranged on the radiation-emitting side of the n-type semiconductor area 2. The p-terminal layer 9 can, for example, be arranged on the back side of the substrate 1 if an electrically conductive substrate 1 is used.

[0042] The Fig. Figure 2 schematically shows the electron density n eas a function of a vertically oriented spatial coordinate z in one embodiment of the superlattice structure. For simplification, a superlattice structure with only three periods is shown here, although the superlattice structure can actually have, for example, between 5 and 70, preferably between 30 and 50 periods. A comparatively high electron density is present in the undoped first semiconductor layers 21, which are arranged between the doped second semiconductor layers 22. The high electron density and high mobility of the electrons in the undoped first semiconductor layers 21 advantageously increase the electrical conductivity of the superlattice structure.

[0043] Fig. Figure 3 schematically shows the course of the conduction band edge E. L , the Fermi energy E F as well as the valence band edge E VIn an example of the superlattice structure, the conduction band edge of the undoped first semiconductor layers 21 is advantageously located below the Fermi energy. Therefore, free electrons are present in the conduction band of the undoped first semiconductor layers 21, forming a so-called two-dimensional electron gas. The free electrons in the undoped first semiconductor layers 21 have high mobility, which increases the electrical conductivity of the superlattice structure.

[0044] The in Fig. The second embodiment of the optoelectronic semiconductor chip 100 shown in Figure 4 differs from the one shown in Figure 4. Fig. 1 optoelectronic semiconductor chip shown in Figure 1 by the fact that the undoped first semiconductor layers 21 are arranged in the superlattice structure 20 between an undoped first intermediate layer 23 and an undoped second intermediate layer 24.

[0045] In this embodiment, the periods of the superlattice structure 20 each have four layers, wherein the first undoped intermediate layer 23, the undoped first semiconductor layer 21, the undoped second intermediate layer 24, and the doped second semiconductor layer 22 follow one another in each period. Advantageously, the undoped first intermediate layer 23 and the undoped second intermediate layer 24 each have substantially the same electronic band gap as the doped second semiconductor layer 22. In particular, apart from the doping, the undoped first intermediate layer 23 and the undoped second intermediate layer 24 can each have the same semiconductor material as the doped second semiconductor layer 22.

[0046] For example, the undoped first intermediate layer has 23 in 0,5 Al 0,28 Ga 0,22 P, the undoped first semiconductor layer 21 In 0,3 Al 0,1 Ga 0,4P, the undoped second intermediate layer 23 In 0,S Al 0,28 Ga 0,22 P and the doped second semiconductor layer 22 In 0,5 Al 0,28 Ga 0,22 P. The doped second semiconductor layer 22 is preferably doped with Si or Te and has a dopant concentration of, for example, 1*10 18 cm -3 on.

[0047] For example, the thickness of the undoped first intermediate layer 23 is about 6 nm, the thickness of the undoped first semiconductor layer 21 is about 7 nm, the thickness of the undoped second intermediate layer 24 is about 4 nm and the thickness of the doped second semiconductor layer 22 is about 25 nm.

[0048] The undoped first semiconductor layers 21 of the superlattice structure each form potential wells with a high electron density. In particular, a two-dimensional electron gas can form in the undoped first semiconductor layers 21, as in the first embodiment, which increases the conductivity. If the undoped first semiconductor layers 21 were directly adjacent to the doped second semiconductor layers 22, electrons would be scattered by phonons at the interface between the undoped first semiconductor layers 21 and the doped second semiconductor layers 22. The arrangement of the undoped first semiconductor layers 21 between the undoped intermediate layers 23, 24 has the advantage of reducing electron scattering.

[0049] Furthermore, the exemplary embodiment corresponds to the Fig. 4 with regard to its functioning and further advantageous designs, the one in Fig. 1 illustrated embodiment. Reference symbol list 1 carrier 2 n-type semiconductor area 3 active layer 4 p-type semiconductor area 5 dielectric layer 6 Mirror layer 7. Compound layer 8 n-connection layer 9 p-connection layer 10 Semiconductor layer sequence 20 Superstructure 21 undoped first semiconductor layer 22 doped second semiconductor layer 23 unpaid first intermediate shift 24 unpaid first intermediate shift 31 Quantum well layer 32 quantum well layer 100 optoelectronic semiconductor chips

Claims

[1] Semiconductor chip (100) with a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material, wherein the semiconductor layer sequence (10) includes a p-type semiconductor region (4) and an n-type semiconductor region (2), and an active layer (3) arranged between the p-type semiconductor region (4) and the n-type semiconductor region (2), wherein - the n-type semiconductor region (2) comprises a superlattice structure (20) to improve current expansion, wherein the superlattice structure (20) has a periodic arrangement of semiconductor layers (21, 22, 23, 24), - a period of the superlattice structure (20) has at least one undoped first semiconductor layer (21) and one doped second semiconductor layer (22), wherein an electronic band gap E2 of the doped second semiconductor layer (22) is larger than an electronic band gap E1 of the undoped first semiconductor layer (21), and - the undoped first semiconductor layer (21) in the superlattice structure (20) is arranged between an undoped first intermediate layer (23) and an undoped second intermediate layer (24), and - the doped second semiconductor layer (22) is between 10 nm and 200 nm thick. [2] Semiconductor chip according to claim 1, wherein the undoped first semiconductor layer (21) In 0,5 Al x1 Ga 0,5-x1 P with 0 ≤ x1 ≤ 0.27 or Al y1 Ga 1-y1 As with 0 ≤ y1 < 0.4, and the doped second semiconductor layer (22) In 0,5 Al x2 Ga 0,5-x2 P with 0 ≤ x2 ≤ 0.5 and x1 < x2 or Al y2 Ga 1-y2 As has 0 < y2 ≤ 1 and y1 < y2. [3] Semiconductor chip according to claim 2, wherein the aluminium content x1 of the undoped first semiconductor layer (21) is less than 0.

25. [4] Semiconductor chip according to one of the preceding claims, wherein the doped second semiconductor layer (22) has a dopant concentration between 1 * 10 16 cm -3 and 1*10 20 cm -3 exhibits. [5] Semiconductor chip according to any of the preceding claims, wherein the undoped first semiconductor layer (21) is between 3 nm and 15 nm thick. [6] Semiconductor chip according to one of the preceding claims, wherein the doped second semiconductor layer (22) is between 20 nm and 30 nm thick. [7] Semiconductor chip according to one of the preceding claims, wherein the undoped first intermediate layer (23) and the undoped second intermediate layer (24) have the same electronic band gap E2 as the doped second semiconductor layer (22). [8] Semiconductor chip according to any of the preceding claims, wherein the undoped first intermediate layer (23) and / or the undoped second intermediate layer (24) is between 0.5 nm and 20 nm thick. [9] Semiconductor chip according to any of the preceding claims, wherein the superlattice structure (20) has between 5 and 70 periods. [10] Semiconductor chip according to any of the preceding claims, wherein the specific resistance of the superlattice structure (20) is less than 0.05 Ωcm. [11] Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip is an optoelectronic semiconductor chip, and the optoelectronic semiconductor chip has the active layer (3) arranged between the p-type semiconductor region (4) and the n-type semiconductor region (2). [12] Semiconductor chip according to claim 11, wherein the active layer (3) has a quantum well structure comprising at least one quantum well layer (31) and at least one barrier layer (32), and wherein the electronic band gap E1 of the undoped first semiconductor layer (21) of the superlattice structure (20) is larger than an electronic band gap E QW the at least one quantum well layer (31) of the quantum well structure.

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