ORDINARY MODIFICATION OF QUALITY OF SERVICE

Abstract

Data processing device, comprising: a first master with a first ordinal Quality of Service (QoS) profile; a second master with a second ordinal QoS profile, where the second ordinal QoS profile is of a higher order than the first QoS profile; a slave; a multiplexed interconnect for communicative coupling of the first master and the second master with the slave, each with a priority according to the order of the ordinal QoS profile of the respective master; and a QoS machine that is trained to perform the following steps: Determine whether the conditions are met that the first master has initiated a slave operation over the interconnect and that the slave operation is at risk of not being carried out within a deadline set by the second master; to determine that the conditions are met, upgrading the first master to a third ordinal QoS profile with a higher order than the second ordinal QoS profile.

Description

TECHNICAL FIELD OF DISCLOSURE

[0001] This disclosure relates generally to the field of data processing and, more particularly, though not exclusively, to a system and method for ordinal modification of quality of service. BACKGROUND

[0002] A computing system, such as a system chip (SoC), may have multiple masters that need to access system resources, such as L2 memory (or multiple resources, such as L2 and L3 memory). An interconnect, such as a network access control (NOC), may couple the masters to the resource. Each master may be assigned a priority that governs the priority of access to the NOC and the resource.

[0003] US 7 373 445 B2 relates to a method for allocating bus access rights in a multi-master bus system (2), comprising the following steps: addresses (MASTER 0 - MASTER 15) are explicitly assigned to master devices (3-1, ... 3-N) in the multi-master bus system, each master device (3-1, ... 3-N) is assigned a priority value (P0, ... P15) from an organized priority list (5) of priority values ​​(P0... P15), requests from at least one master device (3-1, ... 3-N) to access a slave device (4-1, ... 4-M) via the bus system (2) are received, the priority values ​​(P0, ... P15) of all requesting master devices (3-1, ... 3-N) are compared, if a single requesting master device (3-1, ... 3-N) has the highest priority value (P0, ... P15): The requesting master device (3-1, ... 3-N) that has the highest priority value (P0, ... P15) is granted exclusive access to the respective slave device (4-1, ... 4-M), or if there are multiple requesting master devices (3-1, ...3-N) have the same priority value (P0, ... P15) .. 3-N) have the same highest priority value (P 0, ... P 15): Access to the respective slave devices (4-1, ... 4-M) is granted one after the other to those requesting master devices (3-1, ...3-N) which have the highest priority value (P 0, ... P15) due to the address assignment of the master devices (3-1, ...3-N).

[0004] US 2014 / 0 372 648 A1 relates to a multi-master system on a chip (SoC) comprising a plurality of masters, including a first master and a second master, each configured to generate a request. A next state generator in the multi-master SoC is configured to generate a next state of the round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Furthermore, the next state of the round robin pointer is generated such that a priority is maintained for the first master until a request is received from the second master. SHORT DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be understood that, in accordance with standard industry practice, various features are not necessarily drawn to scale and are for illustrative purposes only. Any explicit or implied representation of scale is merely an illustrative example. In other embodiments, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a block diagram of a digital signal processor according to one or more examples of the present specification. Fig. 2 is a block diagram of a system chip according to one or more examples of the present specification. Fig. 3 is a block diagram of a plurality of selected elements of an SoC according to one or more examples of the present specification. Fig. 4 is a block diagram of a plurality of selected elements of an SoC according to one or more examples of the present specification. Fig. 5 is a block diagram of a plurality of selected elements of an SoC according to one or more examples of the present specification. Fig. 6 is a flowchart of a method according to one or more examples of the present specification. DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE DISCLOSURE

[0006] In one example, a computing device is disclosed comprising: a first master having a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, the second ordinal QoS profile being of a higher order than the first QoS profile; a slave; a multiplexed interconnect for communicatively coupling the first master and the second master, with the slave having a priority according to the ordinal QoS profiles; and one or more logical elements comprising at least one hardware logic element providing a QoS engine for: determining that the first master has initiated a slave operation over the interconnect; determining that performing the slave operation requires increased QoS according to a QoS criterion provided by the second master; and promoting the first master to a third ordinal QoS profile having a higher order than the second ordinal QoS profile.

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. Further, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed. Different embodiments may have different advantages, and no particular advantage of any embodiment is necessarily required.

[0008] In an exemplary embedded system chip (SoC), there are many masters in a system, including, for example, one or more of each of central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), direct memory access (DMA), and peripherals such as high-speed serial ports, USB, sensors, and electromechanical interfaces, as non-limiting examples. These masters can communicate with slaves and memory via an interconnect network, such as a network interface card (NOC).

[0009] As a design consideration, the masters may have different quality of service (QoS) needs, such as latency and bandwidth requirements. The NOC can provide many different transaction attributes to meet these QoS needs. For example, the attributes can include priority assignments, pending transaction throttling, bandwidth throttling, maximum latency, priority levels, transaction excellence, or other factors. Each master can have an associated QoS profile that is a synthesis of its transaction needs and priorities. The QoS profiles of the different masters are ordinal in the sense that the NOC controller must decide for each transaction which master receives priority for instantaneous access to the NOC.

[0010] In a conventional priority scheme, each master is assigned an ordinal priority of a single number. For example, the CPU is priority 0, the DSP is priority 1, the GU is priority 2, and so on. The higher-priority master always trumps the lower-priority master. While such schemes are fully compatible with the tenets of this specification, they are not restrictive. Other factors can also be introduced to improve fairness and efficiency or to limit the impact of a bandwidth-hungry master on the system. For example, a master may have minimum latency requirements that can prevent higher-priority masters from monopolizing the interconnect. If a lower-priority master has waited long enough for access, it can temporarily trump the higher-priority master and gain access to the interconnect.Many other factors can influence the arbitration, ordering, or flow control of priority queue transactions. Therefore, when this specification refers to an ordinal QoS profile, the ordinal aspect need not be a simple ranking that is always followed. Instead, the ordinal priority of a master can change contextually over time. As used throughout this specification, the term "ordinal QoS profile" should be interpreted broadly to include any priority, queuing, or decision structure that enables a controller to make decisions regarding which master should be granted access to a limited resource. The "ordinal aspect" (or, in other words, the "order" of the profile) may comprise a static ordinal priority or a dynamic, contextual, or instantaneous ordinal priority, as applicable to a particular embodiment.

[0011] In this context, it is understood that "boosting" or "promoting" an ordinal QOS profile is not limited to simply changing a single priority number. Instead, it can include any action that advances a master's request further in the queue or otherwise ensures or increases the likelihood that it will be served more quickly than it would have been without the boost or promotion. It should also be noted that in some cases, promoting or promoting one master can be achieved by demoting or downgrading another master.

[0012] The design and implementation of QoS profiles can have a significant impact on the system-level performance of an SoC. For example, in some existing systems, QoS profile controls may be located in the NOC, giving certain masters the ability to program them either at initialization or later in the application runtime.

[0013] However, there are problems determining an optimal or even an acceptable set of QoS profiles for a complex interconnect network a priori or at runtime. A system may also provide a mechanism for automatically modifying QoS profiles at runtime based on the system's behavior.

[0014] For example, consider an SoC where one or more masters are DSP cores and one or more masters are DMAs. The SoC also includes an NOC and a multi-level memory hierarchy, such as L1 and L2. Consider an application scenario where the DSP core processes data transferred from L2 and L3 memory to the core's L1 memory via DMA.

[0015] Application software running on the core attempts to minimize or eliminate the time the core spends waiting for DMA data transfers, but the software is limited by the non-deterministic behavior of DMA transfers due to the dynamic nature of system traffic. Therefore, it is sometimes possible for the core to wait for a DMA transfer to complete, which in turn is held up by other system traffic.

[0016] Different masters may have different latency requirements. For example, in a latency-sensitive master, the master's performance is directly affected by memory latency—the longer the memory latency, the lower the performance. In a latency-critical master, a specific maximum acceptable latency may be specified for each individual transaction, and if this latency is not met, a fatal error occurs (e.g., a video stream breaks or clicks / pops / pauses in the audio). However, as long as the minimum requirements are met, further reducing latency may not improve performance. A bandwidth-hogging master is a node that has high bandwidth requirements and flow control, meaning that increased latency does not result in a critical error.

[0017] This is a situation where a latency-sensitive master (e.g., a DSP core) is waiting for another master (e.g., a DMA) to perform a non-deterministic operation. To illustrate this specifically, a first master (here, the DMA) has a first ordinal QoS profile. A second master (here, the DSP core) has a second ordinal QoS profile. The second ordinal QoS profile is of a higher order (or conversely, a lower integer value) than the second ordinal QoS profile. e.g., the DSP has an ordinal priority of 1, while the DMA has an ordinal priority of 3. Meanwhile, a GPU may have a third ordinal QoS profile, in this case, with an ordinal priority of 2.

[0018] The consequence is that the DSP with an ordinal priority of 1 has to wait for the GPU with an ordinal priority of 2 because the DSP needs data from the DMA, which has an ordinal priority of 3.

[0019] In this case, it would make sense for the DMA to "take over" the DSP's higher priority. For example, the DMA could be assigned an ordinal QoS profile with a priority of 2. In certain embodiments, this is sufficient to guarantee priority over the GPU, since the DMA's request is older, and race situations between masters of the same order are resolved in favor of the oldest. Advantageously, this also ensures that the DMA does not interfere with operations that the DSP itself may need to perform in the meantime.

[0020] Alternatively, it may be desirable to request that the DMA obtain absolute priority over the GPU, regardless of the request's age. In this case, the DMA can be given an ordinal priority of 1 or 0, thus ensuring priority over the DMA or even the DSP.

[0021] Note that a non-negative integer priority marker is an example of just one of many possible fields in a QoS profile that could be modified to ensure that a request receives priority from a higher-order master. Any other field within a QoS profile could be modified to achieve the desired priority. For example, the maximum queue size for requests from the master could be adjusted downward, even to zero, to ensure immediate service of its next pending request. The maximum allowable latency for that master could also be adjusted downward, down to zero, to ensure priority is achieved. In another example, flags such as "ABSOLUTE_PRIORITY" could be used.When the flag is set, the master always receives priority over masters of the same order, regardless of other QoS profile factors (conceptually, this roughly means that the master receives a priority of 1.5—lower than all masters with priority 1, but higher than all masters with priority 2). Thus, a combination of priority 0 with an ABSOLUTE_PRIORITY flag could be used to force the interconnect to serve that master in the next available cycle. Many other QoS factors could be adapted and fall within the scope of this disclosure.

[0022] In a general case, it can be said that the system comprises a QoS engine that has several logical functions, which include, but are not limited to: a. a capability for one or more masters to automatically detect conditions that benefit from QoS profile schema adjustments involving ordinal priority elevation, including the optional capability to notify other masters of the need to do so. For example, a first lower-priority master (e.g., the DMA) can signal a second higher-priority master that it requires increased priority to satisfy QoS parameters; b. a capability for automatically identifying a dependency relationship between the second master (e.g., the DSP) and the first master (e.g., the DMA) and determining that a higher-order master is forced to wait for a lower-order master or that it is appropriate for the lower-order master to assume the priority of the higher-order master; and c. an ability to elevate the first master to a higher ordinal priority.

[0023] The QoS engine may be partially embedded in one of the masters, such as the master that has sufficient system privileges to override priority (e.g., the CPU or DSP), and supported by logic encoded as microcode instructions, instructions in ROM, encoded in special-purpose hardware, or encoded in another non-transitory computer-readable storage medium. In other embodiments, the QoS engine may be a separate hardware block that monitors the masters and performs ordinal priority elevation as needed. In this case, the hardware QoS engine may be designed to have all of the privileges necessary to effect ordinal privilege elevation.

[0024] Advantageously, certain embodiments optionally achieve an ordinal priority increase without making any changes to the NOC itself. This can be important in embodiments where the NOC is provided separately as an "IP block." In a semiconductor design, third parties may provide IP blocks as black boxes, and the system designer may have little or no control over the block beyond its placement and routing. Thus, in embodiments where a black-box NOC is used, adjustments to the ordinal priority can still be realized.

[0025] Many different mechanisms can be used to adjust ordinal priority. For example, ordinal priority can be regulated or adjusted through special-purpose registers or buffers. In this case, the original QoS profile is stored in the buffer or register. When ordinal priority boosting is requested, the QoS profile for the affected master can be temporarily changed. In another embodiment, an out-of-band (OOB) signaling bus, which can comprise one or more wires, can be provided for signaling the need for an ordinal priority boost or other change to a QoS profile. In yet another example, an in-band adjust signal can be sent to the NOC. In yet another example, an interrupt can be triggered to notify the NOC that a QoS profile change is needed.In yet another example, a master may have permission to modify its own QoS profile. QoS profile changes may also apply only to the affected master, to other masters in the system, or to the NOC itself. In yet another embodiment, QoS profiles may include one or more programmable values ​​that can be set by application software. In some embodiments, the QoS profile may be reset to its default value before the start of the next transmission. To further enhance the signaling mechanism, there could be various ways to signal modifications to transaction attributes. In another example, the first master sends a signal to a triggering unit, which triggers modifications to one or more QoS profile registers in the second master.The new QoS profile can either be located in the second master itself (as a set of registers), or it can be part of a memory descriptor loaded for a specific data transfer to provide better application control for the user.

[0026] Another aspect of the QoS engine is logic for determining when it is appropriate to provide an ordinal priority boost. This could, for example, include explicit logic, where, for example, upon de-enrollment of an instruction resulting in a DMA operation, the DSP can explicitly increase the ordinal priority of the DMA, with the timing sensitive and dependent on the DMA access to the NOC. In another example, the QoS engine can include a heuristic engine that independently monitors all masters. The QoS engine can determine that the DSP has issued an instruction that depends on the DMA and that the instruction's execution is in danger of not being met within a latency threshold, which may be part of the QoS profile for the DSP. In this case, after waiting a sufficient amount of time (e.g.,3 / 4 of the maximum latency) immediately increase the ordinal priority of the DMA, optionally to a maximum or other optimal value, to ensure that the DSP request is met within the latency threshold. This latter method has the advantage that adjustments to the QoS scheme can be minimized and only performed when a time-critical function is in danger of not being executed. In some embodiments, a user or programmer may have application-level visibility into the scheme, enabling the programmer to mark certain operations as time-critical and, if necessary, explicitly set latency thresholds for the operations, or even explicitly increase the ordinal priority of the DMA in association with a specific command.

[0027] A system and method for ordinal QoS enhancement will now be described with particular reference to the accompanying FIGURES. It should be understood that certain reference numerals are repeated throughout the FIGURES to indicate that a particular device or block is entirely or substantially the same throughout the FIGURES. This is not intended, however, to imply that a particular relationship exists between the various embodiments. In certain embodiments, a genus of elements may be designated by a particular reference numeral ("widget 10"), while individual species or examples of the genus may be designated by a hyphenated reference numeral ("first specific widget 10-1" and "second specific widget 10-2").

[0028] Fig. 1 is a schematic block diagram of an exemplary digital signal processor (DSP) core 100 according to one or more examples of the present specification. Note that DSP core 100 is provided as a non-limiting example of a processor type, and the term "processor," as used throughout this specification, generally encompasses any combination of hardware, software, or firmware that provides programmable logic, including, as non-limiting examples, a microprocessor, a digital signal processor, a field-programmable gate array, a programmable logic array, an application-specific integrated circuit, or a virtual machine processor.The DPS core 100 may be part of a larger "computing device," which various embodiments may include, as non-limiting examples, or form part of, a computer, an embedded computer, an embedded controller, an embedded sensor, a personal digital assistant (PDA), a laptop computer, a cellular phone, an IP phone, a smartphone, a tablet computer, a calculator, or any other electronic, microelectronic, or microelectromechanical device for processing and communicating data. Fig. Figure 1 has been simplified for clarity and to better understand the novel concepts of the present disclosure. Therefore, additional features may be added to DSP core 100, and some of the features described below may be replaced or eliminated in other embodiments of DSP core 100.

[0029] The DSP core 100 may include a control unit 110, a memory 120, and a compute matrix 130. In one example, the control unit 110 and the compute matrix 130 form a core processor that can perform computational and data processing functions of the DSP core 100. Some embodiments of the DSP core 100 include other components, such as a microcontroller for executing microcontroller instructions, a direct memory access (DMA) unit, and various interfaces to off-chip devices. Further, although the memory 120 is depicted here as a single logic block, it should be understood that the memory 120 may include system main memory, various levels of on-chip or local memory, a cache, and / or other volatile or non-volatile memory technologies.

[0030] The control unit 110 enables program execution of the DPS core 100. The control unit 110 may include an arithmetic logic unit and data address generation (ALU-DAG) unit 112, a program flow controller 114, and local program memory 116. The control unit 110 may also include other components, such as an instruction cache, a timer, and an instruction register. In one example, the ALU-DAG unit 112 supports general integer calculations and provides memory addresses. For example, the ALU-DAG 112 provides memory addresses when transferring data between the memory 120 and registers (such as register files of the computation matrix 130, described below). The ALU-DAG unit 112 may provide addresses to a data memory (e.g., memory 120) and / or the program memory 116. The program flow controller 114 provides instruction addresses to the program memory 116 for instruction fetching.Program memory 116 stores programs implemented by DSP core 100 for processing data (such as data stored in memory 120), and may also store process data. "Programs," as used throughout this specification, include any ordered set of executable instructions configured to instruct a processor, such as DSP core 100, to perform a specified task. DSP core 100 may implement programs by retrieving the instructions, for example, by retrieving them from memory 120 and loading them into program flow controller 114, decoding the instructions, providing the decoded instructions to processing elements PE for execution, and executing them locally in ALU-DAG unit 112.In one example, the programs may include instruction sets for implementing various DSP algorithms, including algorithms that can be executed in parallel by executing across two or more processing elements (PEs) or in a single instruction multiple data (SIMD) mode, where two or more processing elements execute the same instruction, as received from the program flow controller 114, on different data elements. SIMD is commonly used, for example, for fast processing of large data arrays by dividing the array into n sub-arrays and then allowing n processing elements to each process a sub-array separately.

[0031] Memory 120 stores data to be processed by DSP core 100 (data memory), programs implemented by DSP core 100 to process the data (program memory), or a combination thereof. In some examples, memory 120 may have an interleaved multi-bank memory structure such that memory 120 includes memory banks M1-Mn, where n is a total number of memory banks in memory 120. In one example, memory 120 is a random access memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), read-only memory (ROM), flash memory, or other suitable memory technology. In one example, one or more memory banks M form a separate RAM.Alternatively, memory 120 may represent a multi-level memory structure, including, for example, a fast L1 memory, an intermediate L2 memory, and a slow main memory, where the size and cost of each memory may vary inversely with the access speed of the memory. In yet another example, memory 120 may include a cache or any other suitable memory type. In some cases, direct memory access (DMA) control may also be provided to enable DMA operations from DSP core 100 to memory 120.

[0032] As an example, three buses 170 are shown. As used throughout the specification, a "bus" includes any interconnection lines, networks, links, trunks, single buses, multiple buses, crossbar networks, single-level networks, multi-level networks, or other routing media configured to carry data between parts of a computing device or between computing devices. If necessary or appropriate, the buses 170 may also include corresponding controllers, such as a memory management unit (MMU) or the like. In this example, a main system bus 170-1 is provided to communicatively couple the DSP core 100 to other system components, as described by a more detailed example in Fig. 2. Compute bus 170-2 communicatively couples compute matrix 130 to control unit 110. Memory bus 170-3 communicatively couples processing elements PE to memory 120. It should be noted that these uses are disclosed only as non-limiting examples, and that some embodiments may omit one or more of the above buses, while others may employ additional or different buses.

[0033] The control unit 110 can issue instructions and data addresses to the compute matrix 130 via the compute bus 170-2. The compute bus 170-2 transfers addresses for instructions and data to various processing elements PE of the compute matrix 130. The memory bus 170-3 can transfer data and / or instructions from a memory (e.g., the memory 120, the program memory 116, another memory, or combinations thereof) such that the contents of a register in the DSP core 100 can be transferred to any other register or memory location, and the memory 120 can provide data operands (values) to the compute matrix 130.

[0034] In the illustrated example, the computation matrix 130 includes four processing elements PE1-PE4. In other embodiments, the computation matrix 130 may include zero or more discrete processing elements. The processing elements PE perform numerical processing and, in one example, may include specialized hardware for executing specific types of calculations, such as DSP algorithms. The processing elements PE may function independently, in parallel, or as a SIMD machine. In the present example, each processing element PE may be a vector processor. Alternatively, processing elements PE may be scalar processors or a combination of scalar processors and vector processors.

[0035] The processing elements PE may each include a respective arithmetic unit (CU) 152. In the illustrated embodiment, the arithmetic units 152 may be identical, although the present disclosure also contemplates embodiments in which the arithmetic units 152 are not identical. The present disclosure further contemplates configurations in which the processing elements PE do not include arithmetic unit 152. In the present example, the arithmetic units 152 each include an arithmetic unit (ALU), a multiplier-accumulator (MAC), a shifter, another arithmetic unit, or combinations thereof. An ALU may perform arithmetic and logical operations such as adding, subtracting, negating, incrementing, decrementing, absolute value, AND, OR, XOR, NOT, primitive division, other arithmetic operations, other logical operations, or combinations thereof.An exemplary MAC may perform multiplication operations, such as multiplication and accumulation operations, for example, single-cycle multiplication, multiplication / addition, multiplication / subtraction, other operations, or combinations thereof. A shifter may perform logical and arithmetic shifts, bitwise processing, normalization, denormalization, exponent derivation operations, other operations, or combinations thereof. The various arithmetic operations, logical operations, and other operations may be performed in both fixed-point and floating-point formats. In various embodiments, the ALU, MAC, and / or shifter include registers associated therewith.

[0036] The processing elements PE may also each include a respective register file 154. In the illustrated embodiment, the register files 154 may be identical, although the present disclosure also contemplates embodiments in which the register files 154 are not identical. The present disclosure further contemplates configurations in which one or more processing elements PE do not include a register file 154. The register files 154 include registers that transfer data between processing elements PE and memory bus 170-3 and store results.In the present example, the register files 154 may include a respective general-purpose register set 155, which may include general-purpose registers with widths that depend on the design requirements of the DSP core 100, such as 32-bit general-purpose registers, 40-bit general-purpose registers, 64-bit general-purpose registers, 128-bit general-purpose registers, general-purpose registers of other widths, or a combination thereof. For the purposes of the following discussion, the general-purpose registers 155 include 32-bit general-purpose registers.

[0037] In the present example, register files 154 may also include special-purpose registers 158. In particular, a QoS profile register may be provided. Note that special-purpose registers 158 may be general-purpose registers designated for a specific purpose and therefore need not include any special hardware. Instead, their "special purpose" is defined in terms of their role, namely, their role in providing ordinal QoS enhancement according to the methods disclosed herein.

[0038] In one example, a special register 158 is called the QoS profile register. A high-priority master (e.g., the processor or DSP of Fig. 3) can write to the special register 158 with a value that indicates, for example, which master has been assigned a temporarily elevated QoS profile, and a value that represents the temporarily elevated QoS profile. It should be noted that the QoS profile in one example may be a simple integer ordinal number from 0...n, with lower values ​​having higher priority. However, this should be treated as a non-limiting example. In fact, the QoS profile may be a multi-dimensional profile with many factors influencing the ordering, such as NOC congestion, the latency of currently pending requests, a maximum allowable latency, or any other factors that require a selector (e.g., the selector 304 of Fig. 3) enable the selection of multiple masters. Therefore, the ordinal promotion discussed in this specification should be understood to encompass any scheme in which different masters receive ordinal priority, including schemes in which priority is a contextual or other variable.

[0039] DSP core 100 can perform various parallel operations. For example, processing elements PE can access an instruction (via interconnect network 142) and access N data operands from memory for synchronous processing (via memory bus 170-3) during a single cycle. In SIMD mode, DSP core 100 can process multiple data streams in parallel.For example, when DSP core 100 is in SIMD mode, it may dispatch a single instruction to each or a plurality of processing elements PE in a single cycle over compute bus 170-2; load N records, one record for each processing element PE (in one example, each record may include two data operands), from memory (memory 120, program memory 116, other memory, or a combination thereof) over memory bus 170-3; execute the single instruction synchronously in processing elements PE; and store data results from the synchronous execution in memory 120.

[0040] Fig. Figure 2 is a block diagram of a system chip 200 according to one or more examples of the present specification. Note that the system chip (SoC) 200 is provided herein only as an illustrative example. In a general case, the SoC 200 may be any suitable computing device.In various embodiments, a "computing device" may be or include, as non-limiting examples, a computer, a workstation, a server, a mainframe computer, a virtual machine (whether emulated or on a bare metal hypervisor), an embedded computer, an embedded controller, an embedded sensor, a personal digital assistant, a laptop computer, a cellular phone, an IP phone, a smartphone, a tablet computer, a computing device, a network device, a receiver, a wearable computer, a calculator, or any other electronic, microelectronic, or microelectromechanical device for processing and communicating data.

[0041] The SoC 200 includes a processor 210 connected to a memory 120 via a DMA controller 222. Other components of the SoC 200 include a DSP core 100, a graphics processing unit (GPU) 140, a data memory 250, and a network interface 260. This architecture is provided only as an example and is neither exclusive nor limiting. Furthermore, the various disclosed portions are intended to be logical divisions only and may not necessarily represent physically separate hardware and / or software components. For example, some computing devices provide main memory 220 and data memory 250 in a single physical storage device, and in other cases, the main memory 220 and / or data memory 250 are functionally distributed across multiple physical devices.In the case of virtual machines or hypervisors, all or part of a function may be provided in the form of software or firmware executed via a virtualization layer to provide the disclosed logical function. In other examples, a device, such as network interface 260, may provide only the minimum hardware interfaces necessary to perform its logical operations and rely on a software driver to provide additional required logic. Therefore, each logic block disclosed herein is generally intended to include one or more logical elements configured and arranged to provide the disclosed logical operations of that block.As used throughout the specification, “logical elements” can include hardware, external (digital, analog, or mixed-signal) hardware, software, reciprocating software, services, drivers, interfaces, components, modules, algorithms, sensors, components, firmware, microcode, programmable logic, or objects that can coordinate to achieve a logical operation.

[0042] In one example, processor 210 is communicatively coupled to memory 220 via DMA controller 222, although many other memory architectures are possible, including those in which memory 220 communicates with processor 210 via a system bus or other bus. Processor 210 may be communicatively coupled to other devices via interconnect 270, which may be, for example, a network interface card (NOC) or any other suitable bus. As used throughout this specification, a "bus" includes any wireless interconnect, network, link, trunk, single-bus, multiple-bus, crossbar network, single-stage network, multi-stage network, or other circuit media configured to carry data, signals, or power between parts of a computing device or between computing devices.It should be noted that these uses are disclosed only as non-limiting examples, and that some embodiments may omit one or more of the above buses, while others may employ additional or different buses.

[0043] The interconnect 270 may be controlled by a NOC controller 272, which may assign ordinal priority to the various masters and route data according to that priority.

[0044] In various examples, a "processor" may include any combination of logical elements configured to execute instructions, whether loaded from memory or implemented directly in hardware, and may include, as non-limiting examples, a microprocessor, a digital signal processor, a field-programmable gate array, a graphics processing unit, a programmable logic array, an application-specific integrated circuit, or a virtual machine processor. In certain architectures, a multi-core processor may be provided, in which case processor 210 may be treated as only one core of a multi-core processor or as the entire multi-core processor, as applicable. In some embodiments, one or more coprocessors may also be provided for special-purpose or support functions.Similarly, the DSP core 100 may be a single core with SIMD capability, or it may be multiple cores, each with SIMD capability.

[0045] Processor 210 may be connected to memory 220 in a DMA configuration via DMA controller 222. To simplify this disclosure, memory 220 is disclosed as a single logic block, but in a physical embodiment, it may comprise one of multiple blocks of any suitable volatile or non-volatile memory technology or technologies, including, for example, DDR RAM, SRAM, DRAM, cache, L1 or L2 memory, on-chip memory, registers, flash, ROM, optical media, virtual memory regions, magnetic or tape storage, or the like. In certain embodiments, memory 220 may comprise relatively low-latency volatile main memory, while data storage 250 may comprise relatively high-latency non-volatile memory.However, main memory 220 and data memory 250 need not be physically separate devices, but in some examples may simply represent a logical separation of functions. It should be noted that although DMA is disclosed as a non-limiting example, it is not the only protocol consistent with this specification; other memory architectures are also available. Similarly, L2 memory 320 is illustrated as a separate logic block as one example. This is intended to illustrate certain features of the present specifications, including the feature of NOC controller 272 arbitrating access to L2 memory 320 between the various masters, represented according to an ordinal QoS scheme.In the general case, however, the NOC controller 272 may arbitrate access to any slave resource shared between different masters, including any addressable device or addressable buffer.

[0046] Data storage 250 may be any type of storage 220 or a separate device. Data storage 250 may comprise one or more non-transitory computer-readable media, including, as non-limiting examples, a hard disk, a solid-state drive, external storage, a redundant array of independent disks (RAID), optical storage, a tape drive, a backup system, cloud storage, or any combination of the foregoing. Data storage 250 may be or include a database or databases or data stored in other configurations, and may include a stored copy of operating software, such as operating system 222, and software portions of QoS engine 502. Many other configurations are also possible and are intended to fall within the general scope of these specifications.

[0047] The network interface 260 may be provided for communicatively coupling the SoC 200 to a wired or wireless network. A "network" or "network," as used throughout this specification, may include any communicative platform designed to exchange data or information within or between computing devices, and may include, as non-limiting examples, a local ad hoc network, an Internet architecture that provides computing devices with the ability to interact electronically, a POTS (Plain Old Telephone System) that could use computing devices to conduct transactions, where they may be assisted by human operators or where they may manually enter data into a telephone or other suitable electronic device, any Packet Data Network (PDN),which provides a communications interface or exchange between any two nodes in a system, or any local area network (LAN), metropolitan area network (MAN), wide area network (WAN), wireless local area network (WLAN), virtual private network (VPN), intranet, or any other suitable architecture or system enabling communications in a network or telephony environment.

[0048] Fig. 3 is a block diagram of selected elements of an SoC 200 according to one or more examples of the present specification. The elements depicted here are chosen to illustrate a priority scheme. In this case, a number of masters are depicted, including CPU 210, DSP 100, DMA 222, and GPU 140. Each of these is communicatively coupled to a slave, such as L2 memory 320, via NOC 270. Note that this specific implementation is provided merely as an illustrative and non-limiting example. Any set of masters could be used, NOC 270 could be replaced by any suitable interconnect or bus, and L2 320 could be replaced by any slave device.

[0049] In this example, a NOC controller 272 is provided to control the selector 304, which selects between the various masters and determines which one will be served in the next cycle. In some cases, the selector 304 or the NOC 270 may include a queue 318 containing a plurality of pending requests, each having an associated QoS profile or QoS parameters that should be met. At or before each cycle in which the NOC 270 becomes available, the NOC controller 272 checks pending requests in the queue 318 and determines which one should be served next. The selector 304 then retrieves the request from the queue and services the request.

[0050] In this example, each master has a QoS profile 340, namely, CPU 210 has a QoS profile 340-1, DSP 100 has a QoS profile 340-2, DMA 222 has a QoS profile 340-3, and the GPU has a QoS profile 340-4. The QoS profiles 340 may be stored in any suitable memory location or encoded by any suitable method, such as hardware encoding, firmware encoding, encoding in a register, encoding in a buffer, or any other suitable memory location.

[0051] Here, each QoS profile 340 includes an ordinal priority value. In this case, the ordinal priority is a simple non-negative integer value. Note that other QoS factors may be encoded in QoS profile 340, and the values ​​presented here are only an illustrative example. In this case, CPU 210 has ordinal priority 0, DSP 100 has ordinal priority 1, DMA 222 has ordinal priority 3, and GPU 140 has ordinal priority 2. In other words, CPU 210 is considered the highest-order master with the highest priority. DSP 100 has the next highest ordinal priority. GPU 140 has the next highest ordinal priority. And DMA 222 has the lowest priority of the presented masters. Of course, many other priority schemes are possible, and this is presented only as a non-limiting example.

[0052] All other things being equal, CPU 210 has first access to NOC 270. DSP 100 has second access to NOC 270. GPU 140 has third access to NOC 270. DMA 222 has fourth access to NOC 270. However, within queue 318, the conditions may not all be the same. For example, a very old queued request from DMA 222 may receive priority over a very new request from CPU 210, particularly if DMA 222 has a QoS profile with a maximum allowable latency and there is a risk of exceeding the latency. Many other QoS factors may also play a role in queuing decisions made by NOC controller 272.

[0053] Fig. 4 is a block diagram of selected elements of an SoC 200 according to one or more examples of the present specification. The figure illustrates an ordinal priority boost. According to the methods disclosed herein, it is determined that the DMA 222 needs a temporary ordinal priority boost, for example, to priority 0. Therefore, the DMA 222 is boosted to priority 0 so that the CPU 210 can receive data it needs to proceed, for example, for a time-sensitive operation. In some cases, the priority boost occurs a priori, so that when the request is enqueued into the queue 318, it already has the boosted priority. In other examples, the priority is boosted after the fact (for example, when a QoS metric for the CPU 210 is at risk of not being met).In this case, a QoS engine may need to notify the NOC controller 272 of the increased priority so that the request can be served in a timely manner.

[0054] Fig. 5 is a block diagram of selected elements of an SoC 200 according to one or more examples of the present specification. In this example, a QoS engine 502 is illustrated. The QoS engine 502 may include instructions, such as microcode or ROM instructions, that may be executed by the CPU 210 (or alternatively, by the DSP 100), in one non-limiting example. Note that in some embodiments, a single QoS engine 502 may be provided, while in other embodiments, each master may have its own full or partial QoS engine 502, and in other embodiments, functions may be divided between a dedicated QoS engine 502 and per-master QoS engines.

[0055] In this example, the QoS engine 502 comprises several logic blocks, defined here in terms of logical functions rather than as specific or discrete hardware units. These include: a. QoS Register 558 - Special registers allocated to store QoS values ​​for different masters. b. Timer 504 - a timer for analyzing the time elapsed since a particular request was issued. This can be used to analyze whether a particular request from a higher-order master is at risk of not being served within the allowable QoS limit because it may be waiting for a lower-order master. c. A QoS analyzer 502 may be configured to automatically detect conditions that benefit from adjustments to the QoS profile scheme that involve ordinal priority elevation, including the optional ability to notify other masters of the need to do so. The QoS analyzer 508 may also be configured to automatically identify a dependency relationship between the second master (e.g., the DSP) and the first master (e.g., the DMA) and determine that a higher-order master is forced to wait for a lower-order master or that it is appropriate for the lower-order master to assume the priority of the higher-order master. d. Out-of-Band Signaler 506 - In cases where the QoS engine 502 is unable to handle an ordinal QoS priority increase internally (e.g., between masters), the OOB signaler 506 may provide signals to the NOC 270 via an OOB bus 508. OOB signaling is provided as an example, but other mechanisms, such as in-band signaling or interrupts, may also be used.

[0056] The QoS engine 502 may be partially embedded in one of the masters, such as the master that has sufficient system privileges to override priority (e.g., the CPU 210 or the DSP 100), and supported by logic encoded as microcode instructions, instructions in ROM, encoded in special-purpose hardware, or encoded in another non-transitory computer-readable storage medium. In other embodiments, the QoS engine 502 may be a separate hardware block that monitors the masters and performs the ordinal priority elevation when necessary. In this case, the QoS engine may be configured to have all the privileges necessary to effect the ordinal privilege elevation.

[0057] Many different mechanisms can be used to adjust ordinal priority. For example, ordinal priority can be regulated or adjusted by QoS registers 558 or buffers. In this case, the original QoS profile is stored in the buffer or register. When ordinal priority boosting is requested, the QoS profile for the affected master can be temporarily changed. In another embodiment, an out-of-band (OOB) signaling bus 508, which can comprise one or more wires, can be provided for signaling the need for an ordinal priority boost or other change to a QoS profile. In yet another example, an in-band adjust signal can be sent to the NOC. In yet another example, an interrupt can be triggered to notify the NOC that a QoS profile change is needed.In yet another example, a master may have permission to modify its own QoS profile. QoS profile changes may also apply only to the affected master, to other masters in the system, or to the NOC itself. In yet another embodiment, QoS profiles may include one or more programmable values ​​that can be set by application software. In some embodiments, the QoS profile may be reset to its default value before the start of the next transmission. To further enhance the signaling mechanism, there could be various ways to signal modifications to transaction attributes. In another example, the first master sends a signal to a triggering unit, which triggers modifications to one or more QoS profile registers in the second master.The new QoS profile can either be located in the second master itself (as a set of registers), or it can be part of a memory descriptor loaded for a specific data transfer to provide better application control for the user.

[0058] The QoS analyzer 508 may be configured to determine when it is appropriate to provide an ordinal priority boost. This could include explicit logic, for example, where the DSP 100 may explicitly increase the ordinal priority of the DMA 222 upon de-assertion of an instruction resulting in a DMA operation, with timing sensitive and dependent on DMA access to the NOC 270. In another example, the QoS engine 508 may include a heuristic engine that independently monitors all masters. The QoS engine 508 may determine that the DSP 100 has issued an instruction that depends on the DMA 222 and that the execution of the instruction is at risk of not being met within a latency threshold, which may be part of the QoS profile for the DSP 100. In this case, the QoS engine 508 can, after waiting a sufficient time (e.g.3 / 4 of the maximum latency) immediately increase the ordinal priority of the DMA 222, optionally to a maximum or other optimal value, to ensure that the DSP request is met within the latency threshold. This latter method has the advantage that adjustments to the QoS scheme can be minimized and only performed when a time-critical function is in danger of not being executed. In some embodiments, a user or programmer may have application-level visibility into the scheme, enabling the programmer to mark certain operations as time-critical and, if necessary, explicitly set latency thresholds for the operations, or even explicitly increase the ordinal priority of the DMA 222 in association with a specific command.

[0059] The QoS engine 502, in one example, is configured to perform computer-implemented methods as described in this specification. The QoS engine 502 may comprise one or more tangible, non-transitory, computer-readable media having executable instructions stored thereon configured to instruct a processor to provide a QoS engine 502. As used throughout this specification, a "engine" includes any combination of one or more logical elements of similar or dissimilar species that are configured and configured to perform one or more methods provided by the engine. Therefore, the QoS engine 502 may comprise one or more logical elements configured to provide methods as disclosed in this specification.In some cases, the QoS engine 502 may comprise a special-purpose integrated circuit or hardware circuit element designed to perform a method or a portion thereof, and may also comprise software or microcode instructions designed to instruct a processor to perform the method. In some cases, the QoS engine 502 may execute as a "daemon" process. A "daemon" may include any program or series of executable instructions, whether implemented in hardware, software, firmware, or any combination thereof, that executes as a background process, in-memory TSR program, service, system extension, system control, boot procedure, BIOS subroutine, or any other similar program that operates without direct user interaction.In certain embodiments, daemon processes may be executed with elevated privileges in a "driver space" or ring 0, 1, or 2 in a protection ring architecture. It should also be noted that QoS engine 502 may also include other hardware and software, including, as non-limiting examples, configuration files, register entries, and interactive or user-mode software.

[0060] In one example, the QoS engine 502 includes executable instructions stored on a non-transitory medium and configured to perform a method according to this specification. The non-transitory medium may explicitly include hardware-encoded logic or firmware in addition to a medium encoding software instructions. At an appropriate time, such as upon startup of the SoC 200 or upon a command from the operating system or a user, the processor may retrieve a copy of the instructions from data storage and load them into main memory. The processor may then iteratively execute the instructions of the QoS engine 502 to provide the desired method.

[0061] Fig.6 is a flowchart of a method 600 for providing ordinal QoS priority enhancement according to one or more examples of the present specification. This method may be performed by QoS engine 502.

[0062] At block 602, the QoS engine 502 detects that a first master has initiated a slave access operation, for example, accessing the L2 memory 322 by the DMA 222 via the NOC 270. It should be noted that this "detecting" could take the form of an independent QoS engine 502 detecting the operation, or a QoS engine 502 (or a portion thereof) within a master becoming aware of the operation. It should be noted that this could be an a priori detection or could occur upon detection of a condition, for example, that an operation is at risk of not being performed within a QoS limit.

[0063] At block 604, the QoS engine 502 determines that a second master has allocated work to the first master. For example, the DSP 100 may have issued a memory request requesting the DMA 222 to access the NOC 270 and is waiting for results before continuing its operation.

[0064] At block 606, the QoS engine 502 determines that the allocated work requires a higher ordinal priority or other QoS parameter. This may be because, for example, the second master is waiting for results from the first master before proceeding.

[0065] At block 608, the QoS engine 502 changes one or more parameters, such as an ordinal priority or one or more factors that affect the ordinal priority. This effectively "promotes" the first master to a higher order for NOC access purposes, or effectively allows the first master to "take over" the priority of the second master so that it can complete its task in a timely manner.

[0066] It should be noted that the activities discussed above with reference to the FIGURES can be applied to any integrated circuits that include signal processing (e.g., gesture signal processing), and in particular those that can execute specialized software programs or algorithms, some of which may be associated with the processing of digitized real-time data. Certain embodiments may relate to multi-DSP signal processing, floating-point processing, signal / control processing, fixed function processing, microcontroller applications, etc.In certain contexts, the features discussed herein may be applied to medical systems, scientific devices and instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, power measurement, metrology (which may be highly precise), amateur radio, home automation, the "Internet of Things," and other systems based on digital processing. Furthermore, various embodiments discussed above may be utilized in digital signal processing technologies for medical imaging, patient monitoring, medical devices and instruments, and home healthcare. This could include lung monitors, accelerometers, heart rate monitors, pacemakers, etc. Other applications may include automotive technologies for safety systems (e.g.,Stability control systems, driver assistance systems, braking systems, infotainment, and interior applications of all kinds). In addition, powertrain systems (for example, in hybrid or electric vehicles) may utilize high-precision data conversion products in battery monitoring, control systems, message control, maintenance activities, etc. In still other example scenarios, the teachings of the present disclosure may be applied to industrial markets, including process control systems that help promote productivity, energy efficiency, and reliability. In consumer applications, the teachings of the signal processing circuits discussed above may be used for image processing, autofocus, and image stabilization (e.g., for digital cameras, camcorders, etc.). Other consumer applications may include audio and video processors for home theater systems, DVD recorders, and high-definition television.Still other consumer applications may include advanced touchscreen controls (e.g., for any type of portable media device). As a result, such technologies could easily be part of smartphones, tablets, security systems, PCs, gaming technologies, virtual reality, simulation training, etc. All of the foregoing are provided merely as illustrative and non-limiting examples. It is understood that the teachings of this specification can be generally applied to a wide variety of technological fields.

[0067] Features of several embodiments have been discussed above to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or obtain the same advantages of the embodiments presented herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0068] The respective embodiments of the present disclosure may readily include a system chip (SOC), a DSP, a CPU, or a similar device. An SOC represents an integrated circuit (IC) that integrates components of a computer or other electronic system into a single chip. It may include digital, analog, mixed-signal, and radio-frequency functions, all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), wherein a plurality of chips are arranged within a single electronic package and configured to closely interact with each other through the electronic package. In various other embodiments, the digital signal processing functionalities may be implemented in one or more silicon cores in application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and other semiconductor chips.

[0069] In example implementations, at least some portions of the processing activities discussed herein may be implemented in software. In some embodiments, one or more of these features may be implemented in hardware external to the elements of the disclosed figures or may be aggregated in any suitable manner to achieve the intended functionality. The various components may include software (or reciprocating software) that can coordinate to perform the operations discussed herein. In still other embodiments, these elements may include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that enable the operations thereof.

[0070] Furthermore, some of the components associated with described processors may be removed or otherwise consolidated. In a general sense, the arrangements depicted in the figures may be more logical in their representations, while a physical architecture may include various permutations, combinations, and / or hybrids of these elements. It is necessary to note that countless possible design configurations may be used to achieve the operational objectives discussed herein. Accordingly, the associated infrastructure includes a myriad of replacement arrangements, design choices, device options, hardware configurations, software implementations, equipment options, etc.

[0071] Any appropriately configured processor component may execute any type of instructions associated with the data to achieve the operations detailed herein. Any of the processors disclosed herein may transform an element or object (e.g., data) from one state or thing to another state or thing.In another example, some of the activities discussed herein may be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by a processor), and the elements identified herein could be a particular type of processor, programmable digital logic (e.g., a field programmable gate array (FPGA), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM)), an ASIC including digital logic, software, code, electronic instructions, flash memory, optical disks, CD-ROMs, DVD-ROMs, magnetic or optical cards, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof.In operation, processors may store information based on their respective needs in any suitable type of non-transitory storage medium (e.g., random access memory (RAM), read-only memory (ROM), field-programmable gate array (FPGA), erasable programmable read-only memory (EPROM), electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or any other suitable component, device, element, or object, as appropriate. Furthermore, the information tracked, sent, received, or stored in a processor could be provided in any database, register, table, cache, queue, checklist, or memory structure, all of which could be referenced at any suitable timeframe, depending on their respective needs and implementations.Each of the memory elements discussed herein should be construed as encompassed by the general term 'memory'. Similarly, each of the potential processing elements and modules described herein, and each of the potential machines described herein, should be construed as encompassed by the general terms 'microprocessor,' 'digital signal processor,' or 'processor.' Furthermore, the processors, memories, network cards, buses, data storage devices, associated peripherals, and other hardware elements described herein may, in various embodiments, be realized by a processor, memory, and other associated devices configured by software or firmware to emulate or virtualize the functions of those hardware elements.

[0072] Computer program logic that implements all or part of the functionality described herein is embodied in various forms, including, but not limited to, source code form, computer-executable form, and various intermediate forms (e.g., forms generated by an assembler, compiler, linker, or locator). In one example, source code comprises a set of computer program instructions implemented in various programming languages, such as object code, assembly language, or a high-level programming language such as OpenCL, Fortran, C, C++, JAVA, or HTML, for use with various operating systems or operating environments. The source code may define and use various data structures and communication messages. The source code may be in computer-executable form (e.g.,by an interpreter), or the source code may be converted into a computer-executable form (e.g., by a translator, assembler, or compiler).

[0073] In the discussions of the above embodiments, the capacitors, buffers, graphics elements, interconnect boards, clocks, DDRs, camera sensors, dividers, inductors, resistors, amplifiers, switches, digital cores, transistors, and / or other components can be easily swapped, replaced, or otherwise modified to accommodate specific circuitry needs. Furthermore, it should be noted that the use of complementary electronic devices, complementary hardware, non-transitory software, etc., provides an equally viable option for implementing the teachings of the present disclosure.

[0074] In an exemplary embodiment, a number of electrical circuits of the FIGURES may be implemented on a circuit board of an associated electronic device. The circuit board may be a general-purpose printed circuit board that may house various components of the internal electronic system of the electronic device and further provide connectors for other peripherals. More specifically, the circuit board may provide the electrical connections through which the other components of the system may communicate electrically. Any suitable processors (including digital signal processors, microprocessors, supporting chipsets, etc.), memory elements, etc., may be suitably coupled to the circuit board based on respective configuration needs, processing requirements, computer designs, etc.Other components, such as external memory, additional sensors, audio / video display controllers, and peripherals, may be connected to the board as plug-in cards or via cables, or may be integrated into the board itself. In another embodiment, the electrical circuits of the FIGURES may be implemented as stand-alone modules (e.g., a device with associated components and associated circuitry configured to perform a specific application or function) or as plug-in modules in application-specific hardware of electronic devices.

[0075] It should be noted that in the numerous examples provided herein, interaction may be described in terms of two, three, four, or more electrical components. However, this was done solely for clarity and as an example. It should be noted that the system may be consolidated in any suitable manner. Along with similar design alternatives, all of the illustrated components, modules, and elements of the FIGURES may be combined in various possible configurations, all of which fall within the general scope of this specification. In certain cases, it may be easier to describe one or more of the functionalities of a particular set of flows by referencing only a limited number of electrical elements.It is understood that the electrical circuits of the FIGURES and their teachings can be readily scaled to accommodate a large number of components and more complicated / sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or preclude the general teachings of the electrical circuits as potentially applied to a variety of other architectures.

[0076] As an example, a data processing device is disclosed comprising: a first master having a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, wherein the second ordinal QoS profile is of a higher order than the first QoS profile; a slave; a multiplexed interconnect for communicatively coupling the first master and the second master, with the slave according to the first ordinal QoS profile and the second ordinal QoS profile; and one or more logic elements comprising at least one logical hardware element comprising a QoS engine for: determining that the first master has initiated a slave operation over the interconnect; determining that performing the slave operation requires an increased QoS according to a QoS criterion provided by the second master;and promoting the first master to a third ordinal QoS profile with a higher order than the second ordinal QoS profile.;

[0077] Further, an example is disclosed wherein the third ordinal QoS profile is of the same order as the second ordinal QoS profile.

[0078] Further, an example is disclosed wherein the third ordinal QoS profile is of higher order than the first ordinal QoS profile and lower order than the second ordinal QoS profile.

[0079] Further, an example is disclosed wherein determining that performing the slave operation according to the QoS criterion provided by the second master requires increased QoS comprises determining that the slave operation is at risk of not being performed within a deadline.

[0080] Furthermore, an example is disclosed wherein the deadline is provided by the second master.

[0081] Further, an example is disclosed wherein the deadline is selected from the group consisting of a number of processor cycles, a fixed time window, or an instantaneous trigger.

[0082] Further, an example is disclosed wherein promoting the first master to the third ordinal QoS profile comprises the second master explicitly associating the third ordinal QoS profile with the first master.

[0083] Further, an example is disclosed wherein associating the third ordinal QoS profile with the first master comprises notifying the interconnect of the third ordinal QoS profile.

[0084] Further, an example is disclosed wherein notifying the interconnect comprises providing a signal via an out-of-band bus.

[0085] Further, an example is disclosed wherein notifying the interconnect comprises writing to a register.

[0086] Further, an example is disclosed wherein notifying the interconnect comprises triggering an interrupt.

[0087] Further disclosed is an example of a system chip (SoC) comprising: a first master having a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, wherein the second ordinal QoS profile is of a higher order than the first QoS profile; a slave; a network chip (NOC) for communicatively coupling the first master and the second master, the NOC comprising a NOC controller for providing access priority according to the first ordinal QoS profile and the second ordinal QoS profile; and an on-chip QoS engine for: determining that the first master has initiated a slave operation over the interconnect; determining that performing the slave operation requires an increased QoS according to a QoS criterion provided by the second master; and promoting the first master to a third ordinal QoS profile with a higher order than the second ordinal QoS profile.

[0088] Further, an example is disclosed wherein determining that performing the slave operation according to the QoS criterion provided by the second master requires increased QoS comprises determining that the slave operation is at risk of not being performed within a deadline.

[0089] Furthermore, an example is disclosed wherein the second master explicitly assigns the third ordinal QoS profile to the first master.

[0090] An example is further disclosed, further comprising a QoS register receiving the third ordinal QoS profile.

[0091] Further disclosed is an example of a method for providing ordinal quality of service (QoS) enhancement for a data processing system having a first master having a first ordinal QoS profile, a second master having a second ordinal QoS profile, and a multiplexed interconnect for communicatively coupling the first master and the second master to a slave resource having a priority according to the ordinal QoS profiles, comprising: determining that the first master has initiated a slave operation over the interconnect; determining that performing the slave operation requires enhanced QoS according to a QoS criterion provided by the second master; and promoting the first master to a third ordinal QoS profile having a higher order than the second ordinal QoS profile.

[0092] Further, an example is disclosed wherein the third ordinal QoS profile is of the same order as the second ordinal QoS profile.

[0093] Further, an example is disclosed wherein the third ordinal QoS profile is of higher order than the first ordinal QoS profile and lower order than the second ordinal QoS profile.

[0094] Further, an example is disclosed wherein determining that performing the slave operation according to the QoS criterion provided by the second master requires increased QoS comprises determining that the slave operation is at risk of not being performed within a deadline.

[0095] Further, an example is disclosed wherein promoting the first master to the third ordinal QoS profile comprises the second master explicitly associating the third ordinal QoS profile with the first master.

[0096] Further, an example of a method for providing the QoS engine according to any one of the preceding examples is disclosed.

[0097] Furthermore, an example of a device is disclosed which comprises means for carrying out the method.

[0098] Furthermore, an example is disclosed wherein the means comprise a system chip.

[0099] Numerous other changes, substitutions, variations, alterations, and modifications may be devised by those skilled in the art, and this disclosure is intended to embrace all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims. To assist the United States Patent and Trademark Office (USPTO) and readers of any patents issued on this application in interpreting the claims appended hereto, applicant wishes to state that applicant: (a) does not intend any of the appended claims to rely on subsection (f) of 35 USCSection 112 as amended on the date of filing hereof, unless the terms "means of" or "steps of" are expressly used in the respective claims; and (b) is not intended to limit this disclosure by any statements in the specification in any manner not otherwise reflected in the appended claims.

Claims

[1] Data processing device comprising: a first master with a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, the second ordinal QoS profile being of higher order than the first QoS profile; a slave; a multiplexed interconnect for communicatively coupling the first master and the second master with the slave, each with a priority according to the order of the ordinal QoS profile of the respective master; and a QoS machine that is designed to perform the following steps: Determine whether the conditions are met that the first master has initiated a slave operation over the interconnect and that the slave operation is in danger of not being completed within a deadline set by the second master; upon determining that the conditions are met, promoting the first master to a third ordinal QoS profile having a higher order than the second ordinal QoS profile. [2] The data processing apparatus of claim 1, wherein the deadline is selected from the group consisting of a number of processor cycles, a fixed time window, or an instantaneous trigger. [3] A data processing device according to any one of the preceding claims, wherein promoting the first master to the third ordinal QoS profile comprises the second master explicitly associating the third ordinal QoS profile with the first master. [4] The data processing device of claim 3, wherein associating the third ordinal QoS profile with the first master comprises notifying the interconnect of the third ordinal QoS profile. [5] The data processing device of claim 4, wherein notifying the interconnect comprises one or more of: a) Providing a signal via an out-of-band bus; b) writing in a register; c) triggering an interrupt; d) providing a signal concurrently with a transaction to which the ordinal QoS profile applies; and / or e) Notify the slave. [6] System chip (SoC), comprising: a first master with a first ordinal quality of service (QoS) profile; a second master having a second ordinal QoS profile, the second ordinal QoS profile being of higher order than the first ordinal QoS profile; a slave; a network chip (NOC) for communicatively coupling the first master and the second master, wherein the NOC comprises a NOC controller for providing respective access priorities according to the order of the ordinal QoS profile of the respective master; and an on-chip QoS engine that is designed to perform the following steps: Determine whether to meet the conditions, that the first master has initiated a slave operation via the interconnect and that the slave operation is in danger of not being completed within a deadline set by the master; on determining that the conditions to be met, Promote the first master to a third ordinal QoS profile with a higher order than the second ordinal QoS profile. [7] The SoC of claim 6, wherein the second master is for explicitly associating the third ordinal QoS profile with the first master. [8] The SoC of any one of claims 6 to 7, further comprising a QoS register receiving the third ordinal QoS profile. [9] A method for providing ordinal quality of service (QoS) enhancement for a data processing system having a first master with a first ordinal QoS profile, a second master with a second ordinal QoS profile, and a multiplexed interconnect for communicatively coupling the first master and the second master to a slave resource, each with a priority according to the order of the ordinal QoS profile of the respective master, comprising: Determine whether the conditions are met that the first master has initiated a slave operation over the interconnect and that the slave operation is in danger of not being completed within a deadline set by the second master; on determining the conditions to be met, Promote the first master to a third ordinal QoS profile with a higher order than the second ordinal QoS profile. [10] The method of claim 9, wherein promoting the first master to the third ordinal QoS profile comprises the second master explicitly associating the third ordinal QoS profile with the first master.

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