Voltage regulators and methods for compensating the effects of an output impedance

Abstract

Voltage regulator (100) configured to provide an output current at an output voltage at an output node of the voltage regulator (100) based on an input voltage at an input node of the voltage regulator (100); wherein the output node of the voltage regulator (100) is coupled to an output capacitor (106) via a conducting path having a parasitic inductance (211, 212); wherein the output capacitor (106) and the parasitic inductance (211, 212) form an LC circuit with an LC resonant frequency; wherein the voltage regulator (100) comprises - an output amplification stage (103) for deriving the output current at the output node from the input voltage at the input node as a function of a driver voltage at an intermediate node of the voltage regulator (100); - an intermediate amplification stage (102) to provide the driver voltage at the intermediate node based on a differential output voltage; - a differential amplification stage (101) configured to determine the differential output voltage as a function of the output voltage and as a function of a reference voltage (108); - a sensing unit (241) configured to provide a load indication that specifies the output current; and - a variable impedance (242) coupled to the intermediate node; wherein the variable impedance (242) depends on the load specification; wherein the voltage regulator (100) without the variable impedance (242) has a bandwidth and / or a gain bandwidth frequency that increases with increasing output current, such that for an output current at or above a threshold current, the LC resonant frequency falls within the bandwidth and / or is lower than the gain bandwidth frequency; and wherein the variable impedance (242) is configured such that for the voltage regulator (100) with the variable impedance (242) - the LC resonant frequency is higher than the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) at an output current at or above the threshold current; and - the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) with the variable impedance (242) corresponds to the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) without the variable impedance (242) for an output current below the threshold current; wherein - the variable impedance (242) has a capacitor (342) which is arranged in series with a variable resistor (341); - the series arrangement of the capacitor (342) and the resistor (341) is arranged to couple the intermediate node to a reference potential of the voltage regulator (100); and - the variable resistance (341) depends on the load specification.

Description

Technical area

[0001] This document concerns a voltage regulator. In particular, this document concerns a high-bandwidth voltage regulator configured to compensate for the effects of an output impedance. background

[0002] Voltage regulators are commonly used to provide a load or output current at a stable load or output voltage for various types of loads (e.g., for the processors of an electronic device). A voltage regulator derives the output current from an input node of the regulator, while the output voltage at the output node of the regulator is regulated according to a reference voltage.

[0003] A voltage regulator is typically used in conjunction with an output capacitor, which is external to the voltage regulator device and coupled to the output node of the voltage regulator via an electrical and / or conductive path. The load is also coupled to the output of the voltage regulator via an electrical and / or conductive path. The conductive paths at the output of a voltage regulator, particularly the parasitic inductances, can, in conjunction with the output capacitor, affect the stability of the voltage regulator, especially at relatively high load currents.

[0004] US 2002 / 0105382 A1 describes an amplifier with an adjustable zero for stabilizing the amplifier under different load conditions. DE 102016207714 A1 describes a voltage regulator with a current reduction mode. US 6603292 B1 describes a voltage regulator with an adjustable zero. US 2016 / 0266591 A1 describes a voltage regulator with load-dependent frequency compensation. US 9766643 B1 describes a voltage regulator with stability compensation. US 2007 / 0159146 A1 describes a voltage regulator with a switching arrangement for stability compensation. US 7843180 B1 describes a voltage regulator with frequency compensation. US 2001 / 0028240A1 describes a voltage regulator with a load-independent step response. US 2007 / 0216382A1 describes a voltage regulator with a compensation arrangement. EP 2520998A1 describes a voltage regulator with load-dependent compensation.US 2017 / 0090494A1 describes a voltage regulator with a compensation network. US 2010 / 0201332A1 describes a voltage regulator with adaptive compensation.

[0005] This document addresses the technical problem of improving the stability of a voltage regulator in the presence of parasitic inductances at the regulator's output. This problem is solved by the subject matter of independent claim 1 and by the method of independent claim 13. Advantageous embodiments are described in the dependent claims. Summary

[0006] The invention describes a voltage regulator, in particular an LDO (linear dropout) voltage regulator. The voltage regulator is configured to provide an output current (here also referred to as load current) at an output voltage at an output node of the voltage regulator based on an input voltage at an input node of the voltage regulator.

[0007] The output node of the voltage regulator is coupled to an output capacitor via a conducting path containing parasitic inductance. The output capacitor and the parasitic inductance form an LC circuit with an LC resonant frequency. This LC circuit can affect the stability of the voltage regulator, especially at relatively high output currents (e.g., 1 A, 1.5 A, or more). The voltage regulator typically exhibits a specific bandwidth and / or gain bandwidth (GBW) frequency. The bandwidth and / or GBW frequency typically increases with increasing output current. At relatively high output currents, for example, output currents at or above a predetermined threshold current, the LC resonant frequency may fall within the bandwidth and / or be lower than the voltage regulator's GBW frequency.In particular, the resonance of the LC circuit can lead to a bandwidth expansion of the voltage regulator for the output current, which occurs at or above the threshold current. The threshold current may depend on the LC resonant frequency. The bandwidth expansion caused by the parasitic inductance can affect the stability of the voltage regulator (especially for output currents at or above the threshold current).

[0008] The voltage regulator includes an output gain stage to derive the output current at the output node from the input voltage at the input node, as a function of a driver voltage at an intermediate node of the voltage regulator. The output gain stage typically includes a forward transistor that couples the input node to the output node. By controlling the forward transistor (via its gate), the level of the output current and / or output voltage can be set. The output gain stage typically has a frequency-dependent gain that depends on the level of the output current. The roll-off frequency of the frequency-dependent gain (and consequently the bandwidth of the output gain stage) typically increases with increasing output current level.

[0009] Furthermore, the voltage regulator includes at least one intermediate amplification stage to provide the driver voltage at the intermediate node based on a differential output voltage. The intermediate amplification stage typically has a frequency-dependent gain, whereby the roll-off frequency of the intermediate amplification stage's gain can be higher than the roll-off frequency of the output amplification stage's gain (at least for output currents below the threshold current).

[0010] Furthermore, the voltage regulator features a differential gain stage configured to determine the differential output voltage as a function of the output voltage and as a function of a reference voltage. The voltage regulator is typically configured to set the output voltage as a function of the reference voltage. For this purpose, the voltage regulator may include a feedback network (e.g., a voltage divider) configured to provide a feedback voltage that is dependent on the output voltage (e.g., proportional to it). The differential gain stage can be configured to determine the differential output voltage as a function of the feedback voltage and as a function of the reference voltage (specifically, as a function of the difference between the feedback voltage and the reference voltage).

[0011] The differential gain stage typically has a frequency-dependent gain with a specific roll-off frequency. Thus, the voltage regulator typically has a frequency-dependent overall gain, which is the result of superimposing the gains of the differential gain stage, the one or more intermediate gain stages, and the output gain stage. This frequency-dependent overall gain typically defines the stability of the voltage regulator. In particular, the bandwidth and / or the GBW frequency of this frequency-dependent overall gain can define the stability of the voltage regulator.

[0012] The voltage regulator includes a sensing unit configured to provide a load signal indicating the output current. The sensing unit may include one or more current mirrors configured to reflect the output current through the forward transistor to provide the load signal. The load signal may be a current and / or voltage proportional to the output current.

[0013] Furthermore, the regulator features a variable impedance coupled to the intermediate node. This allows the effective impedance of the voltage regulator at the intermediate node to be modified by the variable impedance. In particular, the variable impedance can be used to modify the frequency of one pole of the intermediate amplification stage (especially for relatively high output currents at or above the threshold voltage).

[0014] The variable impedance, and in particular its magnitude, depends on the load specification. Specifically, the variable impedance can be such that its magnitude is relatively low when the load specification indicates a relatively high output current (e.g., at or above the threshold current). Conversely, the impedance magnitude can be relatively high when the load specification indicates a relatively low output current (e.g., below the threshold current). In a preferred example, the load current dependence and / or the magnitude of the variable impedance are set based on the LC resonant frequency.

[0015] Thus, a voltage regulator can be provided that is configured to modify the frequency of one pole of an intermediate gain stage of the voltage regulator depending on the output current. This ensures the stability of the voltage regulator even if it is affected by an LC resonance at the output node. Due to the load-dependent adaptation of the pole of the intermediate gain stage, stability can be achieved in a power-efficient manner (without significantly increasing the quiescent current of the voltage regulator).

[0016] As stated above, the intermediate amplification stage typically exhibits a gain bandwidth. The bandwidth of the intermediate amplification stage is typically defined by the frequency of one pole of the intermediate amplification stage. The variable impedance can be configured such that the gain bandwidth is reduced when the load specification indicates a relatively high output current (e.g., an output current at or above the threshold current). Alternatively or additionally, the variable impedance can be configured such that the gain bandwidth remains unaffected when the load specification indicates a relatively low output current (e.g., an output current below the threshold current).

[0017] Alternatively or additionally, the intermediate amplification stage can have a pole (which typically affects the gain bandwidth of the intermediate amplification stage). The variable impedance can be configured such that a pole frequency is reduced when the load specification indicates a relatively high output current (e.g., an output current at or above the threshold current). Alternatively or additionally, the variable impedance can be configured such that the pole frequency remains unaffected when the load specification indicates a relatively low output current (e.g., an output current below the threshold current).

[0018] Therefore, the variable impedance can be used to modify the frequency-dependent gain of the intermediate amplification stage depending on the output current, especially for relatively high output currents, e.g., output currents at or above the threshold current. In this way, the stability of the voltage regulator can be ensured in a power-efficient manner, particularly for relatively high output currents.

[0019] As stated above, the output capacitor and parasitic inductance can form an LC circuit with an LC resonant frequency. The voltage regulator without the variable impedance (i.e., the voltage regulator without the effect of the variable impedance) has a bandwidth and / or a gain bandwidth frequency that increases with increasing output current. Therefore, for an output current at or above the threshold current, the LC resonant frequency falls within the bandwidth and / or the LC resonant frequency is lower than the gain bandwidth frequency. Thus, the resonant gain caused by the LC circuit can lead to a bandwidth expansion of the voltage regulator without the variable impedance (at least for output currents at or above the threshold current).

[0020] On the other hand, for output currents below the threshold current, the LC resonant frequency can be higher than the bandwidth and / or higher than the gain bandwidth frequency of the voltage regulator without the variable impedance. Therefore, the voltage regulator is not (significantly) affected by the LC circuit for output currents below the threshold current.

[0021] The variable impedance is configured such that, for the voltage regulator with the variable impedance, the LC resonant frequency is higher than the bandwidth and / or the gain bandwidth frequency of the voltage regulator at an output current at or above the threshold current. Thus, the variable impedance can reduce the bandwidth and / or the gain bandwidth frequency of the voltage regulator to such an extent that the LC resonant frequency no longer falls within the bandwidth of the voltage regulator, and / or such that the LC resonant frequency is higher than the GBW frequency of the voltage regulator (e.g., by 10%, 20%, or more). This ensures stability for relatively high output currents.

[0022] Furthermore, the variable impedance is such that the bandwidth and / or gain bandwidth frequency of the voltage regulator with the variable impedance (essentially) corresponds to the bandwidth and / or gain bandwidth frequency of the voltage regulator without the variable impedance for an output current below the threshold current. In particular, the deviation for output currents below the threshold current can be 10%, 5%, or less. This allows stability and power efficiency to be maintained for relatively low output currents.

[0023] Alternatively or additionally, the voltage regulator without the variable impedance can have a frequency-dependent (open-loop) gain for an output current at or above the threshold current, with the frequency-dependent gain having a peak around the LC resonant frequency. In other words, the LC circuit at the output node of the voltage regulator can introduce a peak in the frequency-dependent (open-loop) gain of the voltage regulator, resulting in a bandwidth expansion for output currents at or above the threshold current.

[0024] The variable impedance can be configured such that the (open-loop) gain of the voltage regulator with the variable impedance has a reduced peak or no peak at all around the LC resonant frequency for an output current at or above the threshold current. In other words, the variable impedance can attenuate or remove the peak caused by the LC circuit, thereby (at least partially) eliminating the bandwidth expansion caused by the LC circuit. The peak can be reduced by 10%, 20%, or more. By reducing the peak caused by the LC circuit, reliable stability of the voltage regulator can be ensured.

[0025] Alternatively or additionally, the variable impedance can be configured such that the (open-loop) gain of the voltage regulator with the variable impedance is (essentially) equal to the (open-loop) gain of the voltage regulator without the variable impedance for an output current below the threshold current. In particular, the deviation can be 10%, 5%, or less for output currents below the threshold current. This allows stability and power efficiency to be maintained for relatively low output currents.

[0026] The variable impedance circuit features a capacitor connected in series with a variable resistor. The variable resistor can be at least partially controlled by a control transistor with a variable input resistance. The control transistor can be steered based on the load, thus efficiently and reliably controlling the variable resistor and the resulting impedance. The variable resistor is dependent on the load.

[0027] The capacitance of the capacitor and / or the resistance value of the variable resistor (e.g., the aspect ratio of the control transistor) can be chosen depending on the LC resonant frequency to ensure reliable compensation of the effects of the LC circuit at relatively high output currents.

[0028] The variable resistance can depend on the load specification. The variable resistance can be relatively low if the load specification indicates a relatively high output current (e.g., at or above the threshold current). Alternatively or additionally, the variable resistance can be relatively high if the load specification indicates a relatively low output current (e.g., below the threshold current). In this way, the stability of the voltage regulator can be ensured reliably and efficiently.

[0029] The series arrangement of the capacitor and resistor is designed to couple the intermediate node to a reference potential of the voltage regulator, specifically ground. Typically, the input and output voltages are also relative to the voltage regulator's reference potential. This allows the overall impedance at the output of the intermediate amplification stage to be reliably controlled and / or adjusted to ensure the stability of the voltage regulator at relatively high output currents.

[0030] The output amplification stage can include a driver transistor that forms a current mirror with the forward transistor. The output current can correspond to the current through the forward transistor. Furthermore, the output amplification stage can include a first transistor connected in series with the driver transistor, which forms a current mirror with a second transistor. Additionally, the output amplification stage can include a third transistor, controlled based on the driver voltage at the intermediate node, which is connected in series with the second transistor. The transistors can be metal-oxide-semiconductor (MOS) field-effect transistors (FETs). The load rating can depend on, and in particular correspond to, a voltage level at the gates of the first and second transistors. This allows for precise and efficient control of the output current.

[0031] The gate of the control transistor can be coupled to the gates of the first and second transistors to control the variable resistance and / or the variable impedance based on the load specification. This allows the variable impedance to be reduced with increasing output current and / or increased with decreasing output current.

[0032] The sensing unit can include a sensing transistor with a gate coupled to the gates of the first and second transistors and connected in series with a sensing resistor. The gate of the control transistor can be coupled to a midpoint between the sensing transistor and the sensing resistor. The value of the sensing resistor can be used to set the threshold current. By using a sensing transistor and a sensing resistor, the influence of the variable impedance on the voltage regulator, particularly on the open-loop gain and / or the GBW frequency, can be set relatively abruptly for output currents at or above the threshold current. As a result, the stability of the voltage regulator can be ensured at relatively high output currents, while the behavior of the voltage regulator remains unaffected for output currents below the threshold current.

[0033] According to the invention, a method for operating a voltage regulator is described. In particular, a method for compensating for the effects of a parasitic inductance at an output of the voltage regulator is described. As described in this document, the voltage regulator is configured to provide an output current at an output voltage at an output node of the voltage regulator based on an input voltage at an input node of the voltage regulator. The output node of the voltage regulator is coupled to an output capacitor via a conducting path that exhibits the parasitic inductance. The voltage regulator includes an output gain stage for deriving the output current at the output node from the input voltage at the input node as a function of a driver voltage at an intermediate node of the voltage regulator.Furthermore, the voltage regulator includes an intermediate gain stage for providing the driver voltage at the intermediate node based on a differential output voltage. Additionally, the voltage regulator includes a differential gain stage configured to determine the differential output voltage as a function of the output voltage and a reference voltage. The method includes determining a load specification that defines the output current. Furthermore, the method includes setting an impedance at the intermediate node based on the load specification.

[0034] The voltage regulator without the variable impedance has a bandwidth and / or a gain bandwidth frequency at the intermediate node that increases with increasing output current, such that for an output current at or above a threshold current, the LC resonant frequency falls within the bandwidth and / or is lower than the gain bandwidth frequency. The variable impedance is set such that for the voltage regulator with the variable impedance • the LC resonant frequency is higher than the bandwidth and / or the gain bandwidth frequency of the voltage regulator at an output current at or above the threshold current; and the bandwidth and / or the gain bandwidth frequency of the voltage regulator with the variable impedance corresponds to the bandwidth and / or the gain bandwidth frequency of the voltage regulator without the variable impedance for an output current below the threshold current.

[0035] The variable impedance circuit features a capacitor connected in series with a variable resistor. This series arrangement couples the intermediate node to a reference potential of the voltage regulator, and the variable resistor's resistance depends on the load.

[0036] In this document, the term “couple” or “coupled” refers to elements that are electrically connected to each other, whether directly connected, e.g. via wires, or in some other way. Brief description of the characters

[0037] The invention is explained below by way of example with reference to the accompanying drawings, wherein Fig. 1a (state of the art) shows an exemplary block diagram of an LDO controller; Fig. 1b (state of the art) shows the exemplary block diagram of an LDO controller in more detail; Fig. Figure 2a shows exemplary parasitic inductances at the output of a voltage regulator; Fig. 2b shows an exemplary block diagram of a compensation loop for compensating the effects of a parasitic inductance; Fig. Figure 2c shows an example of a controllable impedance for a compensation loop; Fig. Figure 2d shows an example of a current-dependent quantity of a controllable impedance; Fig. 3a shows an example voltage regulator with a compensation loop; Fig. 3b shows the phase margin of a voltage regulator with a compensation loop; Fig. Figure 4 shows another exemplary voltage regulator with a compensation loop; Fig. 5 shows the gain and phase effect of a compensation loop on the overall gain and phase of a voltage regulator; Fig. 6a shows the frequency-dependent gains of the differential gain stages of a voltage regulator; Fig. 6b shows the overall gain of a voltage regulator with a compensation loop; and Fig. Figure 7 shows a flowchart of an exemplary procedure for compensating and / or reducing the effects caused by a parasitic inductance at the output of a voltage regulator. Detailed description

[0038] As stated above, this document concerns the provision of a power-efficient and stable voltage regulator, even when a parasitic inductance is present at the regulator's output. An example of a voltage regulator is an LDO regulator. A typical 100 Ω LDO regulator is in Fig. Figure 1a shows the LDO regulator 100. It has an output gain stage or output stage 103, which may include a field-effect transistor (FET), at the output and a differential or first gain stage 101 (also called an error amplifier) ​​at the input. A first input (fb) 107 of the differential gain stage 101 receives a portion of the output voltage V. OUT , determined by the voltage divider 104, which has resistors R0 and R1. The second input (ref) of the differential gain stage 101 is a stable voltage reference V ref 108 (also known as the bandgap reference). When the output voltage V OUT relative to the reference voltage V ref(or to a setpoint voltage proportional to the reference voltage), the driver voltage to the output gain stage, e.g., to the power FET, changes through a feedback mechanism called the main feedback loop to maintain a constant output voltage V. OUT to maintain.

[0039] The LDO controller 100 from Fig. 1a further features an additional intermediate amplification stage 102, which is configured to amplify the differential output voltage of the differential amplification stage 101. An intermediate amplification stage 102 can be used to provide additional gain within the amplification path. Furthermore, the intermediate amplification stage 102 can provide phase inversion.

[0040] Furthermore, the LDO regulator 100 is typically used in conjunction with an output capacitance C. out(also called output capacitor or stabilizing capacitor) 105 used in parallel with the load 106.

[0041] The output capacitor 105 is used to adjust the output voltage V OUT to stabilize, depending on a change in load 106, in particular depending on a change in the requested load current or the output current I load / I OUT The capacitor value or capacitance of the output capacitor 105 can be selected depending on the application.

[0042] Fig. Figure 1b shows the block diagram of an LDO regulator 100, with the output gain stage 103 shown in more detail. In particular, the pass transistor or pass device 201 and the driver stage 110 of the output gain stage 103 are shown. Typical parameters of an LDO regulator 100 are a supply voltage of 3V, an output voltage of 2V, and an output or load current in the range of 1 mA to 100 or 200 mA, and even up to very high output currents of 1A, 1.5A, or more. Other configurations are possible.

[0043] The connection between the output capacitor 105 and the output terminal of a voltage regulator 100 is typically implemented at the circuit board level, leading to parasitic inductances in the signal path in series with the output capacitor 105. A typical equivalent circuit for such a situation is shown in Fig. 2a shown. In particular, it shows Fig. 2a the parasitic inductances 211, 212 and the resistances 221, 222 of the conducting paths for coupling the output capacitor 105 and the load 106 with the output node of the voltage regulator 100.

[0044] When using a voltage regulator 100 for relatively high output currents and a relatively high bandwidth, the LC resonant frequency of the LC circuit, generated by the parasitic inductances 221, 222 (in conjunction with the output capacitor 105), can fall within the gain bandwidth (GWB) frequency of the voltage regulator 100 at relatively high output currents (e.g., 1 A, 1.5 A, or more). This LC resonance degrades the phase margin to such an extent that the voltage regulator 100 can become unstable. In particular, the GWB frequency of the resulting voltage regulator 100 (including the LC circuit) can be pushed to much higher frequencies due to the resonance peaks, thereby reducing the stability ranges.

[0045] This document concerns improving the stability of a voltage regulator 100 at very high load currents while minimizing the current and / or power consumption of the voltage regulator 100. In particular, a method for modifying one or more poles and / or zero positions (i.e., frequencies) of the voltage regulator 100 is described to manage the external LC resonant frequency contribution and to increase the phase margin.

[0046] One possible solution for stabilizing the voltage regulator 100 is to design it so that the internal poles are driven to the highest possible frequency. However, given that the GBW frequency can become very high, this is typically not achievable with reasonable quiescent current consumption and / or power efficiency for the voltage regulator 100.

[0047] Stability and power efficiency in combination can be achieved by controlling the position (i.e., the frequency) of an internal pole of the voltage regulator 100, in particular a pole that is located at a relatively high frequency, depending on the load conditions (in particular, load current) of the voltage regulator 100.

[0048] For light and medium load currents, the LC resonant frequency of the LC circuit at the output of voltage regulator 100 is typically higher than the GBW frequency of voltage regulator 100. Consequently, the LC resonant frequency does not affect the stability of voltage regulator 100. Thus, the pole and / or zero configuration of voltage regulator 100 can remain unchanged for light and medium load currents. In particular, all non-dominant poles of voltage regulator 100 can be maintained at their maximum frequency.

[0049] On the other hand, for high load currents (at or above a threshold current), the effect of LC resonance on the stability of the voltage regulator 100 can be compensated by shifting at least one of the internal poles of the voltage regulator 100 to lower frequencies. As a result, the shifted pole causes a steeper roll-off of the overall gain of the voltage regulator 100, thereby at least partially compensating for the zero-effect of LC resonance.

[0050] Thus, the voltage regulator 100 can have means for controlling the frequency and / or the position of an internal pole of the voltage regulator 100 depending on the load current. In this way, the stability of the voltage regulator 100 can be achieved in a power-efficient manner.

[0051] The frequency of an internal pole of the voltage regulator 100 can be controlled by loading the output of an internal stage 205 of the voltage regulator 100 (e.g. the output of the intermediate stage 102) with a voltage- and / or current-controlled impedance element. Fig. Figure 2b shows a compensation loop comprising a current sensing unit 230 configured to provide a load indication of the load current at the output of the voltage regulator 100. The compensation loop further includes an impedance control unit 240 for controlling an impedance at the output of the internal stage 205 of the voltage regulator 100. Additionally, Figure 2b shows... Fig. 2b the feedback loop for feeding the output voltage of the voltage regulator 100 back to the input of the differential amplification stage 101 using a feedback network 206 (featuring, for example, the voltage divider 104).

[0052] Fig. Figure 2c shows the impedance control unit 240 in more detail. In particular, the impedance control unit 240 can have a driver unit 241 which is configured to set (the size of) a variable impedance 242 depending on the load specification. Fig. Figure 2d shows an example curve 244 of the variable impedance 242 (of size 243) as a function of the load current. The impedance 242 (of size 243) drops at a threshold current, thereby reducing the overall gain of the voltage regulator 100 to compensate for the effects of LC resonance at the output of the voltage regulator 100. The threshold current typically depends on the LC resonant frequency of the LC circuit at the output of the voltage regulator 100. In other words, the curve 244 of the variable impedance 242 (of size 243) is typically designed to be dependent on the LC resonant frequency.

[0053] The compensation loop typically includes a sensing circuit or unit 230 for sensing the output and / or load current of the voltage regulator 100. This circuit 230 can provide a load specification (e.g., a current and / or a voltage) that is proportional to the load current. The load specification can be used to control the frequency of an internal pole of the voltage regulator 100 as a function of the load current.

[0054] Furthermore, the compensation loop can include a driver 241 for controlling the variable impedance 242. The driver 241 can convert the load input into a signal that controls the impedance 242.

[0055] Additionally, the compensation loop can have a voltage- and / or current-controlled impedance 242. The impedance 242 (value 243) can be relatively high for relatively low and / or moderate load currents so as not to affect the loop dynamics of the voltage regulator 100. Conversely, the impedance 242 (value 243) can be low for relatively high load currents to modify the internal pole of the voltage regulator 100.

[0056] Fig. Figure 3a shows an exemplary circuit diagram of a voltage regulator 100 with an NMOS forward transistor 201, for which the bandwidth can be extremely high at high load currents. It should be noted that the diagrams presented in this document are also applicable to other types of voltage regulators 100.

[0057] The driver stage 110 of the voltage regulator 100 includes a driver transistor 301 for driving the forward transistor 201, with the driver transistor 301 and the forward transistor 201 forming a current mirror. Furthermore, the driver stage 110 includes transistors 302, 303, and 304 for coupling the input of the driver stage 110 (and the output of the intermediate amplifier stage 102) to the driver transistor 301 using a (PMOS) current mirror 302, 303 formed by the transistors. The current through the driver transistor 301 is proportional to the load current. Due to the fact that the driver transistor 301 and transistor 302 are arranged in series, the current through the first transistor 302 is typically indicative (e.g., proportional) of the load current. Thus, by using a control transistor 341, which forms a (PMOS) current mirror with the first transistor 302, a load specification can be provided at the control transistor 341.

[0058] Thus, the gate voltage of the Pdrive stage (buffer) can be used to drive the variable on-resistance of a control transistor 341 to provide a load indication. Since the current through the PMOS current mirror is typically proportional to the load current, the voltage at the Pgate contains information about the load current and can be used to control the on-resistance Ron of a PMOS device, i.e., the control transistor 341.

[0059] When the load is relatively low, the Pgate voltage is close to the supply voltage, and the on-resistance Ron of the control transistor 341 Mres is relatively high. In this state, the capacitor 342 (which forms the controllable impedance 242) is practically isolated from the output node, and the frequency response of the voltage regulator 100 loop is unaffected. However, as the load increases, Pgate decreases, and the on-resistance Ron of the control transistor 341 Mres also decreases, thus connecting the capacitor 342 to the loop via the control transistor 341 Mres. As a result, the pole of the second and / or intermediate gain stage 102 shifts to a lower frequency, thereby (at least partially or completely) compensating for the peak generated by the LC resonant frequency.

[0060] Fig. Figure 3b shows the phase margin of voltage regulator 100 as a function of the load current (from 1 µA to 1.5 A) for voltage regulator 100 without a compensation loop (curve 361) and for voltage regulator 100 with a compensation loop (curve 362). It can be seen that the phase margin is higher for relatively high load currents, while the current consumption of voltage regulator 100 remains unchanged. In fact, the voltage regulator 100 consumes... Fig. The implementation of the compensation loop shown in 3a does not produce a DC current.

[0061] The compensation loop of Fig. 3a provides a relatively smooth variation of the on-resistance Ron of the control transistor 341. As a result, the phase margin of the voltage regulator 100 can be reduced for medium load currents, for which the LC resonant frequency is at higher frequencies than the bandwidth of the voltage regulator 100, so that the stability of the voltage regulator 100 is not affected. A modification of the behavior of the voltage regulator 100 caused by the variable impedance 242 may be undesirable for medium load currents.

[0062] Fig. Figure 4 shows a voltage regulator 100 with a compensation loop that controls the on-resistance Ron of the control transistor 341 in a relatively steep manner to avoid degradation of the phase margin at medium load currents. Steep control of the gate of the control transistor 341 can be used to provide a high impedance 242 when compensation is not required (at load currents below the threshold current), and a low impedance 242 when the LC resonance affects the stability of the voltage regulator 100 (at load currents at or above the threshold current).

[0063] The load current is detected using a replicating device 343 (also referred to here as a sensing transistor), which mirrors the current flowing through the Pdrive transistor 303 (this current being typically proportional to the load current) to a sensing resistor 344. The division ratio of the current mirror formed by transistors 303 and 343 is preferably relatively high to reduce the power dissipation by the sensing resistor 344. Given that the current through the sensing resistor 344 is proportional to the load current, the efficiency of the voltage regulator 100 is only minimally affected for all possible load currents.

[0064] Depending on the level of the load current, a specific voltage drop is generated across the sensing resistor 344. This voltage drop only changes the on-resistance Ron of the control transistor 341 if the voltage drop exceeds the threshold voltage of the control transistor 341. The compensation loop of Fig. 4 leads to a relatively abrupt transition between the compensation and non-compensation modes, thereby reducing the effect of the compensation loop at moderate load currents.

[0065] The compensation loop can be adapted to different values ​​of the parasitic inductance 211, 212 by adjusting the value of the capacitor 342 and / or by adjusting the aspect ratio of the control transistor 341 depending on the value of the parasitic inductance 211, 212. Thus, the voltage regulator 100 can be stabilized for different parasitic inductance conditions in a flexible and efficient manner.

[0066] As explained in this document, high-current voltage regulators 100, especially LDOs, can have a very large bandwidth and can be very sensitive to the parasitic behavior of passive components. In particular, a parasitic inductance 211, 212 can generate an LC resonance in conjunction with the output capacitor 106, thereby degrading the stability of the voltage regulator 100 if the LC resonance frequency falls within the bandwidth of the voltage regulator 100 (which can occur at relatively high load currents).

[0067] This document describes a high-bandwidth voltage regulator 100, wherein the output node of the voltage regulator 100 is coupled to an output inductor 211, 212 and an output capacitor 106, which can generate an LC resonance within the bandwidth of the voltage regulator 100. The voltage regulator 100 has a sensing unit 230 configured to detect the output current of the voltage regulator 100 in order to provide a load specification that indicates the output current. Furthermore, the voltage regulator 100 has an impedance 242 which can be controlled depending on the load specification, in particular depending on a current and / or voltage that is proportional to the output current. Additionally, the voltage regulator 100 has an internal gain stage 102 with a relatively high impedance.The bandwidth of this internal gain stage 102 can be controlled using the variable and / or controllable impedance 242. This allows the voltage regulator 100 to be stabilized even for very high load currents in the presence of relatively large parasitic inductances 211, 212. This can be achieved without significantly increasing the current consumption and without significantly affecting the power efficiency of the voltage regulator 100.

[0068] Fig. Figure 5 shows the open-loop gain of a voltage regulator 100 (size 501 and phase 502). Further, it shows Fig. 5. The contribution of impedance 242 (size 503 and phase 504). It is evident that due to impedance 242, the magnitude of the overall gain of the voltage regulator 100 decreases and the phase margin for relatively high load currents is increased, thereby increasing the stability of the voltage regulator 100.

[0069] The effect of the compensation loop on the stability of the voltage regulator 100 is further discussed in the Fig. 6a and Fig. Figure 6b shows the voltage regulator 100 having a differential (first) gain stage 101, an output (e.g., a third) gain stage 103, and one or more intermediate (e.g., second) gain stages 102. Fig. Figure 6a (1) shows the magnitude of the gain of the differential gain stage 101 (first), the magnitude of the gain of the intermediate gain stage 102 (second), and the magnitude of the gain of the output stage 103 (third) as a function of frequency for a voltage regulator 100 without a compensation loop. The frequency diagram of the magnitude of the gain of the output stage 103 typically depends on the load current. In particular, the roll-off of the magnitude of the gain of the output stage 103 typically increases with increasing load current.

[0070] At very high load currents (e.g., 1 A, 1.5 A or more), the voltage regulator 100 can be affected by an LC resonance of an LC circuit at the output of the voltage regulator 100. This can lead to a bandwidth expansion of the output gain stage 103, as shown in Fig. Figure 6a (2) illustrates this. This bandwidth extension can affect the stability of the voltage regulator 100 at high load currents (e.g. at or above the threshold current).

[0071] As in the Fig. 6a (1) and Fig. As shown in Figure 6a (2), the bandwidth of an intermediate stage 102 is typically relatively high. The compensation loop described in this document is configured to reduce the bandwidth of the intermediate stage 102 (by reducing the frequency of one pole of the intermediate stage 102). This is achieved by the Fig. The arrow shown in Figure 6a (3) illustrates this. As a result, the bandwidth expansion caused by the LC resonance can be (at least partially) compensated, thereby increasing the stability of the voltage regulator 100 at high load currents (e.g., at or above the threshold current).

[0072] Fig. Figure 6b shows the magnitude of the total gain of a voltage regulator 100. In particular, it shows Fig. 6b (1) the total gain for a voltage regulator 100 with an ideal capacitive load. Fig. Figure 6b (2) shows the overall gain for a voltage regulator 100 with uncontrolled bandwidth expansion caused by an LC resonance (i.e., a non-ideal output capacitor 106). Additionally, it shows Fig. 6b (3) the overall gain for a voltage regulator 100 which uses a compensation loop as described in this document. The compensation loop controls the pole of an intermediate gain stage 102 to compensate for the effects of LC resonance at the output of the voltage regulator 100.

[0073] Fig.Figure 7 shows a flowchart of an exemplary method 700 for compensating and / or reducing the effects of a parasitic inductance 211, 212 at an output of a voltage regulator 100, in particular an LDO. The voltage regulator 100 is configured to provide an output current at an output voltage at an output node of the voltage regulator 100 based on an input voltage at an input node of the voltage regulator 100. The input voltage can be provided, for example, by a rechargeable battery. The voltage regulator 100 can include a forward transistor 201, which is controlled using a feedback loop. The input node can correspond to an input terminal (e.g., a source or a drain) of the forward transistor 201, and the output node can correspond to an output terminal (e.g., a drain or a source) of the forward transistor 201.The forward transistor 201 (especially the gate of the forward transistor 201) can be controlled such that the output node is at a predetermined output voltage. The output node of the voltage regulator 100 can be coupled to an output capacitor 106 via a conducting path that has the parasitic inductance 211, 212. Thus, the voltage regulator 100 can be coupled to an LC circuit that has an LC resonant frequency. This LC circuit can affect the stability of the voltage regulator 100, especially at relatively high output (i.e., load) currents. Method 700 can be used to reduce the effects of this LC circuit on the performance and / or stability of the voltage regulator 100.

[0074] The voltage regulator 100 has an output gain stage 103 for deriving the output current at the output node from the input voltage at the input node as a function of a driver voltage at an intermediate node of the voltage regulator 100. The intermediate node can correspond to the input of the output gain stage 103 and / or the output of an intermediate gain stage 102.

[0075] The output gain stage 103 typically includes the forward transistor 201 and a driver stage 110 for the forward transistor 201. The output gain stage 103 can be configured to provide frequency-dependent gain. The gain can depend on the output current. Typically, the roll-off frequency of the frequency-dependent gain of the output gain stage 103 increases with increasing output current. Additionally, the LC circuit at the output of the voltage regulator 100 can cause a bandwidth extension of the frequency-dependent gain of the output gain stage 103 for relatively high output currents (at or above the threshold current).

[0076] Furthermore, the voltage regulator 100 includes one or more intermediate gain stages 102 for providing the driver voltage at the intermediate node based on a differential output voltage. Each intermediate gain stage 102 can be configured to provide frequency-dependent gain. The roll-off frequency of the gain (i.e., the frequency of one pole) of an intermediate gain stage 102 can be higher than the roll-off frequency of the gain (i.e., the frequency of one pole) of the output gain stage 103 (at least for output currents below the threshold current).

[0077] Furthermore, the voltage regulator 100 has a differential gain stage 101, which is configured to determine the differential output voltage as a function of the output voltage and as a function of a reference voltage 108. By using a feedback network 206 (e.g., a voltage divider 104), a feedback voltage 107 can be derived from the output voltage. The differential gain stage 101 can be configured to derive the differential output voltage based on (the difference between) the feedback voltage 107 and the reference voltage 108, in order to set the output voltage as a function of the reference voltage 108.

[0078] Method 700 includes determining 701 a load specification that indicates the output current. The load specification can be determined using one or more current mirrors that reflect the output current. Furthermore, method 700 includes setting 702 (a value) of an impedance 242 at the intermediate node based on the load specification. In particular, the impedance 242 at the intermediate node can be reduced for relatively high output currents. On the other hand, the impedance 242 at the intermediate node can remain unchanged for relatively low output currents (i.e., it can correspond to the impedance of the intermediate gain stage 102). This allows the effects of a parasitic inductance 211, 212 to be at least partially compensated without (significantly) affecting the power efficiency of the voltage regulator 100.

Claims

[1] Voltage regulator (100) configured to provide an output current at an output voltage at an output node of the voltage regulator (100) based on an input voltage at an input node of the voltage regulator (100); wherein the output node of the voltage regulator (100) is coupled to an output capacitor (106) via a conducting path having a parasitic inductance (211, 212); wherein the output capacitor (106) and the parasitic inductance (211, 212) form an LC circuit with an LC resonant frequency; wherein the voltage regulator (100) comprises - an output amplification stage (103) for deriving the output current at the output node from the input voltage at the input node as a function of a driver voltage at an intermediate node of the voltage regulator (100); - an intermediate amplification stage (102) to provide the driver voltage at the intermediate node based on a differential output voltage; - a differential amplification stage (101) configured to determine the differential output voltage as a function of the output voltage and as a function of a reference voltage (108); - a sensing unit (241) configured to provide a load indication that specifies the output current; and - a variable impedance (242) coupled to the intermediate node; wherein the variable impedance (242) depends on the load specification; wherein the voltage regulator (100) without the variable impedance (242) has a bandwidth and / or a gain bandwidth frequency that increases with increasing output current, such that for an output current at or above a threshold current, the LC resonant frequency falls within the bandwidth and / or is lower than the gain bandwidth frequency; and wherein the variable impedance (242) is configured such that for the voltage regulator (100) with the variable impedance (242) - the LC resonant frequency is higher than the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) at an output current at or above the threshold current; and - the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) with the variable impedance (242) corresponds to the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) without the variable impedance (242) for an output current below the threshold current; wherein - the variable impedance (242) has a capacitor (342) which is arranged in series with a variable resistor (341); - the series arrangement of the capacitor (342) and the resistor (341) is arranged to couple the intermediate node to a reference potential of the voltage regulator (100); and - the variable resistance (341) depends on the load specification. [2] The voltage regulator (100) according to claim 1, wherein the variable impedance (242) is such that - a quantity (243) of the impedance (242) is relatively low when the load specification indicates a relatively high output current; and - the magnitude (243) of the impedance (242) is relatively high when the load specification indicates a relatively low output current. [3] The voltage regulator (100) according to a preceding claim, wherein a load current dependency and / or a quantity (243) of the variable impedance (242) is set based on the LC resonant frequency. [4] The voltage regulator (100) according to a preceding claim, wherein - the intermediate amplification stage (102) has a gain bandwidth; and - the variable impedance (242) is such that - the gain bandwidth is reduced when the load specification indicates a relatively high output current; and - the gain bandwidth remains unaffected if the load specification indicates a relatively low output current. [5] The voltage regulator (100) according to a preceding claim, wherein - the intermediate amplification stage (102) has one pole; and - the variable impedance (242) is such that - the frequency of the pole is reduced when the load specification indicates a relatively high output current; and - the frequency of the pole remains unaffected if the load specification indicates a relatively low output current. [6] The voltage regulator (100) according to a preceding claim, wherein - the voltage regulator (100) without the variable impedance (242) has a frequency-dependent open-loop gain for an output current at or above a threshold current that has a peak around the LC resonant frequency; and - the variable impedance (242) is configured such that the open-loop gain of the voltage regulator (100) corresponds to the variable impedance (242) - has a reduced peak or no peak around the LC resonant frequency for an output current at or above the threshold current; and - corresponds to the open-loop gain of the voltage regulator (100) without the variable impedance (242) for an output current below the threshold current. [7] The voltage regulator (100) according to a preceding claim, wherein the variable resistor (341) - is relatively low if the load specification indicates a relatively high output current; and - is relatively high if the load specification indicates a relatively low output current. [8] The voltage regulator (100) according to one of the preceding claims, wherein - the variable resistor (341) is at least partially provided by a control transistor (341) with a variable input resistor; and - the control transistor (341) is controlled based on the load specification. [9] The voltage regulator (100) according to a preceding claim, wherein - the output amplification stage (103) has a driver transistor (301) which forms a current mirror with a forward transistor (201); - the output current corresponds to a current through the forward transistor (201); - the output amplification stage (103) has a first transistor (302) which is arranged in series with the driver transistor (301) and which forms a current mirror with a second transistor (303); - the output amplification stage (103) has a third transistor (304) which is controlled based on the driver voltage at the intermediate node and which is arranged in series with the second transistor (303); and - the load specification depends on a voltage level of the gates of the first and second transistors (302, 303). [10] The voltage regulator (100) according to claim 9, referring back to claim 8, wherein a gate of the control transistor (341) is coupled to the gates of the first and second transistors (302, 303). [11] The voltage regulator (100) according to claim 9, referring back to claim 8, wherein - the detection unit (241) has a detection transistor (343) with a gate that is coupled to the gates of the first and second transistors (302, 303) and is arranged in series with a detection resistor (344); and - a gate of the control transistor (341) is coupled to a midpoint between the sensing transistor (343) and the sensing resistor (344). [12] The voltage regulator (100) according to a preceding claim, wherein - the voltage regulator (100) has a feedback network (206, 104) configured to provide a feedback voltage (107) that depends on the output voltage; and - the differential amplification stage (101) is configured to determine the differential output voltage as a function of the feedback voltage and as a function of the reference voltage (108). [13] A method (700) for compensating and / or reducing the effects of a parasitic inductance (211, 212) at an output of a voltage regulator (100); wherein the voltage regulator (100) is configured to provide an output current at an output voltage at an output node of the voltage regulator (100) based on an input voltage at an input node of the voltage regulator (100); wherein the output node of the voltage regulator (100) is coupled to an output capacitor (106) via a conducting path having the parasitic inductance (211, 212); wherein the voltage regulator (100) includes an output gain stage (103) for deriving the output current at the output node from the input voltage at the input node as a function of a driver voltage at an intermediate node of the voltage regulator (100);wherein the voltage regulator (100) comprises an intermediate gain stage (102) for providing the driver voltage at the intermediate node based on a differential output voltage; and wherein the voltage regulator (100) comprises a differential gain stage (101) configured to determine the differential output voltage as a function of the output voltage and as a function of a reference voltage (108); wherein the output capacitor (106) and the parasitic inductor (211, 212) form an LC circuit with an LC resonant frequency; wherein the method (700) comprises; - Determine (701) a load specification that specifies the output current; and - Setting (702) an impedance (242) at the intermediate node based on the load specification; wherein the voltage regulator (100) without the variable impedance (242) at the intermediate node has a bandwidth and / or a gain bandwidth frequency that increases with increasing output current, such that for an output current at or above a threshold current, the LC resonant frequency falls within the bandwidth and / or is lower than the gain bandwidth frequency; and wherein the variable impedance (242) is set such that for the voltage regulator (100) with the variable impedance (242) - the LC resonant frequency is higher than the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) at an output current at or above the threshold current; and - the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) with the variable impedance (242) corresponds to the bandwidth and / or the gain bandwidth frequency of the voltage regulator (100) without the variable impedance (242) for an output current below the threshold current, wherein - the variable impedance (242) has a capacitor (342) which is arranged in series with a variable resistor (341); - the series arrangement of the capacitor (342) and the resistor (341) is arranged to couple the intermediate node to a reference potential of the voltage regulator (100); and - the variable resistance (341) depends on the load specification.

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