MEMORY CELL MATRIX AND METHOD FOR THE PRODUCTION THEREOF

Abstract

Method (900) for producing a memory cell matrix (200A, 200B) comprising the following steps: Creating (902) a first group of tile elements (602) extending in a first direction (S), wherein creating the first group of tile elements (602) comprises: Creating (902a) a first layout design (300A, 300B) of a first group of memory cells (204), wherein each tile element of the first group of tile elements (602) corresponds to the first layout design (300A, 300B) of the first group of memory cells (204) and is offset from an adjacent tile element of the first group of tile elements (602) in a second direction (Y) different from the first direction (S); Creating (904a) a second group of tile elements (604), wherein creating the second group of tile elements (604) comprises: Creating a second layout design (400A-400B) of a second group of memory cells (206), wherein each tile element of the second group of tile elements (604) corresponds to the second layout design (400A-400B) of the second group of memory cells (206) and is offset from an adjacent tile element of the second group of tile elements (604) in the second direction (Y), wherein each tile element of the first group of tile elements (602) extends in a third direction (X) that is different from the first direction (S) and the second direction (Y), wherein the first group of tile elements (602) and the second group of tile elements (604) alternate with each other in the second direction (Y), and each tile element of the second group of tile elements (604) extends in the third direction (X), at least one of the aforementioned generation steps is carried out by a hardware processor, and the first layout design (300A, 300B) is stored in a non-transitory machine-readable medium; and manufacturing (906) the memory cell matrix (200A, 200B) based on at least the first layout design; wherein the first group of memory cells (204) is arranged in at least a first row and a second row of the memory cell matrix (200A, 200B), wherein the first group of memory cells (204) comprises four memory cells (204a, 204b, 204c, 204d), wherein each memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) comprises a memory cell of a synchronous random access memory (SRAM) with five transistors (5T), and the second group of memory cells (206) is arranged in at least a third row and a fourth row of the memory cell matrix (200A, 200B), wherein the second group of memory cells (206) comprises four memory cells (206a, 206b, 206c, 206d), wherein each memory cell (206a, 206b, 206c, 206d) of the second group of memory cells (206) comprises a 5T SRAM memory cell; wherein generating the first layout design (300A, 300B) of the first group of memory cells (204) comprises: Creating a first part (302a) of the first layout design (300A, 300B), wherein the first part (302a) of the first layout design (300A, 300B) corresponds to the production of a first memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B); Creating a second part (302b) of the first layout design (300A, 300B), wherein the second part (302b) of the first layout design (300A, 300B) corresponds to the production of a second memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B); Creating a third part (302c) of the first layout design (300A, 300B), wherein the third part (302c) of the first layout design (300A, 300B) corresponds to the production of a third memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B); and Creating a fourth part (302d) of the first layout design (300A, 300B), wherein the fourth part (302d) of the first layout design (300A, 300B) corresponds to the production of a fourth memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B), wherein the first part (302a) of the first layout design (300A, 300B) and the third part (302c) of the first layout design (300A, 300B) are mirror images of each other with respect to the second direction (Y), and the second part (302b) of the first layout design (300A, 300B) and the fourth part (302d) of the first layout design (300A, 300B) are mirror images of each other with respect to the second direction (Y).

Description

background

[0001] The IC (semiconductor integrated circuit) industry has developed a wide range of digital components to address problems in several areas. Some of these digital components, such as memory macros, are configured to store data. For example, in some applications, a cache is a special memory macro that can be used on an IC chip. Also, in some applications, a cache may be configured to store recently accessed data, allowing subsequent access to the recently accessed data to be achieved by accessing the cache rather than memory located external to the IC chip (e.g., off-chip). In general, a larger cache allows more recently accessed data to be stored on-chip, resulting in fewer off-chip memory data accesses.The design of smaller memory cells enables denser ICs and increases overall IC performance. Therefore, alternatives to the six-transistor (6T) synchronous random access memory (SRAM) are desirable. A method for fabricating a memory array is known from US 2011 / 0 286 295 A1. Similar methods are also known from US 2016 / 0 308 535 A1, US 2011 / 0 103 137 A1, US 2009 / 0 173 971 A1, or US 2005 / 0 262 293 A1. Short description of the drawings

[0002] The patent or application file contains drawings / photographs executed in color. Copies of this patent with color drawings / photographs will be provided by the Patent Office upon request and upon payment of the required fee.

[0003] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 is a circuit diagram of a memory cell according to some embodiments. Fig. Figure 2A is a block diagram of a memory cell array comprising several of the memory cells of Fig. 1, according to some embodiments. Fig. Figure 2B is a circuit diagram of a memory cell array containing several of the memory cells of Fig. 1, according to some embodiments. Fig. 3A is a schematic of a layout design according to some embodiments. Fig. 3B is a schematic of a layout design according to some embodiments. Fig. 4A is a schematic of a layout design according to some embodiments. Fig. 4B is a schematic of a layout design according to some embodiments. The Fig. 5A to 5H are schematics of at least one integrated circuit according to some embodiments. Fig. 6 is a schematic of a layout design of a memory cell array according to some embodiments. Fig. 7 is a schematic of a layout design of a memory cell array according to some embodiments. Fig. 8 is a schematic of a layout design of a memory cell array according to some embodiments. Fig. 9 is a flow diagram for fabricating a memory cell array according to some embodiments. Fig. 10 is a flowchart for generating a layout design of a memory cell array according to some embodiments. Fig. 11 is a block diagram of an IC manufacturing facility and an associated IC manufacturing flow according to some embodiments. Fig. 12 is a block diagram of a system for designing an IC layout design according to some embodiments. Detailed description

[0004] The following description provides various embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like are described below to facilitate the present invention. Other components, materials, values, steps, arrangements, or the like are also contemplated. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated throughout the various examples in the present invention. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the component in use or operation, in addition to the orientation illustrated in the figures. The component may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] According to some embodiments, a method of fabricating a memory cell array includes creating a first group of tile elements extending in a first direction and creating a second group of tile elements extending in the first direction. In some embodiments, each tile element of the first group of tile elements corresponds to a first layout design of a first group of memory cells. In some embodiments, each tile element of the second group of tile elements corresponds to a second layout design of a second group of memory cells.

[0007] In some embodiments, each memory cell of the first group of memory cells comprises a five-transistor (5T) synchronous random access memory (SRAM) memory cell. In some embodiments, each memory cell of the second group of memory cells comprises a 5T SRAM memory cell.

[0008] In some embodiments, the first group of memory cells is arranged in at least a first row and a second row of the memory cell array. In some embodiments, the second group of memory cells is arranged in at least a third row and a fourth row of the memory cell array.

[0009] In some embodiments, a shape of the first group of tile elements or a shape of the second group of tile elements is non-rectangular, resulting in smaller standard cells than other designs. In some embodiments, due to the smaller standard cells, the first group of tile elements or the second group of tile elements can be used to fabricate integrated circuits that are smaller than other integrated circuits.

[0010] The first group of tile elements and the second group of tile elements alternate in the second direction. In some embodiments, the second group of tile elements is separated from the first group of tile elements in the second direction.

[0011] In some embodiments, each tile element of the first group of tile elements is offset from an adjacent tile element of the first group of tile elements in a second direction that is different from the first direction. In some embodiments, each tile element of the second group of tile elements is offset from an adjacent tile element of the second group of tile elements in the second direction.

[0012] In some embodiments, generating the first group of tile elements comprises generating the first layout design of the first group of memory cells. In some embodiments, generating the second group of tile elements comprises generating the second layout design of the second group of memory cells.

[0013] In some embodiments, each tile element of the first group of tile elements and each tile element of the second group of tile elements extend in a third direction that is different from the first direction and the second direction.

[0014] Fig. 1 is a circuit diagram of a memory cell 100, according to some embodiments.

[0015] Memory cell 100 is a five-transistor (5T) synchronous single-port (SP) random access memory (SRAM) memory cell used for illustration. In some embodiments, a number of transistors other than five is used for memory cell 100. Other types of memories are also within the scope of various embodiments.

[0016] Memory cell 100 includes three p-type metal oxide semiconductor (PMOS) transistors P1, P2, and P3 and two n-type metal oxide semiconductor (NMOS) transistors N1 and N2. Transistors P1, P2, N1, and N2 form a cross-latch or a pair of cross-connected inverters. For example, PMOS transistor P1 and NMOS transistor N1 form a first inverter, while PMOS transistor P2 and NMOS transistor N2 form a second inverter.

[0017] A source terminal of the PMOS transistors P1 and P2 is each configured as a power supply node NODE_1. Each power supply node NODE_1 is connected to a first voltage source VDDI. A drain terminal of the PMOS transistor P1 is connected to a drain terminal of the NMOS transistor N1, a gate terminal of the PMOS transistor P2, and a gate terminal of the NMOS transistor N2 and is configured as a storage node NDB.

[0018] A drain terminal of PMOS transistor P2 is connected to a drain terminal of NMOS transistor N2, a gate terminal of PMOS transistor P1, a gate terminal of NMOS transistor N1, and a source terminal of PMOS transistor P3, and is configured as a storage node ND. A source terminal of NMOS transistors N1 and N2 is each configured as a reference supply voltage node (not labeled) having a reference supply voltage VSS. The source terminal of NMOS transistors N1 and N2 is each connected to the reference supply voltage VSS.

[0019] A word line WL1 is connected to a gate terminal of the PMOS transistor P3. The word line WL1 is also referred to as a write control line because the PMOS transistor P3 is configured to be controlled by a signal on the word line WL1 to transfer data between a bit line BL1 and the node ND.

[0020] A drain terminal of PMOS transistor P3 is connected to bit line BL1. Bit line BL1 is configured for input and output of data for memory cell 100. In some embodiments, during a write operation, applying a logic value to bit line BL1 enables writing of the logic value on bit line BL1 for memory cell 100. Bit line BL1 is referred to as a data line because the data transferred on bit line BL1 is written to and read from node ND. In some embodiments, the source terminal of PMOS transistor P3 is connected to bit line BL1, and the drain terminal of PMOS transistor P3 is connected to storage node ND.

[0021] Fig. 2A is a block diagram of a memory cell array 200A comprising several of the memory cells of Fig. 1, according to some embodiments. The memory cell 100 of Fig. 1 can be used, for example, as one or more memory cells in the memory cell matrix 200A.

[0022] The memory cell matrix 200A includes a matrix of memory cells 202[1,1], 202[1,2] ... 202[2,2] ... 202[M,N] (collectively referred to as the “matrix of memory cells 202A”) having M rows and N columns, where N is a positive integer corresponding to the number of columns in the matrix of memory cells 202A, and M is a positive integer corresponding to the number of rows in the matrix of memory cells 202A. The rows of cells in the matrix of memory cells 202A are arranged in a first direction X. The columns of cells in the matrix of memory cells 202A are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. The memory cell 100 of Fig. 1 can be used as one or more memory cells in the matrix of memory cells 202A.

[0023] The memory cell array 200A further includes 2N bit lines BL[1]...BL[2N], collectively referred to as a "bit line BL"). Each column 1...N in the array of memory cells 200A is overlapped by a pair of bit lines BL[1]...BL[2N]. Each bit line BL runs in the second direction Y and is located above a column of cells (e.g., column 1...N). In some embodiments, the memory cell array 200A does not include one or more bit line rails BLB. Note that the term "rail" used in this context refers to a logically inverted signal; for example, the bit line rail BLB[1]...BLB[N] carries a signal that is logically inverted from a signal carried by the bit line BL[1]...BL[N].

[0024] A bit line of the group of bit lines BL in the matrix of memory cells 202A or the matrix of memory cells 202B of Fig. 2B corresponds to the bit line BL1 of Fig. 1.

[0025] In some embodiments, a pair of memory cells of the memory cell array 202A is arranged between a pair of bit lines BL. For example, in row 1 and column 1 of the memory cell array 200A, the memory cell 202[1,1] and the memory cell 202[1,2] are each arranged between the bit line BL[1] and the bit line BL[2]. Similarly, in row 1 and column 2 of the memory cell array 200A, the memory cell 202[1,3] and the memory cell 202[1,4] are each arranged between the bit line BL[3] and the bit line BL[4].

[0026] The memory cell array 200A further includes 2M word lines WL[1]...WL[2M], collectively referred to as "word line WL"). Each word line WL extends in the first direction X and is located above a row of cells (e.g., row 1...M). Each row 1...M in the array of memory cells 202A is overlapped by a pair of word lines WL[1]...WL[2M]. For example, word line WL[1] and word line WL[2] each overlap row 1 of the array of memory cells 202A. Similarly, word line WL[3] and word line WL[4] each overlap row 2 of the array of memory cells 202A, and word lines WL[7] and WL[2M] each overlap row M of the array of memory cells 202A.

[0027] A word line of the group of word lines WL in the matrix of memory cells 202A or the matrix of memory cells 202B of Fig. 2B corresponds to the word line WL1 of Fig. 1.

[0028] In some embodiments, each row of memory cells of the memory cell array 202A is arranged between a pair of word lines WL. For example, in row 1 of the memory cell array 200A, the memory cells 202[1,1], 202[1,2] ... 202[1,N] are arranged between the word lines WL[1] and WL[2]. Similarly, in row 2 of the memory cell array 200A, the memory cells 202[2,1], 202[2,2] ... 202[2,N] are arranged between the word lines WL[1] and WL[2].

[0029] Each memory cell in the array of memory cells 202A is connected to a corresponding bit line of the bit lines BL and a corresponding word line of the word lines WL. For example, memory cell 202[1,1] is connected to bit line BL[1] and word line WL[1]. Similarly, memory cell 202[1,2] is connected to bit line BL[2] and word line WL[2], memory cell 202[1,3] is connected to bit line BL[3] and word line WL[2], memory cell 202[2,1] is connected to bit line BL[1] and word line WL[4], and memory cell 202[2,2] is connected to bit line BL[2] and word line WL[3].

[0030] The memory cells of the matrix of memory cells 202A are grouped into a first group of memory cells 204 and a second group of memory cells 206.

[0031] The first group of memory cells 204 comprises memory cells 204a, 204b ... 204i.

[0032] The second group of memory cells 206 includes memory cells 206a, 206b, 206c and 206d.

[0033] In some embodiments, the memory cells of the first group of memory cells 204 correspond to memory cells of a first layout design type (e.g., layout designs 300A and 300B of Fig. 3A and Fig. 3B), and the memory cells of the second group of memory cells 206 correspond to memory cells of a second layout design type (e.g., layout designs 400A and 400B of Fig. 4A and Fig. 4B), which is different from the first layout design type.

[0034] In some embodiments, the memory cells of the first group of memory cells 204 correspond to memory cells of the second layout design type (e.g., layout designs 400A and 400B of Fig. 4A and Fig. 4B), and the memory cells of the second group of memory cells 206 correspond to memory cells of the first layout design type (e.g., layout designs 300A and 300B of Fig. 3A and Fig. 3B).

[0035] Fig. 2B is a circuit diagram of a memory cell array 200B comprising several of the memory cells of Fig. 1, according to some embodiments. The memory cell array 200B is an embodiment of the block diagram of the memory cell array 200A of Fig. 2A, which is shown in a circuit diagram. The memory cell 100 of Fig. 1 can be used as one or more memory cells in the memory cell matrix 200B.

[0036] Compared with the memory cell matrix 200A of Fig. 2A, the matrix of memory cells 202B replaces the matrix of memory cells 202A of Fig. 2A. The array of memory cells 202B is an embodiment of the array of memory cells 202A of Fig. 2A.

[0037] Each memory cell of the matrix of memory cells 202B includes a corresponding PMOS transistor P3[1,1], P3[1,2], ... P[M,N] of a group of PMOS transistors 210 (not labeled), each connected to a corresponding inverter I1[1,1], I1[1,2], ... I1[M,N] of a first group of inverters 212 (not labeled) and a corresponding inverter I2[1,1], I2[1,2], ... I2[M,N] of a second group of inverters 214 (not labeled). The first group of inverters 212 and the second group of inverters 214 are part of a group of cross-coupled inverters 216 (not labeled).

[0038] One or more of the PMOS transistors P3[1,1], P3[1,2] ... P3[M,N] of the group of PMOS transistors 210 in the matrix of memory cells 202B correspond to the PMOS transistor P3 of Fig. 1.

[0039] One or more of the inverters I1[1,1], I1[1,2] ... I1[M,N] of the first group of inverters 212 in the matrix of memory cells 202B correspond to the PMOS transistor P2 and the NMOS transistor N2 of Fig. 1.

[0040] One or more of the inverters 12[1,1], 12[1,2] ... 12[M,N] of the second group of inverters 214 in the matrix of memory cells 202B correspond to the PMOS transistor P1 and the NMOS transistor N1 of Fig. 1.

[0041] In some embodiments, one or more memory cells of memory cell array 200A or 200B include one or more single-port (SP) SRAM cells. In some embodiments, one or more memory cells of memory cell array 200A or 200B include one or more dual-port (DP) SRAM cells. Other types of memory cells in memory cell array 200A or 200B are also within the intended scope of the present invention. Other configurations of the array of memory cells 202A or 202B are also within the intended scope of the present invention. Other configurations of the bit lines BL or the word lines WL in the array of memory cells 202A or 202B are also within the intended scope of the present invention.

[0042] In some embodiments, memory cell arrays 200A and 200B comprise an array of 5T SRAM cells ( Fig. 1), resulting in memory cell arrays 200A and 200B having fewer transistors than other memory cell arrays. In some embodiments, by having fewer transistors, memory cell arrays 200A and 200B occupy a smaller area than other memory cell arrays. In some embodiments, by having a smaller area than other memory cell arrays, memory cell arrays 200A and 200B are denser and have a larger storage capacity than other memory cell arrays.

[0043] Fig. 3A is a schematic of a layout design 300A, according to some embodiments. The layout design 300A corresponds to a layout diagram of a portion of the memory cell arrays 200A and 200B of the Fig. 2A and Fig. 2B. For example, the layout design 300A corresponds to a layout design of one or more memory cells 206a, 206b, 206c, or 206d of the second group of memory cells 206 of the Fig. 2A and Fig. 2B.

[0044] Components similar to those in one or more of the Fig. 3B, 4A and 4B and 6 to 8 (which will be described later) are designated by the same reference numerals, and their detailed description is omitted.

[0045] Structural relationships, including orientation, lengths and widths, and configurations of layout designs 400A and 400B ( Fig. 4A and Fig. 4B), of the layout design 600 ( Fig. 6), the layout design 700 ( Fig. 7) or the layout design 800 ( Fig. 8) are the structural relationships and configurations of the layout design 300A or 300B of the Fig. 3A and Fig. 3B and are shown for brevity in the Fig. 4A and 4B and 6 to 8 not described.

[0046] The layout design 300A can be used to manufacture an integrated circuit 500A ( Fig. 5A to 5H) can be used.

[0047] The layout design 300A corresponds to a layout design of the memory cells 202[1,2], 202[1,3], 202[2,2] and 202[2,3] of the Fig. 2A and Fig. 2B. In some embodiments, the layout design 300A corresponds to a layout design of the memory cells 202[1,6], 202[1,7], 202[2,6] and 202[2,7] of the Fig. 2A and Fig. 2B. In some embodiments, the layout design 300A corresponds to a layout design of the memory cells 202[3,2], 202[3,3], 202[4,2] and 202[4,3] of the Fig. 2A and Fig. 2B. In some embodiments, the layout design 300A corresponds to a layout design of the memory cells 202[3,6], 202[3,7], 202[4,6] and 202[4,7] of the Fig. 2A and Fig. 2B. In some embodiments, the layout design 300A corresponds to a layout design of one or more memory cells 204a, 204b ... 204i of the first group of memory cells 204 of the Fig. 2A and Fig. 2B.

[0048] The layout design 300A includes a first portion 302a, a second portion 302b, a third portion 302c, and a fourth portion 302d. A center of the layout design 300A corresponds to a boundary between the first portion 302a, the second portion 302b, the third portion 302c, and the fourth portion 302d. In some embodiments, the first portion 302a corresponds to the layout design of the memory cell 202[1,2], the second portion 302b corresponds to the layout design of the memory cell 202[2,2], the third portion 302c corresponds to the layout design of the memory cell 202[1,3], and the fourth portion 302d corresponds to the layout design of the memory cell 202[2,3]. The first portion 302a, the second portion 302b, the third portion 302c, and the fourth portion 302d have corresponding corner recesses 390a, 390b, 390c, and 390d. Other configurations of the first portion 302a, the second portion 302b, the third portion 302c, and the fourth portion 302d are also within the scope of the present invention.

[0049] The first part 302a includes active area layout structures 304a, 306a, 308a, and 310a (collectively referred to as a "group of active area layout structures 312a"). The active area layout structures 304a, 306a, 308a, and 310a may be used to fabricate respective active areas 504a1, 506a1, 508a1, and 510a1 of the circuit 500A or 500B ( Fig. 5A to 5H) can be used.

[0050] In some embodiments, the group of active area layout structures 312a is referred to as an oxide definition (OD) layout structure that defines source or drain diffusion layout structures of layout designs 300A and 300B. For example, in some embodiments, the active area layout structure 304a may be used to fabricate the source and drain regions of a PMOS transistor P1a of the Fig. 3A and Fig. 3B, the active area layout structure 306a can be used to fabricate the source and drain regions of an NMOS transistor N1a of the Fig. 3A and Fig. 3B, the active area layout structure 308a can be used to fabricate the source and drain regions of an NMOS transistor N2a of the Fig. 3A and Fig. 3B, and the active area layout structure 310a can be used to fabricate the source and drain regions of PMOS transistors P2a and PG1a of the Fig. 3A and Fig. 3B. In some embodiments, the PMOS transistor P1a corresponds to the PMOS transistor P1 ( Fig. 1), the PMOS transistor P2a corresponds to the PMOS transistor P2 ( Fig. 1), the PMOS transistor PG1a corresponds to the PMOS transistor P3 ( Fig. 1), the NMOS transistor N1a corresponds to the NMOS transistor N1 ( Fig. 1), and the NMOS transistor N2a corresponds to the NMOS transistor N2 ( Fig. 1).

[0051] Each of the layout structures of the group of active area layout structures 312a is separated from a neighboring layout structure of the group of active area layout structures 312a in a first direction X by a first distance (not labeled). In some embodiments, a neighboring element is immediately adjacent to another element. Each of the layout structures of the group of active area layout structures 312a extends in a second direction Y, different from the first direction X, and is arranged on a first layout level. In some embodiments, the first layout level corresponds to the active area of ​​the layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B).

[0052] An active area layout pattern 304a is disposed adjacent to or immediately adjacent to a first side of the first portion 302a of the layout design 300A and a corner notch 390a. An active area layout pattern 310a is disposed adjacent to or immediately adjacent to a second side of the first portion 302a of the layout design 300A. The second side of the first portion 302a of the layout design 300A is opposite the first side of the first portion 302a of the layout design 300A. In some embodiments, an active area layout pattern 306a is adjacent to the corner notch 390a. In some embodiments, the active area layout pattern 304a extends from one side of the layout design 300A to the corner notch 390a of the layout design. In some embodiments, the active area layout patterns 304a and 304b extend from the corner notch 390a to the corner notch 390b.In some embodiments, the active area layout pattern 304b extends from the side of the layout design 300A to the corner notch 390b of the layout design. In some embodiments, the active area layout pattern 304c extends from one side of the layout design 300A to the corner notch 390c of the layout design. In some embodiments, the active area layout patterns 304c and 304d extend from the corner notch 390c to the corner notch 390d. In some embodiments, the active area layout pattern 304d extends from the side of the layout design 300A to the corner notch 390d of the layout design.

[0053] In some embodiments, a length of the active area layout pattern 304a in the second direction Y is different from a length of the active area layout pattern 310a in the second direction Y. In some embodiments, a length of the active area layout pattern 306a in the second direction Y is different from a length of the active area layout pattern 308a in the second direction Y. In some embodiments, a length of the active area layout pattern 306a in the second direction Y is equal to the length of the active area layout pattern 308a in the second direction Y. Other sizes or configurations of the group of active area layout patterns 312a are also within the scope of the present invention.

[0054] The first portion 302a further includes gate layout structures 320a, 322a, and 324a (collectively referred to as a "group of gate layout structures 326a"). In some embodiments, the gate layout structures 320a, 322a, and 324a may be used to fabricate corresponding gate structures 520a, 522a, and 524a of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, gate layout pattern 320a may be used to form gate regions of PMOS transistor P1a and NMOS transistor N1a, gate layout pattern 322a may be used to form gate regions of NMOS transistor N2a and PMOS transistor P2a, and gate layout pattern 324a may be used to form a gate region of PMOS transistor PG1a. In some embodiments, gate layout pattern 322a is adjacent to corner recess 390a.

[0055] In some embodiments, each gate layout structure of the group of gate layout structures 326a extends in the first direction X and overlaps the group of active area layout structures 312a. The group of gate layout structures 326a is arranged on a second layout level that is different from the first layout level. In some embodiments, the second layout level corresponds to a POLY level of the layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B). The group of active area layout structures 312a is located below the group of gate layout structures 326a. Other sizes or configurations of the group of gate layout structures 326a are also within the scope of the present invention.

[0056] The first portion 302a further includes conductive element layout structures 330a, 332a, 334a, and 336a (collectively referred to as a "group of conductive element layout structures 338a"). In some embodiments, the conductive element layout structures 330a, 332a, 334a, and 336a may be used to fabricate corresponding conductive structures 530a, 532a, 534a, and 536a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) can be used.

[0057] In some embodiments, the group of conductive element layout patterns 338a extends in the first direction X and is located above the group of active area layout patterns 312a and / or the group of gate layout patterns 326a. The conductive element layout pattern 330a overlaps the active area layout patterns 304a and 306a. The conductive element layout pattern 334a overlaps the active area layout patterns 308a and 310a. The conductive element layout patterns 332a and 336a are located above the respective active area layout patterns 308a and 310a. In some embodiments, the conductive element layout pattern 330a is adjacent to the corner notch 390a.

[0058] In some embodiments, each conductive element layout pattern of the group of conductive element layout patterns 338a is separated from a neighboring layout pattern of the group of conductive element layout patterns 338a in the first direction X and / or the second direction Y. The group of conductive element layout patterns 338a is arranged on a third layout level that is different from the first layout level and the second layout level. In some embodiments, the third layout level corresponds to the metal one (M1) level of layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B). Other sizes or configurations of the group of conductive element layout structures 338a are also within the scope of the present invention.

[0059] The first portion 302a further includes via layout structures 360a, 362a, 364a, 366a, 368a, and 370a (collectively referred to as "group of via layout structures 358a"). In some embodiments, the via layout structures 360a, 362a, 364a, 366a, 368a, and 370a may be used to form corresponding vias 560a, 562a, 564a, 566a, 568a, and 570a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) can be used.

[0060] In some embodiments, each via layout pattern of the group of via layout patterns 358a is located where each conductive element layout pattern of the group of conductive element layout patterns 338a overlaps each active area layout pattern of the group of active area layout patterns 312a. The group of via layout patterns 358a is located between the group of conductive element layout patterns 338a and the group of active area layout patterns 312a. In some embodiments, the group of via layout patterns 358a is located at least at the via zero (V0) level of layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B). In some embodiments, the V0 level is located between the third layout level and the first or second layout level of layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B). In some embodiments, the first portion 302a of the layout design 300A may be used to fabricate the memory cell 202[1,2], 202[1,6], 202[3,2], or 202[3,6] of the second group of memory cells 206 of the memory cell array 200A or 200B. Other sizes or configurations of the group of via layout structures 358a are also within the scope of the present invention.

[0061] The second part 302b includes: active area layout structures 304b, 306b, 308b, and 310b (collectively referred to as "group of active area layout structures 312b"); gate layout structures 320b, 322b, and 324b (collectively referred to as "group of gate layout structures 326b"); conductive element layout structures 330b, 332b, 334b, and 336b (collectively referred to as "group of conductive element layout structures 338b"); and via layout structures 360b, 362b, 364b, 366b, 368b, and 370b (collectively referred to as “group of via layout structures 358b”).

[0062] In some embodiments, the first part 302a and the second part 302b of the layout designs 300A and 300B are mirror images of each other with respect to the second direction Y, and therefore a similar detailed description is omitted.

[0063] In some embodiments, the active area layout structures 304b, 306b, 308b, and 310b may be used to fabricate active areas 504b1, 506a1, 508a1, and 510a1 of the integrated circuit 500A or 500B ( Fig. 5A to 5H). In some embodiments, the gate layout structures 320b, 322b, and 324b may be used to fabricate gate structures corresponding to the gate structures 520a, 522a, and 524a of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the conductive element layout patterns 330b, 332b, 334b, and 336b may be used to fabricate corresponding conductive structures 530a, 532a, 534a, and 536a of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the via layout structures 360b, 362b, 364b, 366b, 368b, and 370b may be used to form vias corresponding to the vias 560a, 562a, 564a, 566a, 568a, and 570a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) are similar.

[0064] In some embodiments, active area layout patterns 304a and 304b are part of the same contiguous active area layout pattern. In some embodiments, active area layout patterns 308a and 308b are part of the same contiguous active area layout pattern. In some embodiments, active area layout patterns 310a and 310b are part of the same contiguous active area layout pattern.

[0065] In some embodiments, the second part 302b of the layout design 300A may be used to fabricate the memory cell 202[2,2], 202[2,6], 202[M,2] or 202[M,6] of the second group of memory cells 206 of the memory cell array 200A or 200B.

[0066] The third part 302c includes: active area layout structures 304c, 306c, 308c, and 310c (collectively referred to as "group of active area layout structures 312c"); gate layout structures 320c, 322c, and 324c (collectively referred to as "group of gate layout structures 326c"); conductive element layout structures 330c, 332c, 334c, and 336c (collectively referred to as "group of conductive element layout structures 338c"); and via layout structures 360c, 362c, 364c, 366c, 368c, and 370c (collectively referred to as “group of via layout structures 358c”).

[0067] In some embodiments, the first part 302a and the third part 302c of the layout designs 300A and 300B are mirror images of each other with respect to the first direction X, and therefore the similar detailed description is omitted.

[0068] In some embodiments, the active area layout patterns 304c, 306c, 308c, and 310c may be used to form active areas, the corresponding active areas 504a1, 506a1, 508a1, and 510a1 of the integrated circuit 500A or 500B ( Fig. 5A to 5H). In some embodiments, the gate layout structures 320c, 322c, and 324c may be used to fabricate gate structures corresponding to the gate structures 520a, 522a, and 524a of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the conductive element layout patterns 330c, 332c, 334c, and 336c may be used to fabricate conductive structures that are similar to the corresponding conductive structures 530a, 532a, 534a, and 536a of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the via layout structures 360c, 362c, 364c, 366c, 368c, and 370c may be used to form vias corresponding to the vias 560a, 562a, 564a, 566a, 568a, and 570a of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, gate layout structures 324a and 324c are part of the same contiguous gate layout structure.

[0069] In some embodiments, the third part 302c of the layout design 300A may be used to fabricate the memory cell 202[1,3], 202[1,7], 202[3,3] or 202[3,7] of the second group of memory cells 206 of the memory cell array 200A or 200B.

[0070] The fourth part 302d includes: active area layout structures 304d, 306d, 308d, and 310d (collectively referred to as "group of active area layout structures 312d"); gate layout structures 320d, 322d, and 324d (collectively referred to as "group of gate layout structures 326d"); conductive element layout structures 330d, 332d, 334d, and 336d (collectively referred to as "group of conductive element layout structures 338d"); and via layout structures 360d, 362d, 364d, 366d, 368d, and 370d (collectively referred to as “group of via layout structures 358d”).

[0071] In some embodiments, the third portion 302c and the fourth portion 302d of the layout designs 300A and 300B are mirror images of each other with respect to the second direction Y, and therefore, the similar detailed description is omitted. In some embodiments, the second portion 302b and the fourth portion 302d of the layout designs 300A and 300B are mirror images of each other with respect to the first direction X, and therefore, the similar detailed description is omitted.

[0072] In some embodiments, the active area layout patterns 304d, 306d, 308d, and 310d may be used to fabricate active areas, the corresponding active areas 504a1, 506a1, 508a1, and 510a1 of the integrated circuit 500A or 500B ( Fig. 5A to 5H) are similar. In some embodiments, the active area layout structures 304b, 304c, and 304d may be used to form the source and drain regions of corresponding PMOS transistors P1b, P1c, and P1d, the active area layout structures 306b, 306c, and 306d may be used to form the source and drain regions of corresponding NMOS transistors N1b, N1c, and N1d, and the active area layout structures 308b, 308c, and 308d may be used to form the source and drain regions of corresponding NMOS transistors N2b, N2c, and N2d, the active area layout structure 310b may be used to form the source and drain regions of the PMOS transistors P2b and P1b, the active area layout structure 310c can be used to manufacture the source and drain regions of the PMOS transistors P2c and PG1c,and the active area layout structure 310d can be used to fabricate the source and drain regions of the PMOS transistors P2d and PG1d.

[0073] In some embodiments, the PMOS transistor P1b, P1c or P1d is associated with the PMOS transistor P1 ( Fig. 1) similarly, the PMOS transistor P2b, P2c or P2d is the PMOS transistor P2 ( Fig. 1) similarly, the PMOS transistor PG1b, PG1c or PG1d is connected to the PMOS transistor P3 ( Fig. 1) similarly, the NMOS transistor N1b, N1c or N1d is the NMOS transistor N1 ( Fig. 1) and the NMOS transistor N2b, N2c or N2d is similar to the NMOS transistor N2 ( Fig. 1) similar.

[0074] In some embodiments, the gate layout structures 320d, 322d, and 324d may be used to fabricate gate structures corresponding to the gate structures 520a, 522a, and 524a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) are similar. In some embodiments, the gate layout structure 320b may be used to form gate regions of the PMOS transistor P1b and the NMOS transistor N1b, the gate layout structure 322b may be used to form gate regions of the NMOS transistor N2b and the PMOS transistor P2b, the gate layout structure 320c may be used to form gate regions of the PMOS transistor P1c and the NMOS transistor N1c, the gate layout structure 322c may be used to form gate regions of the NMOS transistor N2c and the PMOS transistor P2c, the gate layout structure 320d may be used to form gate regions of the PMOS transistor P1d and the NMOS transistor N1d, the gate layout structure 322d may be used to Fabricating gate regions of the NMOS transistor N2d and the PMOS transistor P2d, and the gate layout structures 324b,324c and 324d can be used to fabricate corresponding gate regions of the PMOS transistors PG1b, PG1c and PG1d.

[0075] In some embodiments, the conductive element layout patterns 330d, 332d, 334d, and 336d may be used to fabricate conductive structures corresponding to the conductive structures 530a, 532a, 534a, and 536a of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the via layout structures 360d, 362d, 364d, 366d, 368d, and 370d may be used to form vias corresponding to the vias 560a, 562a, 564a, 566a, 568a, and 570a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) are similar.

[0076] In some embodiments, active area layout patterns 304c and 304d are part of the same contiguous active area layout pattern. In some embodiments, active area layout patterns 308c and 308d are part of the same contiguous active area layout pattern. In some embodiments, active area layout patterns 310c and 310d are part of the same contiguous active area layout pattern.

[0077] Each active area layout structure of the group of active area layout structures 312b, 312c, and 312d is similar to the group of active area layout structures 312a, and therefore, the similar detailed description is omitted. Each gate layout structure of the group of gate layout structures 326b, 326c, and 326d is similar to the group of gate layout structures 326a, and therefore, the similar detailed description is omitted. Each conductive element layout structure of the group of conductive element layout structures 338b, 338c, and 338d is similar to the group of conductive element layout structures 338a, and therefore, the similar detailed description is omitted. Each via layout pattern of the group of via layout patterns 358b, 358c, and 358d is similar to the group of via layout patterns 358a, and therefore the similar detailed description is omitted.In some embodiments, gate layout structures 324b and 324d are part of the same contiguous gate layout structure.

[0078] In some embodiments, the fourth part 302d of the layout design 300A may be used to fabricate the memory cell 202[2,3], 202[2,7], 202[M,3] or 202[M,7] of the second group of memory cells 206 of the memory cell matrix 200A or 200B.

[0079] Other sizes or configurations of the group of active area layout structures 312b, 312c, and 312d, the group of gate layout structures 326b, 326c, and 326d, the group of conductive element layout structures 338b, 338c, and 338d, or the group of via layout structures 358b, 358c, and 358d are also within the scope of the present invention.

[0080] The layout design 300A further includes conductive element layout patterns 340a and 340b (collectively referred to as a "group of conductive element layout patterns 340"). In some embodiments, the conductive element layout patterns 340a and 340b may be used to fabricate a conductive structure 540a or similar conductive structures of the integrated circuits 500A and 500B ( Fig. 5A to 5H) can be used.

[0081] In some embodiments, the group of conductive element layout patterns 340 extends in the first direction X and is located above the gate layout patterns 324a and 324b. The conductive element layout pattern 340a is located above the gate layout pattern 324a. The conductive element layout pattern 340b is located above the gate layout pattern 324b.

[0082] In some embodiments, each conductive element layout pattern of the group of conductive element layout patterns 340 is separated from an adjacent layout pattern of the group of conductive element layout patterns 340 at least in the second direction Y. The group of conductive element layout patterns 340 is located on the third layout level.

[0083] The layout design 300A further includes conductive element layout patterns 342a and 342b (collectively referred to as a "group of conductive element layout patterns 342"). In some embodiments, the conductive element layout patterns 342a and 342b may be used to fabricate corresponding conductive structures 542a and 542b of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the group of conductive element layout patterns 342 extends in the first direction X. The conductive element layout pattern 342a is located above the active area layout patterns 304a and 304b. The conductive element layout pattern 342b is located above the active area layout patterns 308a and 308b. In some embodiments, each conductive element layout pattern of the group of conductive element layout patterns 342 is separated from an adjacent layout pattern of the group of conductive element layout patterns 342 at least in the first direction X. The group of conductive element layout patterns 342 is arranged on the third layout level.

[0084] The layout design 300A further includes conductive element layout patterns 344a and 344b (collectively referred to as a "group of conductive element layout patterns 344"). In some embodiments, the conductive element layout patterns 344a and 344b may be used to fabricate corresponding conductive structures corresponding to the corresponding conductive structures 542a and 542b of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the group of conductive element layout patterns 344 extends in the first direction X. The conductive element layout pattern 344a is located above the active area layout patterns 304c and 304d. The conductive element layout pattern 344b is located above the active area layout patterns 308c and 308d. In some embodiments, each conductive element layout pattern of the group of conductive element layout patterns 344 is separated from an adjacent layout pattern of the group of conductive element layout patterns 344 at least in the first direction X. The group of conductive element layout patterns 344 is arranged on the third layout level.

[0085] The layout design 300A further includes at least one conductive element layout pattern 350a (collectively referred to as a "group of conductive element layout patterns 350"). In some embodiments, the conductive element layout pattern 350a may be used to fabricate a conductive structure 550a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) can be used.

[0086] In some embodiments, the conductive element layout structure 350a extends in the first direction X and is arranged at least over the active area layout structures 310a, 310b, 310c and 310d.

[0087] In some embodiments, each conductive element layout pattern 350a of the group of conductive element layout patterns (not labeled) is separated from a neighboring layout pattern of the group of conductive element layout patterns (not labeled) in the first direction X and / or the second direction Y. The conductive element layout pattern 350a is arranged on a fourth layout level that is different from the first layout level, the second layout level, and the third layout level. In some embodiments, the fourth layout level corresponds to the metal two (M2) level of layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B).

[0088] The layout design 300A further includes via layout patterns 374a and 374b (collectively referred to as a "group of via layout patterns 374"). In some embodiments, the via layout patterns 374a and 374b may be used to form corresponding vias 574a and 574b of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, each via layout pattern of the group of via layout patterns 374 is arranged at the location where the conductive element layout patterns 342a and 342b overlap corresponding active area layout patterns 304a and 304b. The via layout patterns 374a and 374b are arranged between corresponding conductive element layout patterns 342a and 342b and corresponding active area layout patterns 304a and 304b. In some embodiments, the group of via layout patterns 374 is arranged at least at the V0 level of the layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B).

[0089] The layout design 300A further includes via layout patterns 376a and 376b (collectively referred to as a "group of via layout patterns 376"). In some embodiments, the via layout patterns 376a and 376b may be used to form vias that connect the corresponding vias 574a and 574b of the integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, each via layout pattern of the group of via layout patterns 376 is arranged at the location where the conductive element layout patterns 344a and 344b overlap corresponding active area layout patterns 304c and 304d. The via layout patterns 376a and 376b are arranged between corresponding conductive element layout patterns 344a and 344b and corresponding active area layout patterns 304c and 304d. In some embodiments, the group of via layout patterns 376 is at least at the Vo level of the layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B).

[0090] The layout design 300A further includes via layout patterns 378a and 378b (collectively referred to as a "group of via layout patterns 378"). In some embodiments, the via layout patterns 378a and 378b may be used to form a via 578a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) or a via similar to via 578a. In some embodiments, the group of via layout patterns 378 is disposed where the conductive element layout pattern 350a overlaps the active area layout patterns 310a, 310b, 310c, and 310d. The via layout pattern 378a is disposed between the conductive element layout pattern 350a and the active area layout patterns 310a and 310b. The via layout pattern 378b is disposed between the conductive element layout pattern 350a and the active area layout patterns 310c and 310d. In some embodiments, the group of via layout structures 378 is at least at a via-one (V1) level of the layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B). In some embodiments, the V1 level is located between the third layout level and the fourth layout level of the layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B).

[0091] The layout design 300A further includes via layout patterns 380a and 380b (collectively referred to as a "group of via layout patterns 380"). In some embodiments, the via layout patterns 380a and 380b may be used to form a via 580a of the integrated circuits 500A and 500B ( Fig. 5A to 5H) or vias similar to via 580a. In some embodiments, via layout pattern 380a is disposed where conductive element layout pattern 340a overlaps gate layout patterns 324a and 324c. In some embodiments, via layout pattern 380b is disposed where conductive element layout pattern 340b overlaps gate layout patterns 324b and 324d. Via layout pattern 380a is disposed between conductive element layout pattern 340a and gate layout patterns 324a and 324c. The via layout pattern 380b is arranged between the conductive element layout pattern 340 and the gate layout patterns 324b and 324d.In some embodiments, the group of via layout structures 308 is at least at a via-over-gate (VG) level of layout designs 300A and 300B or 400A and 400B (. Fig. 4A and Fig. 4B). In some embodiments, the VG plane is located between the third layout plane and the second layout plane of the layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B).

[0092] Other sizes or configurations of the conductive element layout structures 340a, 340b, 342a, 342b, 344a, 344b or 350a or the via layout structures 374a, 374b, 376a, 376b, 378a, 378b, 380a or 380b are also within the scope of the present invention.

[0093] In some embodiments, layout designs 300A and 300B have a non-rectangular shape, resulting in a smaller standard cell than other designs. In some embodiments, layout designs 300A and 300B, by having a smaller standard cell, can be used to fabricate integrated circuits that are smaller than other integrated circuits.

[0094] Fig. 3B is a schematic of a layout design 300B, according to some embodiments.

[0095] The layout design 300B can be used to manufacture the integrated circuit 500A ( Fig. 5A to 5H). Layout design 300B is a modification of layout design 300A of Fig. 3A. In comparison with the layout design 300A of Fig. 3A, the layout design 300B further includes a first well layout structure 314 and a second well layout structure 316.

[0096] The first well layout structure 314 extends in the second direction Y and is arranged on a fifth layout level. The first well layout structure 314 may be used to manufacture a first well 501 (e.g., having at least parts 501a and 501b) of the integrated circuit 500A ( Fig. 5A to 5H). In some embodiments, the fifth layout level is different from the first layout level, the second layout level, the third layout level, and the fourth layout level. In some embodiments, the fifth layout level corresponds to the well level of layout designs 300A and 300B or 400A and 400B ( Fig. 4A and Fig. 4B). In some embodiments, a portion of the fifth layout level includes the first layout level. The first well layout structure 314 includes layout structures 354a, 354b, and 354c.

[0097] The layout structure 354a extends in the second direction Y and is located below the active area layout structures 304a and 304b. The layout structure 354a is adjacent to a side 352a of the first part 302a or the second part 302b of the layout design 300B and to corner recesses 390a and 390b. The layout structure 354a may be used to manufacture the part 501a of the first well 501 of the integrated circuit 500A ( Fig. 5A to 5H). The layout structure 354a has a width W1 (not labeled) in the first direction X.

[0098] The layout structure 354b extends in the second direction Y and is located below the active area layout structures 310a, 310b, 310c, and 310d. The layout structure 354b is arranged above centerlines 352b1 and 352b2 of the layout design 300B. In some embodiments, a center of the layout structure 354b is aligned with the centerlines 352b1 and 352b2 of the layout design 300B. The layout structure 354b may be used to manufacture at least the portion 501b of the first well 501 of the integrated circuit 500A ( Fig. 5A to 5H). The layout structure 354b has a width W2 (not labeled) in the first direction X.

[0099] Layout structure 354c extends in the second direction Y and is located below active area layout structures 304c and 304d. Layout structure 354c is adjacent to a side 352c of the third portion 302c or the fourth portion 302d of layout design 300B and to corner notches 390c and 390d. Layout structure 354c may be used to fabricate a portion of first well 501 similar to portion 501a. Layout structure 354c has a width W1 (not labeled) in the first direction X.

[0100] The second well layout structure 316 extends in the second direction Y and is arranged on the fifth layout level. The second well layout structure 316 may be used to fabricate a second well 501' (e.g., having at least a portion 501c) of the integrated circuit 500A ( Fig. 5A to 5H) can be used.

[0101] The second tub layout structure 316 has layout structures 356a and 356b.

[0102] The layout structure 356a extends in the second direction Y and is located below the active area layout structures 306a, 306b, 308a, and 308b. The layout structure 356a is arranged between the layout structures 354a and 354b. The layout structure 356a may be used to manufacture the part 501c of the second well 501' of the integrated circuit 500A ( Fig. 5A to 5H). The layout structure 356a has a width W3 (not labeled) in the first direction X.

[0103] The layout structure 356b extends in the second direction Y and is located below the active area layout structures 306c, 306d, 308c, and 308d. The layout structure 356b is arranged between the layout structures 354b and 354c. The layout structure 356b may be used to fabricate a portion of the second well 501' corresponding to the portion 501c of the integrated circuit 500A ( Fig. 5A to 5H). The layout structure 356b has a width W3 (not labeled) in the first direction X.

[0104] In some embodiments, the width W1, the width W2, or the width W3 is the same as another one of the widths W1, W2, and W3. In some embodiments, the width W1, the width W2, or the width W3 is different from another one of the widths W1, W2, and W3.

[0105] Other sizes or configurations of the first well layout structure 314 or the second well layout structure 316 are also within the scope of the present invention. Other sizes or configurations of the layout structures 354a, 354b, 354c, 356a, or 356b are also within the scope of the present invention.

[0106] Fig. 4A is a schematic of a layout design 400A, according to some embodiments. The layout design 400A corresponds to a layout diagram of a portion of the memory cell arrays 200A and 200B of the Fig. 2A and Fig. 2B. For example, the layout design 400A corresponds to a layout design of one or more memory cells 204a, 204b ... 204i of the first group of memory cells 204 of the Fig. 2A and Fig. 2B.

[0107] The layout design 400A is similar to the layout design 300A ( Fig. 3A). Similar elements have a similar reference number increased by 100.

[0108] The layout design 400A can be used to manufacture the integrated circuit 500B ( Fig. 5A to 5H) can be used.

[0109] The layout design 400A corresponds to a layout design of the memory cells 202[2,4], 202[2,5], 202[3,4] and 202[3,5] of the Fig. 2A and Fig. 2B. For example, in some embodiments, the first part 402a corresponds to the layout design of the memory cell 202[2,4] of the Fig. 2A and Fig. 2B, the second part 402b corresponds to the layout design of the memory cell 202[3,4] of Fig. 2A and Fig. 2B, the third part 402c corresponds to the layout design of the memory cell 202[2,5] of the Fig. 2A and Fig. 2B, and the fourth part 402d corresponds to the layout design of the memory cell 202[3,5] of Fig. 2A and Fig. 2B. The first part 402a, the second part 402b, the third part 402c, and the fourth part 402d have corresponding corner notches 490a, 490b, 490c, and 490d. The corner notches 490a, 490b, 490c, and 490d are similar to the corresponding corner notches 390a, 390b, 390c, and 390d, and therefore, the similar detailed description is omitted. In some embodiments, the layout design 400A corresponds to a layout design of the memory cells 206a, 206b, 206c, or 206d of the second group of memory cells 206 of the Fig. 2A and Fig. 2B.

[0110] In some embodiments, the first part 402a of the layout design 400A may be used to fabricate the memory cell 202[2,4], 202[2,N], 202[M,4] or 202[M,N] of the first group of memory cells 204 of the memory cell array 200A or 200B.

[0111] In some embodiments, the second part 402b of the layout design 400A may be used to fabricate a memory cell 202[1,4], 202[1,N], 202[3,4] or 202[3,N] of the first group of memory cells 204 of the memory cell array 200A or 200B.

[0112] In some embodiments, the third part 402c of the layout design 400A may be used to fabricate a memory cell 202[2,1], 202[2,5], 202[M,1] or 202[M,5] of the first group of memory cells 204 of the memory cell matrix 200A or 200B.

[0113] In some embodiments, the fourth part 402d of the layout design 400A may be used to fabricate a memory cell 202[1,1], 202[1,5], 202[3,1], or 202[3,5] of the first group of memory cells 204 of the memory cell array 200A or 200B.

[0114] Active area layout patterns 404a, 406a, 408a, and 410a (collectively referred to as “group of active area layout patterns 412a”) may be used to fabricate corresponding active areas 504a2, 506a2, 508a2, and 510e of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the group of active area layout patterns 412a is referred to as OD layout patterns that define source or drain diffusion layout patterns of layout designs 400A and 400B. For example, in some embodiments, active area layout pattern 404a may be used to form the source and drain regions of an NMOS transistor N1a' of Fig. 4A and Fig. 4B, the active area layout structure 406a can be used to fabricate the source and drain regions of a PMOS transistor P1a' of the Fig. 4A and Fig. 4B, the active area layout structure 408a can be used to fabricate the source and drain regions of a PMOS transistor P2a' of the Fig. 4A and Fig. 4B, and the active area layout structure 410a can be used to fabricate the source and drain regions of an NMOS transistor N2a' and the source and drain regions of a PMOS transistor PG1a' of the Fig. 4A and Fig. 4B can be used.

[0115] In some embodiments, the active area layout patterns 404b, 406b, 408b, and 410b may be used to fabricate active areas corresponding to the corresponding active areas 504a2, 506a2, 508a2, and 510e of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the active area layout patterns 404c, 406c, 408c, and 410c may be used to fabricate active areas corresponding to the corresponding active areas 504a2, 506a2, 508a2, and 510e of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the active area layout patterns 404d, 406d, 408d, and 410d may be used to fabricate active areas corresponding to the corresponding active areas 504a2, 506a2, 508a2, and 510e of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0116] In some embodiments, the active area layout structures 404b, 404c, and 404d can be used to fabricate source and drain regions of corresponding NMOS transistors N1b', N1c', and N1d', the active area layout structures 406b, 406c, and 406d can be used to fabricate the source and drain regions of corresponding PMOS transistors P1b', P1c', and P1d', the active area layout structures 408b, 408c, and 408d can be used to fabricate the source and drain regions of corresponding PMOS transistors P2b', P2c', and P2d', the active area layout structure 410b can be used to fabricate the source and drain regions of the NMOS transistor N2b' and the source and drain regions of the PMOS transistor PG1b', the active area layout structure 410c can be used to fabricate the source and drain region of the NMOS transistor N2c' and the source and drain region of the PMOS transistor PG1c',and the active area layout structure 410d can be used to fabricate the source and drain regions of the NMOS transistor N2d' and the source and drain regions of the PMOS transistor PG1d'.,

[0117] In some embodiments, the gate layout structures 420a, 422a, and 424a may be used to fabricate the corresponding gate structures 520a, 522a, and 524a of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, gate layout structure 420a may be used to form gate regions of NMOS transistor N1a' and PMOS transistor P1a', gate layout structure 422a may be used to form the gate regions of NMOS transistor N2a' and PMOS transistor P2a', and gate layout structure 424a may be used to form the gate region of PMOS transistor PG1a'.

[0118] In some embodiments, the gate layout structures 420b, 422b, and 424b may be used to fabricate gate structures that correspond to the corresponding gate structures 520a, 522a, and 524a of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the gate layout structures 420c, 422c, and 424c may be used to fabricate gate structures that are similar to the corresponding gate structures 520a, 522a, and 524a of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the gate layout structures 420d, 422d, and 424d may be used to fabricate gate structures that are similar to the corresponding gate structures 520a, 522a, and 524a of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0119] In some embodiments, the gate layout structure 420b can be used to fabricate gate regions of the PMOS transistor P1b' and the NMOS transistor N1b', the gate layout structure 422b can be used to fabricate gate regions of the NMOS transistor N2b' and the PMOS transistor P2b', the gate layout structure 420c can be used to fabricate gate regions of the PMOS transistor P1c' and the NMOS transistor N1c', the gate layout structure 422c can be used to fabricate gate regions of the NMOS transistor N2c' and the PMOS transistor P2c', the gate layout structure 420d can be used to fabricate gate regions of the PMOS transistor P1d' and the NMOS transistor N1d', the Gate layout structure 422d can be used to fabricate gate regions of the NMOS transistor N2d' and the PMOS transistor P2d', and the gate layout structures 424b,424c and 424d can be used to form corresponding gate regions of the PMOS transistors PG1b', PG1c' and PG1d'.

[0120] In some embodiments, the conductive element layout patterns 430a, 432a, 434a, and 436a may be used to fabricate the corresponding conductive structures 530a, 532a, 534b, and 536b of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the conductive element layout patterns 430b, 432b, 434b, and 436b may be used to fabricate conductive structures that correspond to the corresponding conductive structures 530a, 532a, 534b, and 536b of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the conductive element layout patterns 430c, 432c, 434c, and 436c may be used to fabricate conductive structures that correspond to the corresponding conductive structures 530a, 532a, 534b, and 536b of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the conductive element layout patterns 430d, 432d, 434d, and 436d may be used to fabricate conductive structures that correspond to the corresponding conductive structures 530a, 532a, 534b, and 536b of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0121] In some embodiments, via layout structures 460a, 462a, 464a, 466a, 468a, and 470a may be used to form the corresponding vias 560a, 562a, 564a, 566b, 568b, and 570b of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, via layout structures 460b, 462b, 464b, 466b, 468b, and 470b may be used to form vias corresponding to the corresponding vias 560a, 562a, 564a, 566b, 568b, and 570b of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, via layout structures 460c, 462c, 464c, 466c, 468c, and 470c may be used to form vias that correspond to the corresponding vias 560a, 562a, 564a, 566b, 568b, and 570b of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, via layout structures 460d, 462d, 464d, 466d, 468d, and 470d may be used to form vias that correspond to the corresponding vias 560a, 562a, 564a, 566b, 568b, and 570b of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0122] In some embodiments, the conductive element layout patterns 440a and 440b may be used to form the conductive pattern 540a or similar conductive patterns of the integrated circuit 500B ( Fig. 5A to 5H) can be used.

[0123] In some embodiments, the conductive element layout patterns 442a and 442b may be used to form the corresponding conductive structures 542a and 542b of the integrated circuit 500B ( Fig. 5A to 5H) can be used.

[0124] In some embodiments, the conductive element layout patterns 444a and 444b may be used to fabricate conductive structures that correspond to the corresponding conductive structures 542a and 542b of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0125] In some embodiments, a conductive element layout pattern 450a may be used to form a conductive structure 550b of the integrated circuit 500B ( Fig. 5A to 5H) can be used.

[0126] In some embodiments, via layout patterns 474a and 474b may be used to form corresponding vias 574a and 574b of the integrated circuit 500B ( Fig. 5A to 5H) can be used.

[0127] In some embodiments, via layout patterns 476a and 476b may be used to form vias that correspond to the corresponding vias 574a and 574b of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0128] In some embodiments, via layout patterns 478a and 478b may be used to form a via 578b or vias corresponding to the via 578b of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0129] In some embodiments, via layout patterns 480a and 480b may be used to form a via 580a or vias corresponding to the via 580a of the integrated circuit 500B ( Fig. 5A to 5H) are similar.

[0130] In some embodiments, layout designs 400A and 400B have a non-rectangular shape, resulting in a smaller standard cell than other designs. In some embodiments, layout designs 400A and 400B, by having a smaller standard cell, can be used to fabricate integrated circuits that are smaller than other integrated circuits.

[0131] Fig. 4B is a schematic of a layout design 400B, according to some embodiments.

[0132] The layout design 400B can be used to manufacture the integrated circuit 500B ( Fig. 5A to 5H). Layout design 400B is a modification of layout design 400A of Fig. 4A. In comparison with the layout design 400A of Fig. 4A, the layout design 400B further includes a first well layout structure 416 and a second well layout structure 414.

[0133] The first well layout structure 416 extends in the second direction Y and is arranged on the fifth layout level. The first well layout structure 416 may be used to fabricate a first well 502 (e.g., having at least parts 502a and 502b) of the integrated circuit 500B ( Fig. 5A to 5H) can be used.

[0134] The first tray layout structure 416 includes layout structures 456a, 456b, 456c and 456d.

[0135] The layout structure 456a extends in the second direction Y and is located below the active area layout structures 404a and 404b. The layout structure 456a is adjacent to a side 452a of the first part 402a or the second part 402b of the layout design 400B. The layout structure 456a may be used to manufacture the part 502a of the first well 502 of the integrated circuit 500B ( Fig. 5A to 5H). The layout structure 456a has a width W1 (not labeled) in the first direction X.

[0136] The layout structure 456b extends in the second direction Y and is located below the active area layout structures 404c and 404d. The layout structure 456b is adjacent to a side 452c of the third part 402c or the fourth part 402d of the layout design 400B. The layout structure 456b may be used to fabricate a part of the first well 502 that corresponds to the part 502a of the integrated circuit 500B ( Fig. 5A to 5H). The layout structure 456b has a width W1 (not labeled) in the first direction X.

[0137] The layout structure 456c extends in the first direction X and is located under a portion of the active area layout structures 410a and 410c. In some embodiments, one side of the layout structure 456c is aligned with a first side of the layout structure 454b along a line 452d1 in the first direction X. The layout structure 456c may be used to fabricate the portion 502b of the first well 502 of the integrated circuit 500B ( Fig. 5A to 5H). The layout structure 456c has a width W2 (not labeled) in the first direction X.

[0138] The layout structure 456d extends in the first direction X and is located under a portion of the active area layout structures 410b and 410d. In some embodiments, one side of the layout structure 456d is aligned with a second side of the layout structure 454b along a line 452d2 in the first direction X. The layout structure 456d may be used to fabricate a portion of the first well 502 that corresponds to the portion 502b of the integrated circuit 500B ( Fig. 5A to 5H). The layout structure 456d has a width W2 (not labeled) in the first direction X.

[0139] The second well layout structure 414 extends in the second direction Y and is arranged on the fifth layout level. The second well layout structure 414 may be used to fabricate a second well 502' (e.g., having at least parts 502c and 502d) of the integrated circuit 500B ( Fig. 5A to 5H). The second tub layout structure 414 includes layout structures 454a, 454b, and 454c.

[0140] The layout structure 454a extends in the second direction Y and is located below the active area layout structures 406a, 406b, 408a, and 408b. The layout structure 454a may be used to manufacture the portion 502c of the second well 502' of the integrated circuit 500B ( Fig. 5A to 5H). The layout structure 454a has a width W3 (not labeled) in the first direction X.

[0141] The layout structure 454b extends in the first direction X and is located below the active area layout structures 410a, 410b, 410c, and 410d. The layout structure 454b is arranged above centerlines 452b1 and 452b2 of the layout design 400B. In some embodiments, a center of the layout structure 454b is aligned with the centerlines 452b1 and 452b2 of the layout design 400B. In some embodiments, the first side of the layout structure 454b is aligned with the centerline 452d1 in the first direction X. In some embodiments, the second side of the layout structure 454b is aligned with the centerline 452d2 in the first direction X. The layout structure 454b may be used to manufacture at least the portion 502d of the second well 502' of the integrated circuit 500B ( Fig. 5A to 5H). In some embodiments, the layout structure 454b may be used to fabricate parts corresponding to the part 502d of the second well 502' of the integrated circuit 500B ( Fig. 5A to 5H). The layout structure 454b has a width W2 (not labeled) in the first direction X.

[0142] The layout structure 454c extends in the second direction Y and is located below the active area layout structures 406c, 406d, 408c, and 408d. The layout structure 454c may be used to fabricate a portion of the second well 502' that corresponds to the portion 502c of the integrated circuit 500B ( Fig. 5A to 5H). The layout structure 454c has a width W3 (not labeled) in the first direction X.

[0143] In some embodiments, layout structures 454a, 454b, and 454c are part of the same contiguous layout structure (e.g., second well layout structure 414).

[0144] Layout structure 454a is arranged between layout structure 456a and the individual layout structures 454b, 456c, and 456d. Layout structure 454c is arranged between layout structure 456b and the individual layout structures 454b, 456c, and 456d. Layout structure 454b is arranged between layout structures 456c and 456d. Layout structure 454b is arranged between layout structures 454a and 454c.

[0145] In some embodiments, the width W1, the width W2, or the width W3 is the same as another one of the widths W1, W2, and W3. In some embodiments, the width W1, the width W2, or the width W3 is different from another one of the widths W1, W2, and W3.

[0146] Other sizes or configurations of the first well layout structure 416 or the second well layout structure 414 are also within the scope of the present invention. Other sizes or configurations of the layout structure 454b, 454b, 454c, 456a, 456b, 456c, or 456d are also within the scope of the present invention.

[0147] The Fig. 5A to 5H are schematics of an integrated circuit 500A or 500B, according to some embodiments.

[0148] Fig. 5A is a cross-sectional view of the integrated circuit 500A or 500B corresponding to the layout design 300B or 400B, each cut by a plane A-A'.

[0149] Fig. 5B is a cross-sectional view of the integrated circuit 500A or 500B corresponding to the layout design 300B or 400B, each cut by a plane B-B'.

[0150] Fig. 5C is a cross-sectional view of the integrated circuit 500A or 500B corresponding to the layout design 300B or 400B, each cut by a plane C-C'.

[0151] Fig. 5D is a cross-sectional view of the integrated circuit 500A corresponding to the layout design 300B cut by a plane D - D', and Fig. 5E is a cross-sectional view of the integrated circuit 500B corresponding to the layout design 400B cut by a plane E-E'.

[0152] Fig. 5F is a cross-sectional view of the integrated circuit 500A or 500B corresponding to the layout design 300B or 400B, each cut by a plane F-F'.

[0153] Fig. 5G is a cross-sectional view of the integrated circuit 500A corresponding to the layout design 300B cut by a plane G - G', and Fig. 5H is a cross-sectional view of the integrated circuit 500A corresponding to the layout design 400B cut by a plane H-H'.

[0154] Integrated circuit 500A is manufactured using first portion 302a of layout design 300B, and integrated circuit 500B is manufactured using first portion 402a of layout design 400B. In some embodiments, second portion 302b, third portion 302c, and fourth portion 302d of layout design 300B may be used to manufacture an integrated circuit similar to circuit 500A. In some embodiments, second portion 402b, third portion 402c, and fourth portion 402d of layout design 400B may be used to manufacture an integrated circuit similar to circuit 500B.

[0155] Structural relationships, including orientation, lengths and widths, as well as configurations of the integrated circuits 500A and 500B, are similar to the structural relationships and configurations of the layout designs 300A and 300B of the Fig. 3A and Fig. 3B and the layout designs 400A and 400B of the Fig. 4A and Fig. 4B and are shown for brevity in the Fig. 5A to 5H not described.

[0156] Circuits 500A and 500B are only briefly described below when they Fig. 5A to 5H. For the sake of brevity, elements having the same reference number in integrated circuits 500A and 500B will be described with reference to integrated circuit 500A or 500B, and the similar detailed description will be omitted.

[0157] Integrated circuit 500B is a modification of integrated circuit 500A. Compared to integrated circuit 500A, integrated circuit 500B does not include first well 501 and second well 501'. Compared to integrated circuit 500A, first well 502 of integrated circuit 500B replaces first well 501, and second well 502' of integrated circuit 500B replaces second well 501.

[0158] The integrated circuit 500A has a first well 501 and a second well 501'. The first well 501 and the second well 501' are each located at least on the first level of the integrated circuit 500A and extend in the second direction Y.

[0159] The first well 501 of the integrated circuit 500A comprises dopants of a first type. The second well 501' of the integrated circuit 500A comprises dopants of a second type that is different from the first type. In some embodiments, the first type is an n-type dopant, the second type is a p-type dopant, the first well 501 of the integrated circuit 500A is an n-type well, and the second well 501' of the integrated circuit 500A is a p-type well. In some embodiments, the first type is a p-type dopant, the second type is an n-type dopant, the first well 501 of the integrated circuit 500A is a p-type well, and the second well 501' of the integrated circuit 500A is an n-type well.

[0160] The first well 501 of the integrated circuit 500A has a first part 501a and a second part 501b.

[0161] The first portion 501a of the first well 501 extends in the second direction Y and is adjacent to a first side 590a of the integrated circuit 500A. In some embodiments, the first side 590a of the integrated circuit 500A corresponds to line 352a of the layout design 300B. The first portion 501a of the first well 501 is located at least on the first level of the integrated circuit 500A.

[0162] The second portion 501b of the first well 501 extends in the second direction Y and is adjacent to a second side 590b of the integrated circuit 500A. In some embodiments, the second side 590b of the integrated circuit 500A corresponds to line 352b1 of the layout design 300B. The second portion 501b of the first well 501 is located at least on the first level of the integrated circuit 500A.

[0163] The second well 501' of the integrated circuit 500A has a portion 501c. The second well 501' is arranged between the first portion 501a of the first well 501 and the second portion 501b of the first well 501.

[0164] The portion 501c of the second well 501' extends in the second direction Y and is disposed between the first portion 501a of the first well 501 and the second portion 501b of the first well 501. The portion 501c of the second well 501' is located at least on the first level of the integrated circuit 500A. Other sizes or configurations of the first well 501 or the second well 501' are also within the scope of the present invention.

[0165] The integrated circuit 500A or 500B has a group of active areas 504 extending in the second direction Y. The group of active areas 504 is arranged on the first level of the integrated circuit 500A or 500B.

[0166] The group of active regions 504 includes one or more active regions 504a1, 506a1, 508a1, or 510a1. Each of the active regions 504a1, 506a1, 508a1, and 510a1 of the group of active regions 504 is separated from an adjacent active region of the group of active regions 504 in the first direction X by a first distance (not labeled).

[0167] The active region 504a1 is adjacent to the first side 590a of the integrated circuit 500A. The active region 510a1 is adjacent to the second side 590b of the integrated circuit 500A. The second side 590b of the integrated circuit 500A is opposite the first side 590a of the integrated circuit 500A.

[0168] The active region 504a1 of the group of active regions 504 is embedded in the first part 501a of the first well 501 of the integrated circuit 500A.

[0169] The active region 510a1 of the group of active regions 504 is embedded in the second part 501b of the first well 501 of the integrated circuit 500A.

[0170] The active region 506a1 or 508a1 of the group of active regions 504 is embedded in the part 501c of the second well 501' of the integrated circuit 500A.

[0171] Active regions 506a1 and 508a1 comprise dopants of the first type. Active regions 504a1 and 510a1 comprise dopants of the second type. In some embodiments, the first type is an n-type dopant and the second type is a p-type dopant, and therefore, active regions 504a1 and 510a1 are each p-type active regions embedded in the first well 501 (which is an n-type well), and active regions 506a1 and 508a1 are each n-type active regions embedded in the second well 501' (which is a p-type well). In some embodiments, the first type is a p-dopant and the second type is an n-dopant, and therefore, the active regions 504a1 and 510a1 are each n-type active regions embedded in the first well 501 (which is a p-type well), and the active regions 506a1 and 508a1 are each p-type active regions embedded in the second well 501' (which is an n-type well).

[0172] In some embodiments, a length of at least one of the active regions 504a1, 506a1, 508a1, and 510a1 in the second direction Y is different from a length of another of the active regions 504a1, 506a1, 508a1, and 510a1 in the second direction Y. In some embodiments, a length of at least one of the active regions 504a1, 506a1, 508a1, and 510a1 in the second direction Y is equal to a length of another of the active regions 504a1, 506a1, 508a1, and 510a1 in the second direction Y. Other sizes or configurations of the group of active regions 504 are also within the scope of the present invention.

[0173] The integrated circuit 500A or 500B includes a group of gates 527 extending in the first direction Y. The group of gates 527 overlaps the group of active areas 504 of the integrated circuit 500A or a group of active areas 505 of the integrated circuit 500B. The group of gates 527 is disposed on a second level of the integrated circuit 500A or 500B. The second level is different from the first level of the integrated circuit 500A or 500B. In some embodiments, the second level of the integrated circuit 500A or 500B is referred to as a POLY level.

[0174] The group of gates 527 includes one or more of the gate structures 520a, 522a, and 524a. The gate structures 520a and 524a are separated from the gate structure 522a in the second direction Y by a gate pitch (not labeled). The gate structures 520a and 524a are separated from each other in the first direction X. Other sizes or configurations of the group of gates 527 are also within the scope of the present invention.

[0175] The integrated circuit 500A or 500B includes conductive structures 504b, 504c, 504d, 504e, 504f, 510b, 510e, 510d, 510e, 510f, 516e, 516f, and 520f (collectively referred to as “group of contacts 521”).

[0176] The group of contacts 521 extends in the first direction X or the second direction Y. The group of contacts 521 is arranged above the group of active areas 504 of the integrated circuit 500A or above the group of active areas 505 of the integrated circuit 500B. The group of contacts 521 is located on the second level of the integrated circuit 500A or 500B. In some embodiments, the second level of the integrated circuit 500A or 500B is referred to as a metal diffusion (MD) level.

[0177] The group of contacts 521 electrically connects the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B to upper levels (e.g., Mo, M1, or M2) of the corresponding integrated circuit 500A or 500B. The conductive structures 504b and 510b electrically connect corresponding vias 506b and 512b to the active area 504a1 or 504a2 (which are part of the integrated circuit 500B). The conductive structures 504c and 510c electrically connect corresponding vias 506c and 512c to the active area 506a1 or 506a2 (which are part of the integrated circuit 500B). The conductive structures 504d and 510d electrically connect corresponding vias 506d and 512d to the active area 508a1 or 508a2 (which are part of the integrated circuit 500B).Conductive structures 504e, 510e, and 516e electrically connect corresponding vias 506e, 512e, and 518e to active area 510a1. Conductive structures 504f and 510f electrically connect corresponding vias 506f and 512f to active area 510b. Conductive structures 516f and 520f electrically connect corresponding vias 518f and 522f to active area 510c. Other sizes or configurations of the group of contacts 521 are also within the scope of the present invention.

[0178] The integrated circuit 500A or 500B includes conductive structures 508b, 508c, 508d, 508e, 508f, 514b, 514e, 514f, 516c, 516d, 520e, and 524f (collectively referred to as the "group of conductive structures 529"). The group of conductive structures 529 extends in the first direction X or the second direction Y. The group of conductive structures 529 is disposed over the group of active areas 504 of the integrated circuit 500A or over the group of active areas 505 of the integrated circuit 500B. The group of conductive structures 529 is disposed over the group of contacts 521 and / or the group of gates 527. The group of conductive structures 529 is located on a third level of the integrated circuit 500A or 500B.The third level of the integrated circuit 500A or 500B is different from the first level of the integrated circuit 500A or 500B and the second level of the integrated circuit 500A or 500B. In some embodiments, the third level of the integrated circuit 500A or 500B is referred to as the metal zero (Mo) level.

[0179] The group of conductive structures 529 electrically connects the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B to upper levels (e.g., M1 or M2) of the corresponding integrated circuit 500A or 500B. In some embodiments, the group of conductive structures 529 electrically connects the group of gates 527 to upper levels (e.g., M1 or M2) of the integrated circuit 500A or 500B. Other sizes or configurations of the group of conductive structures 529 are also within the scope of the present invention.

[0180] The integrated circuit 500A or 500B includes vias 504g, 506b, 506c, 506d, 506e, 506f, 512b, 512c, 512d, 512e, 512f, 514c, 514d, 518e, 518f, and 522f (collectively referred to as “group of vias 523”) between the group of conductive structures 529 and the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B. The group of vias 523 electrically connects the group of conductive structures 529 to the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B.In some embodiments, one or more vias of the group of vias 523 are located at the location where one or more conductive structures of the group of conductive structures 529 are disposed over one or more active areas of the group of active areas 504 of the integrated circuit 500A or over one or more active areas of the group of active areas 505 of the integrated circuit 500B.

[0181] Vias 506b and 512b electrically connect corresponding conductive structures 508b and 514b to corresponding conductive structures 504b and 510b. Vias 506c and 512c electrically connect corresponding conductive structures 508c and 516c to corresponding conductive structures 504c and 510c. Vias 506d and 512d electrically connect corresponding conductive structures 508d and 516d to corresponding conductive structures 504d and 510d. Vias 506e, 512e, and 518e electrically connect corresponding conductive structures 508e, 514e, and 520e to corresponding conductive structures 504e, 510e, and 516e. Vias 506f and 522f electrically connect corresponding conductive structures 508f and 524f to corresponding conductive structures 504f and 520f.The vias 512f and 518f electrically connect the conductive structure 514f to the corresponding conductive structures 510f and 516f.

[0182] Vias 514c, 514d, and 504g are disposed over the respective gate structures 522a, 520a, and 524a, respectively. Vias 514c, 514d, and 504g electrically connect the respective conductive structures 516c, 516d, and 506g to the respective gate structures 522a, 520a, and 524a. Vias 514c, 514d, and 504g are disposed over the respective gate structures 522a, 520a, and 524a. In some embodiments, the group of vias 523 is located between the first group of conductive structures 538 and the group of gates 527. The via 504g of the group of vias 523 is arranged at the location where the conductive structure 540a of the first group of conductive structures 538 is located above the gate structure 524a of the group of gates 527.

[0183] The group of vias 523 is located in the via-over-diffusion (VD) level or the via-over-gate (VG) level of the integrated circuit 500A or 500B. The VD level or the VG level of the integrated circuit 500A or 500B is located between the second level and the third level. In some embodiments, the vias 514c, 514d, and 504g are located in the VG level of the integrated circuit 500A or 500B. In some embodiments, vias 506b, 506c, 506d, 506e, 506f, 512b, 512c, 512d, 512e, 512f, 518e, 518f, and 522f are located in the VD plane of integrated circuit 500A or 500B. Other sizes or configurations of the group of vias 523 are also within the scope of the present invention.

[0184] The integrated circuit 500A or 500B includes conductive structures 524e, 528f, 530a, 532a, 534a, 534b, 536a, 536b, 540a, 542a, and 542b (collectively referred to as the "first group of conductive structures 538"). The first group of conductive structures 538 extends in the first direction X. Each conductive structure of the first group of conductive structures 538 is separated from an adjacent conductive structure of the first group of conductive structures 538 in the first direction X and / or the second direction Y. The first group of conductive structures 538 is disposed over the group of active areas 504 of the integrated circuit 500A, the group of active areas 505 of the integrated circuit 500B, the group of gates 527, and / or the group of contacts 521. The first group of conductive structures 538 is located on a fourth level of the integrated circuit 500A or 500B.The fourth level of the integrated circuit 500A or 500B is different from the first level of the integrated circuit 500A or 500B, the second level of the integrated circuit 500A or 500B, and the third level of the integrated circuit 500A or 500B. In some embodiments, the fourth level of the integrated circuit 500A or 500B is referred to as the metal one (M1) level.

[0185] In some embodiments, the conductive structure 540a corresponds to the word line WL1 of the memory cell 100 of Fig. 1 or the word lines WL[1] ... WL[2M] of the memory cell matrices 200A and 200B of the Fig. 2A and Fig. 2B.

[0186] The first group of conductive structures 538 is electrically connected to the group of active areas 504 of the integrated circuit 500A or to the group of active areas 505 of the integrated circuit 500B. In some embodiments, the first group of conductive structures 538 is electrically connected to the group of gates 527. Other sizes or configurations of the first group of conductive structures 538 are also within the scope of the present invention.

[0187] The integrated circuit 500A or 500B includes vias 522e, 526f, 560a, 562a, 564a, 566a, 566b, 568a, 568b, 570a, 570b, 574a, 574b, and 580a (collectively referred to as “first group of vias 572”) between the first group of conductive structures 538 and the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B. The first group of vias 572 electrically connects the first group of conductive structures 538 to the group of active areas 504 of the integrated circuit 500A or to the group of active areas 505 of the integrated circuit 500B.In some embodiments, one or more vias of the first group of vias 572 are arranged at the location where one or more conductive structures of the first group of conductive structures 538 overlap one or more active areas of the group of active areas 504 of the integrated circuit 500A or one or more active areas of the group of active areas 505 of the integrated circuit 500B.

[0188] Vias 560a and 574a electrically connect the corresponding conductive structures 530a and 542a to the corresponding conductive structures 508b and 514b. Vias 562a and 574b electrically connect the corresponding conductive structures 530a and 542b to the corresponding conductive structures 516c and 508c. Via 564a electrically connects the conductive structure 532a to the conductive structure 508d. Vias 566a and 566b electrically connect the corresponding conductive structures 534a and 534b to the conductive structure 516d. The vias 568a, 570a and 522e electrically connect the corresponding conductive structures 536a, 534a and 524e to the corresponding conductive structures 508e, 514e and 520e.Vias 568b, 570b, and 526f electrically connect the corresponding conductive structures 536b, 534b, and 528f to the corresponding conductive structures 508f, 514f, and 524f. Via 580a electrically connects the conductive structure 540a to the conductive structure 506g.

[0189] The first group of vias 572 is located in the via zero (Vo) level of the integrated circuit 500A or 500B. The Vo level of the integrated circuit 500A or 500B is located between the third level and the fourth level. In some embodiments, the Vo level of the integrated circuit 500A or 500B is located between the M1 level and the Mo level. Other sizes or configurations of the first group of vias 572 are also within the scope of the present invention.

[0190] The integrated circuit 500A or 500B includes conductive structures 550a and 550b (collectively referred to as a "group of conductive structures 552"). The second group of conductive structures 552 extends in the first direction X. Each conductive structure of the second group of conductive structures 552 is separated from an adjacent conductive structure of the second group of conductive structures 552 in the first direction X and / or the second direction Y. In some embodiments, the second group of conductive structures 552 is located over one or more active areas of the group of active areas 504 of the integrated circuit 500A, the group of active areas 505 of the integrated circuit 500B, or the group of contacts 521.

[0191] The second group of conductive structures 552 is located at the fifth level of the integrated circuit 500A or 500B. The fifth level of the integrated circuit 500A or 500B is different from the first level of the integrated circuit 500A or 500B, the second level of the integrated circuit 500A or 500B, the third level of the integrated circuit 500A or 500B, and the fourth level of the integrated circuit 500A or 500B. In some embodiments, the fifth level is referred to as a metal two (M2) level.

[0192] In some embodiments, the second group of conductive structures 552 overlaps the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B. The conductive structure 550a overlaps the active area 510a of the group of active areas 504 of the integrated circuit 500A and the second side 590b of the integrated circuit 500A. The conductive structure 550b overlaps the active area 510c of the group of active areas 505 of the integrated circuit 500B and the second side 590b of the integrated circuit 500B. In some embodiments, the conductive structure 550a or 550b corresponds to the bit line BL1 of the memory cell 100 of Fig. 1 or the bit lines BL[1] ... BL[2N] of the memory cell matrices 200A and 200B of the Fig. 2A and Fig. 2B.

[0193] In some embodiments, the second group of conductive structures 552 is electrically connected to the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B. The conductive structure 550a is electrically connected to the active area 510a of the integrated circuit 500A. The conductive structure 550b is electrically connected to the active area 510c of the integrated circuit 500B. Other sizes or configurations of the second group of conductive structures 552 are also within the scope of the present invention.

[0194] The integrated circuit 500A or 500B includes vias 578a and 578b (collectively referred to as “group of vias 576”) between the second group of conductive structures 552 and the first group of conductive structures 538. The group of vias 576 electrically connects the second group of conductive structures 552 to the first group of conductive structures 538. The vias 578a and 578b electrically connect the corresponding conductive structures 550a and 550b to the corresponding conductive structures 524e and 528f. In some embodiments, the group of vias 576 electrically connects the second group of conductive structures 552 to the group of active areas 504 of the integrated circuit 500A or the group of active areas 505 of the integrated circuit 500B.

[0195] In some embodiments, one or more vias of the group of vias 576 are arranged at the location where one or more conductive structures of the first group of conductive structures 538 overlap one or more active areas of the group of active areas 504 of the integrated circuit 500A or one or more active areas of the group of active areas 505 of the integrated circuit 500B.

[0196] The first group of vias 572 is located in the V1 level of the integrated circuit 500A or 500B. The V1 level of the integrated circuit 500A or 500B is located between the fourth level and the fifth level. In some embodiments, the V1 level of the integrated circuit 500A or 500B is located between the M2 level and the M1 level. Other sizes or configurations of the group of vias 572 are also within the scope of the present invention.

[0197] Integrated circuit 500B is a modification of integrated circuit 500A. Compared to integrated circuit 500A, a first well 502 of integrated circuit 500B replaces first well 501, a second well 502' of integrated circuit 500B replaces second well 501, and a group of active areas 505 of integrated circuit 500B replaces group of active areas 504.

[0198] The integrated circuit 500B includes the first well 502 and the second well 502'. The first well 502 and the second well 502' are each located at least on the first level of the integrated circuit 500B and extend at least in the second direction Y.

[0199] The first well 502 of the integrated circuit 500B comprises dopants of the second type. The second well 502' of the integrated circuit 500B comprises dopants of the first type. In some embodiments, the first type is an n-type dopant, the second type is a p-type dopant, the first well 502 of the integrated circuit 500B is a p-type well, and the second well 502' of the integrated circuit 500B is an n-type well. In some embodiments, the first type is a p-type dopant, the second type is an n-type dopant, the first well 502 of the integrated circuit 500B is an n-type well, and the second well 502' of the integrated circuit 500B is a p-type well.

[0200] The first well 502 of the integrated circuit 500B has a first part 502a and a second part 502b.

[0201] The first portion 502a of the first well 502 extends in the second direction Y and is adjacent to the first side 590a of the integrated circuit 500B. In some embodiments, the first side 590a of the integrated circuit 500B corresponds to line 352a of the layout design 400B. The first portion 502a of the first well 502 is located at least on the first level of the integrated circuit 500B.

[0202] The second portion 502b of the first well 502 extends in the second direction Y and is adjacent to the second side 590b of the integrated circuit 500B. In some embodiments, the second side 590b of the integrated circuit 500B corresponds to line 352b1 of the layout design 400B. The second portion 502b of the first well 502 is located at least on the first level of the integrated circuit 500B. Other sizes or configurations of the first well 502, the first portion 502a of the first well 502, or the second portion 502b of the first well 502 are also within the scope of the present invention.

[0203] The second well 502' of the integrated circuit 500B has a first part 502c and a second part 502d.

[0204] The first portion 502c of the second well 502' extends in the second direction Y and is adjacent to the first portion 502a of the first well 502. The first portion 502c of the second well 502' is located at least on the first level of the integrated circuit 500B.

[0205] The second part 502d of the second well 502' extends in the first direction X and / or the second direction Y. The second part 502d of the second well 502' is adjacent to the second side 590b of the integrated circuit 500B, the second part 502b of the first well 502, and the first part 502c of the second well 502', respectively. The second part 502d of the second well 502' is located at least on the first level of the integrated circuit 500B.

[0206] The first portion 502c of the second tub 502' is disposed between the first portion 502a of the first tub 502 and each of the second portion 502b of the first tub 502 and the second portion 502d of the second tub 502'. Other sizes or configurations of the second tub 502', the first portion 502 of the second tub 502', or the second portion 502d of the second tub 502' are also within the scope of the present invention.

[0207] The integrated circuit 500B has a group of active regions 505 extending in the second direction Y. The group of active regions 505 is arranged on the first level of the integrated circuit 500B.

[0208] The group of active regions 505 includes one or more of the active regions 504a2, 506a2, 508a2, and 510a2. Each of the active regions 504a2, 506a2, 508a2, and 510a2 of the group of active regions 505 is separated from an adjacent active region of the group of active regions 505 in the first direction X by a first distance (not labeled).

[0209] The active region 510e includes an active region 510b and an active region 510c. The active region 510b and the active region 510c are separated from each other in the second direction Y.

[0210] The active region 504a2 is adjacent to the first side 590a of the integrated circuit 500B. The active region 510e is adjacent to the second side 590b of the integrated circuit 500B.

[0211] The active region 504a2 of the group of active regions 505 is embedded in the first part 502a of the first well 502 of the integrated circuit 500B.

[0212] The active region 510e of the group of active regions 505 is embedded in the second part 502b of the first well 502 of the integrated circuit 500B and the second part 502d of the second well 502' of the integrated circuit 500B, respectively. The active region 510b is embedded in the second part 502b of the first well 502 of the integrated circuit 500B. The active region 510c is embedded in the second part 502d of the second well 502' of the integrated circuit 500B.

[0213] The active region 506a2 or 508a2 of the group of active regions 505 is embedded in the first part 502c of the second well 502' of the integrated circuit 500B.

[0214] The active regions 504a2 and 510b comprise dopants of the first type. The active regions 506a2, 508a2, and 510c comprise dopants of the second type.

[0215] In some embodiments, the first type is an n-dopant and the second type is a p-dopant, and therefore, active regions 504a2 and 510b are each n-type active regions embedded in the first well 502 (which is a p-well), and active regions 506a2, 508a2, and 510c are each p-type active regions embedded in the second well 502' (which is a p-well). In some embodiments, the first type is a p-dopant and the second type is an n-dopant, and therefore, active regions 504a2 and 510b are each p-type active regions embedded in the first well 502 (which is an n-well), and active regions 506a2, 508a2, and 510c are each n-type active regions embedded in the second well 502' (which is a p-well).

[0216] In some embodiments, a length of at least one of the active regions 504a2, 506a2, 508a2, 510b, 510c, and 510e in the second direction Y is different from a length of another of the active regions 504a2, 506a2, 508a2, 510b, 510c, and 510e in the second direction Y. In some embodiments, a length of at least one of the active regions 504a2, 506a2, 508a2, 510b, 510c, and 510e in the second direction Y is equal to a length of another of the active regions 504a2, 506a2, 508a2, 510b, 510c, and 510e in the second direction Y. Other sizes or configurations of the group of active regions 505 are also within the scope of the present invention.

[0217] In some embodiments, integrated circuits 500A and 500B occupy a smaller area than other integrated circuits. In some embodiments, integrated circuits 500A and 500B, because they occupy a smaller area than other integrated circuits, are used as part of memory cell arrays 200A and 200B, which are denser compared to other approaches. In some embodiments, memory cell arrays 200A and 200B therefore have a larger storage capacity than other memory cell arrays.

[0218] Fig. 6 is a schematic of a layout design 600, according to some embodiments.

[0219] A portion of the layout design 600 may be used to manufacture the integrated circuit 500A or 500B ( Fig. 5A to 5H) can be used.

[0220] The layout design 600 includes a first group of tile elements 602 and a second group of tile elements 604 arranged in a matrix of tile elements. In some embodiments, at least one tile element of the first group of tile elements 602 corresponds to the layout design 300A or 300B, and at least one tile element of the second group of tile elements 604 corresponds to the layout design 400A or 400B. In some embodiments, at least one tile element of the first group of tile elements 602 corresponds to the layout design 400A or 400B, and at least one tile element of the second group of tile elements 604 corresponds to the layout design 300A or 300B. In some embodiments, a shape of the first group of tile elements 602 and a shape of the second group of tile elements 604 are non-rectangular, and therefore, the shape of the layout design 600 may also be non-rectangular.

[0221] The first group of tile elements 602 extends in a third direction S. The third direction S is related to the first direction X and the second direction Y. For example, in some embodiments, the third direction S is rotated from the first direction X by an angle α to the second direction Y. In some embodiments, the angle α is in the range of about 0 degrees to about 180 degrees. The angle α is expressed by a formula (2) (given below). In some embodiments, the third direction S is equal to the first direction X or the second direction Y. In some embodiments, the third direction S is different from the first direction X or the second direction Y. The group of tile elements 602 comprises one or more of the tile elements 608[1,1], 608[2,1] ... 608[P,1], 608[1,3], 608[2,3] ... 608[P,3], 608[1,Q-1], 608[2,Q-1] ...608[P-1,Q-1], where P is a positive integer corresponding to the number of columns in the matrix of tile elements, and Q is a positive integer corresponding to the number of rows in the matrix of tile elements.

[0222] Each tile element of the first group of tile elements 602 extends in the first direction X. Each tile element of the first group of tile elements 602 has four notches (which are not labeled for ease of explanation). In some embodiments, the four notches of each tile element of the first group of tile elements 602 correspond to corner notches 390a, 390b, 390c, and 390d of the group of corner notches 390 of the Fig. 3A and Fig. 3B. For example, the tile element 608[P,Q-1] has notches 630a, 630b, 630c, and 630d. In some embodiments, the notches 630a, 630b, 630c, and 630d are corresponding corner notches 390a, 390b, 390c, and 390d of the Fig. 3A and Fig. 3B. Each notch 630a, 630b, 630c, and 630d is located in a corresponding corner of the tile element 608[P,Q-1]. In some embodiments, each notch (not labeled for ease of explanation) of each tile element of the first group of tile elements 602 is located in a corresponding corner of the tile element of the first group of tile elements 602. A center of each tile element of the first group of tile elements 602 is offset from a center of an adjacent tile element of the first group of tile elements 602 in the second direction Y by a distance D1. For example, the center of tile element 608[1,1] is separated from the center of tile element 608[2,1] by the distance D1 in the second direction Y.

[0223] A center of each tile element of the first group of tile elements 602 is separated from a center of an adjacent tile element of the first group of tile elements 602 in the third direction S by a distance D2. For example, the center of tile element 608[1,1] is separated from the center of tile element 608[2,1] by the distance D2 in the third direction S.

[0224] A center of each tile element of the first group of tile elements 602 is separated from a center of an adjacent tile element of the first group of tile elements 602 in the first direction X by a distance D3. For example, the center of tile element 608[1,1] is separated from the center of tile element 608[2,1] by the distance D3 in the first direction X.

[0225] The relationship between the distances D1, D2 and D3 is expressed by formula (1) as follows: D2=(D12+D32)0.5

[0226] The second group of tile elements 604 extends in the third direction S. The relationship between the angle α and the distances D2 and D3 is expressed by formula (2) as follows: α=ArcCos(D3 / D2)

[0227] The second group of tile elements 604 includes one or more of the tile elements 608[1,2], 608[2,2] ... 608[P,2], 608[1,4], 608[2,4] ... 608[P,4], 608[1,Q], 608[2,Q] ... 608[P,Q]. The second group of tile elements 604 is spaced from the first group of tile elements 602 in the second direction Y.

[0228] The first group of tile elements 602 and the second group of tile elements 604 alternate with each other in the second direction Y. Each tile element of the second group of tile elements 604 extends in the first direction X. Each tile element of the second group of tile elements 604 has four recesses (which are not labeled for ease of explanation). In some embodiments, the four recesses of each tile element of the second group of tile elements 604 correspond to the corner recesses 490a, 490b, 490c, and 490d of the group of corner recesses 490 of the Fig. 4A and Fig. 4B. For example, the tile element 608[P,Q] has notches 640a, 640b, 640c, and 640d. In some embodiments, the notches 640a, 640b, 640c, and 640d are the corresponding corner notches 490a, 490b, 490c, and 490d of the Fig. 4A and Fig. 4B. Each notch 640a, 640b, 640c, and 640d is located in a corresponding corner of the tile element 608[P,Q]. In some embodiments, the notches (not labeled for ease of explanation) of each tile element of the second group of tile elements 604 are each located in a corresponding corner of the tile element of the second group of tile elements 604. A center of each tile element of the second group of tile elements 604 is offset from a center of an adjacent tile element of the second group of tile elements 604 in the second direction Y by a distance D1'. For example, the center of tile element 608[1,2] is separated from the center of tile element 608[2,2] by the distance D1' in the second direction Y.

[0229] A center of each tile element of the second group of tile elements 604 is separated from a center of an adjacent tile element of the second group of tile elements 604 in the third direction S by a distance D2'. For example, the center of tile element 608[1,2] is separated from the center of tile element 608[2,2] by the distance D2' in the third direction S.

[0230] A center of each tile element of the second group of tile elements 604 is spaced from a center of an adjacent tile element of the second group of tile elements 604 in the first direction X by a distance D3'. For example, the center of tile element 608[1,2] is separated from the center of tile element 608[2,2] by the distance D3' in the first direction X.

[0231] The relationship between the distances D1', D2' and D3' is expressed by formula (3) as follows: D2'=(D1'2+D3'2)0.5

[0232] The relationship between the angle α and the distances D2' and D3' is expressed by formula (4) as follows: α=ArcCos(D3' / D2')

[0233] A center of a tile element of the first group of tile elements 602 is separated from a center of an adjacent tile element of the second group of tile elements 604 in a fourth direction T by a distance D4. For example, the center of tile element 608[1,1] is separated from the center of tile element 608[1,2] by the distance D4 in the fourth direction T. The fourth direction T is related to the first direction X and the second direction Y. For example, the fourth direction T is rotated from the first direction X by an angle β to the second direction Y. In some embodiments, the angle β ranges from about 0 degrees to about 180 degrees. The relationship between the angle β and the distances D5 and D4 is given by the following formula (5): β=ArcCos(D5 / D4)

[0234] In some embodiments, the fourth direction T is equal to the first direction X or the second direction Y. In some embodiments, the fourth direction T is different from the first direction X or the second direction Y. The center of a tile element of the second group of tile elements 604 is separated in the first direction X by a distance D5 from the center of an adjacent tile element of the first group of tile elements 604. For example, the center of tile element 608[P,1] is separated in the first direction X by the distance D5 from the center of tile element 608[P,2].

[0235] In some embodiments, two recesses (not labeled) of a tile element in the second group of tile elements 604 are flush with tile elements in the first group of tile elements 602, and the other two recesses (not labeled) are not flush with adjacent tile elements of the first group of tile elements 602 or the second group of tile elements 604, thus creating a corresponding gap (not labeled) between adjacent tile elements. In some embodiments, one or more gaps (not labeled) between adjacent tile elements may be used for well contacts (not shown) or substrate contacts (not shown). In some embodiments, additional well contacts (not shown) or substrate contacts (not shown) may be used for better latch-up prevention.In some embodiments, the latch-up is a short circuit between one or more wells and the substrate. In some embodiments, two notches (not labeled) of a tile element in the second group of tile elements 604 are flush with corresponding notches (not labeled) of two different tile elements in the first group of tile elements 602. For example, notch 610a of tile element 608[2,4] of the second group of tile elements 604 is flush with a corresponding notch 612a of tile element 608[1,Q-1] of the first group of tile elements 602, and notch 610b of tile element 608[2,4] of the second group of tile elements 604 is flush with a corresponding notch 612b of tile element 608[2,3] of the first group of tile elements 602.

[0236] In some embodiments, two recesses (not labeled for ease of explanation) of one tile element in the first group of tile elements 602 are flush with corresponding recesses (not labeled for ease of explanation) of two other tile elements in the second group of tile elements 604. For example, recess 612b of tile element 608[2,3] of the first group of tile elements 602 is flush with a corresponding recess 610b of tile element 608[2,4] of the second group of tile elements 604, and recess 614a of tile element 608[2,3] of the first group of tile elements 602 is flush with a corresponding recess 614b of tile element 608[P,2] of the second group of tile elements 604.In some embodiments, two recesses (not labeled for ease of explanation) of a tile element in the second group of tile elements 604 are not flush with portions of adjacent tile elements in the first group of tile elements 602 or in the second group of tile elements 604, creating a gap (not labeled for ease of explanation) that can be used for well contacts (not shown) or substrate contacts (not shown). For example, in some embodiments, a recess 650a of tile element 608[2,4] is not flush with adjacent tile elements 608[1,4] and 608[1,3], creating a gap 622a. Similarly, in some embodiments, a recess 650b of tile element 608[2,4] is not flush with adjacent tile elements 608[2,Q-1] and 608[P,4], creating a gap 622b. As shown in FIG. Fig. 6, in some embodiments, a gap 620a is located between the tile element 608[2,Q-1] and the tile element 608[1,Q-1] of the first group of tile elements 602, and a gap 620b is located between the tile element 608[2,Q-1] and the tile element 608[P,Q-1] of the first group of tile elements 602. In these embodiments, the gap 622a and the gap 622b can be used for well contacts (not shown) or substrate contacts (not shown). In some embodiments, two recesses (not labeled for ease of explanation) of a tile element in the first group of tile elements 602 are not flush with portions of adjacent tile elements in the second group of tile elements 604 or in the first group of tile elements 602.For example, in some embodiments, a recess 652a of tile element 608[2,Q-1] is not flush with adjacent tile elements 608[2,4] and 608[1,Q-1], creating a gap 620a. Similarly, in some embodiments, a recess 652b of tile element 608[2,Q-1] is not flush with adjacent tile elements 608[P,Q-1] and 608[2,Q], creating a gap 620b. In these embodiments, gap 620a and gap 620b may be used for well contacts (not shown) or substrate contacts (not shown). In some embodiments, the gap 620a, 620b, 622a and / or 622b represents 12.5% ​​of the area of ​​a tile element in the first group of tile elements 602 or the second group of tile elements 604.

[0237] In some embodiments, at least one of the distances D1, D1', D2, D2', D3, D3', D4, and D5 is different from another of the distances D1, D1', D2, D2', D3, D3', D4, and D5. In some embodiments, at least one of the distances D1, D1', D2, D2', D3, D3', D4, and D5 is equal to another of the distances D1, D1', D2, D2', D3, D3', D4, and D5. Other sizes or configurations for the first group of tile elements 602 or the second group of tile elements 604 are also within the scope of the present invention. In some embodiments, the recesses of at least one tile element of the first group of tile elements 602 or the second group of tile elements 604 are each rectangular. In some embodiments, the recesses of at least one tile element of the first group of tile elements 602 or the second group of tile elements 604 are each referred to as a corner recess.In some embodiments, the recesses of at least one tile element of the first group of tile elements 602 or the second group of tile elements 604 are each tapered. Other shapes or configurations of the recesses in the first group of tile elements 602 or the second group of tile elements 604 are also within the scope of the present invention.

[0238] In some embodiments, a shape of the first group of tile elements 602 and a shape of the second group of tile elements 604 are non-rectangular, and therefore, they may be placed closer together as standard cells in the layout design 600 than in other designs. In some embodiments, by placing the first group of tile elements 602 and the second group of tile elements 604 closer together than other cells, the first group of tile elements or the second group of tile elements may be used to fabricate corresponding integrated circuits that are arranged closer together than other integrated circuits. In some embodiments, by fabricating the integrated circuits closer together than other integrated circuits, the area of ​​the fabricated integrated circuits is also smaller than other integrated circuits.

[0239] Fig. 7 is a schematic of a layout design 700, according to some embodiments.

[0240] The layout design 700 is a modification of the layout design 600 ( Fig. 6). Similar elements have a similar reference number increased by 100. The layout design 700 combines elements of the layout design 300A of Fig. 3A, of the layout design 400A of Fig. 4A and the layout draft 600 of Fig. 6.

[0241] The layout design 700 includes a tile element 708[1,2], a tile element 708[2,2], a tile element 708[1,3], and a tile element 708[2,3]. The tile elements 708[1,2], 708[2,2], 708[1,3], and 708[2,3] are a modification of the corresponding tile elements 608[1,2], 608[2,2], 608[1,3], and 608[2,3] of Fig. 6.

[0242] The tile elements 708[1,2] and 708[2,2] each correspond to the layout design 300A of Fig. 3A, and the tile elements 708[1,3] and 708[2,3] each correspond to the layout design 400A of Fig. 4A. In some embodiments, the tile elements 708[1,2] and 708[2,2] each correspond to the layout design 400A of Fig. 4A, and the tile elements 708[1,3] and 708[2,3] each correspond to the layout design 300A of Fig. 3A. For ease of explanation, the elements in the tile elements 708[1,2], 708[2,2], 708[1,3] and 708[2,3] are not labeled.

[0243] The tile elements 708[1,2], 708[2,2], 708[1,3] and 708[2,3] comprise a corresponding group of active area layout structures 702, 704, 712 and 714.

[0244] The group of active areas 702 or 704 corresponds to the group of active area layout structures 412a, 412b, 412c, and 412d of layout design 400A. The group of active areas 712 or 714 corresponds to the group of active area layout structures 312a, 312b, 312c, and 312d of layout design 300A.

[0245] The group of active areas 702 includes active area layout structures 702a, 702b, 702c, 702d, 702e, 702f, 702g, and 702h. The active area layout structure 702a corresponds to the active area layout structures 404a and 404b, the active area layout structure 702b corresponds to the active area layout structures 406a and 406b, the active area layout structure 702c corresponds to the active area layout structures 408a and 408b, the active area layout structure 702d corresponds to the active area layout structures 410a and 410b, the active area layout structure 702e corresponds to the active area layout structures 410c and 410d, the active area layout structure 702f corresponds to the active area layout structures 408c and 408d, the active area layout structure 702g corresponds to the active area layout structures 406c and 406d, and the active area layout structure 702h corresponds to the active area layout structures 404c and 404d.

[0246] The group of active areas 704 includes active area layout structures 704a, 704b, 704c, 704d, 704e, 704f, 704g, and 704h. The active area layout structures 704a, 704b, 704c, 704d, 704e, 704f, 704g, and 704h are similar to the corresponding active area layout structures 702a, 702b, 702c, 702d, 702e, 702f, 702g, and 702h, and therefore, the similar detailed description is omitted.

[0247] The group of active areas 712 includes active area layout structures 712a, 712b, 712c, 712d, 712e, 712f, 712g, and 712h. The active area layout structure 712a corresponds to the active area layout structures 304a and 304b, the active area layout structure 712b corresponds to the active area layout structures 306a and 306b, the active area layout structure 712c corresponds to the active area layout structures 308a and 308b, the active area layout structure 712d corresponds to the active area layout structures 310a and 310b, the active area layout structure 712e corresponds to the active area layout structures 310c and 310d, the active area layout structure 712f corresponds to the active area layout structures 308c and 308d, the active area layout structure 712g corresponds to the active area layout structures 306c and 306d, and the active area layout structure 712h corresponds to the active area layout structures 304c and 304d.

[0248] The group of active areas 714 includes active area layout structures 714a, 714b, 714c, 714d, 714e, 714f, 714g, and 714h. The active area layout structures 714a, 714b, 714c, 714d, 714e, 714f, 714g, and 714h are similar to the corresponding active area layout structures 712a, 712b, 712c, 712d, 712e, 712f, 712g, and 712h, and therefore, the similar detailed description is omitted.

[0249] The n-layout structures of the group of active area layout structures 702 or 704 of the corresponding tile element 708[1,2] or 708[2,2] are aligned in the second direction Y with corresponding n-layout structures of the group of active area layout structures 712 or 714 of the corresponding tile element 708[1,3] or 708[2,3]. For example, the n-active area layout structures 702d, 702e, 702h, 704a, 704d, 704e, and 704h are aligned in the second direction Y with the corresponding n-active area layout structures 712b, 712c, 712f, 712g, 714b, 714c, and 714f.

[0250] The p-type layout structures of the group of active area layout structures 712 or 714 of the corresponding tile element 708[1,2] or 708[2,2] are aligned in the second direction Y with corresponding p-type layout structures of the group of active area layout structures 712 or 714 of the corresponding tile element 708[1,3] or 708[2,3]. For example, the p-type active area layout structures 702c, 702f, 702g, 704b, 704c, 704f, and 704g are aligned in the second direction Y with the corresponding p-type active area layout structures 712a, 712d, 712e, 712h, 714a, 714d, and 714e. Other sizes or configurations of the tile elements 708[1,2], 708[2,2], 708[1,3] and 708[2,3] are also within the scope of the present invention.

[0251] In some embodiments, layout design 700 has a non-rectangular shape, resulting in a smaller standard cell than other designs. In some embodiments, because the standard cell is smaller, layout design 700 can be used to fabricate integrated circuits that are smaller than other integrated circuits.

[0252] Fig. 8 is a schematic of a layout design 800 according to some embodiments.

[0253] The layout design 800 is a modification of the layout design 600 of Fig. 6 and the layout draft 700 of Fig. 7. Similar elements have a similar reference number increased by 200. Layout design 800 combines elements of layout design 300B of Fig. 3B, of the layout draft 400B of Fig. 4B and the layout design 600 of Fig. 6.

[0254] In comparison with the layout design 700 of Fig. 7, the layout design 800 further includes a first well layout structure 802, a second well layout structure 804, a third well layout structure 806, a fourth well layout structure 808, a fifth well layout structure 812, a sixth well layout structure 814, a seventh well layout structure 816, an eighth well layout structure 818, and well layout structures 822a, 824a, and 828a.

[0255] The first tub layout structure 802 and the fifth tub layout structure 812 are the second tub layout structure 414 of the layout design 400B of Fig. 4B, and therefore, the similar detailed description is omitted. The second tub layout structure 804 and the sixth tub layout structure 814 are similar to the first tub layout structure 416 of the layout design 400B of Fig. 4B, and therefore, the similar detailed description is omitted. The third tub layout structure 806 and the seventh tub layout structure 816 are similar to the first tub layout structure 314 of the layout design 300B of Fig. 3B, and therefore, the similar detailed description is omitted. The fourth tub layout structure 808 and the eighth tub layout structure 818 are similar to the second tub layout structure 316 of the layout design 300B of Fig. 3B, and therefore the similar detailed description is omitted.

[0256] The first tub layout structure 802 includes tub layout structures 802a, 802b, and 802c. The tub layout structures 802a, 802b, and 802c are corresponding to the tub layout structures 454a, 454b, and 454c of the layout design 400B of Fig. 4B, and therefore the similar detailed description is omitted.

[0257] The second tub layout structure 804 includes tub layout structures 804a, 804b, 804c, and 804d. The tub layout structures 804a, 804b, 804c, and 804d are similar to the corresponding tub layout structures 456a, 456b, 456c, and 456d of the layout design 400B of Fig. 4B, and therefore the similar detailed description is omitted.

[0258] The third tub layout structure 806 includes tub layout structures 806a, 806b, and 806c. The tub layout structures 806a, 806b, and 806c are similar to the corresponding tub layout structures 354a, 354b, and 354c of the layout design 300B of Fig. 3B, and therefore the similar detailed description is omitted.

[0259] The fourth tub layout structure 808 includes tub layout structures 808a and 808b. The tub layout structures 808a and 808b are similar to the corresponding tub layout structures 356a and 356b of the layout design 300B of Fig. 3B, and therefore the similar detailed description is omitted.

[0260] The fifth tub layout structure 812 includes tub layout structures 812a, 812b, and 812c. The tub layout structures 812a, 812b, and 812c are similar to the corresponding tub layout structures 454a, 454b, and 454c of the layout design 400B of Fig. 4B, and therefore the similar detailed description is omitted.

[0261] The sixth tub layout structure 814 includes tub layout structures 814a, 814b, 814c, and 814d. The tub layout structures 814a, 814b, 814c, and 814d are similar to the corresponding tub layout structures 456a, 456b, 456c, and 456d of the layout design 400B of Fig. 4B, and therefore the similar detailed description is omitted.

[0262] The seventh tub layout structure 816 includes tub layout structures 816a, 816b, and 816c. The tub layout structures 816a, 816b, and 816c are similar to the corresponding tub layout structures 354a, 354b, and 354c of the layout design 300B of Fig. 3B, and therefore the similar detailed description is omitted.

[0263] The eighth tub layout structure 818 includes tub layout structures 818a and 818b. The tub layout structures 818a and 818b are similar to the corresponding tub layout structures 356a and 356b of the layout design 300B of Fig. 3B, and therefore the similar detailed description is omitted.

[0264] The tray layout structure 822a is the tray layout structure 456a of the layout design 400B of Fig. 4B, and therefore the similar detailed description is omitted. The tub layout structure 824a is similar to the tub layout structure 454a of the layout design 400B of Fig. 4B, and therefore the similar detailed description is omitted. The tub layout structure 828a is similar to the tub layout structure 356a of the layout design 300B of Fig. 3B, and therefore the similar detailed description is omitted.

[0265] In some embodiments, well layout structures 804a and 808a are part of the same contiguous well layout structure. In some embodiments, at least two of well layout structures 802a, 802b, 802c, 806a, and 806b are part of the same contiguous well layout structure. In some embodiments, well layout structures 804c and 808a are part of the same contiguous well layout structure. In some embodiments, well layout structures 802c and 806b are part of the same contiguous well layout structure. In some embodiments, at least two of well layout structures 804b, 802a, and 808b are part of the same contiguous well layout structure.

[0266] In some embodiments, at least two of the well layout structures 812a, 812b, 812c, 816a, and 816b are part of the same contiguous well layout structure. In some embodiments, the well layout structures 814c and 818a are part of the same contiguous well layout structure. In some embodiments, the well layout structures 812c and 816b are part of the same contiguous well layout structure. In some embodiments, at least two of the well layout structures 822a, 814b, and 818b are part of the same contiguous well layout structure. In some embodiments, the well layout structures 816c and 824a are part of the same contiguous well layout structure.

[0267] Other sizes or configurations of one or more of the first well layout structure 802, the second well layout structure 804, the third well layout structure 806, the fourth well layout structure 808, the fifth well layout structure 812, the sixth well layout structure 814, the seventh well layout structure 816, the eighth well layout structure 818, and the well layout structures 822a, 824a, and 828a are also within the scope of the present invention.

[0268] In some embodiments, layout design 800 has a non-rectangular shape, resulting in a smaller standard cell than other designs. In some embodiments, because the standard cell is smaller, layout design 800 can be used to fabricate integrated circuits that are smaller than other integrated circuits.

[0269] Fig. 9 is a flow diagram of a method 900 for manufacturing a memory cell array according to some embodiments. It is understood that further steps may be performed before, during, and / or after the Fig. 9, and that some further processes may only be briefly described here. In some embodiments, the method 900 may be used to fabricate one or more memory cells, such as memory cell 100 ( Fig. 1), one or more memory cell arrays, such as memory cell arrays 200A and 200B ( Fig. 2A and Fig. 2B) or one or more integrated circuits, such as integrated circuits 500A and 500B ( Fig. 5A to 5H). In some embodiments, the method 900 may be used to fabricate memory cell arrays or integrated circuits having similar structural relationships as one or more of the layout designs 300A and 300B, 400A and 400B, and 600 to 800 ( Fig. 3A and 3B, 4A and 4B and 6 to 8).

[0270] In step 902 of the method 900, a first group of tile elements 602 is generated that extends in a first direction (e.g., the third direction S). In some embodiments, generating the first group of tile elements 602 in step 902 includes a step 902a.

[0271] In some embodiments, step 902a comprises generating a first layout design (e.g., layout designs 300A and 300B) of a first group of memory cells 204. In some embodiments, at least one tile element of the first group of tile elements 602 corresponds to layout design 300A or 300B. In some embodiments, each tile element of the first group of tile elements 602 corresponds to layout design 300A or 300B of the first group of memory cells 204. In some embodiments, each tile element of the first group of tile elements 602 is offset from an adjacent tile element of the first group of tile elements 602 in the second direction Y, which is different from the first direction (e.g., the third direction S).

[0272] In some embodiments, generating the first layout design (e.g., layout designs 300A and 300B) of the first group of memory cells 204 in step 902a includes generating a first portion 302a of the first layout design (e.g., layout designs 300A and 300B), generating a second portion 302b of the first layout design, generating a third portion 302c of the first layout design, and generating a fourth portion 302d of the first layout design.

[0273] In some embodiments, the first part 302a of the first layout design (e.g., layout designs 300A and 300B) corresponds to fabricating a first memory cell 202[1,2] of the first group of memory cells 204 of the memory cell arrays 200A and 200B. In some embodiments, the second part 302b of the first layout design (e.g., layout designs 300A and 300B) corresponds to fabricating a second memory cell 202[2,2] of the first group of memory cells 204 of the memory cell arrays 200A and 200B. In some embodiments, the third part 302c of the first layout design (e.g., layout designs 300A and 300B) corresponds to fabricating a third memory cell 202[1,3] of the first group of memory cells 204 of the memory cell arrays 200A and 200B. In some embodiments, the fourth part 302d of the first layout design (e.g.,of the layout designs 300A and 300B) the fabrication of a fourth memory cell 202[2,3] of the first group of memory cells 204 of the memory cell matrices 200A and 200B.

[0274] In some embodiments, the first portion 302a of the first layout design (e.g., layout designs 300A and 300B) and the second portion 302b of the first layout design are mirror images of each other with respect to the second direction Y. In some embodiments, the third portion 302c of the first layout design (e.g., layout designs 300A and 300B) and the fourth portion 302d of the first layout design are mirror images of each other with respect to the second direction Y.

[0275] In step 904 of the method 900, a second group of tile elements 604 is generated that extends in the first direction (e.g., the third direction S). In some embodiments, the second group of tile elements 604 is spaced from the first group of tile elements 602 at least in the second direction Y. In some embodiments, generating the second group of tile elements 604 in step 904 includes a step 904a.

[0276] In some embodiments, step 904a comprises generating a second layout design (e.g., layout designs 400A and 400B) of a second group of memory cells 206. In some embodiments, at least one tile element of the second group of tile elements 604 corresponds to layout design 400A or 400B. In some embodiments, each tile element of the second group of tile elements 604 corresponds to the second layout design (e.g., layout designs 400A and 400B) of the second group of memory cells 206. In some embodiments, each tile element of the second group of tile elements 604 is offset from an adjacent tile element of the second group of tile elements 604 in the second direction Y.

[0277] In some embodiments, generating the second layout design (e.g., layout designs 400A and 400B) of the second group of memory cells 206 in step 904a includes generating a first portion 402a of the second layout design (e.g., layout designs 400A and 400B), generating a second portion 402b of the second layout design, generating a third portion 402c of the second layout design, and generating a fourth portion 402d of the second layout design.

[0278] In some embodiments, the first part 402a of the second layout design (e.g., layout designs 400A and 400B) corresponds to fabricating a first memory cell 202[2,4] of the second group of memory cells 206 of the memory cell arrays 200A and 200B. In some embodiments, the second part 402b of the second layout design (e.g., layout designs 400A and 400B) corresponds to fabricating a second memory cell 202[3,4] of the second group of memory cells 206 of the memory cell arrays 200A and 200B. In some embodiments, the third part 402c of the second layout design (e.g., layout designs 400A and 400B) corresponds to fabricating a third memory cell 202[2,5] of the second group of memory cells 206 of the memory cell arrays 200A and 200B. In some embodiments, the fourth part 402d of the second layout design (e.g.,of the layout designs 400A and 400B) the fabrication of a fourth memory cell 202[3,5] of the second group of memory cells 206 of the memory cell matrices 200A and 200B.

[0279] In some embodiments, the first portion 402a of the second layout design (e.g., layout designs 400A and 400B) and the third portion 402c of the second layout design are mirror images of each other with respect to the third direction S (e.g., the first direction X). In some embodiments, the second portion 402b of the second layout design (e.g., layout designs 400A and 400B) and the fourth portion 402d of the second layout design are mirror images of each other with respect to the third direction S (e.g., the first direction X).

[0280] In some embodiments, the first group of tile elements 602 and the second group of tile elements 604 alternate with each other in the second direction Y. In some embodiments, each tile element of the first group of tile elements 602 and each tile element of the second group of tile elements 604 extend in a third direction (e.g., the first direction X) that is different from the first direction and the second direction.

[0281] In some embodiments, step 902 and / or step 904 are performed with a processing device, e.g., a processor 1202 ( Fig. 12) configured to execute instructions to generate the first group of tile elements 602 or the second group of tile elements 604. In some embodiments, the first group of tile elements 602 or the second group of tile elements 604 is stored in a memory, e.g., a non-transitory machine-readable medium 1204 ( Fig. 12), saved as a layout draft 1216.

[0282] In some embodiments, layout designs 300A and 300B, 400A and 400B, and / or 600 to 800 are a graphical database system (GDSII) file format.

[0283] In step 906 of the method 900, a memory cell array 200A or 200B or an integrated circuit 500A or 500B is manufactured based on the first layout design (the layout design 300A or 300B), the second layout design (the layout design 400A or 400B) and / or the layout designs 600 to 800. In some embodiments, step 906 of method 900 includes fabricating memory cell array 200A or 200B or integrated circuit 500A or 500B based on the first group of tile elements 602 and / or the second group of tile elements 604. In some embodiments, step 906 includes fabricating memory cell 100 based on the first layout design 300A or 300B and / or the second layout design 400A or 400B.In some embodiments, step 906 of method 900 includes fabricating memory cell array 200A or 200B or integrated circuit 500A or 500B based on the first group of tile elements 602 and / or the second group of tile elements 604.

[0284] In some embodiments, step 906 of method 900 includes fabricating at least one mask based on the first layout designs 300A and 300B, 400A and 400B, and / or 600 to 800, and fabricating the memory cell array (e.g., memory cell 100, memory cell arrays 200A and 200B) or the integrated circuit (e.g., integrated circuit 500A or 500B) based on the at least one mask.

[0285] In some embodiments, one or more of steps 902, 904, and 906 are not performed.

[0286] In some embodiments, method 900 generates one or more layout designs (e.g., first layout designs 300A and 300B, second layout designs 400A and 400B, or layout designs 600-800) that occupy a smaller area than other approaches. In some embodiments, method 900 is used to fabricate a memory cell array (e.g., memory cell 100, memory cell arrays 200A and 200B, or integrated circuits 500A and 500B) that occupy a smaller area than other memory cell arrays.

[0287] The Fig. 10A and Fig. 10B is a flow diagram of a method 1000 for generating a layout design of a memory cell array according to some embodiments. It is understood that further steps may be performed before, during, and / or after the Fig. 10A and Fig. 10B, and that some further processes may only be briefly described here. The method 1000 is an embodiment of steps 902a and / or 904a. In some embodiments, the method 1000 may be used to generate one or more of the layout designs 300A and 300B ( Fig. 3A and Fig. 3B) or Fig. 400A and Fig. 400B ( Fig. 4A and Fig. 4B) or Fig. 600 and Fig. 700 ( Fig. 6 and Fig. 7) of the memory cell 100 ( Fig. 1), the memory cell matrices 200A and 200B ( Fig. 2A and Fig. 2B) or the integrated circuits 500A and 500B ( Fig. 5A to 5H) can be used.

[0288] In step 1002 of the method 1000, a first group of active area layout patterns 312a or 412a is generated. In some embodiments, generating the group of active area layout patterns 312a or 412a corresponds to fabricating a group of active areas 504 or 505 of the memory cell arrays 200A and 200B. In some embodiments, the layout patterns of the group of active area layout patterns 312a or 412a are each separated in the first direction X by a first distance from an adjacent layout pattern of the group of active area layout patterns 312a or 412a. In some embodiments, the group of active area layout structures 312a or 412a extends in the second direction Y, which is different from the first direction X, and is arranged on a first layout level (e.g., an active area or a well).

[0289] In some embodiments, the group of active area layout patterns in method 1000 includes one or more of the groups of active area layout patterns 312b, 312c, 312d, 412a, 412b, and 412c.

[0290] In some embodiments, generating the group of active area layout patterns 312a or 412a in step 1002 includes generating a first active area layout pattern 304a or 404a adjacent to a first side 352a or 452a of the layout designs 300A and 300B or 400A and 400B of the memory cell 100, and generating a second active area layout pattern 310a or 410a adjacent to a second side 352b1 or 452b1 of the memory cell 100 that is opposite to the first side 352a or 452a of the memory cell 100. In some embodiments, a length of the first active area layout pattern 304a or 404a in the second direction Y is different from a length of the second active area layout pattern 310a or 410a in the second direction Y.

[0291] In step 1004, a group of active area layout patterns 312a or 412a is placed on a first layout level. In some embodiments, the first layout level corresponds to the active area of ​​layout designs 300A and 300B or 400A and 400B (Figures 400A and 400B).

[0292] In step 1006, a group of gate layout patterns 326a or 426a is generated. In some embodiments, the group of gate layout patterns 326a or 426a corresponds to the formation of a group of gate structures 527 of the memory cell arrays 200A and 200B or the integrated circuits 500A and 500B. In some embodiments, the group of gate layout patterns 326a or 426a extends in the first direction X and overlaps the group of active area layout patterns 312a or 412a.

[0293] In some embodiments, the group of gate layout structures in method 1000 includes one or more gate layout structures from the group of gate layout structures 326b, 326c, 326d, 426b, 426c, and 426d.

[0294] In step 1008, the group of gate layout structures 326a or 426a is placed on a second layout level (e.g., POLY) that is different from the first layout level.

[0295] In step 1010, a first group of conductive element layout patterns 338a or 438a is generated. In some embodiments, the first group of conductive element layout patterns 338a or 438a corresponds to the formation of a first group of conductive patterns 538 of the memory cell arrays 200A and 200B or the integrated circuits 500A and 500B. In some embodiments, the first group of conductive element layout patterns 338a or 438a extends in the first direction X and is located above the group of active area layout patterns 312a or 412a and / or the group of gate layout patterns 326a or 426a. In some embodiments, each conductive element layout pattern of the first group of conductive element layout patterns 338a or 438a is spaced in the first direction X and / or the second direction Y from an adjacent layout pattern of the first group of conductive element layout patterns 338a or 438a.

[0296] In some embodiments, the first group of conductive element layout patterns 338a or 438a in method 1000 comprises one or more conductive element layout patterns of the group of conductive element layout patterns 338b, 338c, 338d, 340, 342, 344, 438b, 438c, 438d, 440, 442, and 444.

[0297] In step 1012, the first group of conductive element layout patterns 338a or 438a is placed on a third layout level (e.g., M1) that is different from the first layout level and the second layout level.

[0298] In step 1014, a second group of conductive element layout patterns 350 or 450 is generated. In some embodiments, the second group of conductive element layout patterns 350 or 450 corresponds to fabricating a second group of conductive patterns 552 of the memory cell arrays 200A and 200B or the integrated circuits 500A and 500B. In some embodiments, the second group of conductive element layout patterns 350 or 450 extends in the first direction X and overlaps the second active area layout pattern 310a, 310b, 310c, 310d, 410a, 410b, 410c, or 410d and / or the second side 352b1 or 452b1 of the layout designs 300A and 300B or 400A and 400B of the memory cell 100.In some embodiments, each conductive element layout pattern of the second group of conductive element layout patterns 350 or 450 is spaced apart in the first direction X and / or the second direction Y from an adjacent layout pattern of the second group of conductive element layout patterns 350 or 450.

[0299] In step 1016, the second group of conductive element layout patterns 350 or 450 is placed on a fourth layout level (e.g., M2) that is different from the first layout level, the second layout level, and the third layout level.

[0300] In step 1018, a second group of via layout patterns 358a or 458a is created. In some embodiments, the first group of via layout patterns 358a or 458a corresponds to the formation of a first group of vias 572. In some embodiments, the first group of vias 572 connects the first group of conductive patterns 538 to the group of active areas 504 or 505. In some embodiments, each via layout pattern of the first group of via layout patterns 358a or 458a is arranged at the location where each conductive element layout pattern of the first group of conductive element layout patterns 338a or 438a overlaps each active area layout pattern of the group of active area layout patterns 312a or 412a.

[0301] In some embodiments, the first group of via layout structures in method 1000 includes one or more of via layout structures 358b, 358c, 358d, 458b, 458c, 458d, 374, 376, 378, 380, 474, 476, 478, and 480.

[0302] In step 1020, the first group of via layout patterns 358a or 458a is placed between the first group of conductive element layout patterns 338a or 438a and the group of active area layout patterns 312a or 412a. In some embodiments, the first group of via layout patterns 358a or 458a is located at least at the Vo level of layout designs 300A and 300B or 400A and 400B.

[0303] In step 1022, a second group of via layout structures 380 or 480 is created. In some embodiments, the second group of via layout structures 380 or 480 corresponds to the formation of a second group of vias 532. In some embodiments, the second group of vias 532 connects the first group of conductive element layout structures 338a or 438a to the group of gates 527. In some embodiments, a first via layout structure 380a or 480a of the second group of via layout structures 380 or 480 is arranged at the location where a first conductive element layout structure 340a or 440a of the group of conductive element layout structures 340 or 440 connects a first gate layout structure 324a, 324c, 424a or 424c of the group of gate layout structures 326a or 426a overlaps.

[0304] In some embodiments, the second group of via layout structures in method 1000 includes one or more of via layout structures 358a, 358b, 358c, 358d, 458a, 458b, 458c, 458d, 374, 376, 378, 474, 476, and 478.

[0305] In step 1024, the second group of via layout patterns 380 or 480 is arranged between the first group of conductive element layout patterns 340 or 440 and the group of gate layout patterns 326a or 426a. In some embodiments, the second group of via layout patterns 380 or 480 is located at least at the VG level of layout designs 300A and 300B or 400A and 400B.

[0306] The method 1000 includes either steps 1026 to 1032 or steps 1026' to 1032'.

[0307] Steps 1026 through 1032 are discussed with reference to layout designs 300A and 300B. For example, the first tub layout structure 314 corresponds to the first tub layout structure of steps 1026 through 1032, and the second tub layout structure 316 corresponds to the second tub layout structure of steps 1026 through 1032 of layout designs 300A and 300B.

[0308] Steps 1026' to 1032' are discussed with reference to layout designs 400A and 400B, where the first tub layout structure 416 corresponds to the first tub layout structure of steps 1026' to 1032' and the second tub layout structure 414 corresponds to the second tub layout structure of steps 1026' to 1032'.

[0309] For simplicity, steps 1026' to 1032' are discussed after the discussion of steps 1026 to 1032.

[0310] In step 1026, a first well layout structure 314 is created. In some embodiments, the first well layout structure 314 corresponds to the formation of a first well 501 of the memory cell arrays 200A and 200B or the integrated circuit 500A. In some embodiments, the first well 501 has a first dopant type. In some embodiments, the first dopant type is an n-type dopant. In some embodiments, the first dopant type is a p-type dopant.

[0311] In some embodiments, step 1026 includes one or more of steps 1026a and 1026b.

[0312] In some embodiments, step 1026a comprises generating a first layout structure (e.g., layout structure 354a or 354c). In some embodiments, first layout structure 354a corresponds to forming a first portion 501a of first well 501. In some embodiments, first layout structure 354a extends in second direction Y and is adjacent to first side 352a of layout structure 300B of memory cell 100.

[0313] In some embodiments, step 1026b comprises creating a second layout structure (e.g., layout structure 354b). In some embodiments, second layout structure 354b corresponds to forming a second portion 501b of first well 501. In some embodiments, the second layout structure extends in the second direction and is adjacent to the second side of memory cell 100.

[0314] In step 1028, the first well layout structure 314 is placed on a fourth layout level (e.g., the well level) that is different from the first layout level, the second layout level, and the third layout level. In some embodiments, a portion of the fourth layout level includes the first layout level. In some embodiments, a portion of the fourth layout level is the same as the first layout level.

[0315] In some embodiments, step 1028 includes step 1028a and / or step 1028b.

[0316] In some embodiments, step 1028a includes placing the first layout pattern 354a under the first active area layout pattern 304a.

[0317] In some embodiments, step 1028b includes placing the second layout pattern 354b under the second active area layout pattern 310a.

[0318] In step 1030, a second well layout structure 316 is created. In some embodiments, the second well layout structure 316 corresponds to the formation of a second well 501' of the memory cell arrays 200A and 200B or the integrated circuit 500A. In some embodiments, the second well 501' has a second dopant type that is different from the first dopant type. In some embodiments, the second dopant type is a p-dopant. In some embodiments, the second dopant type is an n-dopant.

[0319] In some embodiments, step 1030 includes step 1030a and / or step 1030b.

[0320] In some embodiments, step 1030a comprises creating a third layout structure (e.g., layout structure 356a). In some embodiments, third layout structure 356a corresponds to fabricating a portion 501c of second well 501'. In some embodiments, third layout structure 356a extends in second direction Y. In some embodiments, third layout structure 356a is disposed between first layout structure 354a and second layout structure 354b.

[0321] In some embodiments, step 1030b comprises creating a fourth layout structure (e.g., layout structure 356b). In some embodiments, fourth layout structure 356b corresponds to fabricating a portion of second well 501' that is similar to portion 501c. In some embodiments, fourth layout structure 356b extends in second direction Y. In some embodiments, fourth layout structure 356b is disposed between second layout structure 354b and third layout structure 354c.

[0322] In step 1032, the second well layout structure 316 is placed on the fourth layout level. In some embodiments, step 1032 further comprises arranging the second well layout structure 316 between the first layout structure 354a and the second layout structure 354b. In some embodiments, step 1032 further comprises arranging the second well layout structure 316 below a third active area layout structure 306a of the group of active area layout structures 312a and a fourth active area layout structure 308a of the group of active area layout structures 312a.

[0323] In some embodiments, step 1032 includes step 1032a and / or step 1032b.

[0324] In some embodiments, step 1032a includes placing the third layout pattern 356a below the third active area layout pattern 306a of the group of active area layout patterns 312a and the fourth active area layout pattern 308a of the group of active area layout patterns 312a.

[0325] In some embodiments, step 1032b includes placing the fourth layout pattern 356b below the fourth active area layout pattern 306b of the group of active area layout patterns 312a and the active area layout pattern 308b of the group of active area layout patterns 312a.

[0326] For simplicity, steps 1026' to 1032' are discussed after the discussion of steps 1026 to 1032.

[0327] In step 1026', a first well layout structure 416 is generated. In some embodiments, the first well layout structure 416 corresponds to the fabrication of a first well 502 of the memory cell arrays 200A and 200B or the integrated circuit 500B. In some embodiments, the first well 502 has a first dopant type. In some embodiments, the first dopant type is a p-dopant. In some embodiments, the first dopant type is an n-dopant.

[0328] In some embodiments, step 1026' includes step 1026a' and / or step 1026b'.

[0329] In some embodiments, step 1026a' comprises generating a first layout structure (e.g., layout structure 456a or 456b). In some embodiments, first layout structure 456a corresponds to forming a first portion 502a of first well 502. In some embodiments, first layout structure 456a extends in second direction Y and is adjacent to first side 452a of layout structure 400B of memory cell 100.

[0330] In some embodiments, step 1026b' comprises generating a second layout structure (e.g., layout structure 456c or 456d). In some embodiments, second layout structure 456c corresponds to fabricating a second portion 502b of first well 501. In some embodiments, second layout structure 456c extends in second direction Y and is adjacent to second side 452b1 of layout design 400B of memory cell 100.

[0331] In step 1028', the first well layout structure 416 is placed on the fourth layout level. In some embodiments, step 1028' includes step 1028a' and / or step 1028b'.

[0332] In some embodiments, step 1028a' includes placing the first layout pattern 456a below the first active area layout pattern 404a.

[0333] In some embodiments, step 1028b' includes placing the second layout pattern 456c under a first portion 410a1 of the second active area layout pattern 410a.

[0334] In step 1030', a second well layout structure 414 is created. In some embodiments, the second well layout structure 414 corresponds to the formation of a second well 502' of the memory cell arrays 200A and 200B or the integrated circuit 500B. In some embodiments, the second well 502' has a second dopant type that is different from the first dopant type. In some embodiments, the second dopant type is an n-type dopant. In some embodiments, the second dopant type is a p-type dopant.

[0335] In some embodiments, step 1030' includes step 1030a' and / or step 1030b'.

[0336] In some embodiments, step 1030a' comprises creating a third layout structure (e.g., layout structure 454a or 454c). In some embodiments, third layout structure 454a corresponds to forming a first portion 502c of second well 502'. In some embodiments, third layout structure 454a extends in second direction Y.

[0337] In some embodiments, step 1030b' comprises generating a fourth layout structure (e.g., layout structure 454b). In some embodiments, fourth layout structure 454b corresponds to forming a second portion 502d of second well 502'. In some embodiments, fourth layout structure 454b extends in second direction Y and is adjacent to second side 452b1 of layout design 400B of memory cell 100.

[0338] In step 1032', the second tray layout structure 414 is placed on the fourth layout level.

[0339] In some embodiments, step 1032' includes step 1032a' and / or step 1032b'.

[0340] In some embodiments, step 1032a' comprises arranging the third layout structure 454a between the first layout structure 456a and the second layout structure 456c and / or the fourth layout structure 456d. In some embodiments, step 1032a' comprises arranging the third layout structure 454a below a third active area layout structure 406a of the group of active area layout structures 412a and a fourth active area layout structure 408a of the group of active area layout structures 412a.

[0341] In some embodiments, step 1032b' includes arranging the fourth layout pattern 454b under a second part 410a2 of the second active area layout pattern 410a.

[0342] In some embodiments, one or more of steps 1002 to 1024, 1026 to 1032, and 1026' to 1032' are not performed.

[0343] One or more of the steps of the method 1000 are performed with a processing device, e.g., a processor 1202 ( Fig. 12) configured to execute instructions to generate a layout design (e.g., the first layout designs 300A and 300B, the second layout designs 400A and 400B, or the layout designs 600 to 800). In some embodiments, the first layout designs 300A and 300B, the second layout designs 400A and 400B, or the layout designs 600 to 800 are stored in a memory, e.g., a non-transitory machine-readable medium 1204 ( Fig. 12), stored as a layout draft 1216. In some embodiments, one or more steps of methods 900 and 1000 are performed with the same processing device as that used in one or more other steps of methods 900 and 1000. In some embodiments, a different processing device than that used to perform one or more other steps of methods 900 and 1000 is used to perform one or more steps of methods 900 and 1000.

[0344] In some embodiments, method 1000 generates one or more layout designs (e.g., first layout designs 300A and 300B, second layout designs 400A and 400B, or layout designs 600-800) that occupy a smaller area than other approaches.

[0345] Fig. 11 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an associated IC manufacturing process, in accordance with at least one embodiment of the present invention.

[0346] In Fig. 11, the IC manufacturing facility 1100 includes multiple units, such as a design house 1120, a mask house 1130, and an IC manufacturer ("chip fab") 1140, that interact with each other in the design, development, and manufacturing cycles and / or in the services associated with the manufacture of an IC device 1160. The units in the facility 1100 are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network includes various networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each unit interacts with one or more of the other units and provides and / or receives services to one or more of the other units.In some embodiments, two or more of the design house 1120, mask house 1130, and IC factory 1140 units are owned by a single larger company. In some embodiments, two or more of the design house 1120, mask house 1130, and IC factory 1140 units coexist in a common facility and share common resources.

[0347] The design house (or design team) 1120 creates an IC design layout 1122. The IC design layout 1122 includes various geometric structures designed for the IC device 1160. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 1160 to be manufactured. The various layers combine to form various IC structural elements. For example, a portion of the IC design layout 1122 includes various IC structural elements, such as an active area, a gate electrode, a source electrode, and a drain electrode, metal lines or vias of an interlayer interconnect, and openings for bond pads to be manufactured in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate.The design house 1120 implements a suitable design process for producing the IC design layout 1122. The design process includes one or more of the steps of logic design, physical design, and placement and routing. The IC design layout 1122 is represented in one or more data files containing information about the geometric structures. The IC design layout 1122 can be represented, for example, in a GDSII file format or a DFII file format.

[0348] In the mask house 1130, mask data preparation 1132 and mask fabrication 1134 are performed. The mask house 1130 uses the IC design layout 1122 to produce one or more masks to be used for fabricating the various layers of the IC device 1160 according to the IC design layout 1122. The mask house 1130 performs mask data preparation 1132, in which the IC design layout 1122 is translated into a representative data file (RDF). During mask data preparation 1132, the RDF is provided for mask fabrication 1134. A mask writer is used in mask fabrication 1134. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer.The IC design layout 1122 is manipulated during mask data preparation 1132 to conform to certain properties of the mask writer and / or to meet requirements of the IC factory 1140. In . Fig. 11, mask data preparation 1132 and mask fabrication 1134 are depicted as separate elements. In some embodiments, mask data preparation 1132 and mask fabrication 1134 may be collectively referred to as mask data preparation.

[0349] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those that may arise from diffraction, interference, other process effects, and the like. OPC aligns IC design layout 1122. In some embodiments, mask data preparation 1132 further includes resolution enhancement techniques (RET), such as off-axis illumination, partial resolution assist elements, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT), which treats OPC as an inverse imaging problem, is also used.

[0350] In some embodiments, mask data preparation 1132 utilizes a mask rule checker (MRC), which checks the IC design layout that has undergone processes in the OPC against a set of mask generation rules containing certain geometric and / or interconnect constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. To comply with the mask generation rules, in some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during mask fabrication 1134 that may undo some of the modifications performed by the OPC.

[0351] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), which simulates the processing implemented by IC fabricator 1140 to manufacture IC device 1160. LPC simulates this processing based on IC design layout 1122 to produce a simulated manufactured device, such as IC device 1160. The processing parameters in LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with equipment used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as inter-image contrast, depth of field (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, if after the LPC generates a simulated fabricated device, the simulated device is too far from conforming to the design rules in terms of shape, the OPC and / or MRC may need to be repeated to further improve the IC design layout 1122.

[0352] It should be appreciated that the above description of mask data preparation 1132 has been simplified for clarity. In some embodiments, mask data preparation 1132 includes additional functions, such as a logic operation (LOP), to modify IC design layout 1122 according to manufacturing rules. Furthermore, the processes used for IC design layout 1122 during mask data preparation 1132 may be performed in different orders.

[0353] After mask data preparation 1132 and during mask fabrication 1134, a mask or a group of masks is fabricated based on the modified IC design layout. In some embodiments, an electron beam or a multiple electron beam mechanism is used to fabricate a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be fabricated using various technologies. In some embodiments, the mask is fabricated using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the photosensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and is transmitted through the transparent regions.In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) deposited in the opaque areas of the mask. In another example, the mask is fabricated using phase shift technology. In the phase shift mask (PSM), various elements in the structure fabricated on the mask are configured to have a phase difference suitable for improving resolution and image quality. In various examples, the phase shift mask may be an attenuated phase shift mask or a variable phase shift mask. The masks produced by mask fabrication 1144 are used in various processes.Such masks are used, for example, in an ion implantation process for producing different doped regions in a semiconductor wafer, in an etching process for producing different etched regions in the semiconductor wafer and / or in other suitable processes.

[0354] The IC fab 1140 is an IC manufacturing facility that has one or more production lines for manufacturing many different IC products. In some embodiments, the IC fab 1140 is a semiconductor manufacturing facility. For example, there may be one production line for the front-end manufacturing of multiple IC products (FEOL manufacturing; FEOL: Front End of Line), while a second production line enables back-end manufacturing for interconnecting and packaging the IC products (BEOL manufacturing; BEOL: Back End of Line), and a third production line provides other services to the manufacturing facility.

[0355] In the IC fabricator 1140, the one or more masks manufactured by the mask house 1130 are used to fabricate the IC device 1160. Thus, the IC fabricator 1140 at least indirectly uses the IC design layout 1122 to fabricate the IC device 1160. In some embodiments, a semiconductor wafer 1142 is fabricated by the IC fabricator 1140 using the one or more masks to fabricate the IC device 1160. The semiconductor wafer 1142 includes a silicon substrate or other suitable substrate on which layers of material are fabricated. The semiconductor wafer further includes one or more various doped regions, dielectric features, multilevel interconnects, and the like (which are fabricated in later fabrication steps).

[0356] Details of an IC manufacturing facility (e.g., IC Manufacturing Facility 1100 of Fig. 11) and an IC manufacturing process associated therewith can be found, for example, in the following documents, which are incorporated by reference: U.S. Patent No. 9,256,709, issued on February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published on October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published on February 6, 2014; and U.S. Patent No. 7,260,442, issued on August 21, 2007.

[0357] Fig. 12 is a block diagram of a system 1200 for creating an IC layout design, according to some embodiments. In some embodiments, the system 1200 creates or places one or more layout designs described herein. The system 1200 includes a hardware processor 1202 and a non-transitory machine-readable storage medium 1204 encoded with (i.e., storing) computer program code 1206, i.e., a set of executable instructions. The machine-readable storage medium 1204 is configured for connection to machines for manufacturing the integrated circuit (e.g., the memory cell array). The processor 1202 is electrically connected to the machine-readable storage medium 1204 via a bus 1208. The processor 1202 is also electrically connected to an I / O interface 1210 via the bus 1208. In addition, a network interface 1212 is electrically connected to the processor 1202 via the bus 1208.The network interface 1212 is connected to a network 1214 so that the processor 1202 and the machine-readable storage medium 1204 can be connected to external elements via the network 1214. The processor 1202 is configured to execute the computer program code 1206 encoded in the machine-readable storage medium 1204 so that the system 1200 can be used to perform some or all of the steps described in the method 900 or 1000.

[0358] In some embodiments, processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or any suitable processing unit.

[0359] In some embodiments, machine-readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). Machine-readable storage medium 1204 includes, for example, semiconductor or read-only memory, magnetic tape, removable disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or an optical disk. In some embodiments that utilize optical disks, machine-readable storage medium 1204 includes compact disc read-only memory (CD-ROM), compact disc read / write (CD-R / W), and / or digital video disk (DVD).

[0360] In some embodiments, storage medium 1204 stores computer program code 1206 configured to cause system 1200 to perform method 900 or 1000. In some embodiments, storage medium 1204 also stores information required to perform method 900 or 1000, as well as information generated in performing method 900 or 1000, such as layout design 1216 and a user interface 1218, and / or a set of executable instructions for performing the steps of method 900 or 1000. In some embodiments, layout design 1216 includes one or more of layout designs 300A, 300B, 400A, 400B, and 600-800.

[0361] In some embodiments, storage medium 1204 stores instructions (e.g., computer program code 1206) for interfacing with manufacturing machines. Using the instructions (e.g., computer program code 1206), processor 1202 can generate manufacturing instructions that can be read by the manufacturing machines to effectively implement method 900 or 1000 during a manufacturing process.

[0362] System 1200 includes an I / O interface 1210. I / O interface 1210 connects to external circuitry. In some embodiments, I / O interface 1210 includes a keyboard, keypad, mouse, trackball, touchpad, and / or cursor direction keys for sending information and commands to processor 1202.

[0363] System 1200 also includes a network interface 1212 connected to processor 1202. Network interface 1212 enables system 1200 to communicate with network 1214 to which one or more other computer systems are connected. Network interface 1212 includes wireless network interfaces, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or wired network interfaces, such as ETHERNET, USB, or IEEE-1394. In some embodiments, method 900 or 1000 is implemented in two or more systems 1200, and information, such as layout design and user interface, is exchanged between different systems 1200 over network 1214.

[0364] The system 1200 is configured to receive layout design information via the I / O interface 1210 or the network interface 1212. The information is sent via bus 1208 to the processor 1202 to specify a layout design for fabricating the memory cell 100, the memory cell array 200A or 200B, and / or the memory cell array 500A or 500B. The layout design is then stored in the machine-readable medium 1204 as layout design 1216. The system 1200 is configured to receive user interface information via the I / O interface 1210 or the network interface 1212. The information is stored in the machine-readable medium 1204 as user interface 1218.

[0365] In some embodiments, the method 900 or 1000 is implemented as an independent software application for execution by a processor. In some embodiments, the method 900 or 1000 is implemented as a software application that is part of another software application. In some embodiments, the method 900 or 1000 is implemented as a plug-in for a software application. In some embodiments, the method 900 or 1000 is implemented as a software application that is part of an EDA tool. In some embodiments, the method 900 or 1000 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of the integrated circuit device or the memory cell array. In some embodiments, the layout is stored on a non-transitory machine-readable medium.In some embodiments, the layout is created using a tool such as VIRTUOSO. ® available from CADENCE DESIGN SYSTEMS, Inc., or with another suitable layout generation tool. In some embodiments, the layout is generated based on a netlist generated from the schematic design. In some embodiments, the method 900 or 1000 is implemented with a manufacturing apparatus for manufacturing an integrated circuit (e.g., the memory cell 100 or the memory cell arrays 300A and 300B, 400A and 400B, 600 to 800, or 500A to 500H) using a set of masks manufactured based on one or more layout designs (e.g., the layout designs 300A, 300B, 400A, 400B, and 600 to 800) generated by the system 1200.

[0366] The System 1200 from Fig.12 produces layout designs (e.g., layout designs 300A, 300B, 400A, 400B, or 600 to 800) of memory cell 100, memory cell array 200A or 200B, or memory cell array 500A or 500B that occupy a smaller area than other approaches.

[0367] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Method (900) for producing a memory cell matrix (200A, 200B) comprising the following steps: Creating (902) a first group of tile elements (602) extending in a first direction (S), wherein creating the first group of tile elements (602) comprises: Creating (902a) a first layout design (300A, 300B) of a first group of memory cells (204), wherein each tile element of the first group of tile elements (602) corresponds to the first layout design (300A, 300B) of the first group of memory cells (204) and is offset from an adjacent tile element of the first group of tile elements (602) in a second direction (Y) different from the first direction (S); Creating (904a) a second group of tile elements (604), wherein creating the second group of tile elements (604) comprises: Creating a second layout design (400A-400B) of a second group of memory cells (206), wherein each tile element of the second group of tile elements (604) corresponds to the second layout design (400A-400B) of the second group of memory cells (206) and is offset from an adjacent tile element of the second group of tile elements (604) in the second direction (Y), wherein each tile element of the first group of tile elements (602) extends in a third direction (X) that is different from the first direction (S) and the second direction (Y), wherein the first group of tile elements (602) and the second group of tile elements (604) alternate with each other in the second direction (Y), and each tile element of the second group of tile elements (604) extends in the third direction (X), at least one of the aforementioned generation steps is carried out by a hardware processor, and the first layout design (300A, 300B) is stored in a non-transitory machine-readable medium; and manufacturing (906) the memory cell matrix (200A, 200B) based on at least the first layout design; wherein the first group of memory cells (204) is arranged in at least a first row and a second row of the memory cell matrix (200A, 200B), wherein the first group of memory cells (204) comprises four memory cells (204a, 204b, 204c, 204d), wherein each memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) comprises a memory cell of a synchronous random access memory (SRAM) with five transistors (5T), and the second group of memory cells (206) is arranged in at least a third row and a fourth row of the memory cell matrix (200A, 200B), wherein the second group of memory cells (206) comprises four memory cells (206a, 206b, 206c, 206d), wherein each memory cell (206a, 206b, 206c, 206d) of the second group of memory cells (206) comprises a 5T SRAM memory cell; wherein generating the first layout design (300A, 300B) of the first group of memory cells (204) comprises: Creating a first part (302a) of the first layout design (300A, 300B), wherein the first part (302a) of the first layout design (300A, 300B) corresponds to the production of a first memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B); Creating a second part (302b) of the first layout design (300A, 300B), wherein the second part (302b) of the first layout design (300A, 300B) corresponds to the production of a second memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B); Creating a third part (302c) of the first layout design (300A, 300B), wherein the third part (302c) of the first layout design (300A, 300B) corresponds to the production of a third memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B); and Creating a fourth part (302d) of the first layout design (300A, 300B), wherein the fourth part (302d) of the first layout design (300A, 300B) corresponds to the production of a fourth memory cell (204a, 204b, 204c, 204d) of the first group of memory cells (204) of the memory cell matrix (200A, 200B), wherein the first part (302a) of the first layout design (300A, 300B) and the third part (302c) of the first layout design (300A, 300B) are mirror images of each other with respect to the second direction (Y), and the second part (302b) of the first layout design (300A, 300B) and the fourth part (302d) of the first layout design (300A, 300B) are mirror images of each other with respect to the second direction (Y). [2] The method of claim 1, wherein generating the second layout design (400A-400B) of the second group of memory cells (206) comprises: Creating a first part (402a) of the second layout design (400A-400B), wherein the first part (402a) of the second layout design (400A-400B) corresponds to the production of a first memory cell (202[1,2]) of the second group of memory cells (206) of the memory cell matrix; Creating a second part (402b) of the second layout design (400A-400B), wherein the second part (402b) of the second layout design (400A-400B) corresponds to the production of a second memory cell (202[2,2]) of the second group of memory cells (206) of the memory cell matrix; Creating a third part (402c) of the second layout design (400A-400B), wherein the third part (402c) of the second layout design (400A-400B) corresponds to the production of a third memory cell (202[1,3]) of the second group of memory cells (206) of the memory cell matrix; and Creating a fourth part (402d) of the second layout design (400A-400B), wherein the fourth part (402d) of the second layout design (400A-400B) corresponds to the production of a fourth memory cell (202[2,3]) of the second group of memory cells (206) of the memory cell matrix, wherein the first part (402a) of the second layout design (400A-400B) and the third part (402c) of the second layout design (400A-400B) are mirror images of each other with respect to the second direction (Y), and the second part (402b) of the second layout design (400A-400B) and the fourth part (402d) of the second layout design (400A-400B) are mirror images of each other with respect to the second direction (Y). [3] The method of claim 1 or 2, wherein generating the first layout design of the (300A, 300B) first group of memory cells (204) or generating the second layout design (400A-400B) of the second group of memory cells (206) comprises: Creating a group of active area layout structures (312a) corresponding to producing a group of active areas (504a1, 506a1, 508a1) of the memory cell matrix (200A, 200B), wherein each active area layout structure (304a, 306a, 308a) of the group of active area layout structures (312a) is separated from an adjacent layout structure of the group of active area layout structures (312a) in the third direction (S) by a first distance, the group of active area layout structures (312a) extends in the second direction (Y) and is arranged on a first layout level, wherein creating the group of active area layout structures (312a) comprises: Creating a first active area layout structure (304a), Creating a second active area layout structure (304b), Creating a third active area layout structure (304c) between the first active area layout structure (304a) and the second active area layout structure (304b), and Creating a fourth active area layout structure (304d) between the third active area layout structure (304c) and the second active area layout structure (304b), wherein a length of the first active area layout structure (304a) is different from a length of the second active area layout structure (304b); Creating a group of gate layout structures (326a) corresponding to the fabrication of a group of gate structures (520a, 522a, 524a) of the memory cell matrix (200A, 200B), wherein the group of gate layout structures (326a) extends in the third direction (S), overlaps the group of active area layout structures (312a), and is arranged on a second layout level that is different from the first layout level; and Creating a first group of conductive element layout structures (338a) corresponding to the production of a first group of conductive structures (530a, 532a, 534a, 536a) of the memory cell matrix (200A, 200B), wherein the first group of conductive element layout structures (338a) extends in the third direction (S) and over the group of active area layout structures (312a) and / or the group of gate layout structures (326a), wherein each conductive element layout structure (330a, 332a, 334a, 336a) of the first group of conductive element layout structures (338a) is separated from an adjacent layout structure of the first group of conductive element layout structures (338a) in the second direction (Y) and / or the third direction (S) separated and arranged on a third layout level that is different from the first layout level and the second layout level. [4] A method according to any one of the preceding claims, wherein a center of each tile element of the first group of tile elements (602) is offset from a center of an adjacent tile element of the first group of tile elements (602) in the second direction (Y) by a distance D1, separated in the first direction (S) by a distance D2, and separated in the third direction (X) by a distance D3, the relationship between the distances D1, D2 and D3 being defined by the formula (1) D2 = (D1 2 + D3 2 ) 0,5 is expressed. [5] The method according to claim 4, wherein the first direction (S) is rotated from the third direction (X) by an angle α to the second direction (Y), the relationship between the angle α and the distances D2 and D3 being expressed by the formula (2) α = arccos(D3 / D2). [6] A method (900, 1000) for producing a memory cell matrix (200A, 200B) having four memory cells (202[1,2], 202[1,3], 202[2,2], 202[2,3]), wherein the memory cells (202[1,2], 202[1,3], 202[2,2], 202[2,3]) correspond to a memory cell having five transistors (5T), comprising the following steps: Generating (902, 904, 1000), with a processor, a layout design (300A, 300B) for manufacturing each of the memory cells (202[1,2], 202[1,3], 202[2,2], 202[2,3]), the layout design having a corner notch (390a), wherein generating the layout design (300A, 300B) comprises: Creating (1002) a group of active area layout structures (304a, 304b, 304c, 304d) corresponding to the production of a group of active areas of the memory cell matrix (200A, 200B), wherein each active area layout structure of the group of active area layout structures (304a, 304b, 304c, 304d) is separated from an adjacent layout structure of the group of active area layout structures (304a, 304b, 304c, 304d) in a first direction (X) by a first distance, wherein the group of active area layout structures (304a, 304b, 304c, 304d) extends in a second direction (Y) different from the first direction (X) and is arranged on a first layout level, wherein the group of active area layout structures (304a, 304b, 304c, 304d), a first active area layout structure (304a) adjacent to the corner recess (390a) and a first side of the memory cell (202[1,2]),and a second active area layout structure (310a) adjacent to the second side of the memory cell (202[1,2]) opposite the first side of the memory cell (202[1,2]), wherein at least one of the aforementioned layout structures (304a, 304b, 304c, 304d) is stored in a non-transitory machine-readable medium and at least one of the aforementioned generating steps is performed by a hardware processor;, wherein a first of the memory cells (202[1,2]) and a second of the memory cells (202[2,2]) are arranged mirror-symmetrically to one another with respect to the first direction (X), and a third of the memory cells (202[1,3]) and a fourth of the memory cells (202[2,3]) are arranged mirror-symmetrically to one another with respect to the first direction (X), wherein the first and the third memory cells (202[1,2], 202[1,3]) are arranged mirror-symmetrically to one another with respect to the second direction (Y), and the second and the fourth memory cells (202[2,2], 202[2,3]) are arranged mirror-symmetrically to one another with respect to the second direction (Y); and Manufacturing (906) the memory cell matrix (200A, 200B) based on the layout design (300A, 300B). [7] The method of claim 6, further comprising: Creating (1006) a group of gate layout structures (326a, 426a) corresponding to the fabrication of a group of gate structures (527) of the memory cell matrix (200A, 200B), wherein the group of gate layout structures (326a, 426a) extends in the first direction (X), overlaps the group of active area layout structures (312a, 412a) and is arranged on a second layout level that is different from the first layout level; and Creating (1010) a first group of conductive element layout structures (338a, 438a) corresponding to the production of a first group of conductive structures (538) of the memory cell matrix (200A, 200B), wherein the first group of conductive element layout structures (338a, 438a) extends in the first direction (X) and over the group of active area layout structures (312a, 412a) and / or the group of gate layout structures (326a, 426a), wherein each conductive element layout structure of the first group of conductive element layout structures (338a, 438a) is separated from an adjacent layout structure of the first group of conductive element layout structures (338a, 438a) in the first direction (X) and / or the second direction (Y) and is arranged on a third layout level which is different from the first layout level and the second layout level. [8] The method of claim 7, wherein generating the layout design (300A, 300B) of the memory cell matrix (200A, 200B) further comprises: Creating a second group of conductive element layout structures (350, 450) corresponding to producing a second group of conductive structures (552) of the memory cell matrix (200A, 200B), wherein the second group of conductive element layout structures (350, 450) extends in the first direction (X) and overlaps at least the second active area layout structure (310a, 410a) and the second side of the memory cell, wherein each conductive element layout structure of the second group of conductive element layout structures (350, 450) is separated from an adjacent layout structure of the second group of conductive element layout structures (350, 450) in the first direction (X) and / or the second direction (Y) and is arranged on a fourth layout level that is different from the first layout level, the second layout level and the third layout level. [9] The method of claim 7 or 8, wherein generating the layout design (300A, 300B) of the memory cell matrix (200A, 200B) further comprises: Creating a first group of via layout structures (358a) between the first group of conductive element layout structures (338a, 438a) and the group of active area layout structures (312a, 412a), wherein the first group of via layout structures (358a) corresponds to the production of a first group of vias (560a, 562a, 564a, 566a, 568a, 570a), the first group of vias connects the first group of conductive structures (529) to the group of active areas (504), and each via layout structure of the first group of via layout structures (358a) is arranged at the location at which each conductive element layout structure (330a, 332a, 334a, 336a) of the first group of conductive element layout structures (338a, 438a) overlaps each active area layout structure of the group of active area layout structures (312a). [10] The method of claim 9, wherein generating the layout design (300A, 300B) of the memory cell matrix (200A, 200B) further comprises: Creating a second group of via layout structures (358a, 458a) between the first group of conductive element layout structures (338a, 438a) and the group of gate layout structures (326a, 426a), wherein the second group of via layout structures (358a, 458a) corresponds to the production of a second group of vias (572), the second group of vias (572) connects the first group of conductive structures (529) to the group of gate structures (527), and a first via layout structure of the second group of via layout structures (572) is arranged at the location at which a first conductive element layout structure (330a, 332a, 334a, 336a) of the first group of conductive element layout structures (338a) overlaps a first gate layout structure of the group of gate layout structures (326a). [11] Method according to one of claims 6 to 10, wherein the first active area layout structure (304a, 404a) corresponds to a first active area of ​​a first p-transistor, the second active area layout structure corresponds to a second active area of ​​a second p-type transistor connected to the first p-type transistor and a pass-gate transistor connected to the second p-type transistor, wherein the pass-gate transistor, the first p-type transistor, and the second p-type transistor are each part of a memory cell of a five-transistor (5T) synchronous random access memory (SRAM), and a length of the first active area layout structure (304a, 404a) is different from a length of the second active area layout structure (310a, 410a), wherein the first active area layout structure (304a, 404a) extends from one side of the layout structure (456c) to the corner notch of the layout structure and the second active area layout structure (310a, 410a) extends from the side of the layout design to another side of the layout design (300A, 300B). [12] The method of claim 11, wherein generating the layout design (300A, 300B) of the memory cell matrix (200A, 200B) further comprises: Creating a first well layout structure (314) corresponding to the fabrication of a first well (501) of the memory cell matrix (200A, 200B), wherein the first well (501) has a first dopant type and the first well layout structure (314) is arranged on a fourth layout level different from the first layout level, the second layout level and the third layout level, wherein creating the first well layout structure (314) comprises: Creating a first layout structure (314) corresponding to the production of a first part (501a) of the first well (501), wherein the first layout structure (314) extends in the second direction (Y), is adjacent to the first side of the memory cell and the corner recess, and is arranged below the first active area layout structure (304a, 404a), and Creating a second layout structure (354b) corresponding to the formation of a second part (501b) of the first well (501), wherein the second layout structure (354b) extends in the second direction (Y), is adjacent to the second side of the memory cell, and is arranged below the second active area layout structure (310a, 410a); and Creating a second well layout structure (316) corresponding to the fabrication of a second well (501') of the memory cell matrix (200A, 200B), wherein the second well (501') has a second dopant type that is different from the first dopant type, and the second well layout structure (316) is arranged on a fourth layout level, between the first layout structure (314) and the second layout structure (354b), and below a third active area layout structure (306a) of the group of active area layout structures (312a) and a fourth active area layout structure (308a) of the group of active area layout structures (312a). [13] Method according to one of claims 6 to 10, wherein the first active area layout structure (304a, 404a) corresponds to a first active area of ​​a first n-transistor, the second active area layout structure (310a, 410a) corresponds to a second active area of ​​a second n-type transistor connected to the first n-type transistor and a pass-gate transistor connected to the second n-type transistor, wherein the pass-gate transistor, the first n-type transistor, and the second n-type transistor are each part of a memory cell of a synchronous random access memory (SRAM) having five transistors (5T), and a length of the first active area layout structure (304a, 404a) is different from a length of the second active area layout structure (310a, 410a), wherein the first active area layout structure (304a, 404a) extends from one side of the layout design (300A, 300B) to the corner notch (390a, 390b, 390c, 390d) of the layout design (300A, 300B). [14] The method of claim 13, wherein generating the layout design (300A, 300B) of the memory cell matrix (200A, 200B) further comprises: Creating a first well layout structure (314) corresponding to the fabrication of a first well (501) of the memory cell matrix (200A, 200B), wherein the first well (501) has a first dopant type and the first well layout structure (802) is arranged on a fourth layout level different from the first layout level, the second layout level, and the third layout level, wherein creating the first well layout structure (802) comprises: Creating a first layout structure (456a) corresponding to the formation of a first part (501a) of the first well (501), wherein the first layout structure (300A, 300B) extends in the second direction (Y), is adjacent to the first side of the memory cell, and is arranged below the first active area layout structure (304a, 404a), and Creating a second layout structure (354b) corresponding to the formation of a second part (501b) of the first well (501), wherein the second layout structure (354b) extends in the second direction (Y), is adjacent to the second side of the memory cell, and is arranged under a first part (410a1) of the second active area layout structure (310a, 410a); and Creating a second well layout structure (316) corresponding to the fabrication of a second well (502') of the memory cell matrix (200A, 200B), wherein the second well (502') has a second dopant type that is different from the first dopant type, and the second well layout structure (316) is arranged on the fourth layout level, wherein the creation of the second well layout structure (316) comprises: Creating a third layout structure (454a, 454c) corresponding to the production of a first part (502c) of the second well (502'), wherein the third layout structure (454a, 454c) extends in the second direction (Y) and is arranged between the first layout structure (456a) and the second layout structure (454b) and below a third active area layout structure (406a) of the group of active area layout structures (412a) and below a fourth active area layout structure (408a) of the group of active area layout structures (412a), and Creating a fourth layout structure (456d) corresponding to the formation of a second part (502d) of the second well (502'), wherein the fourth layout structure (456d) extends in the second direction (Y), is adjacent to the second side of the memory cell, and is arranged under a second part (410a2) of the second active area layout structure (410a). [15] Memory cell matrix (200A, 200B) with: a first memory cell (202[1,2]) arranged in a first row and a first column in a first direction (X); a first bit line (BL2) extending in a second direction (Y) different from the first direction (X) and connected to the first memory cell (202[1,2]); a second memory cell (202[1,3]) arranged in the first row and a second column in the first direction (X); and a second bit line (BL3) extending in the second direction (Y) and connected to the second memory cell (202[1,3]), a third memory cell (202[2,2]) arranged in a second row and the first column in the first direction (X) and connected to the first bit line (BL2); a fourth memory cell (202[2,3]) arranged in the second row and the second column in the first direction (X) and connected to the second bit line (BL3); wherein the first memory cell (202[1,2]) and the third memory cell (202[2,2]) each correspond to a memory cell with five transistors (5T) and comprise: a first active region adjacent to a first side of the first and third memory cells (202[1,2], 202[2,2]), respectively, and a second active region adjacent to a second side of the first and third memory cells (202[1,2], 202[2,2]), which is opposite to the first side of the first and third memory cells (202[1,2], 202[2,2]), wherein a length of the first active region is less than a length of the second active region, wherein the first and second active regions extend in the second direction (Y), are arranged on a first plane, and are separated from each other in the first direction (X), wherein the second memory cell (202[1,3]) and the fourth memory cell (202[2,3]) each correspond to a memory cell with five transistors (5T), and the second and fourth memory cells (202[1,3], 202[2,3]) have: a first active region adjacent to a first side of the second or fourth memory cell (202[1,3], 202[2,3]), and a second active region adjacent to a second side of the second or fourth memory cell (202[1,3], 202[2,3]), which is opposite to the first side of the second or fourth memory cell (202[1,3], 202[2,3]), wherein a length of the first active region is less than a length of the second active region, wherein the first and second active regions extend in the second direction (Y), are arranged on a first plane, and are separated from each other in the first direction (X), wherein the second side of the first memory cell (202[1,2]) and the second side of the second memory cell (202[1,3]) face each other and the first side of the first memory cell (202[1,2]) and the first side of the second memory cell (202[1,3]) face away from each other, and wherein the second side of the third memory cell (202[2,2]) and the second side of the fourth memory cell (202[2,3]) to each other and the first page of the third memory cell (202[2,2]) and the first side of the fourth memory cell (202[2,3]) point away from each other, wherein the first and second memory cells (202[1,2], 202[1,3]) are arranged mirror-inverted to the third and fourth memory cells (204) with respect to the first direction (X) and are adjacent to them. [16] The memory cell matrix (200A, 200B) of claim 15, further comprising: a group of gates (527) extending in the first direction (X), overlapping the first and second active regions and arranged on a second level different from the first level; and a first group of conductive structures (538) extending in the first direction (X) and over at least the first and second active regions and / or over the group of gates (527), wherein each conductive structure of the first group of conductive structures (538) is separated from an adjacent conductive structure of the first group of conductive structures (538) at least in the first direction (X) and / or the second direction (Y) and is arranged on a third level that is different from the first level and the second level. [17] Memory cell matrix (200A, 200B) according to claim 16, further comprising: a second group of conductive structures (552) extending in the first direction (X) and overlapping at least the second active area and the second side of the first memory cell, wherein each conductive structure of the second group of conductive structures (552) is separated from an adjacent structure of the second group of conductive structures (552) at least in the first direction (X) and / or the second direction (Y) and is arranged on a fourth level that is different from the first level, the second level and the third level; a first group of vias (572) between the first group of conductive structures (538) and the first and second active regions, wherein the first group of vias (572) connects the first group of conductive structures (538) to the first and second active regions, and at least one via of the first group of vias (572) is arranged at the location where at least one conductive structure of the first group of conductive structures (538) overlaps the first and / or second active regions; and a second group of vias (532) between the first group of conductive structures (538) and the group of gates (527), the second group of vias (532) connecting the first group of conductive structures (538) to the group of gates (527), and a first via of the second group of vias (532) being arranged at the location where a first conductive structure of the first group of conductive structures (538) is located above a first gate of the group of gates (527). [18] A memory cell matrix (200A, 200B) according to claim 16 or 17, further comprising: a first well (501) having a first dopant type disposed at least on the first level, the first well (501) comprising: a first part (501a) extending in the second direction (Y) and adjacent to the first side of the first memory cell, wherein the first active region is embedded in the first part (501a) of the first well (501), and a second part (501b) extending in the second direction (Y) and adjacent to the second side of the first memory cell, wherein the second active region is embedded in the second part (501b) of the first well (501); a second well (501') having a second dopant type different from the first dopant type, the second well (501') being arranged between the first part (501a) of the first well (501) and the second part (501b) of the first well (501); a third active region embedded in the second well (501'); and a fourth active region embedded in the second well (501'), wherein the third active region is arranged between the first active region and the fourth active region, and the fourth active region is arranged between the third active region and the second active region. [19] A memory cell matrix (200A, 200B) according to claim 16 or 17, further comprising: a first well (502) having a first dopant type disposed at least on the first level, the first well (502) comprising: a first part (502a) of the first well (502) extending in the second direction (Y) and adjacent to the first side of the first memory cell, wherein the first active region is embedded in the first part (502a) of the first well (502), and a second part (502b) of the first well (502) extending in the second direction (Y) and adjacent to the second side of the first memory cell; a second well (502') having a second dopant type different from the first dopant type, the second well (502') comprising: a first part (502c) of the second trough (502') extending in the second direction (Y) and adjacent to the first part (502a) of the first trough (502), and a second part (502d) of the second well (502') extending in the second direction (Y) and adjacent to the second side of the first memory cell, the second part (502b) of the first well (502) and the first part (502c) of the second well (502'); a third active region embedded in the first part (502c) of the second well (502'); and a fourth active region embedded in the first part (502c) of the second well (502'), wherein the third active region is arranged between the first active region and the fourth active region, and the fourth active region is arranged between the third active region and the second active region, the second active region comprising: a first part of the second active region embedded in the second part (502b) of the first well (502), and a second part of the second active region embedded in the second part (502d) of the second well (502') and aligned with the first part of the second active region in the second direction (Y). [20] The memory cell matrix (200A, 200B) of claim 18 or 19, wherein the first dopant type is an n-dopant and the second dopant type is a p-dopant.

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