BANDPASS FILTER FOR STACKED SENSOR AND METHOD FOR ITS MANUFACTURING

Abstract

Three-dimensional integrated chip, including: a first IC die (102a) with a first image sensor element (104a) configured to generate electrical signals from electromagnetic radiation within a first wavelength range; a second IC die (102b) with a second image sensor element (104b) configured to generate electrical signals from electromagnetic radiation within a second wavelength range that differs from the first wavelength range; a first bandpass filter (106; 106a) arranged between the first IC die (102a) and the second IC die (102b) and configured to reflect electromagnetic radiation within the first wavelength range; and a waveguide (706) arranged over the first IC die (102a), wherein the waveguide (706) has a bottom side facing the first IC die and a top side facing away from the first IC die, the bottom side having a smaller width than the top side.

Description

BACKGROUND

[0001] Integrated circuits (ICs) with image sensors are used in a wide variety of modern electronic devices. In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors have gained widespread use, largely replacing CCD (charge-coupled element) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly preferred due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing costs.

[0002] US 9,184,198 B1 describes a color-sensitive sensor. WO 2018 / 008 062 A1 describes a device for observing fluorescent light. US 8,507,964 B2 describes an image sensor. DE 10 2017 123 338 A1 discloses an integrated chip comprising a light-sensing element. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced as desired for clarity of description. Fig. Figure 1 shows a block diagram of some embodiments of a stacked image sensor device comprising an inter-substrate bandpass filter. Fig. Figure 2 shows a cross-sectional view of some additional embodiments of a stacked image sensor device comprising an inter-substrate bandpass filter. Fig. Figure 3 shows a cross-sectional view of some additional embodiments of a stacked image sensor device comprising an inter-substrate bandpass filter. Fig. Figure 4 shows a cross-sectional view of some embodiments of an in-substrate bandpass filter. Fig. Figure 5 shows a cross-sectional view of some additional embodiments of a stacked image sensor device comprising an inter-substrate bandpass filter. The Fig. Figures 6A - 6D show cross-sectional views of some embodiments of stacked image sensor devices with different inter-substrate bandpass filter configurations. The Fig. Figures 7A - 7C show cross-sectional views of some embodiments of stacked image sensor devices with different sensor configurations, which are incorporated in an inter-substrate bandpass filter. The Fig. Figures 8A and 8B show some additional embodiments of a stacked image sensor device comprising an inter-substrate bandpass filter. Fig. Figure 9 shows a cross-sectional view of some embodiments of an integrated chip structure comprising a stacked image sensor device with an inter-substrate bandpass filter. The Fig. Figures 10-26 show cross-sectional views of some embodiments of a method for forming a stacked image sensor device comprising an inter-substrate bandpass filter. Fig. Figure 27 shows a flowchart of some embodiments of a method for forming a stacked image sensor device comprising an inter-substrate bandpass filter. Fig. Figures 28-35 show cross-sectional views of some additional embodiments of a method for forming a stacked image sensor device comprising an inter-substrate bandpass filter. Fig. Figure 36 shows a flowchart of some additional embodiments of a method for forming a stacked image sensor device comprising an inter-substrate bandpass filter. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may be interpreted accordingly.

[0006] In recent years, three-dimensional integrated chips (3DICs) have found increasingly widespread use in the semiconductor industry. 3DICs are manufactured by stacking multiple integrated chip dies on top of each other. The stacked integrated chip dies are electrically interconnected using substrate vias (TSVs) that extend vertically through the integrated chip die. This vertical interconnection allows the stacked integrated chip dies to behave like a single integrated chip device.

[0007] CMOS (complementary metal-oxide-semiconductor) image sensors can be formed on an image sensor die that can be integrated into 3DICs. Typically, image sensor dies are stacked on integrated chip dies containing logic and / or memory. However, multiple image sensor dies can also be stacked within a single 3DIC, resulting in vertically stacked arrays of image sensor elements. Generally, light supplied to such a stacked image sensor device exhibits a wide range of colors with varying wavelengths. The depth to which light penetrates a semiconductor material depends on the wavelength. Therefore, when image sensor dies are stacked, different wavelengths of the light spectrum can be separated (i.e., filtered) by placing image sensors sensitive to different colors at different heights within the 3DIC.

[0008] The spectral sensitivity of each image sensor element (e.g., a photodiode) spans a range of wavelengths. Therefore, to effectively separate the different wavelengths of light based on penetration depth, the thickness of the image sensor dies is made relatively large. However, as the thickness of the image sensor dies increases, crosstalk between laterally adjacent sensors and vertically adjacent devices (e.g., spectral crosstalk) can also increase. This is because, at large thickness values, light entering a stacked image sensor device at an angle can travel a large lateral distance and thus reach laterally adjacent sensors. Furthermore, while increasing the thickness of the image sensor dies effectively separates the different wavelengths of light, it also increases the sensitivity of the image sensors within the die to broader wavelength ranges of light.The increase in crosstalk degrades the quality of an image captured by an integrated CMOS image sensor (CIS) chip by causing light intended for one pixel to be unintentionally captured by another pixel.

[0009] The present disclosure relates, in some embodiments, to a stacked image sensor device comprising an inter-substrate bandpass filter configured to reduce crosstalk between adjacent image sensor elements. The stacked image sensor device comprises a first substrate with a first image sensor element, which is stacked on a second substrate with a second image sensor element. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first wavelength range. The second image sensor element is configured to generate electrical signals from electromagnetic radiation within a second wavelength range. A bandpass filter is arranged between the first and second substrates.The bandpass filter is configured to transmit electromagnetic radiation within a passband encompassing the second wavelength range, while reflecting electromagnetic radiation encompassing the first wavelength range. Reflecting electromagnetic radiation from the first wavelength range increases the path length of the electromagnetic radiation within the first substrate. Increasing the path length allows for a reduction in the thickness of the first substrate, thereby reducing crosstalk in the stacked image sensor device without compromising electromagnetic absorption.

[0010] Fig. Figure 1 shows a block diagram of some embodiments of a stacked image sensor device 100 comprising an inter-substrate bandpass filter.

[0011] The stacked image sensor device 100 comprises a first IC (integrated chip) die 102a with a first image sensor element 104a, which is stacked on a second IC die 102b with a second image sensor element 104b. The first image sensor element 104a and the second image sensor element 104b are configured to convert electromagnetic radiation 108 (e.g., photons) into electrical signals (i.e., generate electron-hole pairs from the electromagnetic radiation 108). The first image sensor element 104a is configured to generate electrical signals from electromagnetic radiation 108 within a first wavelength range, while the second image sensor element 104b is configured to generate electrical signals from electromagnetic radiation 108 within a second wavelength range that differs from the first range.For example, the first image sensor element 104a can be configured to generate electrical signals from visible light (i.e., electromagnetic radiation with wavelengths in a range between approximately 400 nm and approximately 700 nm), while the second image sensor element 104b can be configured to generate electrical signals from infrared light (i.e., electromagnetic radiation with wavelengths in the range between approximately 700 nm and approximately 1 mm).

[0012] A bandpass filter 106 is arranged between the first IC die 102a and the second IC die 102b. The bandpass filter 106 is configured to transmit electromagnetic radiation 108 within a passband encompassing the second wavelength range, while reflecting electromagnetic radiation 108 outside the passband and including the first wavelength range. For example, the bandpass filter 106 can transmit infrared light (i.e., electromagnetic radiation with wavelengths in a range between approximately 700 nm and approximately 1 mm) while reflecting electromagnetic radiation that is not infrared light (i.e., electromagnetic radiation with wavelengths less than 700 nm and more than 1 mm).

[0013] By reflecting the electromagnetic radiation 108 with wavelengths contained in the first wavelength range, a path of the electromagnetic radiation propagating in the first IC die 102a is lengthened without affecting the path of the electromagnetic radiation outside the first wavelength range. Lengthening the path of the electromagnetic radiation in the first IC die 102a allows the first image sensor element 104a to absorb more radiation, thereby improving the quantum efficiency (QE) of the first image sensor element 104a. Furthermore, lengthening the path of the electromagnetic radiation propagating in the first IC die 102a allows for a reduction in the thickness of the first IC die 102a, thereby reducing crosstalk between adjacent image sensor elements in the first IC die 102a.

[0014] Fig. Figure 2 shows some additional embodiments of a cross-sectional view of a stacked image sensor device 200 comprising an inter-substrate bandpass filter.

[0015] The stacked image sensor device 200 comprises a plurality of stacked IC dies 102a-102d, which in turn comprise a plurality of image sensor elements 104a-104d. The plurality of stacked IC dies 102a-102d are electrically connected via one or more conductive interconnect layers 202 (e.g., metal wires, vias, substrate vias, or the like). The plurality of image sensor elements 104a-104d are configured to generate electrical signals in response to different wavelengths of electromagnetic radiation. In some embodiments, the plurality of stacked IC dies 102a-102d may comprise semiconductor substrates (e.g., silicon substrates, germanium substrates, or the like). In some embodiments, the majority of image sensor elements 104a-104d may comprise photodetectors, photodiodes, charge-coupled devices or the like.

[0016] In some embodiments, the stacked image sensor device 200 comprises a first IC die 102a with a first image sensor element 104a, a second IC die 102b with a second image sensor element 104b, a third IC die 102c with a third image sensor element 104c, and a fourth IC die 102d with a fourth image sensor element 104d. The first image sensor element 104a can be configured to detect blue light (e.g., light with a wavelength between approximately 450 nm and approximately 490 nm). The second image sensor element 104b can be configured to detect green light (e.g., light with a wavelength between approximately 520 nm and approximately 560 nm). The third image sensor element 104c can be configured to detect red light (e.g., light with a wavelength between approximately 635 nm and approximately 700 nm). The fourth image sensor element 104d can be configured to detect infrared light (e.g.Light with a wavelength between approximately 700 nm and approximately 1 mm) is detected.

[0017] The multiple substrates 102a - 102d are separated by a plurality of bandpass filters 106a - 106d. For example, a first bandpass filter 106a is arranged between the first IC die 102a and the second IC die 102b, a second bandpass filter 106b is arranged between the second IC die 102b and the third IC die 102c, a third bandpass filter 106c is arranged between the third IC die 102c and the fourth IC die 102d, and a fourth bandpass filter 106d is arranged below the fourth IC die 102d.

[0018] During operation, incident light 204i strikes a top surface of the first IC die 102a. The incident light 204i comprises electromagnetic radiation spanning the electromagnetic spectrum (e.g., electromagnetic radiation with wavelengths from approximately 1 mm to approximately 10 nm). The incident light 204i interacts with the first image sensor element 104a. The first bandpass filter 106a is configured to receive the incident light 204i and transmit light 206p with a wavelength greater than a first value (e.g., greater than approximately 490 nm) to the second IC die 102b, while reflecting light 206r with a wavelength less than the first value back to the first IC die 102a (where the reflected light 206r can be further absorbed by the first image sensor element 104a). The second bandpass filter 106b is set up to filter out light 208p with a wavelength greater than a second value (e.g.The third bandpass filter 106c is configured to transmit light 210p with a wavelength greater than a third value (e.g., approximately 560 nm) to the third IC die 102c, while reflecting light 210r with a wavelength less than the third value back to the second IC die 102b (where the reflected light 208r can be further absorbed by the second image sensor element 104b). The fourth bandpass filter 106d is configured to transmit light 210p with a wavelength greater than a third value (e.g., approximately 700 nm) to the fourth IC die 102d, while reflecting light 210r with a wavelength less than the third value back to the third IC die 102c (where the reflected light 210r can be further absorbed by the third image sensor element 104c).approximately 600 nm) back to the fourth IC die 102d (where the reflected light 212r can be further absorbed by the fourth image sensor element 104d).

[0019] In some embodiments, the majority of IC dies 102a–102d can comprise semiconductor substrates of varying thicknesses. In some embodiments, the majority of IC dies 102a–102d can comprise semiconductor substrates with a thickness that increases consistently from the first IC die 102a to the fourth IC die 102d. For example, the first IC die 102a can have a first semiconductor substrate with a first thickness t1, the second IC die 102b can have a second semiconductor substrate with a second thickness t2 > t1, the third IC die 102c can have a third semiconductor substrate with a third thickness t3 > t2, and the fourth IC die 102d can have a fourth semiconductor substrate with a fourth thickness t4 > t3.

[0020] By arranging the bandpass filters 106a–106d between the majority of IC dies 102a–102d, the thickness of the semiconductor substrates can be reduced while still effectively separating the light spectrum in the vertical direction. Furthermore, using the bandpass filters 106a–106d to separate the light spectrum in the vertical direction also reduces crosstalk between the image sensor elements 104a–104d. For example, in some embodiments, the first image sensor 104a can be sensitive to blue light, the second image sensor 104b can be sensitive to green light, and the third image sensor 104c can be sensitive to red light. In such embodiments, the second image sensor 104b is not sensitive to blue light if the first substrate 102a is sufficiently thick.However, if the first substrate 102a is sufficiently thick to prevent the second image sensor 104b from being sensitive to blue light, the first image sensor 102a can be sensitive to green and red light. Therefore, it is difficult to improve crosstalk between the first image sensor 104a and / or the second sensor 104b by adjusting the thickness of the first substrate 102a and / or the second substrate 102b. Since the first bandpass filter 106a reflects blue light back to the first image sensor 104a, the path length of the blue light is increased without increasing the path lengths of the green and red light. This means that the second sensor 104b is not sensitive to blue light, even with a thinner first substrate 102a. It also makes the first image sensor 104a insensitive to green and red light, thus reducing crosstalk between both the first image sensor 104a and the second image sensor 104b.

[0021] Fig. Figure 3 shows a cross-sectional view of some additional embodiments of a stacked image sensor device 300 comprising an inter-substrate bandpass filter.

[0022] The stacked image sensor device 300 comprises a first IC die 102a and a second IC die 102b, separated by a bandpass filter 106. The first IC die 102a includes a first image sensor element 104a, and the second IC die 102b includes a second image sensor element 104b. In some embodiments, the first IC die 102a is stacked on the second IC die 102b such that the first image sensor element 104a is located directly above the second image sensor element 104b. In other embodiments (not shown), the first IC die 102a is stacked on the second IC die 102b such that the first image sensor element 104a is laterally offset from the second image sensor element 104b.

[0023] The first IC die 102a comprises a first substrate 302a with a first side 301a and a second side 301c. In some embodiments, the first side 301a can be a front face of the first substrate 302a and the second side 301c can be a back face of the first substrate 302a. In other embodiments, the first side 301a can be a back face and the second side 301c can be a front face. Internal surfaces of the first substrate 302a define one or more trenches extending in the first side 301a of the first substrate 302a on opposite sides of the first image sensor element 104a. The one or more trenches are filled with one or more dielectric layers 304-306 to define deep trench insulation (DTI) structures 308. In various embodiments, the first dielectric layer 304 can comprise a high-k dielectric and the second dielectric layer 306 can comprise an oxide (e.g.silicon dioxide), a nitride (e.g. silicon nitride) or the like.

[0024] The second IC die 102b comprises a second substrate 302b with a first side 303a and a second side 303c. In some embodiments, the first side 303a can be a front face of the second substrate 302b and the second side 303c can be a back face of the second substrate 302b. In other embodiments, the first side 303a can be a back face and the second side 303c can be a front face. Internal surfaces of the second substrate 302b define one or more trenches extending in the second substrate 302b on opposite sides of the second image sensor element 104b. The one or more trenches are filled with the one or more dielectric layers 304-306 to define one or more DTI structures 308 in the second substrate 302b.In some embodiments, the first side 303a of the second substrate 302b can have angled surfaces defining one or more recesses 310, which are arranged to reduce reflection of radiation from the first side 303a of the second substrate 302b. In some embodiments, the angled surfaces defining the one or more recesses 310 can form an angle α1 in a range between approximately 45° and approximately 55° with respect to the second side 303c of the second substrate 302b. In some embodiments, the one or more recesses 310 can be arranged in a periodic structure.

[0025] In some embodiments, reflective elements 316 can be arranged above the DTI structures 308 in the first substrate 302a. The reflective elements 316 are configured to increase the internal reflection of light, thereby reducing the amount of backscattered light emanating from the first substrate 302a. By increasing the internal reflection of light, the first substrate 302a can absorb more radiation, thereby increasing the quantum efficiency of the stacked image sensor device 300. In various embodiments, the reflective elements 316 can comprise a metal such as aluminum (Al), rhodium (Rh), iron (Fe), or the like. In further embodiments, the reflective elements 316 can have air gaps.

[0026] In some embodiments, a color filter 312 can be arranged over the first IC die 102a. In some of these embodiments, the first image sensor element 104a can be sensitive to visible light (e.g., blue light), while the second image sensor element 104b can be sensitive to infrared light. The color filter 312 is configured to transmit certain wavelengths of visible light while blocking other wavelengths. In other embodiments, the color filter 312 can be omitted. A microlens 314 can be arranged over the first IC die 102a. During operation, the microlens 314 is configured to focus incident radiation (e.g., light) onto the first IC die 102a.

[0027] Fig. Figure 4 shows a cross-sectional view of some embodiments of an inter-substrate bandpass filter.

[0028] As shown in cross-sectional view 400, a bandpass filter 106 comprises a multi-film structure with a plurality of stacked layers. The plurality of stacked layers comprise layers of a first material 402 and layers of a second material 404. The layers of the first material 402 and the layers of the second material 404 are stacked in a periodically alternating sequence. For example, the bandpass filter 106 may comprise a layer of the first material 402, a layer above it of the second material 404, a layer above it of the first material 402, and so on. In some embodiments, the bandpass filter 106 may comprise five or more layers of the first material 402 and four or more layers of the second material 404.If the bandpass filter has fewer layers of the first material 402 and the second material 404, the bandpass filter 106 may not be able to filter the incident radiation sufficiently.

[0029] In some embodiments, the layers of the first material 402 have a first refractive index, and the layers of the second material 404 have a second refractive index that differs from the first. In some embodiments, the first refractive index is lower than the second. For example, in some embodiments, the first refractive index may be greater than 3, and the second refractive index may be less than 3. In some additional embodiments, the first refractive index may be in a first range between approximately 3 and approximately 4, while the second refractive index may be in a second range between approximately 1 and approximately 2. In some embodiments, the layers of the first material 402 may comprise silicon, and the layers of the second material 404 may comprise silicon dioxide.

[0030] In some embodiments, the layers of the first material 402 can have a first thickness t1, and the layers of the second material 404 can have a second thickness t2. In some embodiments, the first thickness t1 is less than the second thickness t2. In some embodiments, the first thickness t1 can be in a range between approximately 17 nm and approximately 170 nm. In some embodiments, the second thickness t2 can be in a range between approximately 30 nm and approximately 300 nm.

[0031] Fig. Figure 5 shows a cross-sectional view of some additional embodiments of a stacked image sensor device 500 comprising an inter-substrate bandpass filter.

[0032] The stacked image sensor device 500 comprises a first IC die 102a and a second IC die 102b, separated by a first bandpass filter 106a. A second bandpass filter 106b is separated from the first IC die 102a by the second IC die 102b. The first bandpass filter 106a comprises alternating layers of a first material 402a with a first refractive index and a second material 404a with a second refractive index lower than the first. The second bandpass filter 106b comprises alternating layers of a third material 402b with a third refractive index and a fourth material 404b with a fourth refractive index lower than the third.In some embodiments, the layers of a first material 402a can be made of the same material as the layers of the third material 402b, and the layers of the second material 404a can be made of the same material as the layers of the fourth material 404b. In further embodiments, the layers of a first material 402a can be made of a different material than the layers of the third material 402b, and the layers of the second material 404a can be made of a different material than the layers of the fourth material 404b.

[0033] The first IC die 102a and the second IC die 102b each have several pixel regions 501a–501c, which include a photodiode 510. The first IC die 102a comprises a first substrate 302a and a first dielectric structure 502a arranged on the first substrate 302a. The second IC die 102b comprises a second substrate 302b and a second dielectric structure 502b arranged on the second substrate 302b.

[0034] The first dielectric structure 502a and the second dielectric structure 502b each comprise a plurality of stacked interlayer dielectric (ILD) layers 503 separated by etch stop layers 505. In various embodiments, the plurality of stacked interlayer dielectric (ILD) layers 503 can comprise one or more oxides (e.g., SiO2, SiCO, etc.), a fluorosilicate glass, a phosphate glass (e.g., boron phosphosilicate glass), etc. The plurality of stacked interlayer dielectric (ILD) layers 503 surround a plurality of conductive interconnect layers 506 (e.g., interconnect wires and vias) that are electrically connected to transistor gate structures 504. In some embodiments, the plurality of conductive compound layers 506 may comprise one or more of copper, aluminum, tungsten and carbon nanotubes or the like.

[0035] The majority of transistor gate structures 504 each comprise a gate electrode 504e arranged on a gate dielectric layer 504d. In some embodiments, sidewall spacers 504s are arranged on opposite sides of the gate electrode 504e. In some embodiments, a transistor gate structure 504, corresponding to a transfer transistor, is arranged laterally between a photodiode 510 and a floating diffusion node 512 in the first IC die 102a. In such embodiments, the photodiode 510 can comprise a first region 509 with a first doping type (e.g., n-type doping) and an adjacent second region 511 in the first IC die 102a with a second doping type (e.g., p-type doping) that differs from the first doping type. The transistor gate structure 504 is configured to control the transfer of charge from the photodiode 510 to the floating diffusion node.

[0036] A plurality of shallow trench insulation (STI) structures 508 are also arranged on the front face of the first substrate 302a and the second substrate 302b. The plurality of STI structures 508 comprise one or more dielectrics (e.g., SiO2) arranged in trenches. A plurality of backside deep trench insulation (BDTI) structures 514 are arranged in trenches on the back faces of the first substrate 302a and the second substrate 302b above the plurality of STI structures 508.

[0037] In some embodiments, one or more isolation well regions can be arranged between the STI structures 508 and the BDTI structures 514. The one or more isolation well regions can comprise deep well regions 516 and / or cell well regions 518 with one or more doping types, providing further isolation between the adjacent pixel regions 501a–501c by isolating the transitions. The deep well regions 516 are arranged in the first IC die 102a at a location laterally aligned with the STI structures 508 and / or the BDTI structures 514. The cell well regions 518 are arranged in the first IC die 102a at a location vertically between the deep well regions 516 and the STI structures 508.

[0038] In some embodiments, a dielectric planarization structure 520 can be arranged above the first IC die 102a. The dielectric planarization structure 520 has a substantially planar top surface. In various embodiments, the dielectric planarization structure 520 can comprise one or more stacked dielectrics. In some embodiments, the one or more stacked dielectrics can comprise an oxide (e.g., SiO2), a nitride, a carbide, or the like.

[0039] In some embodiments, a grid structure 522 is arranged over the dielectric planarization structure 520. The grid structure 522 comprises sidewalls that define openings located over the pixel regions 501a-501c. In various embodiments, the grid structure 522 can comprise a metal (e.g., aluminum, cobalt, copper, silver, gold, tungsten, etc.) and / or a dielectric (e.g., SiO2, SiN, etc.). A plurality of color filters 312a-312c are arranged in the openings in the grid structure 522. The plurality of color filters 312a-312c are configured to transmit specific wavelengths of the incident radiation. In some embodiments, the plurality of color filters 312a comprises a first color filter 312a configured to transmit radiation with wavelengths within a first region (e.g.,A second color filter 312b, configured to transmit radiation with wavelengths within a second range (corresponding, for example, to red light), and a third color filter 312c, configured to transmit radiation with wavelengths within a third range (corresponding, for example, to blue light), which differs from the first and second ranges. A plurality of microlenses 314 are arranged over the plurality of color filters 312a–312c. The plurality of microlenses 314 are configured to focus the incident radiation (e.g., light) onto the pixel regions 501a–501c.

[0040] In various embodiments, the disclosed bandpass filter can be arranged in different positions. Fig. Figures 6A-6D show cross-sectional views of stacked integrated chip structures that include bandpass filters at various positions. It can be seen that the stacked integrated chip structures, which are located in the Fig. Figures 6A - 6D are shown, which are non-restrictive embodiments, and which indicate that the disclosed bandpass filters can alternatively be arranged in other positions.

[0041] Fig. Figure 6A shows a cross-sectional view of some additional embodiments of a stacked image sensor device 600 comprising an inter-substrate bandpass filter.

[0042] The stacked image sensor device 600 comprises a first IC die 102a and a second IC die 102b. A first dielectric structure 502a is arranged along a front face of the first IC die 102a. The first dielectric structure 502a surrounds transistor gate structures 504, which are arranged along the front face of the first IC die 102a. A second dielectric structure 502b is also arranged along a front face of the second IC die 102b. The second dielectric structure 502b surrounds transistor gate structures 504, which are arranged along the front face of the second IC die 102b.

[0043] A bandpass filter 106 is arranged between the first dielectric structure 502a and the second IC die 102b. The bandpass filter 106 has a first side that contacts the first dielectric structure 502a (e.g., a passivation layer arranged along a top surface of the first dielectric structure 502a). The bandpass filter 106 has a second side that contacts the second IC die 102b. In some embodiments, the bandpass filter 106 is arranged entirely below the first dielectric structure 502a.

[0044] Fig. Figure 6B shows a cross-sectional view of some additional embodiments of a stacked image sensor device 602 comprising an inter-substrate bandpass filter.

[0045] The stacked image sensor device 602 comprises a bandpass filter 106 embedded in the first dielectric structure 502a, such that the bandpass filter 106 is located between side walls of the first dielectric structure 502a. In some embodiments, the bandpass filter 106 can have a height that is substantially equal to the height of the first dielectric structure 502a. In other embodiments, the bandpass filter 106 can have a height that is less than the height of the first dielectric structure 502a.

[0046] Fig. Figure 6C shows a cross-sectional view of some additional embodiments of a stacked image sensor device 604 comprising an inter-substrate bandpass filter.

[0047] The stacked image sensor device 604 comprises a waveguide 606 embedded within the first dielectric structure 502a between side walls of the first dielectric structure 502a. In some embodiments, the waveguide 606 may have a height that is essentially equal to the height of the first dielectric structure 502a. The waveguide 606 comprises a dielectric material with a different (e.g., a lower) refractive index than the materials of the first dielectric structure 502a in order to guide electromagnetic radiation within the waveguide 606 by means of internal reflection.

[0048] A bandpass filter 106 is arranged between the second IC die 102b and the first dielectric structure 502a and the waveguide 606. The bandpass filter 106 has a first side that contacts the first dielectric structure 502a (e.g., a passivation layer arranged along a top surface of the first dielectric structure 502a) and the waveguide 606. The bandpass filter 106 has a second side that contacts the second IC die 102b.

[0049] Fig. Figure 6D shows a cross-sectional view of some additional embodiments of a stacked image sensor device 608 comprising an inter-substrate bandpass filter.

[0050] The stacked image sensor device 608 comprises a bandpass filter 106 embedded in the first dielectric structure 502a between side walls of the first dielectric structure 502a. The bandpass filter 106 comprises a plurality of nested material layers 402 and 404. The plurality of nested material layers 402 and 404 contact vertically and laterally adjacent material layers on opposite sides. In some embodiments, the plurality of nested material layers 402 and 404 can have a greater thickness along horizontal surfaces than along vertical surfaces (e.g., side walls).

[0051] In various embodiments, the disclosed bandpass filter can be arranged between different combinations of a front-illuminated (FSI) image sensor die and a back-illuminated (BSI) image sensor die. Fig. Figures 7A-7C show cross-sectional views of stacked integrated chip structures comprising various types of image sensor dies. It can be seen that the stacked integrated chip structures used in the Fig. Figures 7A - 7C are shown, but are not restrictive embodiments.

[0052] Fig. Figure 7A shows some embodiments of a stacked image sensor device 700 comprising an inter-substrate bandpass filter arranged between BSI image sensor dies.

[0053] The stacked image sensor device 700 comprises a first IC die 102a stacked on top of a second IC die 102b. The first IC die 102a has a front and a back surface configured to receive incident radiation. A plurality of transistor gate structures 504 are arranged along the front surface. The second IC die 102b also has a front and a back surface configured to receive incident radiation. A plurality of transistor gate structures 504 are arranged along the front surface. A bandpass filter 106 is positioned between the front surface of the first IC die 102a and the back surface of the second IC die 102b.

[0054] Fig. Figure 7B shows some embodiments of a stacked image sensor device 702 comprising an intermediate substrate bandpass filter arranged between an FSI image sensor die and a BSI image sensor die.

[0055] The stacked image sensor device 702 comprises a first IC die 102a stacked on top of a second IC die 102b. The first IC die 102a has a front face configured to receive incident radiation and a back face. A plurality of transistor gate structures 504 are arranged along the front face. The second IC die 102b has a front face and a back face configured to receive incident radiation. A plurality of transistor gate structures 504 are arranged along the front face. The bandpass filter 106 is located between the back face of the first IC die 102a and the back face of the second IC die 102b.

[0056] In some embodiments, an upper dielectric layer 704 is arranged above the first IC die 102a, and a waveguide 706 is embedded in the upper dielectric layer 704. The waveguide 706 comprises a dielectric with a different refractive index (e.g., a lower refractive index) than the materials of the upper dielectric layer 704. The waveguide 706 has a lower surface facing the first IC die 102a and an upper surface facing away from the first IC die 102a. The lower surface has a smaller width than the upper surface.

[0057] Fig. Figure 7C shows some embodiments of a stacked image sensor device 710 comprising an inter-substrate bandpass filter arranged between FSI image sensor dies.

[0058] The stacked image sensor device 710 comprises a first IC die 102a stacked on top of a second IC die 102b. The first IC die 102a has a front face configured to receive incident radiation and a back face. A plurality of transistor gate structures 504 are arranged along the front face. The second IC die 102b also has a front face configured to receive incident radiation and a back face. A plurality of transistor gate structures 504 are arranged along the front face. A bandpass filter 106 is positioned between the back face of the first IC die 102a and the front face of the second IC die 102b.

[0059] The Fig. Figures 8A and 8B show some additional embodiments of a stacked image sensor device comprising an inter-substrate bandpass filter.

[0060] Fig. 8A shows a top view of 800 pixels of a 501 pixel area. Fig. Figure 8B shows a cross-sectional view 812 along the cross-sectional line AA' of Fig. 8A. As shown in the cross-sectional view 812, the stacked image sensor device comprises a first IC die 102a stacked on a second IC die 102b. A first gate structure 802 and a second gate structure 804 are arranged on the first IC die 102a. The first gate structure 802 belongs to a transfer transistor located between a photodiode 510 and a floating diffusion node 512. The second gate structure 804 belongs to a reset transistor located between the floating diffusion node 512 and a source / drain region 810.

[0061] As shown in the top view 800, an STI structure 508 extends as a continuous structure around a pixel area 501. The pixel area 501 comprises the first gate structure 802, the second gate structure 804, a source follower transistor 806, and a row selector transistor 808. The first gate structure 802 is arranged between a photodiode 510 and a floating diffusion node 512. The first gate structure 802 is configured to transfer charge accumulated in the photodiode 510 to the floating diffusion node 512. The second gate structure 804 is configured to clear the charge stored at the floating diffusion node 512. The floating diffusion node 512 controls the source follower transistor 806, which selectively couples a current source (not shown) to the row selector transistor 808. The row selector transistor 808 selectively couples the source follower transistor 806.The source follower transistor 806 is configured to read and amplify charge stored in the floating diffusion node 512 non-destructively, and the row selector transistor 808 is configured to select the pixel area 501 for reading.

[0062] A bandpass filter 106 is arranged across the photodiode 510. In some embodiments, the bandpass filter 106 is located outside the first gate structure 802, the second gate structure 804, a source follower transistor 806, and a row selector transistor 808. In other embodiments (not shown), the bandpass filter can cover the entirety of the pixel area 501.

[0063] Fig. Figure 9 shows a cross-sectional view of some embodiments of an integrated chip structure 900 comprising a stacked image sensor device with an inter-substrate bandpass filter.

[0064] The integrated chip structure 900 comprises a first IC die 102a, a second IC die 102b stacked on top of the first IC die 102a, and a third IC die 102c stacked on top of the second IC die 102b. The first IC die 102a comprises a first substrate 302a and a first dielectric structure 502a. A first array of image sensor elements 908a is arranged in a sensing area 904 within the first substrate 302a. The first array of image sensor elements 908a includes a first image sensor element 104a. A passivation layer 910 is arranged along a rear side of the first substrate 302a. An array of microlenses 312 is arranged above the passivation layer 910. A bond area 906 surrounds the detection area 904 laterally and includes bond pads 912, which are designed for electrically connecting the integrated chip structure 900 to external devices.In some embodiments, the bond pads 912 are arranged in a recess 902 in the first substrate 302a. In such embodiments, the recess 902 may be defined by side walls of the first substrate 302a and a lower dielectric layer 914. A dielectric lining 916 and a dielectric filling 918 may fill the recess 902. A conductive layer 920 extends from the bond pad 912 to beyond the first IC die 102a.

[0065] The second IC die 102b comprises a second substrate 302b and a second dielectric structure 502b. A second array of image sensor elements 908b is arranged in the second substrate 302b in the sensing area 904. The second array of image sensor elements 908b includes a second image sensor element 104b. The second image sensor element 104b is configured to detect electromagnetic radiation at different wavelengths than the first image sensor element 104a.

[0066] The third IC die 102c comprises a plurality of transistor devices 922. In some embodiments, the transistor devices 922 are configured to process signals received from the first array of image sensor elements 908a and / or the second array of image sensor elements 908b. In some embodiments, the interconnect layers in the first dielectric structure 502a are connected to interconnect layers in the second dielectric structure 502b by substrate vias (TSVs) 924. In some embodiments, the TSVs 924 may extend through the bandpass filter 106. In further embodiments (not shown), the TSVs 924 may have outermost sidewalls separated from the outermost sidewalls of the bandpass filter 106 by one or more non-zero distances.

[0067] The Fig. Figures 10-26 show cross-sectional views 1000-2600 of some embodiments for forming a stacked image sensor device that includes an inter-substrate bandpass filter. Although the Fig. Sectional views 10-26 shown in Figures 10-26 describe a method for forming a stacked image sensor device comprising an inter-substrate bandpass filter; it is understood that the cross-sectional views shown in the Fig. The structures shown in 10-26 are not limited to the training procedure, but can stand alone separately from the procedure.

[0068] As shown in the cross-sectional view 1000 of Fig. As shown in Figure 10, a first etching process is carried out on a front face 1002f of a first substrate 1002 according to a first masking layer 1004. The first substrate 1002 can consist of any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.) as well as any other type of semiconductor and / or epitaxial layers associated with it. The first etching process is carried out by exposing unmasked areas of the first substrate 1002 to one or more etchants 1006, which remove portions of the first substrate 1002 in the unmasked areas to define trenches 1008 in the first substrate 1002.

[0069] As shown in the cross-sectional view 1100 of Fig. As shown in Figure 11, one or more dielectric layers 304-306 are formed in the trenches 1008. Subsequently, a planarization process is carried out to define deep trench insulation (DTI) structures 308 in the front face 1002f of the first substrate 1002. The one or more dielectric layers 304-306 may comprise a first dielectric layer 304 and layers of a second dielectric layer 306. In some embodiments, the first dielectric layer 304 may comprise a high-k dielectric layer comprising hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), or the like. In some embodiments, the second dielectric layer 306 may comprise an oxide (e.g. silicon oxide), TEOS or the like.In some embodiments, the first dielectric layer 304 and the second dielectric layer 306 can be deposited by a physical vapor deposition technique (e.g. PVD, CVD, PE-CVD, ALD or the like).

[0070] As shown in the cross-sectional view 1200 of Fig. As shown in Figure 12, a first image sensor element 104a is formed in the pixel regions 501a–501b of the first substrate 1002. The first image sensor element 104a is configured to generate electrical signals in response to electromagnetic radiation with wavelengths within a first region. In some embodiments, the first image sensor element 104a may comprise a photodiode formed by implanting one or more dopants into the front face 1002f of the first substrate 1002. For example, the first image sensor element 104a may be formed by performing a first implantation process (e.g., according to a masking layer) to form a first region with a first doping type (e.g., the n-type) and subsequently performing a second implantation process to form a second region adjacent to the first region with a second doping type (e.g.,the p-type), which differs from the first doping type.

[0071] One or more transistor gate structures 504 are formed along the front face 1002f of the first substrate 1002 in the pixel regions 501a–501b. In various embodiments, the one or more transistor gate structures 504 can comprise a transfer transistor, a source follower transistor, a line selector transistor, and / or a reset transistor. In some embodiments, the one or more transistor gate structures 504 can be formed by depositing a gate dielectric film and a gate electrode film on the front face 1002f of the first substrate 1002. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric layer 504d and a gate electrode 504e. Sidewall spacers 504s can be formed on the outer sidewalls of the gate electrode 504e.In some embodiments, the side wall spacers 504s can be formed by depositing a spacer layer (e.g., a nitride, an oxide, etc.) on the front face 1002f of the first substrate 1002 and selectively etching the spacer layer to form the side wall spacers 504s.

[0072] As shown in the cross-sectional view 1300 of Fig. As shown in Figure 13, a plurality of conductive interconnect layers 506 are formed in a first dielectric structure 502a, which is formed along the front face 1002f of the first substrate 1002. The first dielectric structure 502a comprises a plurality of stacked interlayer dielectric (ILD) layers, while the plurality of conductive interconnect layers 506 comprise alternating layers of conductive wires and vias. In some embodiments, one or more of the plurality of conductive interconnect layers 506 can be formed using a Damascene process (e.g., a single-Damascene process or a dual-Damascene process).The Damascene process is carried out by forming an ILD layer over the first substrate 1002, etching the ILD layer to form a through-hole and / or a metal trench, and filling the through-hole and / or metal trench with a conductive material. In some embodiments, the ILD layer can be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.), and the conductive material can be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the majority of the conductive compound layers 506 can comprise tungsten, copper, aluminum, or the like.

[0073] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14, a second etching process is performed on the first dielectric structure 502a. The second etching process defines waveguide openings 1402 that extend through the first dielectric structure 502a. In some embodiments, the waveguide openings 1402 are located directly above the first image sensor element 104a. In some embodiments, the first dielectric structure 502a is selectively etched according to a second masking layer (not shown).

[0074] As shown in the cross-sectional view 1500 of Fig. As shown in Figure 15, waveguides 706 are formed in the waveguide openings 1402. In some embodiments, the waveguides 706 can be formed by filling the waveguide openings 1402 with a waveguide dielectric and subsequently performing a planarization process to remove the waveguide dielectric above the first dielectric structure 502a. In some embodiments, the waveguide dielectric can comprise an oxide, a nitride, or the like.

[0075] As shown in the cross-sectional view 1600 of Fig. As shown in Figure 16, the first substrate 1002 is thinned to form a first substrate 302a. Thinning the first substrate 1002 allows radiation to reach the first image sensor element 104a in the first substrate 302a more easily. In various embodiments, the first substrate 1002 can be thinned by etching and / or mechanically grinding a back surface 1002b of the first substrate 1002 up to line 1602.

[0076] As shown in the cross-sectional view 1700 of Fig. As shown in Figure 17, a rear side 1702b of a second substrate 1702 is bonded to a support substrate 1704. The second substrate 1702 can consist of any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.) and any other type of semiconductor and / or epitaxial layers bonded to it. In some embodiments, the support substrate 1704 can comprise a silicon substrate. In some embodiments, the second substrate 1702 can be thinned after bonding to form a second substrate 302b. Thinning the second substrate 1702 allows radiation to more easily reach the image sensor elements subsequently formed in the second substrate 302b. In various embodiments, the second substrate 1702 can be thinned by etching and / or mechanically grinding a front side 1702f of the second substrate 1702.

[0077] As shown in the cross-sectional view 1800 of Fig. As shown in Figure 18, a second image sensor element 104b is formed in the pixel regions 501a-501b of the second substrate 302b. In some embodiments, the second image sensor element 104b can comprise a photodiode formed by implanting one or more dopant species into a front face 303f of the second substrate 302b. For example, the photodiode can be formed by performing a first implantation process (e.g., according to a masking layer) to form a first region with a first doping type (e.g., the n-type) and subsequently performing a second implantation process to form a second region adjacent to the first region and having a second doping type (e.g., the p-type) that differs from the first doping type.In some embodiments, a floating diffusion node (not shown) can also be formed using the first and / or the second implantation process.

[0078] One or more transistor gate structures 504 are formed along the front face 303f of the second substrate 302b in the pixel regions 501a–501b. In various embodiments, the one or more transistor gate structures 504 can comprise a transfer transistor, a source follower transistor, a line selector transistor, and / or a reset transistor. In some embodiments, the one or more transistor gate structures 504 can be formed by depositing a gate dielectric film and a gate electrode film on the front face 303f of the second substrate 302b. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric layer 504d and a gate electrode 504e. Sidewall spacers 504s can be formed on the outer sidewalls of the gate electrode 504e.In some embodiments, the side wall spacers 504s can be formed by depositing a spacer layer (e.g., a nitride, an oxide, etc.) on the front face 303f of the second substrate 302b and selectively etching the spacer layer to form the side wall spacers 504s.

[0079] In some embodiments, one or more shallow trench isolation (STI) structures 507 can be formed in the front face 303f of the second substrate 302b on opposite sides of the pixel areas 501a–501b. The STI structures 508 can be formed by selectively etching the front face 303f of the second substrate 302b to form shallow trenches and subsequently forming one or more dielectrics in the shallow trenches. In some embodiments, the STI structures 508 can be formed prior to the formation of the one or more transistor gate structures 504 and / or the second image sensor element 104b.

[0080] As shown in the cross-sectional view from 1900 Fig. As shown in Figure 19, a plurality of conductive interconnect layers 506 are formed in a second dielectric structure 502b, which is formed along the front face 303f of the second substrate 302b. The second dielectric structure 502b comprises a plurality of stacked ILD layers, while the plurality of conductive interconnect layers 506 comprise alternating layers of conductive wires and vias. In some embodiments, one or more of the plurality of conductive interconnect layers 506 can be formed using a Damascene process (e.g., a single-Damascene process or a dual-Damascene process).

[0081] As shown in the cross-sectional view 2000 from Fig. As shown in Figure 20, a structured masking layer 2002 is formed along a back side 303b of the second substrate 302b. The structured masking layer 2002 includes sidewalls that define openings 2004. In some embodiments, the structured masking layer 2002 can be formed by depositing a layer of photosensitive material (e.g., a positive or negative resist) along the back side 303b of the second substrate 302b. The layer of photosensitive material is selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation modifies the solubility of exposed areas in the photosensitive material to define soluble regions. The photosensitive material is then developed to define the openings 2004 by removing the soluble regions.

[0082] As shown in the cross-sectional view 2100 of Fig. As shown in Figure 21, a third etching process is carried out on the back side 303b of the second substrate 302b according to the structured masking layer (2002 by Fig. 20). The third etching process is carried out by exposing the back side 303b of the second substrate 302b to one or more etchants, with the structured masking layer 2002 in place. The one or more etchants remove portions of the second substrate 302b to define a plurality of depressions 310 arranged between a plurality of protrusions extending outward from the second substrate 302b. In some embodiments, the third etching process may comprise a dry etching process. For example, the third etching process may comprise a coupled plasma etching process, such as an inductively coupled plasma etching (ICP) process or a capacitively coupled plasma etching (CCP) process. In other embodiments, the third etching process may comprise a wet etching process.

[0083] As shown in the cross-sectional view 2200 of Fig. As shown in Figure 22, a fourth etching process is carried out on the back side 303b of the second substrate 302b according to a structured masking layer 2202. The fourth etching process is carried out by exposing unmasked areas of the second substrate 302b to one or more etchants that remove portions of the second substrate 302b in the unmasked areas to define trenches 2204 in the second substrate 302b. In some embodiments, the trenches 2204 include tapered sidewalls, causing the width of the trenches 2204 to decrease with increasing distance from the back side 303b of the second substrate 302b.

[0084] As shown in the cross-sectional view 2300 of Fig. As shown in Figure 23, one or more dielectric layers 304-306 are formed in the trenches 2204. Subsequently, a planarization process is carried out to define backside deep trench insulation (BDTI) structures 514. The one or more dielectrics may comprise a first dielectric layer 304 and a second dielectric layer 306. In some embodiments, the first dielectric layer 304 may comprise a high-k dielectric layer, including hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), etc. In some embodiments, the first dielectric layer 304 can be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the second dielectric layer 306 can comprise an oxide (e.g., silicon oxide), TEOS, etc.

[0085] As shown in the cross-sectional view 2400 of Fig. As shown in Figure 24A, a bandpass filter 106 is formed over the second dielectric layer 306. The bandpass filter 106 is formed by depositing a plurality of material layers 402 and 404 over the second dielectric layer 306. The plurality of material layers 402 and 404 comprise alternating layers of a first material 402 and a second material 404. In some embodiments, the layers of the first material 402 can have a first refractive index, and the layers of the second material 404 can have a second refractive index that differs from the first. In some embodiments, the layers of the first material 402 can comprise silicon, and the layers of the second material 404 can comprise silicon oxide.

[0086] In some alternative embodiments, the bandpass filter 106 can be configured as in Fig. 24B is shown. As in the cross-sectional view 2402 of Fig. As shown in Figure 24B, the second dielectric structure 502b is selectively etched to form bandpass recesses 2404 defined by sidewalls of the second dielectric structure 502b. As shown in the cross-sectional view 2406 of Fig. As shown in Figure 24B, the bandpass filter 106 can be formed in the bandpass recesses 2404.

[0087] As shown in the cross-sectional view 2500 of Fig. As shown in Figure 25, the bandpass filter 106 is bonded to the first substrate 302a of the first IC die 102a. In some embodiments, the bandpass filter 106 can be bonded to the first substrate 302a by means of a melt bonding process. In some such embodiments (not shown), an additional dielectric layer can be formed along a back side of the first substrate 302a prior to the melt bonding process.

[0088] As shown in the cross-sectional view 2600 of Fig. As shown in Figure 26, a color filter 312 is formed over the first IC die 102a, and subsequently a microlens 314 is formed over the color filter. The color filter layer is formed from a material that allows the transmission of radiation (e.g., light) with a specific wavelength range, while blocking light of wavelengths outside that range. In some embodiments, the microlens 314 can be formed by depositing a microlens material over the color filter 312 (e.g., by a spin coating process or a deposition process). A microlens template (not shown) with a curved top surface is structured over the microlens material. In some embodiments, the microlens template can comprise a photoresist material that is exposed using a distributed dose of light (e.g.,In a negative resist, more light is exposed at the base of the curvature and less light is exposed at the top of the curvature. The resist is developed and baked to form a rounded shape. The microlens 314 can then be formed by selectively etching the microlens material according to the microlens template.

[0089] Fig. Figure 27 shows a flowchart of some embodiments of a method 2700 for forming a stacked image sensor device comprising an inter-substrate bandpass filter.

[0090] While the disclosed methods (e.g., methods 2700 and 3600) are shown and described below as a sequence of operations or events, it is understood that the sequence of such operations or events shown is not to be interpreted in a restrictive sense. For example, some operations may occur in a different order and / or simultaneously with other operations or events than those shown and / or described here. Additionally, not all of the operations shown need be required to implement one or more aspects or embodiments of the present description. Furthermore, one or more of the operations shown here may be performed in one or more separate steps and / or phases.

[0091] In 2702, a first image sensor element is formed in a first IC die. In some embodiments, the first image sensor element can be formed according to procedures 2704 - 2714.

[0092] In 2704, isolation structures are formed along one front face of a first substrate. Fig. Figures 10-11 show cross-sectional views 1000-1100 of some embodiments belonging to process 2704.

[0093] At 2706, a first image sensor element is formed in the first substrate. Fig. Figure 12 shows a cross-sectional view 1200 of some embodiments belonging to process 2706.

[0094] In the 2708, transistor gate structures are formed along the front side of the first substrate. Fig. Figure 12 shows a cross-sectional view 1200 of some embodiments belonging to process 2708.

[0095] In 2710, a plurality of interconnect layers are formed in a first dielectric structure along the front face of the first substrate. Fig. Figure 13 shows a cross-sectional view 1300 of some embodiments belonging to process 2710.

[0096] In 2712, a waveguide structure is formed in the first dielectric structure. Fig. Figures 14-15 show cross-sectional views 1400-1500 of some embodiments belonging to process 2712.

[0097] At 2714, the thickness of the first substrate is reduced. Fig. Figure 16 shows a cross-sectional view 1600 of some embodiments belonging to process 2714.

[0098] In 2716, a second image sensor element is formed in a second IC die. In some embodiments, the second image sensor element can be formed according to procedures 2718–2728.

[0099] At 2718, the thickness of a second substrate is reduced. Fig. Figure 17 shows a cross-sectional view 1700 of some embodiments belonging to process 2718.

[0100] At 2720, a second image sensor element is formed in the second substrate. Fig. Figure 18 shows a cross-sectional view 1800 of some embodiments belonging to process 2720.

[0101] In the 2722, transistor gate structures are formed along the front side of the second substrate. Fig. Figure 18 shows a cross-sectional view 1800 of some embodiments belonging to process 2722.

[0102] In 2724, a plurality of interconnect layers are formed in a second dielectric structure along the front face of the second substrate. Fig. Figure 19 shows a cross-sectional view 1900 of some embodiments belonging to process 2724.

[0103] In step 2726, the reverse side of the second substrate is selectively etched to define one or more depressions. Fig. Figures 20-21 show cross-sectional views 2000-2100 of some embodiments belonging to process 2726.

[0104] At 2728, isolation structures are formed along the back side of the second substrate. Fig. Figures 22-23 show cross-sectional views 2200-2300 of some embodiments belonging to process 2728.

[0105] At 2730, a bandpass filter is formed on the back side of the second substrate. Fig. Figures 24A - 24B show cross-sectional views 2400 and 2402 of some embodiments belonging to process 2730.

[0106] At 2732, the bandpass filter is bonded to the first substrate of the first IC die. Fig. Figure 25 shows a cross-sectional view 2500 of some embodiments belonging to process 2732.

[0107] At 2734, a color filter is formed over the first IC die. Fig. Figure 26 shows a cross-sectional view 2600 of some embodiments belonging to process 2734.

[0108] At 2736, a microlens is formed above the color filter. Fig. Figure 26 shows a cross-sectional view 2600 of some embodiments belonging to process 2736.

[0109] The Fig. Figures 28-35 show cross-sectional views 2800-3500 of some additional embodiments for forming a stacked image sensor device that includes an inter-substrate bandpass filter. Although the Fig. Sectional views 28-35 shown in Figures 2800-3500 describe a method for forming a stacked image sensor device comprising an inter-substrate bandpass filter; it is understood that the cross-sectional views shown in the Fig. The structures shown in 28-35 are not limited to the training procedure, but can stand separately from the procedure.

[0110] As shown in the cross-sectional view 2800 of Fig. As shown in Figure 28, a first image sensor element 104a is formed in pixel regions 501a–501b of a first substrate 2802. The first image sensor element 104a is configured to generate electrical signals in response to electromagnetic radiation with wavelengths within a first region. In some embodiments, the first image sensor element 104a may comprise a photodiode formed by implanting one or more dopant species into a front face 2802f of the first substrate 2802.

[0111] One or more transistor gate structures 504 are formed along the front face 2802f of the first substrate 2802 in the pixel regions 501a–501b. In various embodiments, the one or more transistor gate structures 504 can comprise a transfer transistor, a source follower transistor, a row selector transistor, and / or a reset transistor. In some embodiments, one or more shallow trench insulation (STI) structures 508 can be formed in the front face 2802f of the first substrate 2802 on opposite sides of the pixel regions 501a–501b.

[0112] As shown in the cross-sectional view 2900 of Fig. As shown in Figure 29, a plurality of conductive interconnect layers 506 are formed in a first dielectric structure 502a, which is formed along the front face 2802f of the first substrate 2802. The first dielectric structure 502a comprises a plurality of stacked interlayer dielectric (ILD) layers, while the plurality of conductive interconnect layers 506 comprise alternating layers of conductive wires and vias. In some embodiments, one or more of the plurality of conductive interconnect layers 506 can be formed using a Damascene process (e.g., a single-Damascene process or a dual-Damascene process).

[0113] As shown in the cross-sectional view 3000 of Fig. As shown in Figure 30A, a bandpass filter 106 is formed over the first dielectric structure 502a. The bandpass filter 106 is formed by depositing a plurality of material layers 402 and 404 over the first dielectric structure 502a. The plurality of material layers 402 and 404 comprise alternating layers of a first material 402 and a second material 404. In some embodiments, the layers of the first material 402 can have a first refractive index, and the layers of the second material 404 can have a second refractive index that differs from the first refractive index.

[0114] In some alternative embodiments, the bandpass filter 106 can be configured as in Fig. 30B is shown. As in the cross-sectional view 3002 of Fig. As shown in Figure 30B, the first dielectric structure 502a is selectively etched to form bandpass recesses 3004 defined by sidewalls of the first dielectric structure 502a. As shown in the cross-sectional view 3006 of Fig. As shown in Figure 30B, the bandpass filter 106 can be formed in the bandpass recesses 3004.

[0115] As shown in the cross-sectional view 3100 of Fig. As shown in Figure 31, the bandpass filter 106 is bonded to a second IC die 102b. In some embodiments, the second IC die 102b can be configured as shown in cross-sectional views 1700–2300 of Figure 31. Fig. Figures 17-23 are shown. In some embodiments, the bandpass filter 106 can be bonded to the second IC die 102b by means of a melt bonding process.

[0116] As shown in the cross-sectional view 3200 of Fig. As shown in Figure 32, the first substrate 2802 is thinned to form a first substrate 302a. Thinning the first substrate 2802 allows radiation to more easily reach the first image sensor element 104a in the first substrate 302a. In various embodiments, the first substrate 2802 can be thinned by etching and / or mechanically grinding a back surface 2802b of the first substrate 2802 up to line 3202.

[0117] As shown in the cross-sectional view 3300 of Fig. Figure 33 shows that an etching process is carried out on the back side 301b of the first substrate 302a according to a second structured masking layer 3302. The etching process is carried out by exposing unmasked areas of the first substrate 302a to one or more etchants that remove portions of the first substrate 302a in the unmasked areas to define trenches 3304 in the first substrate 302a. In some embodiments, the trenches 3304 include tapered sidewalls, causing the width of the trenches 3304 to decrease with increasing distance from the back side 301b of the first substrate 302a.

[0118] As shown in the cross-sectional view 3400 of Fig. As shown in Figure 34, one or more dielectric layers 304-306 are formed in the trenches 3304. Subsequently, a planarization process is carried out to define backside deep trench insulation structures 514. The one or more dielectrics can comprise a first dielectric layer 304 and a second dielectric layer 306. In some embodiments, the first dielectric layer 304 can comprise a high-k dielectric layer. In some embodiments, the second dielectric layer 306 can comprise an oxide (e.g., silicon oxide), TEOS, etc.

[0119] As shown in the cross-sectional view 3500 of Fig. As shown in Figure 35, a color filter 312 is formed over the first IC die 102a and subsequently a microlens 314 is formed over the color filter.

[0120] Fig. Figure 36 shows a flowchart of some embodiments of a method 3600 for forming a stacked image sensor device comprising an inter-substrate bandpass filter.

[0121] In 3602, a first image sensor element is formed in a first IC die. In some embodiments, the first image sensor element can be formed according to procedures 3604 - 3608.

[0122] At 3604, a first image sensor element is formed in the first substrate. Fig. Figure 28 shows cross-sectional views 2800 of some embodiments belonging to process 3604.

[0123] In 3606, transistor gate structures are formed along the front side of the first substrate. Fig. Figure 28 shows a cross-sectional view 2800 of some embodiments belonging to process 3606.

[0124] In 3608, a plurality of interconnect layers are formed in a first dielectric structure along the front face of the first substrate. Fig. Figure 29 shows a cross-sectional view 2900 of some embodiments belonging to process 3608.

[0125] In 3610, a second image sensor element is formed in a second IC die. In some embodiments, the second image sensor element can be formed according to processes 3612 - 3622.

[0126] At 3612, the thickness of the second substrate is reduced. Fig. Figure 17 shows a cross-sectional view 1700 of some embodiments belonging to process 3612.

[0127] At 3614, a second image sensor element is formed in the second substrate. Fig. Figure 18 shows cross-sectional views 1800 of some embodiments belonging to process 3614.

[0128] In 3616, transistor gate structures are formed along the front side of the second substrate. Fig. Figure 18 shows a cross-sectional view 1800 of some embodiments belonging to process 3616.

[0129] In 3618, a plurality of interconnect layers are formed in a second dielectric structure along the front face of the second substrate. Fig. Figure 19 shows a cross-sectional view 1900 of some embodiments belonging to process 3618.

[0130] At 3620, the reverse side of the second substrate is selectively etched to define one or more depressions. Fig. Figures 20-21 show cross-sectional views 2000-2100 of some embodiments belonging to process 3620.

[0131] In 3622, isolation structures are formed along the back side of the second substrate. Fig. Figures 22-23 show cross-sectional views 2200-2300 of some embodiments belonging to process 3622.

[0132] At 3624, a bandpass filter is formed on one front side of the first substrate. Fig. Figures 30A - 30B show cross-sectional views 3300 and 3002 of some embodiments belonging to process 3624.

[0133] At 3626, the bandpass filter is bonded to the second IC die. Fig. Figure 31 shows a cross-sectional view 3100 of some embodiments belonging to process 3626.

[0134] At 3628, the thickness of the first substrate is reduced. Fig. Figure 32 shows a cross-sectional view 3200 of some embodiments belonging to process 3626.

[0135] At 3630, isolation structures are formed along the back side of a first substrate. Fig. Figures 33-34 show cross-sectional views 3300-3400 of some embodiments belonging to process 3630.

[0136] At 3632, a color filter is formed over the first IC die. Fig. Figure 35 shows a cross-sectional view 3500 of some embodiments belonging to process 3632.

[0137] At 3634, a microlens is formed above the color filter. Fig. Figure 35 shows a cross-sectional view 3500 of some embodiments belonging to process 3634.

[0138] Thus, in some embodiments, the present disclosure relates to a stacked image sensor device comprising an inter-substrate bandpass filter configured to reduce crosstalk between adjacent image sensor elements.

Claims

[1] Three-dimensional integrated chip comprising: a first IC die (102a) with a first image sensor element (104a) configured to generate electrical signals from electromagnetic radiation within a first wavelength range; a second IC die (102b) with a second image sensor element (104b) configured to generate electrical signals from electromagnetic radiation within a second wavelength range that differs from the first wavelength range; a first bandpass filter (106; 106a) arranged between the first IC die (102a) and the second IC die (102b) and configured to reflect electromagnetic radiation within the first wavelength range; and a waveguide (706) arranged over the first IC die (102a), wherein the waveguide (706) has a bottom side facing the first IC die and a top side facing away from the first IC die, the bottom side having a smaller width than the top side. [2] Integrated chip according to claim 1, further comprising: a second bandpass filter (106b) which is separated from the first IC die (102a) by the second IC die (102b), wherein the second bandpass filter is configured to reflect electromagnetic radiation which lies in the second wavelength range. [3] Integrated chip according to claim 1 or 2, wherein the first bandpass filter comprises (106; 106a): a first material layer (402) with a first refractive index; and a second material layer (404) with a second refractive index that is lower than the first refractive index. [4] Integrated chip according to claim 1 or 2, wherein the first bandpass filter comprises (106; 106a): a first layer (402) of silicon; a first layer (404) of silicon dioxide; and a second layer (402) of silicon, wherein the first layer of silicon dioxide extends continuously from a first surface touching the first layer of silicon to a second surface touching the second layer of silicon. [5] Integrated chip according to any of the preceding claims, wherein the first IC die comprises: a first substrate; and a first dielectric structure (502a) comprising a plurality of stacked ILD layers surrounding a plurality of conductive compound layers. [6] Integrated chip according to claim 5, wherein the first bandpass filter (106; 106a) is arranged between the first dielectric structure (502a) and the second IC die (102b). [7] Integrated chip according to claim 5 or 6, further comprising: a dielectric waveguide (606) arranged laterally between side walls of the first dielectric structure (502a) and extending vertically through the plurality of stacked ILD layers at a position above the first bandpass filter (106; 106a). [8] Integrated chip according to claim 5, wherein the first bandpass filter (106; 106a) is arranged between side walls of the first dielectric structure (502a). [9] Integrated chip according to one of the preceding claims, wherein the first bandpass filter (106; 106a) is configured to allow electromagnetic radiation to pass through within a passband comprising the second wavelength range. [10] Integrated chip according to one of the preceding claims, wherein the second IC die (102b) comprises a second substrate (302b) with a second upper surface facing the first IC die, wherein the second upper surface comprises angled side walls defining one or more recesses (310) in the second upper surface. [11] Integrated chip according to one of the preceding claims, wherein the first IC die (102a) comprises a first substrate (302a) having a substantially planar first upper surface facing away from the second IC die (102b). [12] Stacked image sensor device comprising: a first image sensor element (104a) arranged in a first substrate (302a) and configured to generate electrical signals from electromagnetic radiation within a first wavelength range, wherein the first substrate has a first surface configured to receive incident radiation and a second surface opposite the first surface; a second image sensor element (104b) arranged in a second substrate (304b) and configured to generate electrical signals from electromagnetic radiation within a second wavelength range that differs from the first wavelength range; a first bandpass filter (106; 106a) arranged between the second surface of the first substrate (302a) and the second substrate (302b) and comprising alternating layers of a first material (402) with a first refractive index and a second material (404) with a second refractive index different from the first, wherein the first bandpass filter (106; 106a) is configured to transmit electromagnetic radiation within the second wavelength range and to reflect electromagnetic radiation within the first wavelength range; and a waveguide (706) arranged above the first image sensor element (104a), wherein the waveguide (706) has a bottom side facing the first IC die and a top side facing away from the first IC die, the bottom side having a smaller width than the top side. [13] Stacked image sensor device according to claim 12, further comprising: a second bandpass filter (106b) separated from the first substrate (302a) by the second substrate (302b), wherein the second bandpass filter has alternating layers of a third material having a third refractive index and a fourth material having a fourth refractive index lower than the third refractive index. [14] Stacked image sensor device according to claim 13, wherein the first bandpass filter (106a) has a different number of layers than the second bandpass filter (106b). [15] Stacked image sensor device according to any one of claims 12 to 14, further comprising: a first dielectric structure (502a) arranged along the second surface of the first substrate (302a) and comprising a first plurality of stacked ILD layers surrounding a first plurality of conductive compound layers; and a second dielectric structure (502b) arranged along a surface of the second substrate (302b) comprising a second plurality of stacked ILD layers surrounding a second plurality of conductive compound layers. [16] Stacked image sensor device according to claim 15, wherein the first bandpass filter (106a) is arranged between side walls of the first dielectric structure (502a). [17] Stacked image sensor device according to claim 15 or 16, further comprising: a substrate via (924) extending through the second substrate (302b) and electrically coupling the first plurality of conductive interconnect layers to the second plurality of conductive interconnect layers, wherein the substrate via (924) extends through the first bandpass filter (106a). [18] Method for forming a three-dimensional integrated chip, comprising: Forming a first image sensor element (104a) in a first substrate (302a; 1002), wherein the first image sensor element (104a) is configured to generate electrical signals from electromagnetic radiation within a first wavelength range; Forming a second image sensor element (104b) in a second substrate (302b), wherein the second image sensor element (104b) is configured to generate electrical signals from electromagnetic radiation within a second wavelength range; Performing several deposition processes to form a first bandpass filter (106) over the second substrate, wherein the first bandpass filter has several alternating layers (402, 404) of a first material with a first refractive index and a second material with a second refractive index lower than the first refractive index; Bonding of the first substrate (302a; 1002) to the first bandpass filter (106); and Arranging a waveguide (706) over the first substrate (302a; 1002), wherein the waveguide (706) has a bottom side facing the first substrate (302a; 1002) and a top side facing away from the first substrate (302a; 1002), the bottom side having a smaller width than the top side.

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