Memory cells and memory devices with novel resistive random access memory

Abstract

Memory cell (200), comprising: a resistive material layer (226) comprising a first portion (226'-2) extending along a first direction and a second portion (226'-1) extending along a second direction, the first and second directions being different from each other; a first electrode (204) coupled to a lower surface of the first portion (226'-2) of the resistive material layer (226); and a second electrode (240) coupled to the second portion (226-1) of the resistive material layer (226); a first cap layer (224) comprising at least a portion coupled between the first electrode (204) and the first portion (226-2) of the resistive material layer (226); and a second cap layer (228) comprising at least a portion coupled between the second portion (226-1) of the resistive material layer (226) and the second electrode (240); wherein the portion of the first cover layer (224) extends along the first direction and the portion of the second cover layer (228) extends along the second direction.

Description

BACKGROUND

[0001] In recent years, unconventional non-volatile memory (NVM) devices, such as ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), and resistive random access memory (RRAM), have emerged. In particular, RRAM devices, which exhibit switching behavior between a high resistance state and a low resistance state, offer several advantages over conventional NVM devices. These advantages include, for example, compatible manufacturing steps with current complementary metal-oxide-semiconductor (CMOS) technologies, low-cost manufacturing, a compact structure, flexible scalability, fast switching, high integration density, etc.

[0002] As integrated circuits (ICs) incorporating such RRAM devices become increasingly more powerful, it is desirable to maximize the number of RRAM devices in the IC accordingly. Generally, an RRAM device includes a top electrode (e.g., an anode) and a bottom electrode (e.g., a cathode) with a variable resistance material layer sandwiched between them. Forming the RRAM device in such a stacked configuration may encounter a limit to maximizing the number of RRAM devices in the IC for various reasons. For example, an active region of the variable resistance material layer typically extends parallel to the top / bottom electrodes, and the number of RRAM devices is typically proportional to a number of such active regions.As such, within a given IC area, the number of RRAM devices that can be integrated is significantly limited. Thus, existing RRAM devices and methods for their fabrication are not entirely satisfactory.

[0003] The document US 8 729 521 B2 relates to a memory device having an array of memory cells comprising upper electrodes with first contact surfaces extending in a first direction, lower electrodes with second contact surfaces and memory material elements electrically coupled to the lower and upper electrodes.

[0004] The document DE 10 2014 014 234 A1 relates to a method for producing an electronic component, comprising depositing a first insulation layer over a transistor structure consisting of a gate electrode over a component layer on a substrate and a first contact region and a second contact region on the component layer on the sides opposite the gate electrode.

[0005] The document US 2017 / 0 018 708 A1 relates to a method for forming memory cells, comprising forming a plurality of heater structures over an array of electrical nodes, the array having rows extending along a first direction and columns extending along a second direction substantially orthogonal to the first direction.

[0006] The document US 2017 / 0 243 922 A1 relates to a variable resistance memory device comprising a substrate, a first insulating layer arranged on the substrate, first conductive traces arranged in a first direction on the first insulating layer, each of the first conductive traces extending in a second direction substantially perpendicular to the first direction.

[0007] The document US 2013 / 0 058 158 A1 relates to a method comprising forming a size of a first dimension and a second dimension of one or more memory components for a first trench and a second trench, wherein the first trench is positioned along a first direction in a dielectric material and the second trench is positioned along a second direction in the dielectric material approximately orthogonal to the first direction.

[0008] The document US 2015 / 0 021 675 A1 relates to a memory device comprising a semiconductor substrate, a first electrode having a conductive column formed above the substrate and extending in a vertical direction, and a second electrode extending in a lateral direction crossing the first direction, wherein the second electrode intersects the first electrode.

[0009] The document US 2015 / 0 069 316 A1 relates to a semiconductor structure comprising a conductive layer, a resistance-configurable structure over the conductive layer, wherein the resistance-configurable structure comprises a first electrode with a first sidewall, a second sidewall and a bottom surface on the conductive layer.

[0010] The document US 2017 / 0 279 036 A1 relates to a magnetoresistive random access memory device comprising a dielectric layer over a substrate and an opening therein, a resistance-variable memory cell in the opening with a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and that of the second electrode.

[0011] The task is to improve corresponding storage devices.

[0012] The object is achieved by a memory cell according to claim 1 and the memory devices according to claims 6 and 14.

[0013] Further embodiments arise from the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that various features are not necessarily drawn to scale. Indeed, the dimensions and geometries of the various features may be arbitrarily exaggerated or reduced for clarity. Fig. 1A and Fig. 1B illustrate a flowchart of a method of forming a semiconductor device according to some embodiments. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years and Fig. 2K illustrate cross-sectional views of a semiconductor device during various stages of fabrication according to the method in Fig. 1, according to some embodiments. Fig. 3 illustrates an example in which the semiconductor device of the Fig. 2A to 2K is coupled to one or more transistors, according to some embodiments. Fig. Figure 4 illustrates a plan view of a semiconductor device manufactured according to the method in Fig. 1 is manufactured according to some embodiments. Fig. Figure 5 illustrates an alternative structure of the semiconductor device of Fig. 2A to 2K, according to some embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following disclosure describes various embodiments for implementing different features of the subject matter. Specific examples of the components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. The formation of a first feature over or on top of a second feature in the description that follows may, for example, include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, spatially relative terms such as "beneath," "under," "deeper," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0017] The present disclosure provides various embodiments of a novel RRAM device and methods of forming the same. In some embodiments, the disclosed RRAM device includes a plurality of RRAM resistors, each including an L-shaped variable resistance material layer. Forming such an L-shaped variable resistance material layer in each RRAM resistor may allow a respective active region of the variable resistance material layer to extend along at least two different directions. In other words, the variable resistance material layer may include at least two portions extending along respective directions. Accordingly, in some embodiments, each top and bottom electrode of the RRAM resistor may be coupled to respective different portions of the variable resistance material layer.Thus, the number of “integrable” RRAM resistors within a given range can be significantly increased.

[0018] Fig. 1A and Fig. 1B illustrate a flowchart of a method 100 for forming a semiconductor device according to one or more embodiments of the present disclosure. It is noted that the method 100 is merely an example and is not intended to limit the present disclosure. In some embodiments, the semiconductor device is at least partially an RRAM device. As used in the present disclosure, the RRAM device refers to a device that includes a variable resistance material layer. It is noted that the method 100 in Fig. 1A and Fig. 1B does not produce a finished RRAM device. A finished RRAM device may be manufactured using complementary metal oxide semiconductor (CMOS) technology. Accordingly, it is understood that additional operations may be performed before, during, and after the method 100 of Fig. 1A and Fig. 1B, and that some other operations may be described only briefly herein.

[0019] First, with reference to Fig. 1A, in some embodiments, the method 100 begins with operation 102, in which a substrate having a conductive feature is provided. In some embodiments, the conductive feature may be a horizontal interconnect structure made of a metal material (e.g., copper (Cu)). In some embodiments, the conductive feature may serve as a common bottom electrode of a plurality of RRAM resistors of the RRAM device. The method 100 proceeds to operation 104, in which one or more dielectric fin structures are formed. In some embodiments, the one or more fin structures are formed on the conductive feature.Furthermore, in some embodiments, each of the one or more dielectric fin structures extends along a vertical direction perpendicular to a major surface of the conductive feature such that a corner can be formed at an intersection of a sidewall of each dielectric fin structure and the major surface of the conductive feature.

[0020] The method 100 proceeds to operation 106, in which a first capping layer is formed over the one or more dielectric fin structures and the substrate. The method 100 proceeds to operation 108, in which a variable resistance material layer is formed over the first capping layer. The method 100 proceeds to operation 110, in which a second capping layer is formed over the variable resistance material layer. In some embodiments, the first capping layer, the variable resistance material layer, and the second capping layer formed in operations 106, 108, and 110, respectively, are each substantially conformal and thin. As such, each of the first capping layer, the variable resistance material layer, and the second capping layer may follow a profile of the aforementioned corner (e.g., an L-shape), which is discussed in more detail below.

[0021] The method 100 proceeds to operation 112, in which the first cap layer, the variable resistance material layer, and the second cap layer are patterned. In some embodiments, during such a patterning operation, portions of the first cap layer, the variable resistance material layer, and the second cap layer that are directly coupled to the conductive feature and / or the substrate and are relatively farther from one of the one or more dielectric fin structures are removed. Thus, the one or more dielectric fin structures overlaid by the respective portions of the first cap layer, the variable resistance material layer, and the second cap layer are laterally spaced apart from one another.In other words, each of the one or more dielectric fin structures may be overlaid by the respective "patterned" first cap layer, variable resistance material layer, and second cap layer. Furthermore, the patterned first cap layer, variable resistance material layer, and second cap layer are laterally spaced from each other.

[0022] Then with reference to Fig. 1B, the method 100 continues with operation 114, in which an insulating layer is formed over the substrate. In some embodiments, the insulating layer overlies a portion of the main surface of the conductive feature, which is again exposed after operation 112, and respective upper surfaces of the "patterned" second capping layers. The method continues with operation 116, in which a dielectric layer is formed over the insulating layer. In some embodiments, an anti-reflective coating (ARC) layer may optionally be formed over the dielectric layer. The method 100 continues with operation 118, in which respective upper surfaces of the one or more dielectric fin structures are exposed. In some embodiments, a polishing process (e.g.,a chemical mechanical polishing (CMP) process is performed on respective portions of the dielectric layer, the insulation layer, the second cap layer, the variable resistance material layer, and the first cap layer until the respective upper surfaces of the one or more dielectric fin structures are exposed. The method 100 continues to operation 120 in which a plurality of recessed regions are formed within the dielectric layer. In some embodiments, a portion of each patterned second cap layer is exposed by one of the plurality of recessed regions, and each of the plurality of recessed regions is coupled to a patterned variable resistance material layer by a respective patterned second cap layer. The method 100 continues to operation 122 in which a plurality of upper electrodes are formed in the recessed regions, respectively.In some embodiments, the top electrodes are each formed by filling the respective recessed region with a conductive material (e.g., copper (Cu)). Accordingly, each top electrode is coupled to a patterned variable resistance material layer through a respective patterned second cap layer. In some embodiments, after operation 122, the plurality of RRAM resistors sharing the conductive feature as the bottom electrode are formed, which is discussed in more detail below.

[0023] In some embodiments, operations of the method 100 may include cross-sectional views of a semiconductor device 200 at various stages of fabrication, as shown in Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years and Fig. 2K. In some embodiments, the semiconductor device 200 may be an RRAM device. The RRAM device 200 may be included in a microprocessor, a memory cell, and / or another integrated circuit (IC). Furthermore, Fig. 2A to 2K for a better understanding of the concepts of the present disclosure. Although the figures illustrate, for example, the RRAM device 200, it should be understood that the IC in which the RRAM device 200 is formed may include a number of other devices, including resistors, capacitors, inductors, fuses, etc. Fig. 2A to 2K are not shown for the purpose of better clarity.

[0024] According to process 102 in Fig. 1A is Fig. 2A shows a cross-sectional view of the RRAM device 200, including a substrate 202 with a conductive feature 204 provided at one of the various manufacturing stages, according to some embodiments. Although the RRAM device 200 in the illustrated embodiment of Fig. 2A includes only one conductive feature 204, it is understood that the conductive feature 204 Fig. 2A and the following figures are provided for illustrative purposes only. Thus, RRAM device 200 may include any desired number of conductive features while remaining within the scope of the present disclosure.

[0025] In some embodiments, substrate 202 is a dielectric material substrate formed over various device features (e.g., a source, drain, or gate electrode of a transistor). Such a dielectric material substrate 202 may include at least one of: silicon oxide, a low-dielectric constant (low-K) material, other suitable dielectric material, or a combination thereof. The low-K material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiOxCy), Black Diamond®, xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (bis-benzocyclobutene), SiLK, polyimide, and / or other future-developed low-K dielectrics.

[0026] In such an embodiment, if the substrate 202 includes a dielectric material, the conductive feature 204 may be a horizontal or vertical conductive structure formed within the substrate 202. The conductive feature 204 may be, for example, an interconnect structure (i.e., a horizontal conductive structure) or a via structure (i.e., a vertical conductive structure). Accordingly, the conductive feature 204 may be electrically coupled to a device feature of a transistor, for example, a source, drain, or gate feature of the transistor, disposed below the level on which the substrate 202 is provided. In some embodiments, the conductive feature 204 may be formed from a metal material (e.g., copper (Cu), aluminum (Al), tungsten (W), etc.).

[0027] As mentioned above, the conductive feature 204 may serve as a common bottom electrode of a plurality of RRAM resistors of the RRAM device 200. In some embodiments, the conductive feature may be formed as a strip, viewed from above, to accommodate the plurality of RRAM resistors. Further, a plurality of such strips, each including a plurality of RRAM resistors, may each be arranged along a row or a column to form an array of RRAM resistors, as described below with reference to Fig. 4 is discussed in more detail.

[0028] According to process 104 in Fig. 1A is Fig. 2B illustrates a cross-sectional view of the RRAM device 200, including a plurality of dielectric fin structures 206, 208, and 210 formed at one of the various manufacturing stages, according to some embodiments. As shown, in some embodiments, the plurality of dielectric fin structures 206-210 are formed on and within a region bounded by the conductive feature 204. Each of the dielectric fin structures 206-210 protrudes beyond a major surface 205 of the conductive feature 204 and extends along a vertical direction perpendicular to the major surface 205 of the conductive feature 204.

[0029] As such, in some embodiments, a plurality of (L-shaped) corners may be formed at an intersection of a sidewall of one of the plurality of dielectric fin structures 206-210 and the main surface 205 of the conductive feature 204.For example, a corner 211 is formed at an intersection of one sidewall 206S of the dielectric fin structures 206 and the main surface 205, and a corner 213 is formed at an intersection of the other sidewall 206S of the dielectric fin structures 206 and the main surface 205; a corner 215 is formed at an intersection of one sidewall 208S of the dielectric fin structures 208 and the main surface 205, and a corner 217 is formed at an intersection of the other sidewall 208S of the dielectric fin structures 208 and the main surface 205; and a corner 219 is formed at an intersection of one side wall 210S of the dielectric fin structures 210 and the main surface 205 and a corner 221 is formed at an intersection of the other side wall 210S of the dielectric fin structures 210 and the main surface 205.

[0030] In some embodiments, each of the dielectric fin structures 206-210 may have a cross-section in any of a variety of shapes, e.g., a polygon. Alternatively, when viewed from above, each of the dielectric fin structures 206-210 has one of the aforementioned shapes. However, in some embodiments, the respective sidewalls of each dielectric fin structure are not directly coupled to each other. Accordingly, corners 211 / 213 around the same dielectric fin structure 206 are not directly coupled to each other; corners 215 / 217 around the same dielectric fin structure 208 are not directly coupled to each other; and corners 219 / 221 around the same dielectric fin structure 210 are not directly coupled to each other. In some embodiments, each of the dielectric fin structures 206-210 may have an aspect ratio (width / height) of about 0.01 to about 0.5.In some embodiments, a width of each of the dielectric fin structures 206-210 may be about 70 nm; and a height of each of the dielectric fin structures 206-210 may be about 140 nm to about 7000 nm. In some embodiments, a distance between two adjacent dielectric fin structures 206-210 may be about twice the width of each of the dielectric fin structures 206-210, e.g., about 140 nm.

[0031] In some embodiments, each of the dielectric fin structures 206-210 may be formed from an oxide material (e.g., silicon oxide). In some embodiments, the dielectric fin structures 206-210 are formed by performing at least some of the following processes: using chemical vapor deposition (CVD), high-density plasma (HDP) CVD, physical vapor deposition (PVD), spin-on coating, and / or other suitable techniques to apply the oxide material over the substrate 202 and the conductive feature 204; and performing one or more patterning processes (e.g., a lithography process, a dry / wet etch process, a cleaning process, a soft / hard bake process, etc.) to form the dielectric fin structures 206-210, respectively or simultaneously.

[0032] According to process 106 in Fig. 1A is Fig. 2C illustrates a cross-sectional view of the RRAM device 200, including a first capping layer 224 formed at one of the various manufacturing stages, according to some embodiments. As shown, the first capping layer 224 is formed to overlie the main surface 205 of the conductive feature 204 and each of the dielectric fin structures 206-210. In some embodiments, the first capping layer 224 is substantially conformal and thin (e.g., about 20-50 nm in thickness) such that the first capping layer 224 can follow an L-shape of each of the corners 211-221.

[0033] In some embodiments, the first capping layer 224 may be formed from materials such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. Although the first capping layer 224 in the illustrated embodiment of Fig. 2C (and the following figures) as a single layer, it should be appreciated that the first capping layer 224 may include multiple layers formed as a stack, each of the multiple layers formed from one of the materials described above, e.g., TaN, TiN, etc. In some embodiments, the first capping layer 224 is formed using chemical vapor deposition (CVD), plasma enhanced (PE) CVD, high density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin-on coating, and / or other suitable techniques to apply the at least one of the materials described above to the substrate 202, the conductive feature 204, and the plurality of dielectric fin structures 206-210.

[0034] According to process 108 in Fig. 1A is Fig. 2D illustrates a cross-sectional view of the RRAM device 200, including a variable resistance material layer 226 formed at one of the various manufacturing stages, according to some embodiments. As shown, the variable resistance material 226 is shaped to overlie the first capping layer 224. In some embodiments, the variable resistance material layer 226 is substantially conformal and thin (i.e., about 2-10 nm in thickness) such that the first variable resistance material layer 226 can still follow the L-shape of each of the corners 211-221.

[0035] In some embodiments, the variable resistance material layer 226 is a layer with a resistance change characteristic (e.g., variable resistance). In other words, the variable resistance layer 226 includes material characterized to exhibit reversible resistance variation according to a polarity and / or an amplitude of an applied electrical pulse. The variable resistance material layer 226 includes a dielectric layer. The variable resistance layer 226 can be changed into a conductor or an insulator based on the polarity and / or strength of an electrical signal.

[0036] In one embodiment, the variable resistance layer 226 may include a transition metal oxide. The transition metal oxide may be M x O ywhere M is a transition metal, O is oxygen, x is the transition metal composition, and y is the oxygen composition. In one embodiment, the variable resistance material layer 226 includes ZrO2. Examples of other materials suitable for the variable resistance material layer 226 include: NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, Nb2O5, Fe2O3, CuO, CrO2, SrZrO3 (Nb-doped), and / or other materials known in the art. In another embodiment, the variable resistance layer 226 may include a colossal magnetoresistance (CMR)-based material such as Pr 0.7 Ca 0.3 , MnO3, etc.

[0037] In yet another embodiment, the variable resistance layer 226 may include a polymer material such as polyvinylidene fluoride and poly[(vinylidene fluoride-co-trifluoroethylene] (PCVDF / TrFE)]. In yet another embodiment, the variable resistance layer 226 may include a conductive bridging direct memory (CBRAM) material such as Ag in GeSe. According to some embodiments, the variable resistance material layer 226 may include multiple layers with properties of a resistance conversion material. A set and / or reset voltage of the variable resistance material layer 226 may be determined by the compositions of the variable resistance material layer 226 (including the values ​​of "x" and "y" in "M x O y “, as discussed above), a thickness and / or other factors known in the art.

[0038] In some embodiments, the variable resistance material layer 226 may be formed by an atomic layer deposition (ALD) technique with a precursor containing a metal and oxygen. In some embodiments, other chemical vapor deposition (CVD) techniques may be used. In some embodiments, the variable resistance material layer 226 may be formed by a physical vapor deposition (PVD) technique, such as a sputtering process with a metallic target and a gas supply of oxygen and optionally nitrogen into the PVD chamber. In some embodiments, the variable resistance material layer 226 may be formed by an electron beam deposition technique.

[0039] According to process 110 in Fig. 1A is Fig. 2E illustrates a cross-sectional view of the RRAM device 200, including a second cap layer 228 formed at one of the various manufacturing stages, according to some embodiments. As shown, the second cap layer 228 is formed to overlay the variable resistance material layer 226. In some embodiments, the second cap layer 228 is substantially conformal and thin (e.g., about 20-50 nm in thickness) such that the second cap layer 228 can still follow an L-shape of each of the corners 211-221.

[0040] In some embodiments, the second capping layer 228 may be formed from a substantially same material as the first capping layer 224. The second capping layer 228 may thus be formed from materials such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. Although the second capping layer 228 in the illustrated embodiment of Fig. 2E (and the following figures) as a single layer, it should be appreciated that the second capping layer 228 may include multiple layers formed as a stack, each of the multiple layers formed from one of the materials described above, e.g., TaN, TiN, etc. In some embodiments, the second capping layer 228 is formed using chemical vapor deposition (CVD), plasma enhanced (PE) CVD, high density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin-on coating, and / or other suitable techniques to deposit the at least one of the materials described above over the variable resistance material layer 226.

[0041] According to process 112 in Fig. 1A is Fig. 2F illustrates a cross-sectional view of the RRAM device 200 in which the first cap layer 224, the variable resistance material layer 226, and the second cap layer 228 are patterned, at one of the various manufacturing stages, according to some embodiments. According to some embodiments, the first cap layer 224, the variable resistance material layer 226, and the second cap layer 228 are patterned to remove a portion of the respective horizontal sections (shown in dashed lines) that are relatively farther from the respective dielectric fin structures 206-210. As such, each of the dielectric fin structures 206-210 overlaid by respective "patterned" first cap layer 224', variable resistance material layer 226', and second cap layer 228' are laterally spaced from each other by a distance that can be filled with a portion of the re-exposed main surface 205.The "patterned" first cap layer 224', variable resistance material layer 226', and second cap layer 228' are laterally spaced apart from each other. And in some embodiments, the patterned first cap layer 224', variable resistance material layer 226', and second cap layer 228' may still follow the L-shape of each of the corners 211 through 221.

[0042] In particular, in some embodiments, the patterned first cap layer 224', variable resistance material layer 226', and second cap layer 228' may each include two vertical portions extending along the sidewalls (e.g., 206S, 208S, 210S, etc.) of the overlaid dielectric fin structure (e.g., 206, 208, 210, etc.) and two horizontal portions each coupled to the two vertical portions and in direct contact with the conductive feature 204. For the sake of clarity, taking the patterned first cap layer 224', variable resistance material layer 226', and second cap layer 228' overlying the dielectric fin structure 206 as a representative example, the patterned first cap layer 224' includes two vertical sections 224'-1, each extending along the sidewalls 206S, and two horizontal sections 224'-2,which are each coupled to the vertical sections 224'-1 and in contact with the conductive feature 204; the patterned variable resistance material layer 226' includes two vertical sections 226'-1, each extending along the sidewalls 206S, and two horizontal sections 226'-2, each coupled to the vertical sections 226'-1 and in direct contact with the conductive feature 204; and the patterned second cap layer 228' includes two vertical sections 228'-1, each extending along the sidewalls 206S, and two horizontal sections 228'-2, each coupled to the vertical sections 228'-1 and in direct contact with the conductive feature 204.

[0043] In some embodiments, the patterning process performed on the first cap layer 224, the variable resistance material layer 226, and the second cap layer 228 may include: a deposition process for forming a patternable layer (e.g., a photoresist layer) over the substrate 202, a lithography process for defining a profile of the patternable layer, a dry / wet etching process for etching respective portions of the first cap layer 224, the variable resistance material layer 226, and the second cap layer 228 that are not covered by the defined profile of the patternable layer, a cleaning process, and a soft / hard bake process.

[0044] According to process 114 in Fig. 1A is Fig. 2G illustrates a cross-sectional view of the RRAM device 200, including an insulation layer 230 formed at one of the various manufacturing stages, according to some embodiments. As shown, the insulation layer 230 is formed to overlie the patterned first cap layer 224', variable resistance material layer 224', second cap layer 228', the re-exposed main surface 205, and the substrate 202.

[0045] In some embodiments, the insulation layer 230 may be silicon carbide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or carbon-doped silicon oxide. The insulation layer 230 is selected to have a different etch selectivity than a dielectric layer 232 (in Fig. 2H), which is discussed below. The insulation layer 230 is deposited over the patterned first cap layer 224', variable resistance material layer 224', second cap layer 228', re-exposed main surface 205, and substrate 202 using a chemical vapor deposition (CVD) technique, such as plasma enhanced (PE) CVD, high density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, or thermal CVD.

[0046] According to process 116 in Fig. 1B is Fig. 2H is a cross-sectional view of the RRAM device 200, including a dielectric layer 232 formed at one of the various manufacturing stages, according to some embodiments. As shown, the dielectric layer 232 is formed to overlie the isolation layer 230. In some embodiments, the dielectric layer 232 has a thickness (e.g., about 100 nm ~ 700 nm) that is substantially greater than a height (e.g., less than about 100 nm) of each of the dielectric fin structures 206-210 overlaid by the respective patterned first cap layer 224', variable resistance layer 226', and second cap layer 228', and the isolation layer 230. In some embodiments, an anti-reflective coating (ARC) layer 234 may optionally be formed over the dielectric layer 232.

[0047] In some embodiments, the dielectric layer 232 may include at least one of: silicon oxide, a low-dielectric constant (Low-K) material, other suitable dielectric material, or a combination thereof. The Low-K material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiOxCy), Black Diamond®, xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (bis-benzocyclobutene), SiLK, polyimide, and / or other future-developed low-K dielectrics. In some embodiments, the dielectric layer 232 is deposited over the insulation layer 230 using a chemical vapor deposition (CVD) technique, such as plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, or a thermal CVD technique.

[0048] According to process 118 in Fig. 1B is Fig. 2I illustrates a cross-sectional view of RRAM device 200 in which upper surfaces 206T, 208T, and 210T of the plurality of dielectric fin structures 206, 208, and 210 are each exposed at one of the various manufacturing stages, according to some embodiments. As shown, when upper surfaces 206T to 210T are re-exposed, respective upper surfaces of vertical portions 224'-1, 226'-1, and 228'-1 of the patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' are also re-exposed. And in some embodiments, the patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' overlying a respective dielectric fin structure 206, 208, or 210 may be separated on two sides of the respective dielectric fin structure.

[0049] For example, the patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' overlying the dielectric fin structure 206 are separated at left and right sides of the dielectric fin structure 206; the patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' overlying the dielectric fin structure 208 are separated at left and right sides of the dielectric fin structure 208; and the patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' overlying the dielectric fin structure 206 are separated at left and right sides of the dielectric fin structure 210.

[0050] For the purpose of clarity, in the following discussions, the patterned second cap layer 228', the variable resistance material layer 226', and the first cap layer 224' separated at the left side of the dielectric fin structure 206 are collectively referred to as "RRAM layer 206-L"; the patterned second cap layer 228', the variable resistance material layer 226', and the first cap layer 224' separated at the right side of the dielectric fin structure 206 are collectively referred to as "RRAM layer 206-R"; the patterned second cap layer 228', the variable resistance material layer 226', and the first cap layer 224' separated at the left side of the dielectric fin structure 208 are collectively referred to as "RRAM layer 208-L";The patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' separated at the right side of the dielectric fin structure 208 are collectively referred to as "RRAM layer 208-R"; the patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' separated at the left side of the dielectric fin structure 210 are collectively referred to as "RRAM layer 210-L"; and the patterned second cap layer 228', variable resistance material layer 226', and first cap layer 224' separated at the right side of the dielectric fin structure 210 are collectively referred to as "RRAM layer 210-R";

[0051] In some embodiments, the process of exposing the upper surfaces 206T to 210T may include: a polishing process (e.g., a chemical mechanical polishing (CMP) process) performed on respective portions of the dielectric layer 232, the insulating layer 230, the patterned second cap layer 228', the patterned variable resistance material layer 226', and the patterned first cap layer 224' until the upper surfaces 206T to 210T are each exposed; and a cleaning process.

[0052] According to process 120 in Fig. 1B is Fig. 2J illustrates a cross-sectional view of the RRAM device 200, including a plurality of recessed regions 234-1, 234-2, 234-3, 234-4, 234-5, and 234-6 formed during one of the various manufacturing steps, according to some embodiments. As shown, the plurality of recessed regions 234-1 through 234-6 are formed within the dielectric layer 232 and the insulation layer 230. More specifically, in some embodiments, forming the recessed regions 234-1 through 234-6 may re-expose an upper sidewall of each of the vertical portions 228'-1 of the patterned second cap layer 228'.

[0053] In some embodiments, the recessed regions 234-1 to 234-6 are formed by performing at least some of the following processes: forming an optional anti-reflective coating (ARC) over the substrate; forming a patternable layer 236 (e.g., a photoresist layer) having a plurality of openings 237, as in Fig. 2J; using the patternable layer 236 as a mask, performing one or more dry etching processes to remove a plurality of upper portions of the insulation layer 232; and removing the patternable layer 236.

[0054] According to process 122 in Fig. 1B is Fig. 2K illustrates a cross-sectional view of the RRAM device 200, including a plurality of top electrodes 240-1, 240-2, 240-3, 240-4, 240-5, and 240-6 formed during one of the various manufacturing steps, according to some embodiments. In some embodiments, the top electrodes 240-1 to 240-6 may be formed by refilling the respective recessed regions 234-1 to 234-6 ( Fig. 2J) may be formed by a metal material (e.g., copper (Cu)). In some embodiments, each of the top electrodes 240-1 to 240-6 may be coupled to one of the "RRAM layers," e.g., 206-L, 206-R, 208-L, 208-R, 210-L, or 210-R. More specifically, each of the top electrodes 240-1 to 240-6 may be coupled to a respective vertical portion 226'-1 of a patterned variable resistance material layer 226' included in each RRAM layer. In one embodiment, the RRAM device 200 is substantially coplanar with the surfaces of the top electrodes 240-1 to 240-6.

[0055] For example, the top electrode 240-1 is coupled to the vertical portion 226'-1 of the patterned variable resistance material layer 226' included in the RRAM layer 206-L; the top electrode 240-2 is coupled to the vertical portion 226'-1 of the patterned variable resistance material layer 226' included in the RRAM layer 206-R; the top electrode 240-3 is coupled to the vertical portion 226'-1 of the patterned variable resistance material layer 226' included in the RRAM layer 208-L; the top electrode 240-4 is coupled to the vertical portion 226'-1 of the patterned variable resistance material layer 226' included in the RRAM layer 208-R; the top electrode 240-5 is coupled to the vertical portion 226'-1 of the patterned variable resistance material layer 226' included in the RRAM layer 210-L;and the top electrode 240-6 is coupled to the vertical portion 226'-1 of the patterned variable resistance material layer 226' included in the RRAM layer 210-R.;

[0056] Further, in some embodiments, any two adjacent top electrodes 240-1 to 240-6 are laterally spaced apart (e.g., electrically insulated) by either one of the dielectric fin structures 206 to 210 or the dielectric layer 232. For example, the top electrodes 240-1 and 240-2 are laterally spaced apart by the dielectric fin structures 206; the top electrodes 240-2 and 240-3 are laterally spaced apart by the dielectric layer 232; the top electrodes 240-3 and 240-4 are laterally spaced apart by the dielectric fin structures 208; the top electrodes 240-4 and 240-5 are laterally spaced apart by the dielectric layer 232; and the top electrodes 240-5 and 240-6 are laterally spaced apart by the dielectric fin structures 210.

[0057] As such, a variety of RRAM resistors can be formed. In the Fig. In the embodiment illustrated in FIG. 2K, a first RRAM resistor is formed from RRAM layer 206-L, top electrode 240-1, and conductive feature 204 serving as the bottom electrode of the first RRAM resistor (and other laterally spaced RRAM resistors), as described above. In particular, top electrode 240-1 is coupled to vertical portion 226'-1 of patterned variable resistance material layer 226' included in RRAM layer 206-L, and bottom electrode 204 is coupled to horizontal portion 226'-2 of patterned variable resistance material layer 226' included in RRAM layer 206-L.Similarly, a second RRAM resistor is formed by RRAM layer 206-R, top electrode 240-2, and conductive feature (bottom electrode) 204; a third RRAM resistor is formed by RRAM layer 208-L, top electrode 240-3, and conductive feature (bottom electrode) 204; a fourth RRAM resistor is formed by RRAM layer 208-R, top electrode 240-4, and conductive feature (bottom electrode) 204; a fifth RRAM resistor is formed by RRAM layer 210-L, top electrode 240-5, and conductive feature (bottom electrode) 204; a sixth RRAM resistor is formed by the RRAM layer 210-R, the top electrode 240-6 and the conductive feature (bottom electrode) 204.

[0058] It should be noted that by using the method 100 for forming the plurality of RRAM resistors, any two adjacent ones of the plurality of RRAM resistors are mirror-symmetrical across one of the dielectric fin structures 206, 208, and 210. For example, the first and second RRAM resistors are mirror-symmetrical across the dielectric fin structure 206; the third and fourth RRAM resistors are mirror-symmetrical across the dielectric fin structure 208; and the fifth and sixth RRAM resistors are mirror-symmetrical across the dielectric fin structure 210.In particular, the respective first capping layers, variable resistance material layers, and second capping layers of the first and second RRAM resistors are mirror-symmetric over the dielectric fin structure 206; the respective first capping layers, variable resistance material layers, and second capping layers of the third and fourth RRAM resistors are mirror-symmetric over the dielectric fin structure 208; and the respective first capping layers, variable resistance material layers, and second capping layers of the fifth and sixth RRAM resistors are mirror-symmetric over the dielectric fin structure 210.

[0059] In some embodiments, the common bottom electrode 204 may be coupled to a bit line (BL) at the circuit design level, and the top electrodes 240-1 to 240-6, corresponding to the respective different RRAM resistors, are each coupled to a respective transistor, also referred to as a select transistor. As such, multiple 1-transistor-1-resistor (1T1R) RRAM bit cells may be formed.

[0060] Fig. 3 illustrates an RRAM device 300 including a plurality of such 1T1R RRAM bit cells. In particular, the RRAM device 300 is shown in Fig. 3 from the RRAM device 200 in Fig. 2K, but the RRAM device 300 further includes a plurality of select transistors 302, 304, 306, 308, 310, and 312. More specifically, in some embodiments, the first RRAM resistor is coupled to a BL 314 via the common bottom electrode 204 and to a drain or source feature of the select transistor 302 via the top electrode 240-1, forming a first 1T1R RRAM bitcell. Similarly, the second RRAM resistor is coupled to the BL 314 via the common bottom electrode 204 and to a drain or source feature of the select transistor 304 via the top electrode 240-2, forming a second 1T1R RRAM bitcell; the third RRAM resistor is coupled to BL 314 via the common bottom electrode 204 and to a drain or source feature of the select transistor 306 via the top electrode 240-3, forming a third 1T1R RRAM bit cell;the fourth RRAM resistor is coupled to the BL 314 via the common bottom electrode 204 and to a drain or source feature of the select transistor 308 via the top electrode 240-4, forming a fourth 1T1R RRAM bit cell; the fifth RRAM resistor is coupled to the BL 314 via the common bottom electrode 204 and to a drain or source feature of the select transistor 310 via the top electrode 240-6, forming a fifth 1T1R RRAM bit cell; and the sixth RRAM resistor is coupled to the BL 314 via the common bottom electrode 204 and to a drain or source feature of the select transistor 312 via the top electrode 240-6, forming a sixth 1T1R RRAM bit cell.;

[0061] Although the selection transistors 302 to 312 in Fig. 3 are illustrated as being arranged across levels in which the common bottom electrode 204 is formed (hereinafter "1st level") and the plurality of RRAM resistors are formed (hereinafter "2nd level"), this is for illustrative purposes only. In some embodiments, such selection transistors 302-312 may be formed below the 1st and 2nd levels.

[0062] As mentioned above, in existing RRAM devices and methods for forming them, a maximum number of RRAM bitcells that can be integrated within a given area is limited because the active area of ​​the variable resistance material layer of each existing RRAM bitcell typically extends parallel to respective top / bottom electrodes. In marked contrast, the variable resistance material layer of the RRAM bitcell of the disclosed RRAM device (e.g., 200 / 300) is formed to have vertical and horizontal portions that allow a respective active area of ​​the variable resistance material layer to extend along more than one direction. Thus, the maximum number of RRAM bitcells that can be integrated into a "row" of the disclosed RRAM device (e.g., 200 / 300) can be significantly increased.Furthermore, multiple such rows may be repeatedly formed to integrate more RRAM bit cells into the disclosed RRAM device (e.g., 200 / 300). Thus, the total number of RRAM bit cells that can be integrated into the disclosed RRAM device (e.g., 200 / 300) can be further increased.

[0063] Fig. Figure 4 illustrates a top view of an RRAM device 400, including a plurality of the aforementioned integrated RRAM bit cells, according to some embodiments. It should be noted that the top view in Fig. 4 is simplified for illustrative purposes to show only top views of the respective RRAM resistors of the plurality of RRAM bit cells. In the illustrated embodiment in Fig. 4, the RRAM device 400 includes a plurality of RRAM units 400-1, 400-2, 400-3, 400-4, 400-4, 400-5, and 400-6, each including at least two RRAM resistors. As shown, the RRAM units 400-1 and up to 400-3 are arranged along a first row, and a plurality of such rows (e.g., a row formed by RRAM units 400-4 and up to 400-6) may be repeatedly arranged across the RRAM device 400.

[0064] Each RRAM unit includes at least two disclosed RRAM resistors. Taking RRAM unit 400-1 as an example, RRAM unit 400-1 includes RRAM resistors 401 and 403, each of which substantially Fig. 2A-2K. In particular, RRAM resistors 401 and 403 are laterally spaced apart by a dielectric fin structure 405 (substantially similar to dielectric fin structures 206, 208, and 210). RRAM resistor 401 is formed by a variable resistance material layer 407 (substantially similar to patterned variable resistance layers 226'), first and second cap layers 409 and 411 (substantially similar to patterned first and second cap layers 224' and 228', respectively), a top electrode 413 (substantially similar to top electrodes 240-1 through 240-6), and a common bottom electrode 414 (substantially similar to common bottom electrode 204).Similarly, the RRAM resistor 403 is formed by a variable resistance material layer 417, first and second cap layers 419 and 421, a top electrode 423, and the common bottom electrode 414.

[0065] Fig. 5 illustrates an alternative structure of the RRAM device 200 as shown in Fig. 2K. For clarity, the alternative structure of RRAM device 200 is referred to herein as an "RRAM device 500." As shown, RRAM device 500 is substantially similar to RRAM device 200, except that each of the patterned second cap layers 228' includes only the respective vertical portion 228'-1.

[0066] In one embodiment, a memory cell includes: a resistive material layer comprising a first portion extending along a first direction and a second portion extending along a second direction, the first and second directions being different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.

[0067] In another embodiment, a memory device includes: a first resistive material layer and a second resistive material layer laterally spaced apart by a dielectric structure, wherein the first and second resistive material layers each comprise a horizontal portion and a vertical portion, and wherein the vertical portions of the first and second resistive material layers each extend along a respective sidewall of the dielectric structure, and the horizontal portions of the first and second resistive material layers extend in opposite directions.

[0068] In yet another embodiment, a memory device includes: a plurality of dielectric structures laterally spaced apart from one another; and a plurality of pairs each comprising first and second resistive material layers, wherein the first and second resistive material layers of each of the plurality of pairs are mirror-symmetric across one of the plurality of dielectric structures, and respective vertical portions of the first and second resistive material layers each extend along a sidewall of the one of the plurality of dielectric structures, and respective horizontal portions of the first and second resistive material layers extend away from the one of the plurality of dielectric structures.

Claims

[1] Memory cell (200), comprising: a resistive material layer (226) comprising a first portion (226'-2) extending along a first direction and a second portion (226'-1) extending along a second direction, the first and second directions being different from each other; a first electrode (204) coupled to a lower surface of the first portion (226'-2) of the resistive material layer (226); and a second electrode (240) coupled to the second portion (226-1) of the resistive material layer (226); a first cap layer (224) comprising at least a portion coupled between the first electrode (204) and the first portion (226-2) of the resistive material layer (226); and a second cap layer (228) comprising at least a portion coupled between the second portion (226-1) of the resistive material layer (226) and the second electrode (240); wherein the portion of the first cover layer (224) extends along the first direction and the portion of the second cover layer (228) extends along the second direction. [2] The memory cell of claim 1, wherein the first and second directions are substantially perpendicular to each other. [3] The memory cell of claim 1 or 2, wherein the resistive material layer (226) has a variable resistance value. [4] A memory cell according to any preceding claim, wherein the first and second electrodes (204, 240) are parallel to each other and each extend along the first direction. [5] Memory cell according to one of the preceding claims, further comprising: a transistor, wherein the second electrode (240) is coupled to a drain feature or a source feature of the transistor. [6] Storage device (200) comprising: a first resistive material layer (226) and a second resistive material layer (226) laterally spaced apart by a dielectric structure (206), wherein the first and second resistive material layers (226) each comprise a horizontal portion (226'-2) and a vertical portion (226'-1), and wherein the vertical portions (226'-1) of the first and second resistive material layers each extend along a respective sidewall of the dielectric structure (206S) and the horizontal portions (226'-2) of the first and second resistive material layers (226) extend in opposite directions; a first electrode (204) coupled to a lower surface of the horizontal portions (226'-2) of the first and second resistive material layers (226); a second electrode (240-1) coupled to the vertical portion (226'-1) of the first resistive material layer (226); and a third electrode (240-2) coupled to the vertical portion (226'-1) of the second resistive material layer (226). [7] The memory device according to claim 6, wherein the first, second and third electrodes (204, 240-1, 240-2) are parallel to each other. [8] The memory device of claim 6 or 7, wherein the second and third electrodes (240-1, 240-2) are insulated from each other by at least the dielectric structure (206). [9] A storage device according to any one of the preceding claims 6 to 8, further comprising: a first transistor, wherein the second electrode (240-1) is coupled to a drain feature or a source feature of the first transistor; and a second transistor, wherein the third electrode (240-2) is coupled to a drain feature or a source feature of the second transistor. [10] The memory device of any one of claims 6 to 9, wherein the first resistive material layer (226), the first electrode, and the second electrode form a first resistive random access memory (RRAM) resistor, and the second resistive material layer, the first electrode, and the third electrode form a second RRAM resistor. [11] The memory device of claim 10, wherein the first RRAM resistor further comprises: a first cap layer (224) comprising at least a portion coupled between the first electrode (204) and the horizontal portion (226'-2) of the first resistive material layer (226); and a second cap layer (228) comprising at least a portion coupled between the vertical portion (226'-1) of the first resistive material layer (226) and the second electrode (240). [12] The memory device of claim 10, wherein the second RRAM resistor further comprises: a first cap layer (224) comprising at least a portion coupled between the first electrode (204) and the horizontal portion (226'-2) of the second resistive material layer (226); and a second cap layer (228) comprising at least a portion coupled between the vertical portion (226'-1) of the second resistive material layer (226) and the third electrode (240-2). [13] The memory device of any one of claims 6 to 12, wherein the first and second resistive material layers (226) each have a respective variable resistance value. [14] A storage device comprising: a plurality of dielectric structures (206) laterally spaced from one another; and a plurality of pairs each comprising first and second resistive material layers (226), wherein the first and second resistive material layers (226) of each of the plurality of pairs are mirror-symmetrical over one of the plurality of dielectric structures (206), and respective vertical portions (226) of the first and second resistive material layers (226) each extend along a sidewall (206S) of the one of the plurality of dielectric structures (206), and respective horizontal portions of the first and second resistive material layers (226) extend away from the one of the plurality of dielectric structures (206); wherein the respective vertical portions (226'-1) of the first and second resistive material layers (226) of each of the plurality of pairs are coupled to respective different upper electrodes (240-1, 240-2), and the respective different upper electrodes are parallel to the respective horizontal portions of the first and second resistive material layers (226) of each of the plurality of pairs. [15] The storage device of claim 14, further comprising: a lower electrode (204) coupled to the respective horizontal portions (226'-2) of the first and second resistive material layers (226) of each of the plurality of pairs, the lower electrode (204) being parallel to the respective horizontal portions (226'-2) of the first and second resistive material layers (226) of each of the plurality of pairs. [16] The memory device (400) of any preceding claim 14 or 15, wherein the first and second resistive material layers (226) of each of the plurality of pairs each have a respective variable resistance value.

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