Bidirectional communication using edge timing in a signal

Abstract

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.

Description

TECHNICAL AREA

[0001] The present disclosure relates to the field of communication protocols and techniques, and in particular methods, systems and circuits for communicating states and data between devices. BACKGROUND

[0002] Many microprocessor applications rely on a robust and simple low-bandwidth communication path between two devices. In safety-critical applications, a large number of communication paths are used to ensure that each safety-critical device functions appropriately. Therefore, it is essential that the communication paths in these applications support fast and reliable communication without requiring a large number of pins or additional components.

[0003] German patent application DE 10 2012 218 454 A1 discloses a system in which a common signal is received by a master device on a signal line between the master device and a slave device, wherein the common signal comprises a series of signal periods with rising and falling edges. The timing of the rising edge is determined.

[0004] US patent 2009 / 070506A1 discloses a method of sending a sequence of signals from a master to a slave, where binary values ​​of 0 and 1 are each encoded by a duration.

[0005] US 2013 / 246675A1 discloses techniques to prevent a master from remaining in an interrupt mode indefinitely after a disturbance signal from a slave, while the slave switches to an active mode.

[0006] EP 1 980 060 B1 reveals that a slave sends an error condition as an acknowledgment to a master. SUMMARY

[0007] This requirement is met by the features of independent claims 1, 9, 16 and 19. The features of the dependent claims define embodiments.

[0008] A method includes receiving, with a master device, a common signal on a signal line between the master device and a slave device. The common signal comprises a series of signal periods. Each signal period comprises a first edge of a first type and a second edge of a second type, which is different from the first type.The procedure also includes, in each signal period of the series of signal periods, with the master device: determining a timing of the second edge with respect to the signal period; determining information to be communicated by the slave device, at least based on the determined timing of the second edge; determining an operating state of the master device; selecting a timing for a subsequent first edge with respect to the signal period, at least based on the determined operating state; and generating the subsequent first edge at the selected timing in a subsequent signal period of the series of signal periods.

[0009] A method includes receiving, with a slave device, a common signal on a signal line between the slave device and a master device. The common signal comprises a series of signal periods. Each signal period comprises a first edge of a first type and a second edge of a second type, which is different from the first type.The procedure also includes, in each signal period of the series of signal periods, with the slave device: determining a timing of the first edge with respect to the signal period; determining an operating state of the master device at least based on the determined timing of the first edge; determining information for communication to the master device; selecting a timing for a subsequent second edge with respect to the signal period at least based on the determined information; and generating the subsequent second edge at the selected timing in a subsequent signal period of the series of signal periods.

[0010] A master device is designed to be connected to a slave device via a signal line. The signal line carries a common signal comprising a series of signal periods. Each signal period includes a first edge of a first type and a second edge of a second type, which is different from the first type. The master device includes a master detection circuit designed to: determine the timing of the second edge with respect to the signal period; and determine information to be communicated by the slave device, at least based on the determined timing of the second edge.The master device also includes a master communication circuit designed to: determine an operating state of the master device; select a timing for a subsequent first edge with respect to the signal period at least based on the determined operating state of the master device; and generate the subsequent first edge at the selected timing in a subsequent signal period of the series of signal periods.

[0011] A slave device is designed to be connected to a master device via a signal line. The signal line carries a common signal comprising a series of signal periods. Each signal period includes a first edge of a first type and a second edge of a second type, which is different from the first type. The slave device includes a slave detection circuit designed to: determine the timing of the first edge with respect to the signal period; and determine an operating state of the master device, at least based on the determined timing of the first edge.The slave device also includes a slave communication circuit designed to: determine information for communication with the master device; select a timing for a subsequent second edge with respect to the signal period at least based on the determined information; and generate the subsequent second edge at the selected timing in a subsequent signal period of the series of signal periods.

[0012] A system includes the slave device and the master device as described above.

[0013] It should be clarified that the features indicated above and those to be explained below can be used not only in the respective combinations shown, but also in other combinations or in isolation, without deviating from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Some examples of circuits, devices and / or procedures are described below only as examples.

[0015] In this context, reference is made to the accompanying characters. Fig. 1A and Fig. Figure 1B illustrates an example of a communication system that includes two devices performing bidirectional communication using edge timing in a signal according to various described aspects. Fig. 2 illustrates an example of the communication system of the Fig. 1A and Fig. 1B according to various described aspects. Fig. Figure 3 illustrates a timing diagram of a communication protocol for bidirectional communication using edge timing in a signal according to various described aspects. Fig. 4 illustrates an example of the communication system of the Fig. 1A and Fig. 1B according to various described aspects. Fig. 5 illustrates an example of the communication system of the Fig. 1A and Fig. 1B according to various described aspects. Fig. Figure 6 illustrates an example of an eight-bit signal format of a universal asynchronous receiver / transmitter (UART). Fig. Figure 7 illustrates an example of the communication system of the Fig. 1A and Fig. 1B according to various described aspects. Fig. 8A and Fig. Section 8B illustrates exemplary procedures for carrying out bidirectional communication using edge timing in a signal according to various described aspects. DETAILED DESCRIPTION OF ILLUSTRATIVE PERFORMANCE FORMS

[0016] In some microprocessor device applications, a central or master controller monitors the integrity or health of many different edge or slave devices under the control of the master controller. If a slave device malfunctions, the master controller takes a corrective action, such as terminating communication with the malfunctioning device and / or switching to some kind of fail-safe mode with respect to the function performed by the malfunctioning device. Each slave device, in turn, monitors the integrity or health of the master controller and switches to a fail-safe mode if the master controller malfunctions. The target response time for these systems is on the order of a few dozen microseconds to a few hundred microseconds.To prevent a malfunction in one slave device from affecting the communication of another, a dedicated communication channel is often installed between each slave device and the main controller. Therefore, continuous status monitoring between the main controller and slave devices requires fast and reliable communication through numerous communication paths.

[0017] For the purposes of this description, the terms "master" and "slave" are used to distinguish between two devices that perform the described communication using edge timing in a signal. It should be clarified that the described techniques can be performed by any two devices, regardless of whether the devices are in a master-slave relationship. While certain functions in the communication techniques may be assigned to one of the master devices or the slave device, it should further be clarified that the functions may be performed by either the master or the slave device instead or in addition to the master or slave device.

[0018] In complex microprocessor applications involving communication between many devices, it is understood that leaner communication techniques offer lower error rates and simpler, more cost-effective implementation. Many conventional safety-related applications include a primary communication channel or line used by the main controller to communicate a "life sign" (e.g., a pulse at a predefined timing) to the slave device. A secondary communication channel or line is used by the slave device to communicate its status or diagnostic information. This dual-channel communication is typically synchronized to a common clock, further complicating communication system implementation.In other solutions, the slave device does not regularly send information to the master, but instead blocks a communication line for a predetermined period and then sends information to the master as needed. This technique slows down communication and potentially disrupts the transmission from the master to the slave that occurs when the line is blocked.

[0019] This document describes methods, systems, and circuits that implement communication using edge timing within a signal. The described methods, systems, and circuits can use a single line to communicate both the master and slave states, as well as additional information, without requiring an external clock signal. This reduces the number of communication lines used and significantly simplifies the implementation of the communication system.

[0020] Fig. 1A and Fig. Figure 1B illustrates a communication system 100 that includes a master device 110 (hereinafter referred to as "master") and a slave device 150 (hereinafter referred to as "slave"). In some examples, the master 110 is a microcontroller that provides pulse-width modulated (PWM) or other control signals to the slave 150 and many other slaves (not shown). In some examples, the slave 150 is a gate driver for a high-power device, such as a fuel injector, a motor, or a solenoid. In some examples, the slave 150 is an isolated gate driver for a measuring device that, as controlled by the master 110, measures a temperature or voltage of another device and generates digital data encoding the measured temperature or voltage.

[0021] The master 110 and the slave 150 are connected via their respective interfaces 115 and 155 to a single signal line 140, which is illustrated as an exemplary common signal. As in Fig. As described in more detail in section 3, the common signal includes a series of edges of alternating types (e.g., rising or falling). The common signal has a signal period defined by the time between adjacent falling edges. Of course, rising edges may determine the common signal period in other examples. Throughout this description, falling edges are generated by the master and interpreted by the slave, while rising edges are generated by the slave and interpreted by the master. It should be noted that in other examples, rising edges may be generated by the master and interpreted by the slave, while falling edges may be generated by the slave and interpreted by the master.

[0022] Fig. Figure 1A illustrates an example of the master 110 in operation. The master 110 includes a master detection circuit 120 and a master communication circuit 130. The master detection circuit 120 detects the timing of a rising edge in each signal period and interprets the timing of the rising edge as a communication of information from the slave 150. For example, the master detection circuit 120 can interpret the timing of the rising edge as an indication of the operating state of the slave 150. The master 110 includes other components, not shown here, designed to perform a corrective action in response to the common signal indicating that the slave 150 is not operating properly. In other examples, the master detection circuit 120 can interpret the timing of the rising edge as a communication of data generated by a component of the slave 150.The master 110 can include components, not shown, that perform additional processing on the decoded data determined by the master detection circuit 120 based on the timing of the rising edges.

[0023] The master communication circuit 130 determines a state of the master 100 at regular intervals and generates a falling edge in a subsequent period based on that determined state. For example, if the master 110 functions appropriately, the master communication circuit 130 can generate a falling edge according to a predetermined timing, thereby setting the signal period of the common signal to a regular time interval.

[0024] Fig. Figure 1B illustrates an example of the slave 150 operating simultaneously with the master 110. The slave 150 includes a slave detection circuit 160 and a slave communication circuit 170. The slave detection circuit 160 detects the timing of the falling edges and interprets the time between adjacent falling edges as defining the signal period of the common signal. In one example, the slave detection circuit 160 determines that the master 110 operates appropriately if a falling edge falls within a predetermined window within the signal period defined by preceding falling edges.

[0025] In each signal period, the slave communication circuit 180 generates a rising edge in the shared signal. The slave communication circuit 180 determines the information to be communicated to the master 110 and selects a timing within the signal period to communicate this information. For example, if the slave is functioning correctly, it generates the rising edge at a first time within the signal period, which is interpreted as such by the master detection circuit 120. If the slave determines that it is not functioning correctly, it may generate the rising edge at a second time within the signal period, which is also interpreted as such by the master detection circuit 120. In another example, the slave 150 may have digital data (e.g., temperature or voltage) to communicate with the master 110.The slave communication circuit 180 can select a first timing of the second edge to communicate a "1", or a second timing of the second edge to communicate a "0".

[0026] It is evident that the communication system 100 provides a single communication line 140 that carries a common signal which simultaneously communicates information from the master 110 to the slave 150 and from the slave to the master using edge timing. Throughout this description, the specific timing of edges is described in such a way as to how it is detected. Edge timing detection can be performed in various ways. For example, the value of the common signal can be checked at a specific timing, and the time of an edge that occurred before the check time can be deduced based on the signal value. Alternatively, a quantity of energy received during a signal period can be used to deduce a point in time during the signal period when a transition from low to high occurred.For example, if the amount of energy corresponds to about one-third of the amount of energy that would result from a signal period where the common signal has a consistently high value, it can be deduced that the rising edge occurred at a time approximately one-third of the signal period has elapsed.

[0027] Fig. Figure 2 illustrates a communication system 200 that includes a master 210, a slave 250, and a signal line 240. The signal line 240 is designed as a "wired AND" gate, in which the signal line 240 is kept at a high voltage using a voltage from a supply 217 in the master 210, which is applied to a pull-up resistor (RPU) and connected to the signal line. For faster signal transmission, an external pull-up resistor (RPU) can be used. In other examples, an internal pull-up resistor may suffice. A master interface 215 and a slave interface 255 are each a single pin on the master 210 and the slave 250, respectively. In one example, a standard I / O pin is used as the interfaces 215 and 255.

[0028] In the example of Fig. The master detection circuit includes a buffer 220, which regenerates and stores the value of the common signal on signal line 240 at a selected time, and a processor 225. Buffer 220 provides the value of the common signal to processor 225, which is designed to interpret the value of the common signal and the selected time to determine the information communicated by slave 250. The slave detection circuit also includes a buffer 260, which regenerates and stores the value of the common signal on signal line 240 at a selected time, and a processor 265. Buffer 260 provides the value of the common signal to processor 265, enabling the processor to interpret the value of the common signal and the selected time to determine the state of master 210.The 265 processor interprets the time between adjacent falling edges as defining the signal period (common signal period in . Fig. 3) and thus also the time period during which Slave 150 is supposed to communicate its information (the “slave communication time period” in Fig. 3).

[0029] The master communication circuit includes an open-drain output 230 and the processor 225. When the open-drain output is closed by the processor 225, the common signal is pulled down or set to a defined level, thereby generating a falling edge in the common signal. The processor 225 is designed to close the open-drain output 230 for a relatively short, predetermined duration when the master 210 is operating. An example of a predetermined standard master communication circuit output is shown in the upper line in Fig. Figure 3 shows the signal period of the common signal shown in the lower line, which is defined as the time between the falling edges generated by the open-drain output 230.

[0030] The slave communication circuit includes an open-drain output 270 and the processor 265. When a falling edge is detected, the open-drain output 270 is closed by the processor 265 for a duration selected to align the rising edge, generated when the open-drain gate opens, with a selected timing within the signal period. The output of the slave communication circuit (in the second line in Fig. (shown in Figure 3) is combined with the standard signal of the master communication circuit to extend the low-order output through the master to generate a rising edge in the common signal (third line) at a selected time. The selected time can be a fraction of the signal period (as defined by the falling edges and not by an external clock) that communicates the appropriate information (e.g., a 1 or 0) or a state (e.g., different levels of slave functionality). For the purposes of this description, the term "fraction" means a segment of the signal period determined based on a specific ratio or percentage of the total signal period (e.g., 20%, 50%, 100%, and so on), as defined by the time interval between successive falling edges.

[0031] Fig. Figure 3 illustrates an example of how three different second-edge positions in three different signal periods can communicate three different slave operating states and / or data values. As shown in the first signal period, the rising edge in the common signal occurs at the end of the pulse sent by the master communication circuit, when the slave is not responding to the common signal at all. If the master detection circuit detects the rising edge (or a high value) at a time corresponding to the end of the master pulse, the master interprets this rising edge as an indication that the slave is unavailable and, if necessary, takes corrective action or waits to determine if the slave will become available later.

[0032] During each signal period, the master detection circuit checks the value of the common signal at a predetermined time after the end of the master pulse (e.g., in the middle or at 50% of the signal period, as indicated by the "master check time" and the circle on the common signal). Fig. (shown in Figure 3) when the slave has responded to the common signal (e.g., is available). In the second signal period, a high value is detected when the master detection circuit checks the common signal at the master check time. This high value at the master check time is interpreted by the master detection circuit as an indication that the slave is operational, or alternatively, that the slave is sending a data value of 1. Accordingly, the slave communication circuit communicates that it is operational or sends a data value of 1 by holding the common signal line low for less than the master check time (e.g., less than 50% of the signal period).

[0033] During the third signal period, a low value is detected when the master detection circuit checks the common signal at the master check time. This low value at the master check time is interpreted by the master detection circuit as either a communication that the slave is not operating or, alternatively, that the slave is sending a data value of 0. Accordingly, the slave communication circuit communicates that it is operating or sends a data value of 0 by keeping the common signal line low for more than the master check time (e.g., more than 50% of the signal period).

[0034] It should be noted that the time at which the master detection circuit checks the common signal (and the time at which the slave communication circuit generates falling edges) can be defined as a function or fraction of the signal period, which in turn is defined by the falling edges generated by the master communication circuit, and not by an external clock. No external clock signal is required. There are no restrictions regarding the baud rate. If the timing of the falling edges changes during operation, the signal period used by both the master and the slave will change, and communication will remain effective.

[0035] The in Fig. The illustrated scheme can be extended to allow the slave to communicate multiple different state modes. For example, a rising edge within an initial time period (e.g., the first 20% of the signal period) can indicate that the slave is operational. A rising edge in a subsequent time period (e.g., the next 20% of the signal period) can indicate that the slave is in an undervoltage state. A rising edge in a subsequent time period (e.g., the next 20% of the signal period) can indicate that the slave is in an overvoltage state. A rising edge in a subsequent time period (e.g., the next 20% of the signal period) can indicate that the slave is in an overtemperature state. A rising edge in a subsequent time period (e.g., the next 20% of the signal period) can indicate that the slave is in a short-circuit state.The master recognizes which of these states the slave has by determining during which time period a high value in the common signal is first detected.

[0036] Fig. Figure 4 illustrates a communication system 400 that includes a microcontroller 410 acting as a master for two safety-related gate drivers 450a and 450b. The microcontroller 410 provides independent PWM control signals to the gate drivers 450a and 450b and also communicates and receives operating state information on the signal lines 440a and 440b, respectively. In one example, the microcontroller 410 sets falling edges in the common signal on the lines 440a and 440b to provide both a state and a timing to the gate drivers 450a and 450b, while the gate drivers 450a and 450b set rising edges to communicate one of several operating state levels (including unavailability), as referenced in Fig. 3 described.

[0037] A safety circuit 490 monitors the common signals on signal lines 440a and 440b. The safety circuit determines the signal period of each common signal and the state of the microcontroller 410 based on the timing of falling edges. It also determines the state of the corresponding gate driver based on the timing of rising edges. If the safety circuit 490 determines that the common signal indicates that the microcontroller 410 or the gate driver 450a or 450b is malfunctioning, the safety circuit 490 sends fail-safe (e.g., emergency or safety mode) commands to the affected gate driver. In this way, the safety circuit provides an additional fail-safe mechanism that operates independently in response to the common signal.It should be noted that the 490 safety circuit can use only a single pin to monitor each common signal, instead of using a dedicated signal line for the microcontroller's vital sign signal and the status signal of each gate driver. Furthermore, no complicated decoding mechanism is required.

[0038] Fig. Figure 5 illustrates a communication system 500 that includes a microcontroller 510 acting as a master for two isolated gate drivers 550a and 550b used in high-voltage applications. Each gate driver includes an analog-to-digital converter (ADC), such as a sigma-delta converter, which converts an analog measurement signal provided by the associated measuring device A or B into a digital signal. In the illustrated example, device A measures the temperature of a circuit breaker, and device B measures a voltage on an isolated secondary side (e.g., an intermediate circuit), as shown in Figure 5. Fig. Figure 5 shows that the 510 microcontroller provides independent PWM control signals to the gate drivers 550a and 550b and also communicates its status information on the signal lines 540a and 540b, respectively. In one example, the 510 microcontroller sets falling edges to provide both a status and timing for the common signal to the gate drivers 550a and 550b. The 510 microcontroller can determine slave availability by performing an "early" check for a high value, as shown in Figure 5. Fig. As described in section 3, the 550a and 550b gate drivers introduce rising edges into the common signal to communicate data from the ADC. In many applications, the measured voltage or temperature changes very slowly, while the measurement signal is very noisy. This makes the use of a sigma-delta ADC in the 550a and 550b gate drivers particularly advantageous.

[0039] In one example, the timing signal provided by the falling edges in the common signal can be used as the clock signal to the sigma-delta ADC, and the ADC can communicate either a 1 or a 0 in each signal period by controlling the position of the rising edge, as in Fig. Figure 3 shows that since the microcontroller also knows the timing signal, decoding the incoming sigma-delta ADC data and timestamping are simplified.

[0040] In another example, the timing of rising edges generated by the gate drivers 550a, 550b can be used to simulate a UART signal that communicates more complex diagnostic and measurement data. Fig. Figure 6 illustrates an example eight-bit UART signal 600. The UART signal encloses a ten-bit data frame, beginning with a start bit and ending with a stop bit. Thus, eight bits of information (e.g., starting with the least significant bit and ending with the most significant bit) can be communicated serially in each frame. The inactive level of either the sender or the receiver is the high level. In UART communication, both devices must use the same duration for the ten-bit frame, which typically requires a synchronized clock signal for both devices.

[0041] Returning to Fig. Gate drivers 550a and 550b can set rising edges in the common signal to communicate data from the ADC in a UART format. Each gate driver determines the duration of the signal period / UART data frame based on the falling edges in the common signal. During each signal period, the gate driver can transmit at least one bit of the UART frame. The complete UART frame can be transmitted in several successive signal periods. In this way, the microcontroller defines the bit timing for the gate driver, and no complex timing settings are required.

[0042] Fig. Figure 7 illustrates a communication system 700 that includes a microcontroller 710 acting as a master for two isolated gate drivers 750a and 750b used in high-voltage applications. Each gate driver includes an analog-to-digital converter (ADC), such as a sigma-delta converter, which converts an analog measurement signal provided by the associated measuring device A or B into a digital signal. In the illustrated example, device A measures the temperature of a circuit breaker, and device B measures a voltage on an isolated secondary side (e.g., an intermediate circuit), as shown in Fig. Figure 7 shows that during normal operation, the 710 microcontroller provides independent PWM control signals to the 750a and 750b gate drivers and also communicates its status information on the 740a and 740b signal lines, respectively. In one example, the 710 microcontroller sets falling edges on the common signal to provide both a status and timing information to the 750a and 750b gate drivers. The 750a and 750b gate drivers can communicate their availability and functionality, as shown in Figure 7. Fig. 3 described.

[0043] The 700 communication system also includes an activation line that the 710 microcontroller uses to put the 750a and 750b gate drivers into configuration mode. When a 750a gate driver is in configuration mode, the microcontroller uses the common signal line 740a to transmit a few bytes of information in UART format, referring to Fig. 5 and Fig. As described in section 6. In configuration mode, the 750a gate driver can use the 740 common signal line to communicate diagnostic or feedback data in UART or PWM format. This allows the update setting to select between operating mode and configuration mode. In configuration mode, the gate driver output can turn off (disable) the power switch regardless of the PWM line's state. The PWM line and the common signal line can then be used as clock and data signals for data transmission between the master and slave devices, for example, to transmit timing information on one line and communication data on the other. This increases communication bandwidth and allows for faster configuration of the slave device.

[0044] Fig. Figure 8A illustrates an exemplary method 800, which is carried out by a device for communicating with another device using edge timing in a common signal. Method 800 can be implemented, for example, by the master 110, 210 or the microcontroller 410, 510, 710 of Fig. 1, Fig. 2, Fig. 4, Fig. 5 or 7 are performed. In the case of 805, the procedure involves receiving a common signal on a signal line between the master device and the slave device. The common signal comprises a series of signal periods, each including a first edge of a first type and a second edge of a second type that is different from the first type.In each signal period of the series of signal periods, at 810 a timing of the second edge is determined with respect to the signal period; at 815 information communicated by the slave device is determined, at least based on the determined timing of the second edge; at 820 an operating state of the master device is determined; at 825 a timing for a subsequent first edge with respect to the signal period is selected, at least based on the determined operating state; and at 830 the subsequent first edge is generated at the selected timing in a subsequent signal period of the series of signal periods.

[0045] Fig. Figure 8B illustrates an exemplary method 850, which is carried out by a device for communicating with another device using edge timing in a common signal. Method 850 can be implemented, for example, by the slave 150, 250 or the driver 450a, 450b, 550a, 550b, 750a, 750b of Fig. 1, Fig. 2, Fig. 4, Fig.5 or 7 are performed. In the case of 855, the procedure involves receiving a common signal on a signal line between the slave device and the master device. The common signal comprises a series of signal periods, each including a first edge of a first type and a second edge of a second type that is different from the first type.In each signal period of the series of signal periods, at 860 a timing of the first edge is determined with respect to the signal period; at 865 an operating state of the master device is determined at least based on the determined timing of the first edge; at 870 information for communication to the other device is determined; at 875 a timing for a subsequent second edge with respect to the signal period is selected at least based on the determined information; and at 880 the subsequent second edge is generated at the selected timing in a subsequent signal period of the series of signal periods.

[0046] It is evident from the foregoing description that the described systems, circuits and methods enable the communication of states and / or data between two devices with a common signal transmitted on a single signal line, by using the timing of one type of edge in the common signal to transmit information about a first device, and the timing of the other type of edge to transmit information about a second device.

[0047] While the invention has been illustrated and described with respect to one or more implementations, changes and / or modifications to the illustrated examples may be made without deviating from the nature and scope of the appended claims. With particular regard to the various functions performed by the components or structures (assemblies, devices, circuits, systems, etc.) described above, the terms used to describe these components (including any reference to a "means") shall, unless otherwise specified, correspond to any component or structure that performs the specified function of the described component (which is, for example, functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function disclosed in the exemplary implementations of the invention illustrated herein.

[0048] Examples may include an object such as a method, a means of performing actions or blocks of the method, at least one machine-readable medium, including instructions which, when executed by a machine, cause the machine to perform actions of the method or of a device or system for bidirectional communication using edge timing according to embodiments and examples described herein.

[0049] Example 1 is a method which, with a master device, includes receiving a common signal on a signal line between the master device and a slave device, wherein the common signal includes a series of signal periods and wherein each signal period includes a first edge of a first type and a second edge of a second type, which is different from the first type.The procedure includes, in each signal period of the series of signal periods: determining a timing of the second edge with respect to the signal period; determining information to be communicated by the slave device, at least based on the determined timing of the second edge; determining an operating state of the master device; selecting a timing for a subsequent first edge with respect to the signal period, at least based on the determined operating state; and generating the subsequent first edge at the selected timing in a subsequent signal period of the series of signal periods.

[0050] Example 2 includes the subject matter of Example 1, optionally including or omitting elements, and further comprising: determining a value of the common signal during a window, including a predetermined fraction of the signal period; and determining an operating state of the slave device based on that value.

[0051] Example 3 includes the subject matter of Example 1, optionally including or omitting elements, and further comprising, in response to a determination that the operating state of the master device is satisfactory, a selection of a predefined default timing for the subsequent first edge.

[0052] Example 4 includes the subject matter of Example 1, optionally including or omitting elements, and further comprising decoding a data output by a component in the slave device at least based on the specified timing of the second edge and performing subsequent processing on the decoded data.

[0053] Example 5 includes the subject matter of Example 1, optionally including or omitting elements, and further comprising determining an operating state of the slave device at least based on the determined timing of the second edge.

[0054] Example 6 includes the subject matter of Example 1, optionally including or omitting elements, and further comprising a determination of one of a variety of failure modes for the slave device, at least based on the determined timing of the second edge.

[0055] Example 7 includes the subject of Example 1, optionally including or omitting elements, wherein the master device and the slave device are connected using a wired-AND connection, and wherein generating the subsequent first edge includes selectively setting the signal line to a defined level at the selected timing in the subsequent signal period of the series of signal periods.

[0056] Example 8 includes the subject of Example 1, optionally including or omitting elements, wherein the signal line between the master device and the slave device includes a single signal line.

[0057] Example 9 is a method which, with a slave device, includes receiving a common signal on a signal line between the slave device and a master device, wherein the common signal includes a series of signal periods and wherein each signal period includes a first edge of a first type and a second edge of a second type, which is different from the first type.The procedure includes, in each signal period of the series of signal periods: determining a timing of the first edge with respect to the signal period; determining an operating state of the master device based at least on the determined timing of the first edge; determining information for communication to the master device; selecting a timing for a subsequent second edge with respect to the signal period based at least on the determined information; and generating the subsequent second edge at the selected timing in a subsequent signal period of the series of signal periods.

[0058] Example 10 includes the subject matter of Example 9, optionally including or omitting elements, and further comprising: determining a duration of the signal period; and determining an operating state of the master device based on the determined duration.

[0059] Example 11 includes the subject matter of Example 9, optionally including or omitting elements, and further comprising determining a duration of the signal period at least based on a time between one or more pairs of successive first edges.

[0060] Example 12 includes the subject matter of Example 11, optionally including or omitting elements, and further comprising: determining a proportion of the signal period that communicates the specified information; and wherein the timing for the subsequent second edge is selected to coincide with the expiration of the specified proportion of the subsequent signal period.

[0061] Example 13 includes the subject matter of Example 1, optionally including or omitting elements, and further comprising: determining a data output by a component in the slave device as the information; and wherein the timing for the subsequent second edge is selected at least on the basis of the data and the determined duration of the signal period.

[0062] Example 14 includes the subject of Example 9, optionally including or omitting elements, wherein the master device and the slave device are interconnected using a wired-AND connection, and wherein generating the subsequent second edge includes selectively setting the signal line to a defined level at the selected timing in the subsequent signal period of the series of signal periods.

[0063] Example 15 includes the subject of Example 9, optionally including or omitting elements, wherein the signal line between the master device and the slave device includes a single signal line.

[0064] Example 16 is a master device designed to be connected to a slave device by a signal line, the signal line carrying a common signal including a series of signal periods, and each signal period including a first edge of a first type and a second edge of a second type different from the first type. The master device includes a master detection circuit and a master communication circuit. The master detection circuit is designed to: determine a timing of the second edge with respect to the signal period; and determine information to be communicated by the slave device, at least based on the determined timing of the second edge.The master communication circuit is designed to: determine an operating state of the master device; select a timing for a subsequent first edge with respect to the signal period at least based on the determined operating state of the master device; and generate the subsequent first edge at the selected timing in a subsequent signal period of the series of signal periods.

[0065] Example 17 includes the subject of Example 16, optionally including or omitting elements, wherein the master device and the slave device are interconnected using a wired-AND connection, and wherein the master communication circuit includes a switch that is controllable to selectively set the signal line to a defined level at the selected time in the subsequent signal period of the series of signal periods.

[0066] Example 18 includes the subject matter of Example 16, optionally including or omitting elements, wherein the master detection circuit is designed to: determine a value of the common signal during a window, including a predetermined fraction of the signal period; and determine an operating state of the slave device based on that value.

[0067] Example 19 includes the subject matter of Example 16, optionally including or omitting elements, wherein the master communication circuit is further designed to select a predefined default timing for the subsequent first edge in response to determining that the operating state of the master device is satisfactory.

[0068] Example 20 includes the subject matter of Example 16, optionally including or omitting elements, wherein the master detection circuit is further configured to decode a data output by a component in the slave device based on the specified timing of the second edge and to perform subsequent processing on the decoded data.

[0069] Example 21 includes the subject matter of Example 16, optionally including or omitting elements, wherein the master detection circuit is further designed to determine one of a variety of fault modes for the slave device at least based on the determined timing of the second edge.

[0070] Example 22 includes the subject of Example 16, optionally including or omitting elements, wherein the signal line between the master device and the slave device includes a single signal line.

[0071] Example 23 is a slave device designed to be connected to a master device by means of a signal line, wherein the signal line carries a common signal including a series of signal periods, and wherein each signal period includes a first edge of a first type and a second edge of a second type, which is different from the first type. The slave device includes a slave detection circuit and a slave communication circuit. The slave detection circuit is designed to: determine a first-edge timing with respect to the signal period; and determine an operating state of the master device at least based on the determined first-edge timing.The slave communication circuit is designed to: determine information for communication to the master device; select a timing for a subsequent second edge with respect to the signal period at least based on the determined information; and generate the subsequent second edge at the selected timing in a subsequent signal period of the series of signal periods.

[0072] Example 24 includes the subject matter of Example 23, optionally including or omitting elements, wherein the slave detection circuit is further configured to: determine a duration of the signal period; and determine an operating state of the master device based on the determined duration.

[0073] Example 25 includes the subject matter of Example 23, optionally including or omitting elements, wherein the slave detection circuit is further configured to determine a duration of the signal period at least based on a time between one or more pairs of successive first edges.

[0074] Example 26 includes the subject matter of Example 25, optionally including or omitting elements, wherein the slave communication circuit is further designed to: determine a portion of the signal period that communicates the specified information; and select the timing of the subsequent second edge to coincide with the expiration of the specified portion of the subsequent signal period.

[0075] Example 27 includes the subject matter of Example 23, optionally including or omitting elements, wherein the slave communication circuit is further designed to: determine a data output by a component in the slave device as the information; and select the timing for the subsequent second edge at least based on the data.

[0076] Example 28 includes the subject of Example 23, optionally including or omitting elements, wherein the signal line between the master device and the slave device includes a single signal line.

[0077] Example 29 includes the subject matter of Example 23, optionally including or omitting elements, wherein the master device and the slave device are interconnected using a wired-AND connection, and wherein the slave communication circuit includes a switch that is controllable to selectively set the signal line to a defined level at the selected timing in the subsequent signal period of the series of signal periods.

[0078] The foregoing description of one or more implementations provides a representation and description, but is not intended to be exhaustive or to limit the scope of protection of the exemplary embodiments to precisely the disclosed form. Modifications and variations are possible in light of the above teachings or may be obtained from the practical implementation of different implementations of the exemplary embodiments.

[0079] Various illustrative logics, logic blocks, modules, circuits, and interconnects described in connection with aspects disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine.

[0080] The foregoing description of illustrated embodiments of the disclosure, including the description in the abstract, is not intended to be exhaustive or to limit the disclosed embodiments to exactly the disclosed form. Although specific embodiments and examples are described herein for illustrative purposes, various modifications are possible which, as those skilled in the relevant field may recognize, are to be considered within the scope of protection of these embodiments and examples.

[0081] Although the disclosed subject matter is described in connection with various embodiments and corresponding figures, it should be clarified in this context that other similar embodiments may be used, or modifications and additions may be made to the described embodiments, in order to perform the same, a similar, alternative, or substitute function of the disclosed subject matter without deviating from it. Therefore, the disclosed subject matter must not be limited to a single embodiment described herein, but instead must be interpreted in breadth and scope in accordance with the claims set forth below.

[0082] Throughout this disclosure, the same reference symbols are used to refer to the same elements, and the illustrated structures and devices are not necessarily drawn to scale. As used herein, the terms "module," "component," "system," "circuit," "circuit," "element," "disk," and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and / or firmware. For example, "circuit" or a similar term may be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer with a processing device. For illustration, an application running on a server and the server itself may also be considered a circuit.One or more circuits can be contained within a process, and a circuit can be localized on one computer and / or distributed between two or more computers. A set of elements or a set of other circuits may be described herein, where the term "set" can be interpreted as "one or more".

[0083] As another example, a circuit or a similar term can be a device with specific functionality provided by mechanical parts operated by electrical or electronic circuits, where the electrical or electronic circuits can be operated by a software application or firmware application executed by one or more processors. The one or more processors can be located inside or outside the device and can execute at least part of the software or firmware application.As yet another example, a circuit can be a device that provides specific functionality through electronic components without mechanical parts; wherein the electronic components may include field gates, logic components, hardware-coded logic, register transfer logic, one or more processors therein for executing software and / or firmware that at least partially provide the functionality of the electronic components.

[0084] It is understood that when an element is described as "electrically connected" or "electrically coupled" to another element, it can be physically connected or coupled to the other element in such a way that current and / or electromagnetic radiation can flow along a conductive path formed by the elements. Intermediate conductive, inductive, or capacitive elements may be present between the element and the other element when the elements are described as electrically coupled or connected. Furthermore, an element may be capable of inducing a voltage or current flow, or propagation of an electromagnetic wave, in the other element without physical contact or intervening components, if they are electrically coupled or connected.Furthermore, when a voltage, current, or signal is described as being “applied” to an element, the voltage, current, or signal may be conveyed to the element by means of a physical connection or by means of capacitive, electromagnetic, or inductive coupling that does not involve a physical connection.

[0085] The use of the word "exemplary" is intended to illustrate concepts in a concrete way. The terminology used herein serves only to describe specific examples and is not intended to limit examples. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, it is understood that the terms "comprises," "comprehensive," "includes," and / or "including," when used herein, indicate the presence of specified features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

Claims

[1] Method, comprehensive, with a master device (110, 210): Receiving a common signal on a signal line (140, 240) between the master device (110, 210) and a slave device (150, 250), wherein the common signal comprises a series of signal periods and wherein each signal period comprises a first edge of a first type and a second edge of a second type, which is different from the first type; and in each signal period of the series of signal periods: Determining the timing of the second edge in relation to the signal period; Determining information to be communicated by the slave device (150, 250) at least based on the specified timing of the second edge; Determining an operating state of the master device (110, 210); Selecting a timing for a subsequent first edge with respect to the signal period, at least based on the specified operating state; and Generating the subsequent first edge at the selected timing in a subsequent signal period of the series of signal periods. [2] The method of claim 1, further comprising: Determining a value of the common signal during a window that covers a predetermined fraction of the signal period; and Determining the operating state of the slave device based on the value. [3] Method according to claim 1 or 2, further comprising, in response to a determination that the operating state of the master device (110, 210) is satisfactory, selecting a predefined default timing for the subsequent first edge. [4] Method according to one of the preceding claims, further comprising decoding a data output by a component in the slave device at least based on the determined timing of the second edge and performing subsequent processing on the decoded data. [5] Method according to any of the preceding claims, further comprising determining an operating state of the slave device (150, 250) at least based on the determined timing of the second edge. [6] Method according to one of the preceding claims, further comprising determining one of a plurality of fault modes for the slave device (150, 250) at least based on the determined timing of the second edge. [7] Method according to one of the preceding claims, wherein the master device (110, 210) and the slave device (150, 250) are connected to each other using a wired AND connection and wherein generating the subsequent first edge comprises selectively setting the signal line (140, 240) to a defined level at the selected timing in the subsequent signal period of the series of signal periods. [8] Method according to one of the preceding claims, wherein the signal line (140, 240) between the master device and the slave device comprises a single signal line (140, 240). [9] Method comprising, with a slave device (150, 250): Receiving a common signal on a signal line (140, 240) between the slave device (150, 250) and a master device (110, 210), wherein the common signal comprises a series of signal periods and wherein each signal period comprises a first edge of a first type and a second edge of a second type, which is different from the first type; and in each signal period of the series of signal periods: Determining the timing of the first edge in relation to the signal period; Determining an operating state of the master device (110, 210) at least based on the determined timing of the first edge; Determining information for communication to the master device (110, 210); Selecting a timing for a subsequent second edge with respect to the signal period, at least based on the specified information; and Generating the subsequent second edge at the selected timing in a subsequent signal period of the series of signal periods. [10] The method of claim 9, further comprising: Determining the duration of the signal period; and Determining an operating state of the master device (110, 210) based on the determined duration. [11] Method according to claim 9 or 10, further comprising determining a duration of the signal period at least based on a time between one or more pairs of successive first edges. [12] The method of claim 11, further comprising: Determining a proportion of the signal period that communicates the specific information; and where the time for the subsequent second edge is selected to coincide with the expiration of a certain proportion of the subsequent signal period. [13] The method of claim 11, further comprising: Determining data output by a component in the slave device as the information; and where the timing for the subsequent second edge is selected at least based on the data and the determined duration of the signal period. [14] Method according to any one of claims 9 to 13, wherein the master device (110, 210) and the slave device (150, 250) are connected to each other using a wired AND connection and wherein generating the subsequent second edge includes selectively setting the signal line (140, 240) to a defined level at the selected timing in the subsequent signal period of the series of signal periods. [15] Method according to any one of claims 9 to 14, wherein the signal line (140, 240) between the master device (110, 210) and the slave device (150, 250) comprises a single signal line (140, 240). [16] Master device (110, 210) designed to be connected to a slave device (150, 250) by means of a signal line (140, 240), wherein the signal line (140, 240) carries a common signal comprising a series of signal periods, and wherein each signal period comprises a first edge of a first type and a second edge of a second type, which is different from the first type; the master device comprising: a master detection circuit (120) designed for: Determining the timing of the second edge in relation to the signal period; and Determining information that is communicated by the slave device, at least based on the specified timing of the second edge; and a master communication circuit (130) designed for: Determining an operating state of the master device; Selecting a timing for a subsequent first edge with respect to the signal period, at least based on the determined operating state of the master device; and Generating the subsequent first edge at the selected timing in a subsequent signal period of the series of signal periods. [17] Master device (110, 210) according to claim 16, wherein the master device (110, 210) is designed to be connected to the slave device (150, 250) using a wired AND connection, and wherein the master communication circuit (130) comprises a switch which is controllable to selectively set the signal line (140, 240) to a defined level at the selected time in the subsequent signal period of the series of signal periods. [18] Master device (110, 210) according to claim 16 or 17, further designed to carry out the method according to any one of claims 1 to 8. [19] Slave device (150, 250) designed to be connected to a master device (110, 210) by means of a signal line (140, 240), wherein the signal line (140, 240) carries a common signal comprising a series of signal periods, and wherein each signal period comprises a first edge of a first type and a second edge of a second type, which is different from the first type; the slave device comprising: a slave detection circuit designed to: Determining the timing of the first edge in relation to the signal period; and Determining an operating state of the master device, at least based on the determined timing of the first edge; and a slave communication circuit designed to: Determining information for communication to the master device; Selecting a timing for a subsequent second edge with respect to the signal period, at least based on the specified information; and Generating the subsequent second edge at the selected timing in a subsequent signal period of the series of signal periods. [20] Slave device (150, 250) according to claim 19, further designed to perform the method according to any one of claims 9 to 15.

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