MULTI-STAGE POWER CONVERTER

Abstract

Power converters (200, 800) for providing an output voltage with a specified conversion ratio, wherein the power converter has a ground port, a first port (202) and a second port (204), wherein, when the power converter operates as a buck converter, the first port (202) receives an input voltage and the second port (204) provides the output voltage, and, when the power converter operates as a boost converter, the second port (204) receives an input voltage and the first port (202) provides the output voltage; wherein the power converter further comprises: a single inductor with a first terminal and a second terminal, wherein the second terminal is coupled to the second port (204); a first flying capacitor that is selectively coupled to the inductor; a second flying capacitor that is selectively coupled to the inductor; a network of switches; and a driver (220) configured to control the network of switches with a sequence of states during a control period, wherein the sequence of states has a first state and a second state, wherein in the first state one of the first port (202) and the ground port is coupled to the second port (204) via a first path which includes the first flying capacitor and bypasses the inductor, and wherein the remaining port consisting of the first port (202) and the ground port is coupled to the second port (204) via a second path which includes the second flying capacitor and the inductor, such that when one flying capacitor consisting of the first and the second flying capacitor receives a current from the first port (202), the other flying capacitor receives a current from the ground port, wherein in the second state one of the first port (202) and the ground port is coupled to the second port (204) via a third path which includes the second flying capacitor and bypasses the inductor, and wherein the remaining port consisting of the first port and the ground port is coupled to the second port (204) via a fourth path which includes the first flying capacitor and the inductor; wherein each of the first flying capacitor and the second flying capacitor has a first terminal selectively coupled to the first port (202) and a second terminal selectively coupled to the ground port; wherein the network of switches comprises: a first capacitor switch to couple the first terminal of the first flying capacitor to the first terminal of the inductor; a second capacitor switch to couple the first terminal of the second flying capacitor to the first terminal of the inductor; a third capacitor switch to couple the second terminal of the first flying capacitor to the second terminal of the inductor; and a fourth capacitor switch to couple the second terminal of the second flying capacitor to the second terminal of the inductor.

Description

RELATED PATENT APPLICATIONS

[0001] This application refers to application no. US 16 / 386,770, filed on April 17, 2019 (Ref: DS19-002G), and application no. US 16 / 386,735, filed on April 17, 2019 (Ref: DS19-012G), which are assigned to a common successor and are incorporated in their entirety by reference. Technical field

[0002] The present disclosure relates to a power converter and a method for operating it. In particular, the present disclosure relates to a multi-stage power converter with an improved transient load response. background

[0003] In recent years, portable computing devices such as smartphones, tablets, and notebooks have increased their processing power, screen resolution, and refresh rate. These advances have been made possible by silicon technology approaching the submicrometer range of 10 nm and below, enabling the formation of ultra-narrow gate structures. Ultra-narrow gate structures exhibit increased leakage current for each transistor.

[0004] Given that central processing units (CPUs) and graphics processing units (GPUs) consist of several hundred million transistors, the leakage current of a modern microprocessor is considerable. To reduce battery consumption, the embedded processing cores are typically disconnected from the power supply as often as possible. As a result, the required computing power is provided within short operating bursts. Therefore, the power profile of a modern mobile computing device is dominated by relatively long periods of standby currents in the milliampere range, interrupted by pulses of high peak currents (in the range of 20 amps and above).The challenge for a power management unit is to provide low currents with high conversion efficiency to optimize battery life, combined with providing high currents without saturation effects and with a stable output voltage.

[0005] One solution to avoid saturation and high resistance losses in the current path from the battery is to use a battery pack with cells connected in series. For Li-ion / Li-poly cells, this results in nominal battery pack voltages of approximately N × 3.7V (where N is the number of cells). For example, a voltage of 7.4V can be obtained for a pack with 2 cells in series (2S), or a voltage of 11V for a pack with 3 cells connected in series (3S). The dominant current draw is typically caused by the processor, which has transistors that can only maintain voltages in or even below the 1V range. This triggers significant voltage conversion ratios that cannot be efficiently provided by DC-DC converters, which are built with relatively large switches with high nominal voltage and high gate charge consumption for each switching operation.As a result, standard step-down converters tend to switch at a relatively low frequency, which is why high-inductance inductors are required to limit current ripple. These high-inductance inductors are typically large, especially when a high peak current needs to be provided.

[0006] The challenge described above can be addressed by providing an intermediate rail between the battery pack's output voltage and the processor's input voltage. This approach allows the use of DC-DC converters with reduced-voltage switches, which can be switched faster for the same switching loss. Consequently, a lower inductance can be used. The lower inductance reduces the coil's DC resistance, allowing for a higher peak current.

[0007] For example, mobile computing devices can implement a 5V or a 3.3V intermediate bus. Using standard (inductive) step-down converters with a power handling capacity greater than the processor's peak load suffers from the limitations mentioned above, and the converter is either large or exhibits poor efficiency at low loads.

[0008] If the intermediate bus follows the battery pack voltage, an unregulated capacitive voltage divider can provide high efficiency over a wide current range without the need for a space-consuming inductor. For example, a 2:1 converter can transform the output of a 2S battery pack to the typical voltage range of a 1S pack, enabling the use of standard low-voltage PMICs. However, the lack of regulation can cause problems when the battery pack is deeply discharged (e.g., towards 5V). Because the converter provides a 2:1 reduced output voltage, the output voltage can drop further, for example, by 100–300mV, when a load current is drawn. Such a low bus voltage is typically below the undervoltage cutoff threshold of cascaded power converters.

[0009] Regulation can be added by using a three-stage DC-DC converter, as described in US 2018 / 0175726A1. The efficiency of a multi-stage converter is typically lower than that of an unregulated capacitive voltage divider using similar switches. This is due to the inductor's direct current resistance (DCR) and inductor magnet core losses. The maximum output current of a conventional multi-stage converter is limited by the rated current of its inductor.

[0010] To increase peak current capability, such a converter must use larger inductors or route the total current through multiple inductors. This results in a larger printed circuit board (PCB) area and a larger bill of materials (BOM).

[0011] If the conversion ratio V in / V outIn the 2:1 ratio (or 1:2 in the case of reverse operation), the converter according to US 2018 / 0175726A1 allows the current through the inductor to be reduced to a fraction of the converter output current. The reduced inductor current results in reduced inductor DCR loss and improved converter efficiency.

[0012] Applications sensitive to current ripple may require a large input capacitance or ferrite beads to address the pulsed current drawn from the converter. For conversion ratios V in / V out Approaches closer to 1:1 or 1:0 are limited by increased switching line losses compared to conventional three-stage DC-DC converter topologies (US 2018 / 0 175 726 A1).

[0013] German patent DE 10 2016 225 795 A1 describes a power converter that converts power between a first converter voltage at a first converter terminal and a second converter voltage at a second converter terminal. It comprises a first capacitor network, an inductor, and a first switching matrix to arrange the first capacitor network and the inductor in different states.

[0014] German patent DE 10 2015 212 331 A1 describes a boost converter for LED backlighting applications. The power converter includes an inductor, a plurality of capacitors, and a plurality of switches.

[0015] German patent DE 10 2015 209 330 A1 describes a power converter for charging batteries with reduced input voltage ripple. The power converter includes an inductor, a capacitor cell, a variety of switches, and a control unit.

[0016] US 2015 / 0084611A1 describes a boost converter comprising a first switch configured to be coupled to an inductor and to assist a charging current in the inductor from a power source, and at least two second switches coupled in series, coupled in parallel to the first switch and configured to selectively conduct current from the inductor to at least two capacitors connected in series.

[0017] WO 2014 / 154 390 A1 describes a voltage modulator with a multi-stage switched capacitor modulator connected in parallel to a switched voltage regulator. Summary

[0018] According to a first aspect of the disclosure, a power converter according to the accompanying claim 1 is provided.

[0019] Optionally, the sequence has an intermediate state, with the driver being configured to select the intermediate state from a multitude of intermediate states based on the desired conversion ratio.

[0020] Optionally, an intermediate state can be provided between the first and second states. For example, a sequence can start with the first state, followed by the intermediate state, then the second state, and end with the intermediate state.

[0021] Optionally, in the intermediate state, the first port is coupled to the second port via at least one of the first path and the third path, and the first port is additionally coupled to the second port via a fifth path comprising the inductor, wherein if the power converter operates as a buck converter, the intermediate state is a magnetization state, and if the power converter operates as a boost converter, the intermediate state is a demagnetization state.

[0022] Optionally, in the intermediate state, the first port is coupled to the second port via at least one of the first path and the third path, and the ground port is coupled to the second port via a sixth path comprising the inductor, wherein, if the power converter operates as a buck converter, the intermediate state is a demagnetization state, and, if the power converter operates as a boost converter, the intermediate state is a magnetization state.

[0023] Optionally, the driver can be configured to maintain the first and second states for a predefined duration during the control period. This predefined duration can be set based on the conversion ratio. The predefined duration can differ for the first and second states; for example, the second state can be maintained for a longer period than the first.

[0024] Optionally, the driver is configured to change the duration of the intermediate state based on the target conversion ratio.

[0025] Optionally, in the second state, the first port is coupled to the second port via a seventh path, which includes the second flying capacitor and the inductor, and the ground port is coupled to the second port via an eighth path, which includes the first flying capacitor and the inductor.

[0026] Optionally, the network of switches includes a first switch for coupling the first flying capacitor to the first port; a second switch for coupling the second flying capacitor to the first port; a first ground switch for coupling the first flying capacitor to the ground port; a second ground switch for coupling the second flying capacitor to the ground port; wherein the inductor has a first terminal and a second terminal, the second terminal being coupled to the second port.

[0027] Optionally, the power converter has a first additional switch provided between the first terminal of the inductor and the ground port or between the first terminal of the inductor and the first ground switch.

[0028] Optionally, the power converter has a second additional switch provided between the first terminal of the inductor and the second ground switch.

[0029] According to a second aspect of the disclosure, a method according to the accompanying claim 12 is provided.

[0030] The options described in relation to the first aspect of revelation are also common to the second aspect of revelation. Brief description of the drawings

[0031] The revelation is described in more detail below by way of example and with reference to the accompanying drawings, in which: Fig. 1 is a flowchart of a process for converting power with a target conversion ratio; Fig. 2A and Fig. 2B Diagrams of a DC-DC converter for implementing the method of Fig. 1 are; Fig. 3A a diagram of the DC-DC converter from Fig. 2 is the one that is operated in a first state; Fig. 3B a diagram of the DC-DC converter of Fig. 2 is the one that is operated in a second state; Fig. 4A a diagram of the DC-DC converter from Fig. 2 is the one that is operated in an intermediate magnetization state; Fig. 4B a diagram of the DC-DC converter of Fig. 2 is, which is operated in a different intermediate magnetization state; Fig. 5A a diagram of the DC-DC converter from Fig. 2 is the one that is operated in an intermediate demagnetization state; Fig. 5B a diagram of the DC-DC converter from Fig. 2 is the one that operates in a different intermediate demagnetization state; Fig. Figure 6 is a timing diagram that shows a control sequence for operating the DC-DC converter of Fig. 2 represents; Fig. Figure 7 is a timing diagram that shows a different control sequence for the operation of the DC-DC converter. Fig. 2 represents; Fig. 8 a diagram of another DC-DC converter for implementing the method of Fig. 1 is; Fig. 9 a diagram of another DC-DC converter for implementing the method of Fig. 1 is; Fig. 10 a diagram of a modified version of the DC-DC converter from Fig. 9 is; Fig. 11 a diagram of an asymmetric DC-DC converter for implementing the method of Fig. 1 is; Fig. 12 a diagram of another asymmetric DC-DC converter for implementing the method of Fig. 1 is; Fig. 13A a diagram of the DC-DC converter from Fig. 2 is the one that is operated in a first upward conversion state; Fig. 13B a ​​diagram of the DC-DC converter of Fig. 2 is the one that operates in a second upward conversion state. Description

[0032] Fig. Figure 1 is a flowchart of a process for converting a voltage with a target conversion ratio. In step 105, a ground connection, an input connection for receiving an input voltage, and an output connection for providing an output voltage are provided. In step 110, an inductor is provided. In step 120, a first flying capacitor is provided, which is selectively coupled to the inductor. In step 130, a second flying capacitor is provided, which is selectively coupled to the inductor. In step 140, a network of switches is provided. In step 150, the network of switches is driven with a sequence of states during a drive period. The sequence of states has a first state and a second state.In the first state, either the input terminal or the ground terminal is coupled to the output terminal via a first path that includes the first flying capacitor and bypasses the inductor. In the first state, the remaining connection from the input terminal and the ground terminal is coupled to the output terminal via a second path that includes the second flying capacitor and the inductor.

[0033] Several second states can be used. For example, in the second state, the input terminal can be coupled to the output terminal via a third path that includes the second flying capacitor and bypasses the inductor. Alternatively, in the second path, the ground terminal can be coupled to the output terminal via a fourth path that includes the first flying capacitor and the inductor.

[0034] Fig. Figure 2B is a diagram of a DC-DC converter 200 for implementing the method of Fig. 1. The DC-DC converter 200 comprises two capacitors C1 and C2 and an inductor L, coupled between an input node 202 and an output node 204 via a network of switches consisting of nine switches S1, S2, S3, S4, S5, S6, S7, S8, and S9. An input capacitor Cin is provided between input node 202 and ground, and an output capacitor Cout is provided between output node 204 and ground. Switch S9 is optional and can be used to provide a body diode current during a dead time. For example, for a conversion ratio of VinVout≤2 Switch S9 may not be required. Capacitors Cin and Cout are connected to a fixed ground voltage and can be described as reservoir capacitors. Capacitors C1 and C2 have terminals with varying voltages and can be described as flying capacitors.

[0035] The first flying capacitor C1 is connected to input node 202 via switch S1 and to ground via switch S4. Similarly, the second flying capacitor C2 is connected to input node 202 via switch S5 and to ground via switch S8. The first flying capacitor C1 has a first terminal connected to node 206 and a second terminal connected to node 208. The second flying capacitor C2 has a first terminal connected to node 210 and a second terminal connected to node 212. The inductor L has a first terminal connected to node 214 and a second terminal connected to output node 204. The first terminal at node 214 is connected to node 206 via switch S2 and to node 210 via switch S6.The output terminal at node 204 is coupled to node 208 via switch S3 and to node 212 via switch S7. A single switch S9 couples the first terminal of inductor L to ground. A driver 220 is provided to generate a variety of control signals Ct1, Ct2, Ct3, Ct4, Ct5, Ct6, Ct7, Ct8, Ct9 to actuate switches S1-S9 accordingly. The driver 220 is located in... Fig. 2A is designed to operate the DC-DC converter 200 with a sequence of states.

[0036] Fig. 3A shows the DC-DC converter from Fig. 2, which operates in a first main state, also referred to as state A, in which switches S1, S3, S6, and S8 are closed, while the remaining switches S2, S4, S5, S7, and S9 are open. In state A, input node 202 is coupled to output node 204 via a first path comprising switch S1, the first flying capacitor C1, and switch S3. Ground is coupled to output node 204 via a second path comprising switch S8, the second flying capacitor C2, switch S6, and inductor L.

[0037] Fig. 3B shows the DC-DC converter from Fig. 2, which operates in a second main state, also referred to as state B, in which switches S2, S4, S5, and S7 are closed, while the remaining switches S1, S3, S6, S8, and S9 are open. In state B, input node 202 is coupled to output node 204 via a third path comprising switch S5, the second floating capacitor C2, and switch S7. Ground is coupled to output node 204 via a fourth path comprising switches S2 and S4, the first floating capacitor C1, and inductor L.

[0038] The driver is therefore configured to perform interleaved switching, so that when the first inline capacitor draws current from the input, the second inline capacitor draws current from ground, and vice versa. The voltages V C1 and V C2Above the flying capacitor C1 and C2 are defined by equation 1 as: VC1=VC2=Vin−Vout

[0039] The voltage V L L can be expressed as: VL=VC2−Vout

[0040] Therefore, V can L depending on the value of V out It could be either positive or negative.

[0041] The DC-DC converter 200 can dissipate energy due to line losses through the switches, inductor, and flying capacitors, as well as core losses due to energy dissipated by the core of the inductor L. If the conversion ratio VinVout=2,VC1=VC2=Vin / 2. As a result, V L = 0 and the DC-DC converter has no inductor core losses. The low-side switches S3, S4, S7 and S8 are rated for a voltage V out designed.

[0042] Fig. Figure 4A shows a diagram of the DC-DC converter from Fig. 2, which operates in an intermediate magnetization state designated as state I1. Switches S1, S2, S3, S5, and S6 are closed, while the remaining switches S4, S7, S8, and S9 are open. In intermediate state I1, input node 202 is coupled to output node 204 via three paths, comprising the first path (with switch S1, the first flying capacitor C1, and switch S3) and two parallel magnetization paths defined by switches S1, S2, L and S5, S6, L, respectively.

[0043] Fig. Figure 4B shows a diagram of the DC-DC converter of Fig. 2, which operates in a different intermediate magnetization state, designated as state I2. Switches S1, S2, S5, S6, and S7 are closed, while the remaining switches S3, S4, S8, and S9 are open. In intermediate state I2, input node 202 is coupled to output node 204 via three paths, comprising the third path (with switch S5, the second flying capacitor C2, and switch S7) and the two magnetization paths defined by switches S1, S2, L and S5, S6, L, respectively.

[0044] Fig. Figure 5A shows a diagram of the DC-DC converter from Fig. 2, which operates in an intermediate demagnetization state, designated as state I3. Switches S1, S3, and S9 are closed, while the remaining switches S2, S4, S5, S6, S7, and S8 are open. In intermediate state I3, input node 202 is coupled to output node 204 via the fifth path (with switch S1, the first flying capacitor C1, and switch S3) and a sixth path, also called the demagnetization path. The demagnetization path is defined by demagnetization switch S9 and inductor L.

[0045] Fig. Figure 5B shows a diagram of the DC-DC converter from Fig. 2, which operates in a different intermediate demagnetization state, designated as state I4. Switches S5, S7, and S9 are closed, while the remaining switches S1, S2, S3, S4, S6, and S8 are open. In intermediate state I4, input node 202 is coupled to output node 204 via the third path (using switch S5, the second flying capacitor C2, and switch S7) and the sixth path, defined by demagnetization switch S9 and inductor L.

[0046] Fig. Figure 6 shows a control sequence for operating the DC-DC converter of Fig. 2 with a conversion ratio VinVout=2. In this example, driver 220 controls DC-DC converter 200 with state A (waveform 610) between times t0 and t1 for a duration TA, then with state B (waveform 620) between times t1 and t2 for a duration TB. This sequence is then repeated over time to provide the required output power. With a conversion ratio VinVout=2 TA = TB = T / 2 and the driver operates the DC-DC converter in V 50% of the time. out The DC-DC converter operates in state A for 50% of the time and in state B for 50% of the time. Consequently, 50% of the current supplied at the output of the DC-DC converter does not flow through inductor L. This reduces inductor losses by 75% compared to a conventional DC-DC converter. It is evident that a delay, also known as dead time, can be introduced at times t1 and t2.

[0047] Fig. Figure 7 shows a different control sequence for operating the DC-DC converter of Fig. 2. In this example, the driver controls the DC-DC converter with state A (waveform 710) between times t0 and t1 for a duration TA, with intermediate state I (waveform 730) between times t1 and t2 for a duration TI, with state B (waveform 720) between times t2 and t3 for a duration TB, and then with intermediate state I between times t3 and t4. This sequence is then repeated over time to provide the required output power. It is evident that a dead time can be introduced at times t1, t2, t3, and t4.

[0048] The driver 220 can select the intermediate state I from the intermediate magnetization states I1 and I2 or the demagnetization states I3 and I4. For example, for a conversion ratio VinVout>2, This leads to lower output voltages, and the DC-DC converter can be operated in the intermediate state I3 or I4 for a predetermined period. The values ​​of TA, TB, and TI can be adjusted to achieve a desired conversion ratio. For example, TA = TB can be set to 40% of the drive period T, and TI can be set to 10% of T, so that TA + TB + 2TI = T.

[0049] It is obvious that the driver can select different intermediate states within the same sequence. For example, for a conversion ratio VinVout<2 A possible sequence would start with state A, followed by state I1, then state B, and end with state I2.

[0050] The DC-DC converter 200 offers improved efficiency along with reduced footprint and height compared to conventional three-stage DC-DC topologies. As described above, converter states A, B, I1, I2, I3, and I4 implement a capacitive connection between the input and output terminals, either via the first path, which includes flying capacitor C1, or via the third path, which includes flying capacitor C2. As a result, current is present at the input terminal during all switching states. This reduces input ripple noise and improves transient response by readily providing output current during sudden load increases.

[0051] The flying capacitors C1 and C2 connect the input power source and the input capacitor C in parallel with the output capacitor C out The effective capacitance provided by the capacitors C inin series with C1 and in parallel with capacitor C out The capacity provided is greater than capacity C out As a result, the DC-DC converter exhibits reduced output voltage ripple. A smaller output capacitor can also be used compared to existing converter topologies.

[0052] During an increase in the load current, the equivalent series resistance (ESR) of the output capacitance of C leads to out This results in an immediate voltage drop. This voltage drop is more significant if the converter output current is higher than the average load current for a given period. During this period, the output capacitor C charges. outTypically, the inductor must switch its operation to discharge to provide a suddenly increased load current until the current through the inductor rises to the changed load current. The output voltage drop is proportional to a delta current, defined as the discharge current minus the charge current. A product of the output voltage drop and the equivalent series resistance of the capacitor is applied to the DC-DC converter. The first and second paths through the flying capacitors C1 and C2, respectively, are in a continuous state of charge, and the additional load current increases their level. As a result, the current through the flying capacitor does not change direction, leading to a reduced output voltage drop. The topology of the DC-DC converter is shown below. Fig. 2 can be modified to reduce the rated voltage of switch S9.

[0053] Fig. Figure 8 shows another DC-DC converter 800 for implementing the method of Fig. 1. The 800 converter is similar to the one with reference to Fig. The converter 200 described in section 2 has been modified with the addition or modification of certain circuit components. The same reference symbols were used to represent the corresponding components, and their descriptions are omitted for brevity.

[0054] In this embodiment, switch S9 has a first terminal coupled to inductor L at node 214 and a second terminal coupled to floating capacitor C1 at node 208. Alternatively, or in combination, another switch S10 can be provided. Switch S10 has a first terminal coupled to inductor L at node 214 and a second terminal coupled to floating capacitor C2 at node 212.

[0055] In operation, the inductor L can be demagnetized either via switches S9 and S4, or via switches S10 and S8, or via both pairs of switches. The optional switch S10 allows switch S8 to be conducted in parallel with S4 during the inductor's demagnetization process. This improves the converter efficiency for output voltages below V. in / 2. Switches S9 and S10 can also be used with a reduced rated voltage of V out instead of V in be implemented.

[0056] For a conversion ratio VinVout≥2 The converter can be implemented without switches S9 and S10, thereby improving the efficiency of the converter and reducing its cost.

[0057] Fig. Figure 9 shows another DC-DC converter 900 for implementing the method of Fig. 1. The converter 900 is similar to the one with regard to Fig. The converter 200 described in Figure 2 has been modified with the addition or addition of certain parts of the circuit. The same reference numerals have been used to represent corresponding components, and their descriptions are not repeated for brevity. In this embodiment, the inductor L has a first terminal coupled to switch S3 at node 914 and a second terminal coupled to output node 204. The inductor is coupled to the input via switch S9' at node 914.

[0058] A nested switching configuration is provided as follows. In state A, input node 202 is coupled to output node 204 via a first path comprising S1, C1, S3, and L. Ground is coupled to output node 204 via a second path comprising S8, C2, and S6. In state B, input node 202 is coupled to output node 204 via a third path comprising S5, C2, S7, and L. Ground is coupled to output node 204 via a fourth path comprising S4, C1, and S2. Intermediate states can be provided to magnetize or demagnetize the inductor. Inductor L can be magnetized via S9' and demagnetized via S3 and S4 or S7 and S8.

[0059] The voltage across the inline capacitors C1 and C2 is approximately V out and for a conversion ratio VinVout=2 The voltage across inductor L is zero. Therefore, V outThe rated voltage of the low-side switches S3, S4, S7, and S8 can be reduced. This topology also reduces the switching noise to VS. in via the series connection of the inductor L. With a conversion ratio VinVout≥2 The converter can be implemented without the switches S9', which further increases the efficiency of the converter and reduces its cost.

[0060] Fig. Figure 10 is a diagram of a modified version of the DC-DC converter from Fig. 9. In this embodiment, switch S9' has a first terminal coupled to C1 at node 206 and a second terminal coupled to inductor L at node 1014. Alternatively, or in combination, an additional switch S10' may be provided. Switch S10 has a first terminal coupled to C2 at node 210 and a second terminal coupled to inductor L at node 1014. Inductor L can be magnetized via switches S1 and S9', or via switches S5 and S10', or via both pairs of switches. Switches S9' and S10' can be implemented with a rated voltage lower than Vin. For a conversion ratio VinVout=2 The converter can be implemented without switches S9' and S10', thereby increasing the efficiency of the converter and reducing its cost.

[0061] Fig. Figure 11 is a diagram of a DC-DC converter implemented with only eight switches. The DC-DC converter 1100 comprises two flying capacitors C1 and C2 and an inductor L, coupled via a network of eight switches S1, S2, S3, S4, S5, S6, S7, and S8 between an input node 1102 and an output node 1104. An input capacitor Cin is provided between the input node 1102 and ground, and an output capacitor Cout is provided between the output node 1104 and ground.

[0062] The first flying capacitor C1 is coupled to input node 1102 via switch S1 and to ground via switch S4. Similarly, the second flying capacitor C2 is coupled to input node 1102 via switch S5 and to ground via switch S8. The first flying capacitor C1 has a first terminal coupled to node 1106 and a second terminal coupled to node 1108. The second flying capacitor C2 has a first terminal coupled to node 1110 and a second terminal coupled to node 1112. The second flying capacitor C2 is also coupled to output node 1104 via switch S7. The inductor L has a first terminal connected to node 1114 and a second terminal connected to output node 1104.The first connection at node 1114 is coupled to node 1106 via switch S2, to node 1110 via switch S6, and to node 1108 via switch S3. A driver (not shown) is provided to generate a variety of control signals for actuating switches S1-S8.

[0063] In operation, the driver operates the converter 1100 using a sequence of states comprising a first state and a second state. In the first state, switches S2, S4, S5, and S7 are closed, while the remaining switches S1, S3, S6, and S8 are open. The input node 1102 is coupled to the output node 1104 via a path comprising S5, C2, and S7. Ground is coupled to the output node 1104 via another path comprising S4, C1, S2, and L. In the second state, switches S1, S3, S6, and S8 are closed, while the remaining switches S2, S4, S5, and S7 are open. The input node 1102 is coupled to the output node 1104 via a path comprising S1, C1, S3, and L. The mass is coupled to the output node 1104 via another path that includes S8, C2, S6, and L. The second state can last longer than the first state.For example, the duration of the second state can be twice as long as the duration of the first state.

[0064] The topology of the converter of Fig. Circuit 11 is described as having an asymmetric topology because the voltage across C1 can differ from the voltage across C2. The voltage across C2 is V in - V out , while the voltage across C1 has different values ​​between 0 and V in can assume. An input current with relatively small fluctuations can be achieved if C1 is set to approximately V out is being charged. In this case, the small amplitude fluctuations of the input current can be due to the switching dead time and the demagnetization of the inductor.

[0065] For the sake of completeness, it should be noted that the converter from Fig. 11 can be operated using an alternative sequence, with the voltage across C1 V in - V outIn a first state, switches S1, S3, S5, and S7 are closed, while the remaining switches S2, S4, S6, and S8 are open. Input node 1102 is coupled to output node 1104 via a first path comprising S1, C1, S3, and L. The input is also coupled to output node 1104 via a second path comprising S5, C2, and S7. Each flying capacitor is therefore charged individually via the first path and the second path, respectively. In a second state, switches S1 and S5 are open to discharge capacitors C1 and C2 and provide the output current. For example, the duration of the second state can be twice as long as the duration of the first state.

[0066] Fig. Figure 12 shows another asymmetric DC-DC converter. In this embodiment, switch S2 has a first terminal coupled to node 1206 with C1, and a second terminal coupled to output node 1204. Switch S6 has a first terminal coupled to node 1210 with C2, and a second terminal coupled to the output via inductor L. The voltage across C1 is V out , while the voltage across C2 has different values ​​between 0 and V in can assume.

[0067] In operation, the driver operates the converter 1200 using a sequence of states comprising a first state and a second state. In the first state, switches S2, S4, S5, and S7 are closed, while the remaining switches S1, S3, S6, and S8 are open. The input node 1202 is coupled to the output node 1204 via a path comprising S5, C2, S7, and L. Ground is coupled to the output node 1204 via another path comprising S4, C1, and S2. In the second state, switches S1, S3, S6, and S8 are closed, while the remaining switches S2, S4, S5, and S7 are open. The input node 1202 is coupled to the output node 1204 via a path comprising S1, C1, S3, and L. The mass is coupled to the output node 1204 via another path that includes S8, C2, S6, and L. The second state can last longer than the first state.For example, the duration of the second state can be twice as long as the duration of the first state. In the exemplary embodiment of the... Fig. 11 and Fig. 12 is the maximum proportion of the output current that bypasses the inductor, 25%.

[0068] For the sake of completeness, it should be noted that the converter from Fig. 12 can be operated using an alternative sequence in which the switching is non-nested and the voltage across C2 V outIn a first state, switches S1, S3, S5, and S7 are closed, while the remaining switches S2, S4, S6, and S8 are open. Input node 1202 is coupled to output node 1204 via a first path comprising S1, C1, S3, and L. The input is also coupled to output node 1204 via a second path comprising S5, C2, S7, and L. Each flying capacitor is therefore charged individually via the first path and the second path, respectively. In a second state, switches S2, S4, S6, and S8 are closed, while the remaining switches S1, S3, S5, and S7 are open. The ground node is coupled to output node 1204 via a third path comprising S4, C1, and S2.

[0069] The mass is also coupled to output node 1204 via a fourth path comprising S8, C2, S6, and L. For example, the duration of the first state can be twice as long as the duration of the second state.

[0070] The in relation to the Fig. The DC-DC converters described in sections 2 to 12 were described as step-down converters, also known as buck converters. It is obvious that the DC-DC converters of the Fig. Two to twelve converters can be operated in reverse as boost converters (that is, the input is used as the output and the output as the input) to achieve step-up conversion. Alternatively, step-up conversion can be achieved by modifying the switching sequence.

[0071] Fig. Figure 13 shows a sequence of states for operating the DC-DC converter of Fig. 2 as a step-up converter. Fig. Figure 13A shows the states of the switches in a first step-up conversion state. Switches S1, S2, S4, S5, S6, and S8 are closed, while the remaining switches S3, S7, and S9 are open. The input node 202 is coupled to the output node 204 via two inductor paths, one comprising switches S1, S2, L and the other S5, S6, L, thus demagnetizing the inductor. The input is coupled to ground via a path comprising S1, C1, and S4, and another path comprising S5, C2, and S8, thus connecting the first and second capacitors C1 and C2 to V. in will be loaded. Fig.Figure 13B shows the switch states in a second step-up conversion state. Switches S2, S3, S6, and S7 are closed, while the remaining switches S1, S4, S5, and S8 are open. In this state, capacitors C1 and C2 transfer their energy to inductor L, magnetizing the inductor. Under low-load conditions, a step-up conversion can be achieved using a single path, for example, by switching only capacitor C1 by closing S1, S2, and S4 or S2 and S3. Using a single phase further reduces switching losses.

[0072] It is obvious to those skilled in the art that variations of the disclosed arrangements are possible without deviating from the disclosure. For example, the flying capacitors can be implemented as single or multiple capacitors connected in series and / or parallel. Alternatively, a capacitor network can be used. Such a capacitor network can change its configuration during operation of the converter. Accordingly, the above description of the specific embodiment is only exemplary and not intended to limit the scope of the design. It is obvious to those skilled in the art that minor modifications can be made without substantially altering the described operation.

Claims

[1] Power converter (200, 800) for providing an output voltage with a set conversion ratio, wherein the power converter has a ground port, a first port (202) and a second port (204), wherein, when the power converter operates as a buck converter, the first port (202) receives an input voltage and the second port (204) provides the output voltage, and, when the power converter operates as a boost converter, the second port (204) receives an input voltage and the first port (202) provides the output voltage; wherein the power converter further comprises: a single inductor with a first terminal and a second terminal, wherein the second terminal is coupled to the second port (204); a first flying capacitor that is selectively coupled to the inductor; a second flying capacitor that is selectively coupled to the inductor; a network of switches; and a driver (220) configured to control the network of switches with a sequence of states during a control period, wherein the sequence of states has a first state and a second state, wherein in the first state one of the first port (202) and the ground port is coupled to the second port (204) via a first path which includes the first flying capacitor and bypasses the inductor, and wherein the remaining port consisting of the first port (202) and the ground port is coupled to the second port (204) via a second path which includes the second flying capacitor and the inductor, such that when one flying capacitor consisting of the first and the second flying capacitor receives a current from the first port (202), the other flying capacitor receives a current from the ground port, wherein in the second state one of the first port (202) and the ground port is coupled to the second port (204) via a third path which includes the second flying capacitor and bypasses the inductor, and wherein the remaining port consisting of the first port and the ground port is coupled to the second port (204) via a fourth path which includes the first flying capacitor and the inductor; wherein each of the first flying capacitor and the second flying capacitor has a first terminal selectively coupled to the first port (202) and a second terminal selectively coupled to the ground port; wherein the network of switches comprises: a first capacitor switch to couple the first terminal of the first flying capacitor to the first terminal of the inductor; a second capacitor switch to couple the first terminal of the second flying capacitor to the first terminal of the inductor; a third capacitor switch to couple the second terminal of the first flying capacitor to the second terminal of the inductor; and a fourth capacitor switch to couple the second terminal of the second flying capacitor to the second terminal of the inductor. [2] The power converter according to claim 1, wherein the sequence has an intermediate state, wherein the driver (220) is configured to select the intermediate state from a plurality of intermediate states based on the desired conversion ratio. [3] The power converter according to claim 2, wherein the intermediate state between the first state and the second state is provided. [4] The power converter according to claim 2, wherein in the intermediate state the first port (202) is coupled to the second port (204) via at least one of the first path and the third path and wherein the first port is additionally coupled to the second port via a fifth path comprising the inductor, wherein, when the power converter operates as a buck converter, the intermediate state is a magnetization state and, when the power converter operates as a boost converter, the intermediate state is a demagnetization state. [5] The power converter according to claim 2, wherein in the intermediate state the first port (202) is coupled to the second port (204) via at least one of the first path and the third path and wherein the ground port is coupled to the second port via a sixth path comprising the inductor, wherein, when the power converter operates as a buck converter, the intermediate state is a demagnetization state and, when the power converter operates as a boost converter, the intermediate state is a magnetization state. [6] The power converter according to one of the preceding claims, wherein the driver (220) is configured to maintain the first state and the second state for a predetermined duration during the control period. [7] The power converter according to claim 2, wherein the driver (220) is configured to change the duration of the intermediate state based on the target conversion ratio. [8] The power converter according to one of the preceding claims, wherein in the second state the first port (202) is coupled to the second port (204) via a seventh path comprising the second flying capacitor and the inductor, and the ground port is coupled to the second port via an eighth path comprising the first flying capacitor and the inductor. [9] The power converter according to any of the preceding claims, wherein the network of switches comprises: a first switch to couple the first flying capacitor to the first port (202); a second switch to couple the second flying capacitor to the first port (202); a first ground switch to couple the first flying capacitor to the ground port; a second ground switch to couple the second flying capacitor to the ground port; wherein the inductor has a first terminal and a second terminal, the second terminal being coupled to the second port (204). [10] The power converter according to one of the preceding claims, comprising a first additional switch provided between the first terminal of the inductor and the ground port or between the first terminal of the inductor and the first ground switch. [11] The power converter according to claim 10, comprising a second additional switch provided between the first terminal of the inductor and the second ground switch. [12] Method for converting power with a target conversion ratio, wherein the method comprises: Providing a power converter (200, 800) with a ground port, a first port (202) and a second port (204), wherein, when the power converter operates as a buck converter, the first port (202) receives an input voltage and the second port provides an output voltage, and, when the power converter operates as a boost converter, the second port (204) receives an input voltage and the first port provides an output voltage; wherein the power converter further comprises a single inductor with a first terminal and a second terminal, the second terminal being coupled to the second port (204); a first flying capacitor selectively coupled to the inductor; a second flying capacitor selectively coupled to the inductor; and a network of switches; and Controlling the network of switches with a sequence of states during a control period, wherein the sequence of states has a first state and a second state; wherein in the first state one of the first port (202) and the ground port is coupled to the second port (204) via a first path which includes the first flying capacitor and bypasses the inductor, and wherein the remaining port consisting of the first port (202) and the ground port is coupled to the second port (204) via a second path which includes the second flying capacitor and the inductor, such that when one flying capacitor consisting of the first and the second flying capacitor receives a current from the first port (202), the other flying capacitor receives a current from the ground port, wherein in the second state one of the first port (202) and the ground port is coupled to the second port (204) via a third path which includes the second flying capacitor and bypasses the inductor, and wherein the remaining port consisting of the first port (202) and the ground port is coupled to the second port (204) via a fourth path which includes the first flying capacitor and the inductor; wherein each of the first flying capacitor and the second flying capacitor has a first terminal selectively coupled to the first port (202) and a second terminal selectively coupled to the ground port; wherein the network of switches comprises: a first capacitor switch to couple the first terminal of the first flying capacitor to the first terminal of the inductor; a second capacitor switch to couple the first terminal of the second flying capacitor to the first terminal of the inductor; a third capacitor switch to couple the second terminal of the first flying capacitor to the second terminal of the inductor; and a fourth capacitor switch to couple the second terminal of the second flying capacitor to the second terminal of the inductor.

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