Light detection device, optical device and method for its manufacture

Abstract

Light detection device, comprising: an insulating layer (21); a silicon layer (22) over the insulating layer (21); a light detection layer (23) above the silicon layer (22) and extending within at least one section of the silicon layer (22); N first doped regions (22n, 22p) of a first dopant type within the light detection layer (23); and M second doped regions (22n, 22p) of a second dopant type within the light detection layer (23), wherein the first doped regions (22n, 22p) and the second doped regions (22n, 22p) are arranged alternately along a first direction and are arranged perpendicular to the first direction across the light detection layer (23) along a second direction; and where M and N are integers greater than or equal to 2.

Description

BACKGROUND

[0001] Optical signals can be used in a variety of applications, including high-speed and secure data transmission between two or more devices. Photodiodes are used to convert received photons into electrical currents. The performance of a photodiode is typically evaluated based on several parameters, such as quantum efficiency, operating wavelength, sensitivity, and the like. It is desirable to improve the performance of a photodiode.

[0002] Publication US 2014 / 0 246 571 A1 discloses a photodetector that detects signals in a detection region of a waveguide. A detector layer is arranged above the waveguide, in which a PIN diode is defined by doped regions and is optically coupled to the waveguide. The doped regions are connected to metal contacts at periodic intervals, thus minimizing metal absorption losses. A reflector on the waveguide increases signal absorption in the detection region.

[0003] Publication US 2018 / 0 358 342 A1 discloses integrated photodetectors with an absorbing Ge section arranged over p- and n-doped silicon sections to implement PIN diodes. To increase the bandwidth, the Ge section is partially p-doped in one corner to provide vertical diode sections. A light signal can be injected asymmetrically into the structure, and the structure can be periodically mirrored along the light propagation direction, increasing the light intensity near the p-doped corner. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practices, various features are not drawn to scale. Indeed, the dimensions of various features may be exaggerated or reduced as desired for clarity. Fig. 1A illustrates a top view of a light detection device according to some embodiments of the present disclosure. Fig. Figure 1B illustrates a cross-sectional view of the light detection device as shown in Fig. 1A, according to some embodiments of the present disclosure. Fig. Figure 1C illustrates a cross-sectional view of the light detection device as shown in Fig. 1A, according to some embodiments of the present disclosure. Fig. Figure 1D illustrates a cross-sectional view of the light detection device as shown in Fig. 1A, according to some embodiments of the present disclosure. Fig. 2A illustrates a top view of a light detection device according to some embodiments of the present disclosure. Fig. Figure 2B illustrates a cross-sectional view of the light detection device as shown in Fig. 2A, according to some embodiments of the present disclosure. Fig. Figure 2C illustrates a cross-sectional view of the light detection device as shown in Fig. 2A, according to some embodiments of the present disclosure. Fig. 3A illustrates a top view of a light detection device according to some embodiments of the present disclosure. Fig. Figure 3B illustrates a cross-sectional view of the light detection device as shown in Fig. 3A, according to some embodiments of the present disclosure. Fig. Figure 3C illustrates a cross-sectional view of the light detection device as shown in Fig. 3A, according to some embodiments of the present disclosure. Fig. 4A illustrates a top view of a light detection device according to some embodiments of the present disclosure. Fig. 4B illustrates a schematic diagram of a power generation circuit according to some embodiments of the present disclosure. Fig. 5A-5D are a series of cross-sectional views illustrating processing steps for fabricating a light detection device, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] An improved photodiode with increased AC bandwidth is provided by devices and a method of manufacture according to claims 1, 9 and 14. The following disclosure provides many different embodiments or examples of implementing different features of the presented subject matter. Specific examples of the components and arrangements are described below to simplify the present disclosure. The formation of a first feature over or on top of a second feature in the following description may, for example, include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact.Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not, in and of itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "deeper," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0007] The making and using of the embodiments are discussed in detail below. However, it should be appreciated that the present invention provides many applicable inventive concepts that may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0008] Fig. 1A illustrates a top view of a light detection device 2 according to some embodiments of the present disclosure. Fig. Figure 1B illustrates a cross-sectional view of the light detection device, along the line B-B', as shown in Fig. 1A, according to some embodiments of the present disclosure. Fig. Fig. 1C illustrates a cross-sectional view of the light detection device 2 along the line C-C' as shown in Fig. 1A, according to some embodiments of the present disclosure. Fig. Fig. 1D illustrates a cross-sectional view of the light detection device 2 along the line D-D' as shown in Fig. 1A, according to some embodiments of the present disclosure. In some embodiments, the light detection device 2 is a photodiode or a photodetector. The light detection device 2 may include a substrate 20, an insulating layer 21, a silicon layer 22, and a light detection layer 23.

[0009] The substrate 20 contains a semiconductor material, such as silicon. In some embodiments, the substrate 20 may contain other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. Alternatively, the substrate 20 contains another elemental semiconductor, such as germanium; a composite semiconductor including gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or combinations thereof. In yet another embodiment, the substrate 20 is an SOI. In other alternatives, the substrate 20 may contain a doped epitaxial layer, a graded semiconductor layer, and / or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on top of a silicon germanium layer.

[0010] The insulation layer 21 is arranged on the substrate 20. The insulation layer 21 can be STI or LOCOS. In some embodiments, the insulation layer 21 can contain an oxide (e.g., silicon oxide or Ge oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., GaP oxynitride), SiO2, a nitrogen-containing oxide (e.g., nitrogen-containing SiO2), a nitrogen-doped oxide (e.g., N2-implanted SiO2), Si x O y N z , a polymer material, or the like. In some embodiments, the insulating layer 21 may also be referred to as a buried oxide or a BOX layer.

[0011] The silicon layer 22 is arranged on the insulation layer 21. As in Fig. 1A and Fig. As shown in Figure 1D, the silicon layer 22 may include a plurality of n-doped regions 22n1, 22n2, 22n3, 22n4 and p-doped regions 22p1, 22p2, 22p3, 22p4. The n-doped regions 22n1, 22n2, 22n3, 22n4 and the p-doped regions 22p1, 22p2, 22p3, 22p4 are arranged alternately. In other words, there is an n-doped region between two adjacent p-doped regions, or there is a p-doped region between two adjacent n-doped regions. For example, the n-doped region 22n1 may be arranged between two adjacent p-doped regions 22p1 and 22p2. The p-doped region 22p2 may be arranged between two adjacent n-doped regions 22n1 and 22n2. In some embodiments, there may be any number of n-doped regions and p-doped regions depending on various design specifications.For example, there may be N n-doped regions and N p-doped regions, where N is an integer greater than 1. The doping concentration amounts for the n-doped regions 22n1, 22n2, 22n3, 22n4 and the p-doped regions 22p1, 22p2, 22p3, 22p4 may vary with the process used and the particular design. In some embodiments, doping concentrations of a p-type material or an n-type material may be in a range of approximately 10 17 atoms / cm 3 up to 10 19 atoms / cm 3 lay.

[0012] The light-sensing layer 23 is disposed over the silicon layer 22 and diffuses within at least a portion of the silicon layer 22. In some embodiments, the light-sensing layer 23 may be formed of or include silicon, germanium, indium, gallium arsenide, lead sulfide, mercury cadmium telluride, or any other suitable materials.

[0013] In some embodiments, the p-doped region 22p1 may be formed as shown in Fig. 1B, diffuse or extend within the light detection layer 23. The p-doped region 22p1 may, for example, include a first portion disposed within a portion of the silicon layer 22 adjacent to a side surface 231 of the light detection layer 23, and a second portion disposed within the light detection layer 23. In some embodiments, a thickness of the p-doped region 22p1 within the light detection layer 23 (e.g., the second portion of the p-doped region 22p1) is less than or equal to a thickness of the light detection layer 23. In some embodiments, the thickness of the p-doped region 22p1 within the light detection layer 23 is greater than a thickness of the p-doped region 22p1 within the silicon layer 22 (e.g., the first portion of the p-doped region 22p1).In some embodiments, the p-doped region 22p1 may diffuse from the side surface 231 of the light detection layer 23 to an opposite side surface 232. A width of the p-doped region 22p1 within the light detection layer 23 may be substantially equal to a width of the light detection layer 23.

[0014] In other embodiments, the p-doped region 22p1 diffuses as in Fig. 2A and Fig. 2B, which respectively illustrate a top view and a cross-sectional view of a light detection device 3 according to some embodiments of the present disclosure, not to the side surface 232 of the light detection layer 23. The width of the p-doped region 22p1 within the light detection layer 23 may, for example, be smaller than the width of the light detection layer 23. For example, there may be a distance between the side surface 232 of the light detection layer 23 and the p-doped region 22p1.

[0015] In other embodiments, the p-doped region 22p1 diffuses as in Fig. 3A and Fig. 3B, which respectively illustrate a top view and a cross-sectional view of a light detection device 4 according to some embodiments of the present disclosure, further from the side surface 232 of the light detection layer 23 and diffuses within a portion of the silicon layer 22 adjacent to the side surface 232 of the light detection layer 23. The p-doped region 22p1 may, for example, include a first portion disposed within a portion of the silicon layer 22 adjacent to the side surface 231 of the light detection layer 23, a second portion disposed within the light detection layer 23, and a third portion disposed within a portion of the silicon layer 22 adjacent to the side surface 232 of the light detection layer 23.

[0016] With reference to Fig. 1C, the n-doped region 22n1 can diffuse or extend within the light detection layer 23. In some embodiments, a thickness of the n-doped region 22n1 within the light detection layer 23 is less than or equal to the thickness of the light detection layer 23. In some embodiments, the thickness of the n-doped region 22n1 within the light detection layer 23 is greater than a thickness of the n-doped region 22n1 within the silicon layer 22. In some embodiments, the n-doped region 22n1 can diffuse from the side surface 232 of the light detection layer 23 to the side surface 231. A width of the n-doped region 22n1 within the light detection layer 23 can, for example, be substantially equal to a width of the light detection layer 23.

[0017] In other embodiments, the n-doped region 22n1 diffuses as in Fig. 2A and Fig. 2C, which respectively illustrate a top view and a cross-sectional view of the light detection device 3 according to some embodiments of the present disclosure, not to the side surface 231 of the light detection layer 23. The width of the n-doped region 22n1 within the light detection layer 23 may, for example, be smaller than the width of the light detection layer 23. For example, there may be a distance between the side surface 231 of the light detection layer 23 and the n-doped region 22n1.

[0018] In other embodiments, the p-doped region 22n1 diffuses as in Fig. 3A and Fig. 3C, which respectively illustrate a top view and a cross-sectional view of a light detection device 4 according to some embodiments of the present disclosure, further from the side surface 231 of the light detection layer 23 and diffuses within a portion of the silicon layer 22 adjacent to the side surface 231 of the light detection layer 23.

[0019] With reference to Fig. 1D, the light-sensing layer 23 is disposed on the silicon layer 22. A portion of the light-sensing layer 23 is located within the silicon layer 22. For example, the silicon layer 22 may include an opening or trench, and the light-sensing layer 23 may be disposed within the opening or trench. The light-sensing layer 23 may protrude from a top surface of the silicon layer 22. In some embodiments, a portion of the silicon layer 22 is disposed between the light-sensing layer 23 and the insulation layer 21.

[0020] As in Fig. As shown in Figure 1A, the silicon layer 22 may include or define a waveguide structure 22w. The waveguide structure 22w may extend in a first direction (e.g., axial direction) substantially parallel to the length of the light-detection layer. The waveguide structure 22w may serve as a channel for guiding light (or photons) into the light-detection layer 23 in the first direction. The p-doped regions 22p1, 22p2, 22p3, 22p4 and the n-doped regions 22n1, 22n2, 22n3, 22n4 are arranged alternately in a direction substantially perpendicular to the first direction.

[0021] In operation, the p-doped regions 22p1, 22p2, 22p3, 22p4 are electrically coupled to cathode nodes V21, V23, V25, V27, respectively, and the n-doped regions 22n1, 22n2, 22n3, 22n4 are electrically coupled to anode nodes V22, V24, V26, V28, respectively. When the light-detecting device 2 is biased with an appropriate voltage across the cathode nodes V21, V23, V25, V27 and the anode nodes V22, V24, V26, V28, incident photons trigger the generation of lone electron-hole pairs in the light-detecting layer 23. The holes move towards the anode nodes V22, V24, V26, V28 and electrons move towards the cathode nodes V21, V23, V25, V27 and a photocurrent (or sensing current) is produced.

[0022] As in Fig. As shown in Figure 1A, the light detection layer 23 can be divided into a plurality of regions. The light detection layer 23 may include, for example, the region defined by the p-doped region 22p1 and the n-doped region 22n1, the region defined by the n-doped region 22n1 and the p-doped region 22p2, the region defined by the p-doped region 22p2 and the n-doped region 22n2, the region defined by the n-doped region 22n2 and the p-doped region 22p3, the region defined by the p-doped region 22p3 and the n-doped region 22n3, the region defined by the n-doped region 22n3 and the p-doped region 22p4, the region defined by the p-doped region 22p4 and the n-doped region 22n4.

[0023] As light passes through the p-doped region 22p1 and enters the region defined by the light-sensing layer 23, the p-doped region 22p1, and the n-doped region 22n1, incident photons trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-doped region 22p1, and the n-doped region 22n1. The holes move toward the anode node V22, and electrons move toward the cathode node V21, producing a photocurrent (or sensing current).Similarly, when incident photons pass through the p-type region 22p1, the n-type region 22n1, and the p-type region 22p2 and enter the region defined by the light-sensing layer 23, the p-type region 22p2, and the n-type region 22n2, they trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-type region 22p2, and the n-type region 22n2. The holes move toward the anode node V24, and electrons move toward the cathode node V23, producing a photocurrent (or sensing current).Similarly, when incident photons pass through the p-type region 22p1, the n-type region 22n1, the p-type region 22p2, the n-type region 22n2, and the p-type region 22p3 and enter the region defined by the light-sensing layer 23, the p-type region 22p3, and the n-type region 22n3, they trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-type region 22p3, and the n-type region 22n3. The holes move toward the anode node V26, and electrons move toward the cathode node V25, producing a photocurrent (or sensing current).Similarly, when incident photons pass through the p-type region 22p1, the n-type region 22n1, the p-type region 22p2, the n-type region 22n2, the p-type region 22p3, the n-type region 22n3, and the p-type region 22p4 and enter the region defined by the light-sensing layer 23, the p-type region 22p4, and the n-type region 22n4, they trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-type region 22p4, and the n-type region 22n4. The holes move toward the anode node V28, and electrons move toward the cathode node V27, producing a photocurrent (or sensing current).

[0024] In some embodiments, a light detection device may include an n-doped region and a p-doped region located at two opposite ends of a light detection layer of the light detection device, and thus the distance between the n-doped region and the p-doped region is limited by the width of the light detection layer, and the photocurrent generation rate is also limited by the width of the light detection layer. According to the Fig. 1A, Fig. 2A and Fig. 3A, the distance between two adjacent doped regions would not be limited by the width W21 of the light detection layer 23, since the p-doped regions 22p1, 22p2, 22p3, 22p4 and the n-doped regions 22n1, 22n2, 22n3, 22n4 are arranged completely or partially across the light detection layer 23. In some embodiments, a distance between a p-doped region and its adjacent n-doped region (e.g., the p-doped region 22p1 and the n-doped region 22n1) is in a range of about a few nanometers (nm) to about 500 nm, which is less than the width W21 (e.g., 0.5 µm to 10 µm) of the light-detecting layer 23. Therefore, the light-detecting device 2, 3, or 4 has a higher photocurrent generation rate. An AC bandwidth of the photocurrent generated by the light-detecting device 2, 3, or 4 is greater than 10 GHz and can reach approximately several hundred GHz.In some embodiments, the AC bandwidth of the photocurrent when the distance between two adjacent doped regions (e.g., the p-doped region 22p1 and the n-doped region 22n1) is 100 nm is about 100 GHz.

[0025] Furthermore, if a length of the n-doped region and the p-doped region is substantially equal to the length of the light-detecting layer (e.g., from about 1 µm to about 100 µm), the conductive electrodes connected to the n-doped region and the p-doped region may have a relatively high parasitic capacitance, which would further reduce the AC bandwidth of the light-detecting device. Fig. 1A, Fig. 2A and Fig. 2A, the problem of parasitic capacitance of the conductive electrodes connected to the n-doped regions 22n1, 22n2, 22n3, 22n4 and the p-doped regions 22p1, 22p2, 22p3, 22p4 can be mitigated if the length of the n-doped regions 22n1, 22n2, 22n3, 22n4 and the p-doped regions 22p1, 22p2, 22p3, 22p4 is substantially equal to the width W21 of the light detection layer 13 (e.g., from about 0.5 µm to about 10 µm). In some embodiments, the parasitic capacitance among the conductive electrodes (connected to the n-doped regions 22n1, 22n2, 22n3, 22n4 and the p-doped regions 22p1, 22p2, 22p3, 22p4) and ground may be reduced by N, where N is a sum of the n-doped regions and the p-doped regions.

[0026] Fig. 4A illustrates the light detection device 2 as shown in Fig. 1A, which is connected to a power generation circuit 50, according to some embodiments of the present disclosure. In some embodiments, the light detection device 2 may be replaced by the light detection device 3, as shown in Fig. 2A, the light detection device 4, as shown in Fig. 3A, or any other suitable light detection devices. In some embodiments, current generation circuit 50 may be or include an equalizer. Current generation circuit 50 may include one or more DC bias circuits B51, B52, B53, B54, one or more delay circuits D51, D52, D53, and one or more adding circuits (or adders) A51, A52, A53.

[0027] In some embodiments, as in Fig. 4A, the cathode nodes V21, V23, V25, V27 are connected to ground or a low DC voltage (compared to the DC voltage applied to the anode nodes V22, V24, V26, V28), and the anode nodes V22, V24, V26, V28 are connected to a higher DC voltage (compared to the DC voltage applied to the cathode nodes V21, V23, V25, V27). For example, the anode nodes V22, V24, V26, V28 may be connected to the respective DC bias circuits B51, B52, B53, and B54. In other embodiments, all of the anode nodes V22, V24, V26, V28 may be connected to a single DC bias circuit. In some embodiments, the anode nodes V22, V24, V26, V28 are provided with the same DC voltage. Alternatively, the anode nodes V22, V24, V26, V28 can be provided with different DC voltages.

[0028] In operation, as light passes through the p-doped region 22p1 and enters the region defined by the light-sensing layer 23, the p-doped region 22p1, and the n-doped region 22n1, incident photons trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-doped region 22p1, and the n-doped region 22n1. The holes move toward the anode node V22, and electrons move toward the cathode node V21 to generate a photocurrent (or sensing current) I O1When the light passes through the p-doped region 22p1, the n-doped region 22n1, and the p-doped region 22p2 and enters the region defined by the light-sensing layer 23, the p-doped region 22p2, and the n-doped region 22n2, incident photons trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-doped region 22p2, and the n-doped region 22n2. The holes move toward the anode node V 24 and electrons move towards the cathode node V 23 to generate a photocurrent (or sensing current) I O2As the light passes through the p-doped region 22p1, the n-doped region 22n1, the p-doped region 22p2, the n-doped region 22n2, and the p-doped region 22p3 and enters the region defined by the light-sensing layer 23, the p-doped region 22p3, and the n-doped region 22n3, incident photons trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-doped region 22p3, and the n-doped region 22n3. The holes move toward the anode node V26, and electrons move toward the cathode node V25 to generate a photocurrent (or sensing current) I O3When the light passes through the p-doped region 22p1, the n-doped region 22n1, the p-doped region 22p2, the n-doped region 22n2, the p-doped region 22p3, the n-doped region 22n3, and the p-doped region 22p4 and enters the region defined by the light-sensing layer 23, the p-doped region 22p4, and the n-doped region 22n4, the incident photons trigger the generation of lone electron-hole pairs in the region defined by the light-sensing layer 23, the p-doped region 22p4, and the n-doped region 22n4. The holes move toward the anode node V28, and electrons move toward the cathode node V27 to generate a photocurrent (or sensing current) I O4 to generate.

[0029] In some embodiments, the photocurrent I O2due to the optical propagation delay along the light detection layer 23, a time delay (or a phase difference) relative to the photocurrent I O1 the photocurrent I O3 has a time delay (or a phase difference) relative to the photocurrent I O2 and the photocurrent I O4 has a time delay (or a phase difference) relative to the phase current I O3 Compared to the photocurrent I O1 the photocurrent I O2 have a phase difference φ1, the photocurrent I O3 can be a phase difference of 2φ1 and the photocurrent I O4 can have a phase difference of 3φ1.

[0030] Furthermore, as the light passes through the p-doped region 22p1, the n-doped region 22n1, the p-doped region 22p2, the n-doped region 22n2, the p-doped region 22p3, the n-doped region 22n3, and the p-doped region 22p4, the intensity of the light would decrease as the light travels away from the waveguide structure 22w. In some embodiments, the loss of light intensity within the light-detection layer 23 is less than or equal to about 5 dB / cm. Therefore, the amplitude of the photocurrent I O2 smaller than the amplitude of the photocurrent I O1 , the amplitude of the photocurrent I O3 is smaller than the amplitude of the photocurrent I O2 and the amplitude of the photocurrent I O4 is smaller than the amplitude of the photocurrent I O3 .

[0031] The photocurrent I O1is sent to the delay circuit D51 to generate a delayed current I51. In some embodiments, the delay time of the delay circuit D51 is the delay time between the photocurrent I O2 and the photocurrent I O1 essentially the same. Therefore, the current I51 sent from the delay circuit D51 to the adder A51 has no time delay relative to the photocurrent I O2 (or has the same phase). The adder circuit A51 is configured to add the current I51 and the photocurrent I O2 to combine to generate a current I52.

[0032] The current I52 is sent to the delay circuit D52 to generate a delay current I53. In some embodiments, the delay time of the delay circuit D52 is equal to the delay time between the photocurrent I O3 and the photocurrent I O2essentially the same. Therefore, the current I53 sent from the delay circuit D52 to the adder A52 has no time delay relative to the photocurrent I O3 (or has the same phase). The adder circuit A52 is configured to add the current I53 and the photocurrent I O3 to combine to produce a current I54.

[0033] The current I54 is sent to the delay circuit D53 to generate a delay current I55. In some embodiments, the delay time of the delay circuit D53 is equal to the delay time between the photocurrent I O4 and the photocurrent I O3 essentially the same. Therefore, the current I55 sent from the delay circuit D53 to the adder A53 has no time delay relative to the photocurrent I O4 (or has the same phase). The adder circuit A53 is configured to add the current I54 and the photocurrent I O4to combine to produce a current I56.

[0034] In some embodiments, a light detection device may contain only a single p-doped region and a single n-doped region, wherein the signal width of the photocurrent generated by the light detection device is substantially equal to the pulse width of the light input to the light detection device plus the optical propagation delay along the light detection layer of the light detection device. Therefore, the signal width of the photocurrent generated by the light detection device is further limited by the optical propagation delay along the light detection layer, which would limit the AC bandwidth of the light detection device. According to the Fig. In the embodiments shown in Figure 4A, the light detection device 2 includes many pairs of n-type regions and p-type regions, each pair generating the respective photocurrent, and the photocurrents are sent to the delay circuits D51, D52, D53 and the adder circuit A51, A52, A53 to generate the output current I56. Thus, the problem of optical propagation delay can be mitigated. The signal width of the output current I56 generated by the light detection device 2 is substantially equal to the pulse width of the light input to the light detection device 2 plus the optical propagation delay along the light detection layer 23 divided by N, where N is a sum of the n-type regions and the p-type regions. This would further increase the AC bandwidth of the light detection device 2.

[0035] Fig. Figure 4B illustrates a schematic diagram of a portion of the power generation circuit 50 as shown in Fig. 4A, according to some embodiments of the present disclosure. For simplicity and clarity, some elements or components have been omitted from the drawing. The current generation unit 50 may include a plurality of transistors M510, M511, M520, M521, M530, M531, M540, M541, M550, M551, M560, M561, M570, and M571 connected to or configured to form a plurality of current mirror circuits. The PMOS current mirror circuits may be formed, for example, by the pairs "the transistors M520 and M521," "the transistors M540 and M541," and "the transistors M560 and M561." The NMOS current mirror circuits can be formed, for example, by the pairs “the transistors M510 and M511,” “the transistors M530 and M531,” “the transistors M550 and M551,” and “the transistors M570 and M571.” As shown in Fig. As shown in Figure 4B, each of the adding circuits A51, A52 and A53 may include one or more current mirror circuits.

[0036] In some embodiments, each of the delay circuits D51, D52, and D53 can be reached by a transmission line. In some embodiments, the delay time of each of the delay circuits D51, D52, and D53 can be determined based on the length of the transmission line. The delay time of the transmission line can be expressed, for example, by: τ=L / Vg, where τ represents the delay time of the transmission line, L represents the length of the transmission line, and Vg represents the group velocity of the transmission line.

[0037] In some embodiments, the transistors of each PMOS current mirror circuit may have the same aspect ratio (W / L) or width. For example, the aspect ratio of transistor M520, M540, or M560 is the same as that of transistor M521, M541, or M561, respectively. Therefore, the amplitude of the current flowing through transistor M520, M540, or M560 would be substantially the same as the amplitude of the current flowing through transistor M521, M541, or M561, respectively. The amplitude of the current I O1 ' is essentially the same as the amplitude of the photocurrent I O1 , the amplitude of the current I52' is essentially the same as the amplitude of the current I52 and the amplitude of the current I54' is essentially the same as the amplitude of the current I54. Therefore, the amplitude of the output current I56 is essentially a sum of the amplitudes of the photocurrents I O1 , I O2 , I O3 and I O4even.

[0038] In some embodiments, the transistors of each PMOS current mirror circuit may include different aspect ratios or widths. For example, the aspect ratio of transistor M520, M540, or M560 may be different from that of transistor M521, M541, or M561, respectively. Therefore, the amplitude of the current flowing through transistor M520, M540, or M560 would be different from the amplitude of the current flowing through transistor M521, M541, or M561, respectively. The amplitude of the current I O1 ' differs from the amplitude of the photocurrent I O2 , the amplitude of the current I52' differs from the amplitude of the current I52 and the amplitude of the current I54' differs from the amplitude of the current I54. Therefore, the amplitude of the output current I56 is a ratio multiplied by the sum of the amplitudes of the photocurrents I O1 , I O2 , I O3 and I O4essentially the same, with the ratio corresponding to the aspect ratios of the transistors in each PMOS current mirror circuit. By selecting transistor M521, M541, or M561 with a relatively larger aspect ratio or width than the respective transistor M521, M541, or M561, the amplitude of the output current I56 can be increased. This would increase circuit design flexibility.

[0039] Fig. 5A to 5D are cross-sectional views of the intermediate structures of a method for manufacturing a light detection device according to some embodiments. In some embodiments, the Fig. 5A to 5D can be used to control the light detection device 2 as shown in Fig. 1A, Fig. 1B, Fig. 1C and Fig. 1D. Alternatively, the Fig. 5A to 5D may be used to form any other light detecting devices.

[0040] With reference to Fig. 5A, a substrate 20 is provided or received. The substrate 20 includes a semiconductor material, such as silicon. In some embodiments, the substrate 20 may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. Alternatively, the substrate 20 includes another elemental semiconductor, such as germanium; a composite semiconductor including gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or combinations thereof. In yet another embodiment, the substrate 20 is an SOI. In other alternatives, the substrate 20 may include a doped epitaxial layer, a graded semiconductor layer, and / or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on top of a silicon germanium layer.The substrate 20 may be doped with an n-type dopant such as arsenic, phosphorus, or the like, or it may be doped with a p-type dopant such as boron or the like.

[0041] Then, an insulating layer 21 is formed on the substrate 20. The insulating layer 21 may be STI or local oxidation of silicon LOCOS. The insulating layer 21 may be formed of electrically insulating materials, such as dielectric materials. In some embodiments, the insulating layer 21 is made of an oxide (e.g., silicon oxide or Ge oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., GaP oxynitride), SiO2, a nitrogen-containing oxide (e.g., nitrogen-containing SiO2), a nitrogen-doped oxide (e.g., N2-implanted SiO2), silicon oxynitride (Si x O y N z), a polymer material, or the like. The dielectric material may be formed using a suitable process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. In some embodiments, a planarization process, such as grinding or chemical mechanical planarization (CMP) processes, may be used to remove excess materials of the insulating layer 21.

[0042] With reference to Fig. 5B, a silicon layer 22 is formed or disposed on the insulation layer 21. A trench 22t is formed from a top surface of the silicon layer 22 into the silicon layer 22. In some embodiments, a portion of the silicon layer 22 remains to define a bottom surface of the trench 22t. In some embodiments, the silicon layer 22 may be formed, for example, by an etching (e.g., dry etching, wet etching, reactive ion etching (RIE), or the like) or any other suitable processes. Then, as in Fig. As shown in Figure 5C, the trench 21t is filled with a light-detecting layer 23. The light-detecting layer 23 may protrude from the upper surface of the silicon layer 22.

[0043] With reference to Fig. 5D, p-doped regions 22p1, 22p2, 22p3, 22p4 and n-doped regions 22n1, 22n2, 22n3, 22n4 are formed in the silicon layer 22 and the light detection layer 23. As shown in Fig.As shown in Figure 5D, the n-doped regions 22n1, 22n2, 22n3, 22n4 and the p-doped regions 22p1, 22p2, 22p3, 22p4 are arranged alternately. In other words, there is an n-doped region between two adjacent p-doped regions, or there is a p-doped region between two adjacent n-doped regions. In some embodiments, there may be any number of n-doped regions and p-doped regions depending on different design specifications. For example, there may be N n-doped regions and N p-doped regions, where N is an integer greater than 1.

[0044] In some embodiments, the p-doped regions 22p1, 22p2, 22p3, 22p4 and the n-doped regions 22n1, 22n2, 22n3, 22n4 may be formed by implanting dopants through an ion implantation process, an epitaxial process, or any other suitable processes. Ions or dopants are implanted into desired portions of the silicon layer 22 and the light-detecting layer 23. In some embodiments, a photomask may be used to allow only the desired portions to receive dopants. The doping concentration amounts for the n-doped regions 22n1, 22n2, 22n3, 22n4 and the p-doped regions 22p1, 22p2, 22p3, 22p4 may vary depending on the process used and the particular design. In some embodiments, doping concentrations of a p-type material or an n-type material may be in a range of about 10 17 atoms / cm 3 up to 10 19 atoms / cm 3 lay.

[0045] In some embodiments, a waveguide structure may be formed or defined when the silicon layer 22 is formed. The waveguide structure may extend in a first direction (e.g., axial direction) substantially parallel to the length of the light-detection layer. The waveguide structure may serve as a channel for guiding light (or photons) into the light-detection layer 23 in the first direction. The p-doped regions 22p1, 22p2, 22p3, 22p4 and the n-doped regions 22n1, 22n2, 22n3, 22n4 are arranged alternately in a direction substantially perpendicular to the first direction.

[0046] In some embodiments, the present disclosure provides a light detection device. The light detection devices include an insulating layer, a silicon layer, a light detection layer, N first doped regions, and M second doped regions. The silicon layer is disposed over the insulating layer. The light detection layer is disposed over the silicon layer and extends within at least a portion of the silicon layer. The first doped regions have a first dopant type and are disposed within the light detection layer. The second doped regions have a second dopant type and are disposed within the light detection layer. The first doped regions and the second doped regions are arranged alternately. M and N are integers greater than or equal to 2.

[0047] In some embodiments, the present disclosure provides a light detection device. The light detection device includes an insulating layer, a silicon layer, a light detection layer, a waveguide structure, a first doped region, and a second doped region. The silicon layer is disposed over the insulating layer. The light detection layer is disposed over the silicon layer and extends within at least a portion of the silicon layer. The waveguide structure is disposed adjacent to the silicon layer and extends in a first direction. The first doped region has a first dopant type and is disposed within the light detection layer. The second doped region has a second dopant type and is disposed within the light detection layer.The first doped region and the second doped region are arranged in a second direction substantially perpendicular to the first direction.

[0048] In some embodiments, the present disclosure provides an optical device. The optical device includes an insulating layer, a silicon layer, and a light-sensing layer. The silicon layer is disposed over the insulating layer. The light-sensing layer is disposed over the silicon layer and extends within at least a portion of the silicon layer. The light-sensing layer has a first region and a second region spaced from the first region. The first region of the light-sensing layer is configured to convert light into a first photocurrent. The second region is configured to convert the light received by the first region into a second photocurrent. An amplitude of the second photocurrent is smaller than an amplitude of the first photocurrent.

[0049] In some embodiments, the present disclosure provides a method of fabricating a light detection device. The method comprises (a) providing a substrate; (b) forming an insulating layer on the substrate; (c) forming a silicon layer on the insulating layer; (d) forming a light detection layer on the silicon layer and extending within at least a portion of the silicon layer; (e) forming two or more first doped regions of a first dopant type within the light detection layer; and (f) forming two or more second doped regions of a second dopant type within the light detection layer. The first doped regions and the second doped regions are arranged alternately.

Claims

[1] Light detection device comprising: an insulating layer (21); a silicon layer (22) over the insulation layer (21); a light detection layer (23) over the silicon layer (22) and extending within at least a portion of the silicon layer (22); N first doped regions (22n, 22p) of a first dopant type within the light detection layer (23); and M second doped regions (22n, 22p) of a second dopant type within the light detection layer (23), wherein the first doped regions (22n, 22p) and the second doped regions (22n, 22p) are arranged alternately along a first direction and are arranged along a second direction perpendicular to the first direction across the light detection layer (23); and where M and N are integers greater than or equal to 2. [2] The light detection device according to claim 1, wherein one of the first doped regions (22n, 22p) comprises a first portion within a portion of the silicon layer (22) adjacent to a first side surface (231) of the light detection layer (23) and a second portion within the light detection layer (23). [3] The light detection device according to claim 2, wherein a width of the second portion of the first doped region (22n, 22p) is the same as a width of the light detection layer (23). [4] The light detection device according to claim 3, wherein the first doped region (22n, 22p) further comprises a third portion within a portion of the silicon layer (22) adjacent to a second side surface (232) of the light detection layer (23) opposite to the first side surface (231) of the light detection layer (23). [5] The light detection device according to claim 2, wherein a width of the second portion of the first doped region (22n, 22p) is smaller than a width of the light detection layer (23). [6] A light detection device according to any preceding claim, wherein the silicon layer (22) includes a waveguide structure (22w) extending in a first direction and configured to guide a light to the light detection layer (23). [7] A light detection device according to claim 6, wherein the first doped regions (22n, 22p) and the second doped regions (22n, 22p) are arranged in a second direction perpendicular to the first direction. [8] A light detection device according to any one of the preceding claims, wherein a distance between one of the first doped regions (22n, 22p) and one of the second doped regions (22n, 22p) adjacent to the first doped region (22n, 22p) is in a range (22n, 22p) of 10 nanometers (nm) to 500 nm. [9] Optical device comprising: an insulating layer (21); a silicon layer (22) over the insulation layer (21); a light detection layer (23) over the silicon layer (22) and extending within at least a portion of the silicon layer (22), the light detection layer (23) having a first region (22n, 22p) and a second region (22n, 22p) spaced from the first region (22n, 22p), wherein the first region (22n, 22p) of the light detection layer (23) is configured to convert a light into a first photocurrent, wherein the second region (22n, 22p) is configured to convert the light received by the first region (22n, 22p) into a second photocurrent, and wherein an amplitude of the second photocurrent is smaller than an amplitude of the first photocurrent, further comprising a delay circuit (D51-D53) configured to receive the first photocurrent and generate a first current, the first current delaying the first photocurrent by the first time. [10] The optical device of claim 9, further comprising: a first doped region (22n, 22p) of a first dopant type within the light detection layer (23); a second doped region (22n, 22p) of a second dopant type within the light detection layer (23); a third doped region (22n, 22p) of the first dopant type within the light detection layer (23); and a fourth doped region (22n, 22p) of the second dopant type within the light detection layer (23), wherein the first doped region (22n, 22p) and the second doped region (22n, 22p) define the first region (22n, 22p) of the light detection layer (23), and wherein the third doped region (22n, 22p) and the fourth doped region (22n, 22p) define the second region (22n, 22p) of the light detection layer (23). [11] An optical device according to claim 9 or 10, wherein the first photocurrent precedes the second photocurrent by a first time. [12] The optical device according to claims 9 to 11, further comprising an adding circuit (A51-A53) configured to receive the first current and the second photocurrent and to combine the first current and the second photocurrent. [13] The optical device according to claims 9 to 12, wherein an amplitude of the first current is greater than or equal to the amplitude of the first photocurrent. [14] A method of manufacturing a light detection device comprising: (a) providing a substrate (20); (b) forming an insulating layer (21) on the substrate (20); (c) forming a silicon layer (22) on the insulating layer (21); (d) forming a light detection layer (23) on the silicon layer (22) and extending within at least a portion of the silicon layer (22); (e) forming two or more first doped regions (22n, 22p) of a first dopant type within the light detection layer (23); and (f) forming two or more second doped regions (22n, 22p) of a second dopant type within the light detection layer (23), wherein the first doped regions (22n, 22p) and the second doped regions (22n, 22p) are arranged alternately along a first direction and are arranged along a second direction perpendicular to the first direction across the light detection layer (23). [15] The method of claim 14, wherein process (d) further comprises: Forming a trench (22t) from an upper surface of the silicon layer (22) into the silicon layer (22); and Filling the trench (22t) with the light detection layer (23). [16] The method of claim 14 or 15, further comprising forming a waveguide structure (22w) adjacent to the silicon layer (22) and extending in a first direction, wherein the first doped regions (22n, 22p) and the second doped regions (22n, 22p) are arranged in a second direction perpendicular to the first direction. [17] The method according to any one of the preceding claims 14 to 16, wherein the first doped regions (22n, 22p) are further arranged within a portion of the silicon layer (22) adjacent to a first side surface (231) of the light detection layer (23) and diffusing from the first side surface (231) of the light detection layer (23) to a second side surface (232) of the light detection layer (23) opposite the first side surface (231) of the light detection layer (23). [18] The method of claim 17, wherein a distance exists between the second side surface (232) of the light detection layer (23) and the first doped region (22n, 22p). [19] The method of claim 17 or 18, wherein the first doped regions (22n, 22p) diffuse to a portion of the silicon layer (22) adjacent to the second side surface (232) of the light detection layer (23).

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