Display device and control method therefor

Abstract

Display device comprising: a display panel (100) comprising a screen (AA) having data lines (DL1 to D6) and gate lines (GL1, GL2) crossing each other, and pixels (P) arranged in a matrix form defined by the data lines (DL1 to D6) and the gate lines (GL1, GL2); a gate driver unit (120) configured to supply a scanning signal (SCAN) to the gate lines (GL1, GL2); a driver device (300) configured to supply a data voltage (Vdata) to the data lines (DL1 to D6) and to generate a shift clock (GCLK); a shift clock line (51) configured to supply the shift clock (GCLK) to the gate driver unit (120); and a scanning device (M9, 52, 230) configured to detect a pulse width of a feedback signal supplied to the display panel (100), wherein the sampling device (M9, 52, 230) is configured to compare the feedback signal with a predetermined reference voltage (Vref) and to detect an interval of the feedback signal in which a voltage of the feedback signal is less than or equal to the reference voltage (Vref) as the pulse width of the feedback signal, wherein the driver device (300) is configured to change a pulse width of the shift clock (GCLK) and / or a pulse voltage of the shift clock (GCLK) depending on a pixel position on the screen in response to the pulse width of the feedback signal detected by the scanning device, wherein the gate driver unit (120) comprises a shift register configured to receive a start pulse (VST) and the shift clock (GCLK) and to sequentially shift and output the scanning signal (SCAN), and the shift register comprises cascade-connected stages, each of the stages comprising a pull-up transistor turned on according to a voltage of a Q node, wherein the sampling device (M9, 52, 230) further comprises at least one feedback transistor (M9) which is switched on according to the voltage of the Q node of a stage of the shift register, the feedback transistor (M9) being configured to connect the shift clock line (51) to a feedback line (52) to supply the feedback signal to the sampling device.

Description

BACKGROUND1. Field of InterestThe present disclosure relates to a display device configured to sense the electrical characteristics of a driving element and compensate for a variation or change in the electrical characteristics, and a driving method thereof.2. Discussion of the Prior ArtAn electroluminescence display is classified according to the material of a light emitting layer as an inorganic light emitting display device and an organic light emitting display device. An active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light by itself and has advantages in terms of a fast response speed, a high light emission efficiency, a high luminance, and a large viewing angle. An organic light emitting display device includes OLEDs formed in the pixels. An organic light emitting device can exhibit both a black gray level as perfect black and a fast response speed, a high light emitting efficiency, a high luminance and a large viewing angle, and thus has an excellent contrast ratio and a superior color range.An organic light emitting display device does not require a backlight unit, and may be implemented on a flexible plastic substrate, a thin glass substrate, or a metal substrate. Accordingly, a flexible display may be implemented as the organic light emitting display device.A flexible display may include a screen whose size and shape is variable by winding, folding, or bending a display panel. A flexible display may be implemented as a roll-up display, a flexible display, a foldable display, a slidable display, or the like. Such a flexible display device can be used for a television, a vehicle display, a portable device, and the like, and extends the field of application, in addition to a mobile device such as a smartphone and a tablet PC.The pixels of an organic light emitting display device include an OLED, a driving element for driving the OLED by adjusting current flowing through the OLED according to a gate-source voltage Vgs, a storage capacitor for maintaining the gate voltage of the driving device, and the like.The driver element may be implemented as a transistor. In order to uniformize the image quality of the entire screen of an organic light emitting display device, a driving element may have uniform electrical characteristics for each pixel. Due to a process deviation and a deviation of device characteristics caused in a manufacturing process for a display panel, there may be differences between the electrical characteristics of the driving elements of the pixels, which differences may increase as the driving time of the pixels elapses. In order to compensate for the deviation of the electrical characteristics of the driving elements of the pixels, an internal compensation technique or an external compensation technique may be applied to an organic light emitting display device.US 2008 / 0007505 A1 describes a liquid crystal display having a timing controller, a pulse width regulator, a panel, a gate driver and a data driver. The timing controller generates gate control signals and data control signals. The gate control signals include an output enable signal for defining the width of a gate-on voltage. The data control signals include a horizontal start signal and a data clock signal. The pulse width regulator is connected to at least two adjacent gate lines among the gate lines, generates a predetermined signal, and returns the generated signal to the timing controller. The timing controller adjusts the width of the output enable signal based on the pulse width control signal fed back from the pulse width controller, and controls the widths of the gate-on pulses so as not to overlap.KR 10 2014 0092685 A describes a timing controller that can reduce flicker of a displayed image and a driving method thereof. The timing controller includes: a timing signal generation unit that outputs a scan start signal and clock signals to a scan driving unit; a detection unit that detects state transition timings of the scan start signal and the scan signal output from the scan driving unit during a plurality of frame periods; a calculation unit that calculates delay values and jitter values for the state transition timings; and an offset signal generation unit that generates an offset signal to control timing of the scan start signal and the clock signals based on the delay values and the jitter values. The clock signal generating unit controls the timing of the scan start signal and the clock signals in response to the offset signal.SUMMARYThe internal compensation technique uses an internal compensation circuit embedded in each pixel to sample the threshold voltage of the driver element for each sub-pixel and to compensate the threshold voltage for the gate-source voltage Vgs of the driver element.The external compensation technique uses an external compensation circuit to sense the current or voltage of the driver element that changes according to the electrical characteristics of the driver element. The external compensation technique compensates for the variations (changes) in the electrical characteristics of the driver element of each pixel by modulating the pixel data (digital data) of the input image by the variations (changes) in the electrical characteristics of the driver element sampled for each pixel.In order to drive the pixels of an organic light emitting display device, voltages such as a pixel driving voltage VDD and a low potential power supply voltage VSS are commonly supplied to the pixels. However, these voltages VDD and VSS have voltage drop amounts that vary depending on the position of a pixel on a screen by an IR drop or an ohmic drop. When the VDD changes, the gate-source voltage Vgs and the drain-source current Ids of the driving element that drives the OLED change, and thus a change in luminance of the pixels may occur.In the case of the internal compensation technique, all pixels should have the same sampling period in which the threshold voltage of a driving element is sampled. However, when the on-time of a gate signal varies depending on the pixels, the sampling period is changed. The on-time of the gate signal is determined according to the pulse width of the gate signal. The on-time of the gate signal may vary depending on a resistor-capacitor (RC) delay of a shift clock line applied to a gate driver circuit. For example, the sampling period may be decreased in the pixels at a position where the RC delay of the shift clock line is large. In a display panel, a line through which a clock or an analog voltage is applied may have an RC delay. When the scan signal varies depending on the pixels, the threshold voltage of the driving element is not accurately sampled.According to the experimental measurements, in the case of an organic light emitting display device, the influence of the IR drop that causes luminance fluctuation for each grayscale level of the pixel data is changed. For a high gray level, the amount of current flowing through an OLED is high, and thus the amount of IR drop is high. The amount of IR drop increases as the distance between a pixel and a driver IC increases. For a low gray level, the amount of IR decay is small because the amount of current flowing through an OLED is small. According to the experimental result, in the case of a low grayscale level, a decrease in luminance due to a decrease in the sampling period is larger than a decrease in luminance due to the IR drop.The present disclosure is directed to solving the above-mentioned needs and / or problems.The invention is set out in claim 1 and in the subordinate claim. Embodiments are set out in the dependent claims. The present disclosure provides a display device that can reduce a difference in luminance between pixels due to a variation in the sampling period, and a method for it.It should be noted that the objects of the present disclosure are not limited to the above-described object, and other objects not described herein will be apparent to those skilled in the art from the following descriptions.According to an embodiment of the present disclosure, there is provided a display device including a display panel in which the data lines and the gate lines cross each other and in which the pixels are arranged in a matrix form; a gate driving unit formed in the display panel and configured to supply a scan signal to the gate lines; a shift clock line formed in the display panel and configured to supply a shift clock to the gate driving unit; a sensing device configured to receive a feedback signal supplied to the display panel and sense a pulse width of the scan signal; and a driving device configured to supply a data voltage to the data lines and generate the shift clock. The display device, e.g., the driver device, may be configured to perform a method according to any of the embodiments described herein. The driving means changes one or both of a pulse width of the shift clock and a pulse voltage of the shift clock for each screen position of the display panel in response to a pulse width of the feedback signal sensed by the sensing means. That is, the driving device may be configured to change at least one of a pulse width of the shift clock and a pulse voltage of the shift clock depending on a pixel position, particularly depending on a position of the respective gate line or a distance of the respective gate line to the driving device, on the screen in response to the pulse width of the feedback signal detected by the sensing device.According to another embodiment of the present disclosure, there is provided a driving method of a display device, in particular, a method of driving a display device according to any one of the embodiments described herein, the driving method including receiving a feedback signal supplied to the display panel and sampling a pulse width of the sampling signal; and changing one or both of a pulse width of the shift clock and a pulse voltage of the shift clock for each screen position of the display panel in response to a pulse width of the sampled feedback signal.The method and / or the display device may include one or more of the following features:A screen of the display panel may include the data lines, the gate lines crossing the data lines, and a pixel array in which the pixels are arranged in a matrix form. The pixels may be arranged in the pixel array in a matrix form defined by the data lines and the gate lines. The screen may also be referred to as a display area of the display panel.A position or "screen position" may be a position on or within the screen and may be a position of a pixel of the screen. The position of a pixel may define the distance of the pixel from the driver unit in the direction of or along the data lines and / or in the direction of or along the gate lines. For example, depending on their screen position, the pixels may be connected to different gate lines, and the pixels connected to the same gate line may be arranged at the same screen position with respect to the driving unit. In other words, the screen position of a pixel may correspond to the gate line to which the pixel is connected. A lower position may be a position on the screen adjacent to the driver unit. An upper position may be a position opposite, i.e., far from, the driving unit on the screen. A center position may be a position between the lower position and the upper position on the screen. These positions may be arranged along a direction parallel to the data lines and perpendicular to the gate lines.The pulse voltage of the shift clock and a pulse voltage of the scan signal may be or have the same gate turn-on voltage. Each of the pixels may include one or more pixel switching elements that are turned on according to the gate turn-on voltage.A pulse signal supplied to the display panel may include the shift clock supplied to the shift clock line.The sensing device may include a feedback line connected to the gate driver unit. The sensing device may include a sensing unit configured to compare the feedback signal input through the feedback line with a predetermined reference voltage, detect a voltage interval having voltages less than or equal to the reference voltage from the feedback signal as the pulse width of the feedback signal. The sampling unit may be configured to output digital data indicating the pulse width of the feedback signal.The gate driving unit may include a shift register configured to receive a start pulse and the shift clock, and sequentially shift and output the scan signal. The shift register may comprise cascaded stages. The stages may each include a pull-up transistor that is turned on according to a voltage of a Q node and is configured to charge an output node connected to the gate lines with a gate turn-on voltage. The pixels may include one or more pixel switching elements that are turned on according to the gate turn-on voltage.The sensing device may further include a feedback transistor that is turned on according to the voltage of the Q node and is configured to connect the shift clock line to the feedback line.The feedback transistor may be connected to each of the stages or may be connected to at least two stages spaced apart from each other by a predetermined distance.The display panel may further include: an enable line configured to receive an enable signal from the driving unit; a test data line configured to receive a pulse signal from the driving unit; and a switching element that is turned on in response to the enable signal and is configured to supply the pulse signal to one of the data lines.The signal supplied to the display panel may include the pulse signal supplied to the test data line.The sensing device may include: the data line through which the pulse signal is supplied through the switching element; and a sensing unit configured to compare the pulse signal input through the data line with a predetermined reference voltage, detect a voltage interval having voltages less than or equal to the reference voltage from the feedback signal as the pulse width of the feedback signal. The sampling unit may be configured to output the digital data indicating the pulse width of the feedback signal.The driving device may include a timing controller configured to, in response to the digital data received from the sensing device, reduce the pulse width of the shift clock synchronized with the sensing signal supplied to the pixels close to the driving device to be smaller than the pulse width of the shift clock synchronized with the sensing signal supplied to the pixels far from the driving device.The driving device may include a level shifter configured to convert the pulse voltage of the shift clock output from the timing controller to a gate turn-on voltage. The pixels may include one or more pixel switches that are turned on according to the gate turn-on voltage.The driving device may change the pulse width of the shift clock using a look-up table in which a compensation pulse width corresponding to a pulse width value of the digital data received from the sampling device is defined.The driving device may reduce, in response to the digital data received from the sensing device, a voltage of the shift clock synchronized with the sensing signal supplied to the pixels close to the driving device to be lower than a voltage of the shift clock synchronized with the sensing signal supplied to the pixels far from the driving device.The driving device may include a timing controller configured to output, in response to the digital data received from the sensing device, the digital data that changes the pulse voltage of the shift clock according to the positions of the pixels.The driver device may further include a digital-to-analog converter configured to convert the digital data received from the timing controller to an analog voltage. The driving device may include a level shifter configured to convert a voltage received from the digital-to-analog converter to a gate turn-on voltage. The pixels may include one or more pixel switches that are turned on according to the gate turn-on voltage.Each of the pixels may include: a light emitting element; a driving element configured to adjust the current flowing through the light emitting element according to a gate-source voltage; and an internal compensation circuit configured to sample a threshold voltage of the driving element in a sampling period defined by a pulse of the sampling signal and supply the threshold voltage to a capacitor. The internal compensation circuit may include: a capacitor connected to a gate of the driving element; and one or more switching elements configured to connect the capacitor, the driving element, and the light emitting element. The switching element may be turned on according to the pulse voltage of the sensing signal.At a high grayscale level and an intermediate grayscale level of the pixel data written to the pixels, the driving device may increase and output a pixel driving voltage supplied to the pixels far from the driving device to be larger than a pixel driving voltage supplied to the pixels close to the driving device.At a low grayscale level of the pixel data written to the pixels, the driving device may output the pixel driving voltage supplied to the pixels far from the driving device to be equal to the pixel driving voltage supplied to the pixels close to the driving device.BRIEF DESCRIPTION OF THE DRAWINGSThe above-mentioned and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art from describing in detail their exemplary embodiments with reference to the accompanying drawings, wherein: FIG. 1 is a block diagram showing a display device according to an embodiment of the present disclosure; FIG. 2 is a diagram showing an example of a PenIle pixel array; FIG. 3 is a diagram showing an example of a real pixel array; FIG. 4 is a block diagram showing a configuration of a driver integrated circuit (driver IC) shown in FIG. 1 ; FIG. 5 is a diagram schematically showing a circuit configuration of a shift register in a gate driving unit; FIGS. 6A and 6B are diagrams schematically showing a pass gate circuit and an edge trigger circuit; FIG. 7 is a waveform diagram showing a Q node voltage, a QB node voltage, and an output voltage of an Nth stage shown in FIG. 6 ; FIG. 8 is a circuit diagram showing a single stage circuit in a gate driving unit according to an embodiment of the present disclosure; FIG. 9 is a waveform diagram showing input / output waveforms of a circuit shown in FIG. 8; FIG. 10 is a diagram schematically showing a pixel circuit of the present disclosure; FIGS. 11 and 12 are flowcharts specifically showing a pixel circuit shown in FIG. 10 ; FIGS. 13A to 15B are graphs showing stepwise the operation of the pixel circuit shown in FIG. 11; FIGS. 16A to 18B are graphs showing stepwise the operation of the pixel circuit shown in FIG. 12; FIG. 19 is a graph showing the gray-scale-based luminance measurement positions on a screen; FIG. 20 is a graph showing the luminance values based on gray levels measured at the measurement positions shown in FIG. 19 ; FIG. 21 is a graph showing the sampling periods corresponding to the positions on a screen; FIG. 22 is a graph showing the change in gate-source voltage of a driving element measured according to the positions and the gray level levels on a screen; FIG. 23 is a diagram showing a sensing device according to a first embodiment of the present disclosure; FIG. 24 is a circuit diagram specifically showing an Nth stage in a gate driver unit shown in FIG. 23 ; FIGS. 25 and 26 are graphs for comparing sensing operations according to the presence or absence of a ninth transistor shown in FIG. 24 ; FIG. 27 is a diagram showing an AP test circuit on a display panel connectable to a sensing device of the present disclosure; FIG. 28 is a diagram showing a sensing device according to a second embodiment of the present disclosure; FIG. 29 is a diagram showing a multiplexer connected between a pixel array and a sensing unit; FIG. 30 is a graph specifically showing a vertical blanking period and an active interval in a frame period; FIG. 31 is a waveform diagram showing a sampling method of one sampling period for each position on a screen; FIG. 32 is a waveform diagram showing an example of a pulse width modulation method of a shift clock for reducing a variation of a sampling period in all pixels of a screen; FIGS. 33 and 34 are diagrams showing an apparatus that modulates a pulse width of a shift clock using a look-up table and a sampling unit; FIG. 35 is a waveform diagram showing an example of a shift clock having a pulse width modulated for each position on a screen during one frame period; FIG. 36 is a waveform diagram showing a sampling period for each position on a screen and a shift clock applied to the pixels; FIG. 37 is a waveform diagram showing a change in a gate turn-on voltage applied to a display panel along the time axis; FIG. 38A is a waveform diagram showing a shift clock measured at an output node of a level shifter; FIG. 38B is a waveform diagram showing a waveform of a shift clock in which a resistor-capacitor (RC) delay is reflected when a shift clock as shown in FIG. 38A is applied to a shift clock line in a display panel; FIGS. 39 and 40 are diagrams showing a device that modulates a gate on voltage of a shift clock using a look-up table and a sampling unit; FIGS. 41 and 42 are graphs illustrating a gate turn-on voltage having a voltage level different for each position on a screen; FIG. 43 is a graph showing an example in which a pixel driving voltage varies depending on the gray level; FIG. 44 is a luminance measurement result graph showing improvement in luminance uniformity of a screen at higher grayscale levels when a pixel driving voltage and a gate turn-on voltage are modulated in the same manner as that of an embodiment of the present disclosure; FIG. 45 is a luminance measurement result graph showing improvement in luminance uniformity of a screen at lower grayscale levels when a pixel driving voltage and a gate turn-on voltage are modulated in the same manner as that of an embodiment of the present disclosure; and Fig. 46 is a graph showing the positions of luminance measurement on a screen.DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTSThe advantages and features of the present disclosure and its implementation methods will be made clear by the following embodiments, which are described with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but is implemented in various forms. The exemplary embodiments of the present disclosure make the disclosure of the present disclosure thorough and are provided so that the scope of the present disclosure will be fully understood by those skilled in the art. Therefore, the present disclosure is defined by the scope of the appended claims.The figures, dimensions, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present disclosure are merely illustrative and are not limited to the subject matters shown in the present disclosure. Like reference numerals refer to like elements throughout. Further, in describing the present disclosure, detailed descriptions of well-known techniques will be omitted when it is determined that they may unnecessarily obscure the gist of the present disclosure. Terms such as "including" and "having" used herein are intended to allow other elements to be added unless the terms are used with the term "only.". All references to the singular may include the plural, unless expressly stated otherwise.The components are interpreted to include a common error range, even if not expressly stated.For describing a positional relationship, for example, when the positional relationship between two parts is described as being "on", "over", "under", and "next", etc., one or more parts may be interposed therebetween unless the term "immediately" or "directly" is used in the term.In the description of embodiments, terms such as "first", "second", etc. are used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. Therefore, a first element discussed below could be referred to as a second element without departing from the teachings of the present disclosure.Like reference numerals refer to like elements throughout.The features of various embodiments may be partially or wholly connected or combined with each other. The embodiments may cooperate and be embodied in various forms, and may be implemented independently or in conjunction with one another.Each of a gate driving unit and a pixel circuit in a display device of the present disclosure may include a plurality of transistors. Each transistor may be implemented as an oxide thin film transistor (oxide TFT) including an oxide semiconductor, a low temperature polysilicon TFT (LTPS TFT) including LTPS, and the like. Each transistor may be implemented as a transistor having a p-channel or n-channel metal oxide semiconductor field effect transistor (p-channel or n-channel MOSFET) structure. The following embodiments will be described directed to an example in which the transistors of the pixel circuit are implemented as p-channel transistors, but the present disclosure is not limited thereto.A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode through which charge carriers are supplied to the transistor. In the transistor, the carriers start to flow from the source. The drain electrode is an electrode through which the charge carriers exit the transistor. The flow of charge carriers in the transistor takes place from the source to the drain. In the case of an n-channel transistor, the charge carriers are electrons. Consequently, the source voltage is lower than the drain voltage, so that the electrons can flow from the source to the drain. In an n-channel transistor, the current flows from the drain to the source. In the case of a p-channel transistor, the charge carriers are holes. Consequently, the source voltage is higher than the drain voltage, so that the holes can flow from the source to the drain. Because the holes in the p-channel transistor flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. The source and the drain may be changed depending on an applied voltage, for example. Accordingly, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first and second electrodes, respectively.A gate signal oscillates between a gate turn-on voltage and a gate turn-off voltage. The gate turn-on voltage is set to be a voltage higher than the threshold voltage of the transistor, while the gate turn-off voltage is set to be a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate turn-on voltage, while the transistor is turned off in response to the gate turn-off voltage. In the case of an n-channel transistor, the gate turn-on voltage may be a gate high voltage VGH / VEH, while the gate turn-off voltage may be a gate low voltage VGL / VEL. In the case of a p-channel transistor, the gate turn-on voltage may be a gate low voltage VGL / VEL, while the gate turn-off voltage may be a gate high voltage VGH / VEH.Each of the pixels of the present disclosure includes a light emitting element, a driving element configured to adjust the current flowing through the light emitting element according to a gate-source voltage, and an internal compensation circuit configured to sample the threshold voltage of the driving element in a sampling period defined by a pulse of the sampling signal and supply the threshold voltage to a capacitor. The internal compensation circuit includes a capacitor connected to the gate of the driving element and one or more switching elements configured to connect the capacitor to the driving element and the light emitting element.The internal compensation circuit may include a plurality of switching elements and capacitors shown in FIGS. 11 and 12.The display device of the present disclosure includes a sensing device configured to receive a feedback signal for a pulse supplied to a display panel and sense a pulse width of a sensing signal, and a driving device configured to supply a data voltage to the data lines and generate a shift clock. In response to a pulse width of a feedback signal sampled by the sampling device in real time, the driving device changes one or both of a pulse width of a shift clock and a pulse voltage of the shift clock based on the screen positions of the display panel.In the following embodiment, the driving device will be described as a driver integrated circuit (IC). In the following embodiment, the feedback signal may also be a feedback signal for a shift clock supplied to a shift clock line connected to the gate driving unit or a feedback signal for a pulse applied to a test data line.Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.In FIGS. 1 to 4, the display device of the present disclosure includes a display panel 100 and the display panel driving units 120 and 300.The display panel driving units 120 and 300 write the pixel data of an input image into the pixels of a screen and display the image on the screen. The display panel driving units 120 and 300 include a gate driving unit 120 configured to supply a gate signal to the gate lines GL 1 and GL 2 of the display panel 100, a data driving unit 306 configured to convert the pixel data into a voltage of a data signal and supply the voltage to the data lines through the activated data output channels, and a timing controller 303 configured to control the operation timing of the data driving unit 306 and the gate driving unit 120. The data driving unit 306 and the timing controller 303 may be integrated into a driving IC 300. The driver IC 300 may be referred to as the "driver unit" 300.The screen of the display panel 100 includes the data lines DL 1 to DL 6, the gate lines GL 1 and GL 2 crossing the data lines DL 1 to DL 6, and a pixel array in which the pixels P are arranged in a matrix form. The pixels P are arranged in the pixel array in a matrix form defined by the data lines DL 1 to DL 6 and the gate lines GL 1 and GL 2.For color display, each of the pixels P includes sub-pixels having different colors. The sub-pixels include a red sub-pixel RED (hereinafter referred to as "R sub-pixel"), a green sub-pixel GREEN (hereinafter referred to as "G sub-pixel"), and a blue sub-pixel BLUE (hereinafter referred to as "B sub-pixel"). Although not shown, each of the pixels may further include a white sub-pixel. The sub-pixels are arranged in a matrix form defined by the data lines DL 1 to DL 6 and the gate lines GL 1 and GL 2. Hereinafter, a "pixel" may also be interpreted as a sub-pixel.Each of the sub-pixels may include an internal compensation circuit configured to sense the electrical characteristics, e.g., the threshold voltage, of the driver element and compensate the gate voltage of the driver element.The pixels P may be arranged in the form of real color pixels or PenIle pixels. The PenT pixels may implement a higher resolution than the real color pixels by driving two or more sub-pixels having different colors than one pixel P using a predetermined PenT pixel rendering algorithm, as shown in FIG. 2. The PenIle pixel rendering algorithm compensates for the lack of color in each pixel P with the color of the light emitted in an adjacent pixel P.For the true color pixels, pixel P consists of R, G and B sub-pixels, as shown in Figure 3.When the resolution of the pixel array is N*M, the pixel array includes N pixel columns COLUMN and M pixel rows crossing the pixel columns. The pixel columns include the pixels arranged in the y-axis direction. The pixel lines include the pixels arranged in the direction of the x-axis. In FIGS. 2 and 3, No. 1 and No. 2 indicate the numbers of pixel lines. A horizontal period 1H is a time period obtained by dividing a frame period by M, which is the number of pixel lines. The gate driving unit 120 may scan the pixels by outputting a gate signal in an order from a first pixel line to an M-th pixel line progressively in units of one line. The pixels in a pixel row may operate to initialize, sample, and write data within a horizontal period.The pixel array of the display panel 100 may be formed on a glass substrate, a metal substrate, or a plastic substrate. A plastic OLED panel may be implemented as a flexible panel by forming the pixel array on the plastic substrate. The plastic OLED panel has a pixel array formed on an organic thin film bonded to a back plate. A touch sensor array may be formed over the pixel array.The backplate may be a polyethylene terephthalate (PET) substrate. The organic thin film is formed on the back plate. A pixel array and a touch sensor array may be formed on the organic thin film. The back plate blocks the penetration of moisture into the organic thin film so that the pixel array is not exposed to the moisture. The organic thin film may be a polyimide (PI) thin film substrate. A multilayer buffer layer may be formed on the organic thin film and formed of an insulating material (not shown). Lines for supplying power or signals to the pixel array and the touch sensor array may be formed on the organic thin film.The gate driving unit 120 may be mounted on the substrate of the display panel 100 together with the pixel array. The gate driver unit 120 formed directly on the substrate of the display panel 100 is referred to as a gate-in-panel (GIP) circuit.The gate driving unit 120 may be disposed at one of the left and right bezels BEZEL of the display panel 100 to supply a gate signal in a single-feed manner to the gate lines GL 1 and GL 2. In this case, one of the two gate driving units 120 shown in FIG. 1 is not required.The gate driving units 120 may be disposed at the left and right rims of the display panel 100 to supply a gate signal in a double feed manner to the gate lines GL 1 and GL 2. In the double feed, a gate signal may be simultaneously applied to both ends of a gate line.The gate driving unit 120 is driven according to a gate timing signal supplied from the driving IC 300 using a shift register to sequentially supply the gate signals GATE 1 and GATE 2 to the gate lines GL 1 and GL 2. The shift register may sequentially supply the gate signals GATE 1 and GATE 2 to the gate lines GL 1 and GL 2 by shifting the gate signals GATE 1 and GATE 2. The gate signals GATE 1 and GATE 2 may include the scan signals SCAN 1, SCAN 2, SCAN(N- 1) and SCAN(N), the emission control signals EM and EM(N), and the like shown in FIGS. 11 and 12. In the following description, an emission control signal is referred to as an EM signal.The driver IC 300 is connected to the data lines DL 1 to DL 6 through the data output channels to supply the voltage of the data signal (hereinafter referred to as "data voltage") to the data lines DL 1 to DL 6. The driver IC 300 may output a gate timing signal for controlling the gate driver unit 120 through the gate timing signal output channels.The driver IC 300 may be connected to a host system 200, a first memory 301, and the display panel 100, as shown in FIG. 4. The driver IC 300 may include a data receiving and calculating unit 308, a timing controller 303, and a data driving unit 306. The driver IC 300 may further include a gamma compensation voltage generation unit 305, a power supply unit 304, a second memory 302, a level shifter 307, and the like. The driver IC 300 may further include a sensing unit 230 connected between the timing controller 303 and a feedback line 52 of the display panel 100.The timing controller 303 provides the pixel data of an input image received from the host system 200 to the data driving unit 306. The timing controller 303 may generate a gate timing signal for controlling the gate driving unit 120 and a source timing signal for controlling the data driving unit 306 to control the operation timing of the gate driving unit 120 and the data driving unit 306.The sampling unit 230 samples one sampling period for each position of the screen based on the feedback signal received by the feedback line 52. The sampling period is defined by the pulse width of the sampling signal. The pulse of the scan signal may be generated with the same pulse width and voltage as those of the pulse of the shift clock GCLK input to the gate driving unit 120. The sensing unit 230 senses the sensing period of the pixel for each position of the screen by measuring a resistor-capacitor (RC) delay of a pulse for each position of the screen from a feedback signal for a separate pulse signal or a pulse of the shift clock GCLK. The feedback signal is fed back to the sensing unit 230 through the feedback line 52 formed on the display panel 100.The timing controller 303 may change the pulse width or voltage of the shift clock applied to the gate drive circuit in consideration of a deviation of the sampling period of a pixel P for each position of the screen sampled by the sampling unit 230 in real time. As a result, by accurately sampling the electric characteristics of the driving element in all pixels of a planar display panel with an RC delay of a shift clock line, it is possible to realize uniform image quality over the entire screen.The driver IC 300 may generate the gate timing signals for driving the gate driver unit 120 through the level shifter 307 and the timing controller 303. The gate timing signals include the gate timing signals such as a start pulse VST, a shift clock GCLK, and the like, and the gate voltages such as a gate-on voltage VGL / VEL and a gate-off voltage VGH / VEH. The start pulse VST and the shift clock GCLK swing between the gate turn-on voltage VGL / VEL and the gate turn-off voltage VGH / VEH.The data receiving and calculating unit 308 includes a receiving unit configured to receive the input data input as a digital signal from the host system 200, and a data calculating unit configured to modulate the pixel data of an input image signal input by the receiving unit using a predetermined image quality algorithm to improve image quality. The data calculation unit may include a data recovery unit configured to perform the recovery by decoding compressed pixel data, an optical compensation unit configured to add a predetermined optical compensation value to the pixel data, and so on. The optical compensation value may be set as a value for compensating luminance of each part of the pixel data based on luminance of the screen measured based on a camera image captured in a manufacturing process.The data driving unit 306 converts the pixel data (a digital signal) received from the timing controller 303 into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as a "DAC"), and outputs the voltage of the data signals DATA 1 to DATA 6 (hereinafter referred to as the data voltages). The data voltage output from the data driving unit 306 is supplied to the data lines DL1 to DL6 of the pixel array through an output buffer (a source AMP) connected to the data channels of the driving IC 300.The gamma compensation voltage generation unit 305 generates a gamma compensation voltage for each grayscale level by dividing a gamma reference voltage received from the power supply unit 304 by a voltage divider circuit. The gamma compensation voltage is an analog voltage at which a voltage is set for each grayscale level of the pixel data. The gamma compensation voltage output from the gamma compensation voltage generation unit 305 is provided to the data driving unit 306.The level shifter 307 converts the low level voltage of the gate timing signal received from the timing controller 303 into the gate turn-on voltage VGL / VEL, and converts the high level voltage of the gate timing signal into the gate turn-off voltage VGH / VEH. The level shifter 307 outputs the gate timing signal and the gate voltages VGH / VEH and VGL / VEL through the gate timing signal output channels, and supplies the gate timing signal and the gate voltages VGH and VGL to the gate driving unit 120.The power supply unit 304 generates, using a DC-DC converter, the power required to drive the driver IC 300, the gate driver unit 120, and the pixel array of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply unit 304 may generate DC voltages such as a gamma reference voltage, a gate turn-on voltage VGL / VEL, a gate turn-off voltage VGH / VEH, a pixel driving voltage VDD, a low potential power supply voltage ELVSS, an initialization voltage Vini, a reference voltage Vref, and the like by adjusting an input DC voltage received from the host system 200. The gamma reference voltage is supplied to the gamma compensation voltage generation unit 305. The gate turn-on voltage VGL and the gate turn-off voltage VGH are supplied to the level shifter 307 and the gate driver unit 120, respectively. Pixel power such as pixel driving voltage VDD, low potential supply voltage ELVSS, and initialization voltages Vini and Vref are commonly supplied to pixels P.The gate voltages VGH / VEH and VGL / VEL may be set to 8 V and -7 V, while the pixel power voltages VDD, VSS and Vini (or Vref) may be set to 4.6 V, -2 V to -3 V and -3 V to -4 V, but the present disclosure is not limited thereto. The data voltage Vdata may be set to 3 V to 6 V, but the present disclosure is not limited thereto.The power supply unit 304 may change the gate on voltage VGL under the control of the timing controller 303. The gate turn-on voltage VGL may be changed in the range of -7.5 V and -8.0 V, for example, as shown in FIG. 41.The Vini or Vref is lower than the VDD and is set to be a DC voltage lower than the threshold voltage of the light emitting element (OLED) to suppress light emission of the light emitting element (OLED).When power is input to the driver IC 300, the second memory 302 stores a compensation value, the register setting data, etc. received from the first memory 301. The compensation value may be applied to various algorithms for improving image quality. The compensation value may include an optical compensation value.The register setting data defines the operation of the data driving unit 306, the timing controller 303, the gamma compensation voltage generating unit 305, and the like. The first memory 301 may include a flash memory. The second memory 302 may include a static RAM (SRAM).The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home security system, a mobile system, or a portable system.In the mobile system, the host system 200 may be implemented as an application processor (AP). The host system 200 may transmit the pixel data of the input image to the driver IC through a mobile industry processor interface (MIPI). The host system 200 may be connected to the driver IC 300 through a flexible printed circuit board, e.g., a flexible printed circuit board (FPC) 310.FIG. 5 is a diagram schematically showing a circuit configuration of a shift register in a gate driving unit. FIGS. 6A and 6B are diagrams schematically showing a pass gate circuit and an edge trigger circuit. FIG. 7 is a waveform diagram showing a Q node voltage, a QB node voltage, and an output voltage of an Nth stage shown in FIG. 6.In FIG. 5, the shift register of the gate driving unit 120 includes the stages ST(n-1) to ST(n+2) connected in cascade. The shift register receives a start pulse VST or the carry signals CAR1 to CAR4 received from the preceding stage as a start pulse and generates the outputs Gout(n-1) to Gout(n+2) in synchronism with the rising edges of the shift clocks GCLK1 to GCLK4. The shift clocks GCLK1 to GCLK4 are input to the stages ST(n-1) to ST(n+2) through the shift clock lines 51. In FIGS. 11 and 12, the output signals Gout(n-1) to Gout(n+2) of the shift register may be the gate signals SCAN 1, SCAN 1, SCAN(N-1), SCAN(N), EM, and EM(N).Each of the stages of the shift register may be implemented as a pass gate circuit as shown in FIG. 6A or as an edge trigger circuit as shown in FIG. 6B.In the pass gate circuit, a clock GCLK is input to a pull-up transistor Tup that is turned on or off according to the voltage of the Q node. In contrast, the gate-on voltage VGL is supplied to the pull-up transistor Tup of the edge trigger circuit, and the start pulse VST and the shift clocks GCLK to GCLK4 are input to the pull-up transistor Tup. A pull-down transistor Tdn is turned on or off according to the voltage of the QB node. In the pass gate circuit, the Q node is floating while the voltage of the Q node is changed to the gate-on voltage VGL according to the start pulse. When the shift clock GCLK is applied to the pull-up transistor Tup while the Q node is floating, the voltage of the Q node is changed to 2WD higher than the gate turn-on voltage VGL shown in FIG. 7 by bootstrapping, thus turning on the pull-up transistor Tup. In this case, the voltage of the output signal Gout(n) is changed to the gate turn-on voltage VGL.Because the edge trigger circuit is synchronized with the edge of the clock GCLK so that the voltage of the output signal Gout(n) is changed to the voltage of the start pulse, the output signal Gout(n) is generated in a waveform having the same phase as that of the start pulse. When the waveform of the start pulse is changed, the waveform of the output signal is changed accordingly. In the edge trigger circuit, the input signal may overlap the output signal.FIG. 8 is a circuit diagram showing a single stage circuit in the gate driving unit 120 according to an embodiment of the present disclosure. Fig. 9 is a waveform diagram showing input / output waveforms of a circuit shown in Fig. 8. The circuit of the gate driving unit 120 is not limited to the circuit shown in FIG. 8.In FIGS. 8 and 9, the gate driving unit 120 includes a plurality of transistors M 1 to M 7 and a plurality of capacitors CQ and CQB.A first transistor M1a or M1b is turned on according to the gate-on voltage VGL of a second GCLK node to which the second shift clock GCLK2 is supplied, to apply a voltage of a signal applied to a VST node to a Q' node. The carry signal received from the preceding stage or the start pulse VST is supplied to the VST node. The Q' node and the Q node are charged with the gate turn-on voltage VGL applied from the first transistor M1a or M1b. When an eighth transistor M8 is turned on, the Q node is connected to the Q' node.The first transistor M 1 aor M 1 bmay include two transistors M 1 aand M 1 bconnected to each other in a double gate structure to reduce the leakage current. The first a-transistor M 1 aincludes a gate connected to the second GCLK node, a first electrode connected to the VST node, and a second electrode connected to the first b-transistor M 1 b. The first b-transistor M1b includes a gate connected to the second GCLK node, a first electrode connected to the second electrode of the first a-transistor M1a, and a second electrode connected to the Q' node.The second transistor M 2 is turned on according to the gate turn-on voltage VGL of a first GCLK node to which the first shift clock GCLK 1 is applied. The third transistor M 3 is turned on according to the gate turn-on voltage VGL of the QB node. When the voltage of the QB node is the gate turn-on voltage VGL and the voltage of the first GCLK node is the gate turn-on voltage VGL, the second and third transistors M 2 and M 3 are turned on. In this case, the Q node and the Q' node are connected to the VGH node, and thus the Q node and the Q' node are charged with the gate off voltage VGH. The gate off voltage VGH is supplied to the VGH node. The second transistor M2 includes a gate connected to the first GCLK node, a first electrode connected to the Q' node, and a second electrode connected to the first electrode of the third transistor M3. The third transistor M 3 includes a gate connected to the QB node, a first electrode connected to the second electrode of the second transistor M 2, and a second electrode connected to the VGH node.The fourth transistor M 4 is turned on according to the gate turn-on voltage VGL of the second GCLK node to connect the VGL node to the QB node and discharge the voltage of the QB node to the VGL. The gate turn-on voltage VGL is supplied to the VGL node. The fourth transistor M 4 includes a gate connected to the second GCLK node, a first electrode connected to the VGL node, and a second electrode connected to the QB node.The fifth transistor M5 is turned on according to the gate turn-on voltage VGL of the Q' node to connect the second GCLK node to the QB node. The fifth transistor M5 includes a gate connected to the Q' node, a first electrode connected to the second GCLK node, and a second electrode connected to the QB node. When the gate voltage of the fourth transistor M 4 is the gate turn-on voltage VGL and the gate voltage of the third transistor M 3 is the gate turn-off voltage VGL, the VGL node and the QB node may be short-circuited. In this case, the fifth transistor M 5 is turned on to the gate node of the fourth transistor M 4 to the VGH node. By turning off the fourth transistor M 4, the short-circuiting of the VL node and the QB node is prevented.The sixth transistor M 6 is a pull-up transistor that is turned on when the voltage of the Q node is changed to a voltage (2VGL) lower than the gate turn-on voltage VGL by bootstrapping, so that the voltage of the output signal Gout(n) is changed to the gate turn-on voltage VGL. The sixth transistor M 6 includes a gate connected to the Q node, a first electrode connected to the first GCLK node, and a second electrode connected to an output node. The output node is connected to a gate line connected to the pixels.The seventh transistor M 7 is a pull-down transistor that is turned on when the voltage of the QB node is the gate-on voltage VGL, so that the voltage of the output signal Gout(n) is changed to the gate-off voltage VGH. The seventh transistor M 7 includes a gate connected to the QB node, a first electrode connected to an output node, and a second electrode connected to the VGH node.The eighth transistor M8 is turned on according to the gate turn-on voltage VGL of the VGL node to connect the Q' node to the Q node. The eighth transistor M 8 includes a gate connected to the VGL node, a first electrode connected to the QB node, and a second electrode connected to the Q node. When the voltage of the Q' node is the VGL and the voltage of the Q node is 2WD, the eighth transistor M8 is turned off to disconnect the Q' node and the Q node.The first capacitor CQ is formed between the Q node and the output node. The first capacitor CQ is a capacitor for bootstrapping the Q node. The first capacitor CQ connects the output node and the Q node by capacitor coupling to increase the Q node, so that the Q node is charged with 2VGL when the voltage of the output node is charged with the VGL of the shift clock GCLK. The second capacitor CQB is formed between the QB node and the VGH node. The second capacitor CQB maintains the voltage of the QB node at the gate turn-on voltage VGL when the seventh transistor M 7 is turned on, so that the voltage of the output node is maintained at the gate turn-off voltage.The second shift clock GCLK2 may be generated as a clock having a phase opposite to that of the first shift clock GCLK2. As seen in FIG. 9, the circuit of the gate driving unit 120 shown in FIG. 8 changes the voltage of the Q node and the QB node to the gate turn-on voltage VGL when the second shift clock GCLK 2 is the gate turn-on voltage VGL. When the voltage of the Q' node is the gate turn-on voltage VGL, the fourth and fifth transistors M4 and M5 are turned on, and thus the voltage of the QB node becomes the gate turn-on voltage VGL.When the voltage of the Q node is the gate turn-on voltage VGL and the first shift clock GCLK is changed to the gate turn-on voltage VGL, the voltage Q of the Q node is changed to 2WD while the voltage of the output signal Gout(n) is changed to the gate turn-on voltage VGL. Subsequently, when the second shift clock GCLK 2 is changed to the gate turn-on voltage VGL, the voltage of the QB node is changed to the gate turn-on voltage VGL, and the voltages of the Q node, the QB node, and the output node are changed to the gate turn-off voltage VGH.FIG. 10 is a diagram schematically showing a pixel circuit of the present disclosure.In FIG. 10, the pixel circuit may include the first to third circuit units 10, 20, and 30 and the first to third terminal units 12, 23, and 13. One or more elements may be omitted from the pixel circuit or added to the pixel circuit.The first circuit unit 10 supplies the pixel driving voltage VDD to a driving element DT. The driving element DT may be implemented as a transistor including a gate DRG, a source DRS, and a drain DRD. The second circuit unit 20 charges a capacitor CST connected to the gate DRG of the driving element DT, and maintains the voltage of the capacitor CST during a frame period. The third circuit unit 30 provides a current supplied from the pixel driving voltage VDD through the driving element DT to the light emitting element EL to convert the current into light. The first connection unit 12 connects the first circuit unit 10 and the second circuit unit 20, and the second connection unit 23 connects the second circuit unit 20 and the third circuit unit 30.This pixel circuit may be implemented as a pixel circuit shown in FIG. 11 or FIG. 12.FIGS. 11 and 12 are circuit diagrams specifically showing the pixel circuit shown in FIG. 10. The pixel circuits shown in Figs. 11 and 12 are any sub-pixel circuits belonging to an N-th pixel row. The pixel circuits may include an internal compensation circuit configured to sample the threshold voltage Vth of the driving element DT and compensate the threshold voltage Vth for the gate voltage of the driving element DT.As shown in FIGS. 11 and 12, the display panel may further include a first power supply line 61 for supplying the pixel driving voltage VDD to the pixels P, a second power supply line 62 for supplying the low potential power supply voltage VSS to the pixels P, and a third power supply line 63 for supplying the initialization / reference voltages Vini and Vref for initializing the pixel circuit to the pixels P. The power supply lines 61, 62, and 63 are connected to the output channels of the power supply unit 304.In FIG. 11, a pixel circuit according to a first embodiment of the present disclosure includes a light emitting element EL, a plurality of transistors T 1 to T 5 and DT, a capacitor CST, and so on.The transistors T 1 to T 5 and DT may be implemented as P-channel transistors. The transistors T 1 to T 5 and DT include the switching elements T 1 to T 5 and a driving element DT.The light emitting element EL may be implemented with an OLED. The OLED includes an organic composite layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light emission layer EML, an electron transport layer ETL, an electron injection layer EIL, and the like, but the present disclosure is not limited thereto. The anode of the OLED is connected to the fourth and fifth switching elements T 4 and T 5 through a fourth node N 4. The cathode of the OLED is connected to the second power supply line 62, through which the low-potential power supply voltage VSS is applied. The driving element DT drives the light emitting element EL by adjusting the amount of current flowing through the light emitting element EL according to the gate-source voltage Vgs. The current flowing through the light emitting element EL may be switched by the fourth switching element T 4.The capacitor CST is connected between a first node n 1 and a second node n 2. The first node n 1 is connected to the second electrode of the first switching element T 1, the first electrode of the third switching element T 3, and the first electrode of the capacitor CST. The second node n 2 is connected to the second electrode of the capacitor CST, the gate of the driving element DT, and the first electrode of the second switching element T 2. The capacitor CST is charged with the data voltage Vdata for which the threshold voltage Vth of the driving element DT is compensated.The first switching element T 1 supplies the data voltage Vdata to the first node n 1 in response to the second scan signal SCAN 2. The first switching element T 1 includes a gate connected to the second gate line 122, a first electrode connected to the data line 131, and a second electrode connected to the first node n 1.The second scan signal SCAN 2 is supplied to the pixels P through the second gate line 122. The second scan signal SCAN 2 is generated as a pulse of the gate turn-on voltage VGL. The pulse of the second scan signal SCAN2 defines a scan period Ts. The pulse width of the second scan signal SCAN 2 may be set to be about a horizontal period 1H. The second scan signal SCAN 2 is changed to the gate turn-on voltage VGL later than the first scan signal SCN 1, and is changed to the gate turn-off voltage VGH simultaneously with the first scan signal SCAN 1. The pulse width of the second scan signal SCAN 2 may be set to be smaller than that of the first scan signal SCAN 1. During the initialization period Ti and the emission period Tem, the voltage of the second scan signal SCAN 2 is maintained at the gate off voltage VGH.The second switching element T 2 connects the gate of the driving element DT and the second electrode of the driving element DT in response to the first scan signal SCAN 1 to allow the driving element DT to function as a diode. The second switching element T 2 includes a gate connected to the first gate line 121, a first electrode connected to the second node n 2, and a second electrode connected to the third node N 3.The first scan signal SCAN 1 is supplied to the pixels P through the first gate line 121. The first scan signal SCAN 1 may be generated as a pulse of the gate turn-on voltage VGL. The pulse of the first scan signal SCAN1 defines the initialization period Ti and the sampling period Ts. During the emission period Tem, the voltage of the first scan signal SCAN 1 is maintained at the gate off voltage VGH.The third switching element T 3 supplies a predetermined reference voltage Vref to the first node n 1 in response to an EM signal EM(N). The reference voltage Vref is supplied to the pixels P through the third power supply line 63. The third switching element T 3 includes a gate connected to a third gate line 123, a first electrode connected to the first node n 1, and a second electrode connected to the third power supply line 63. The EM signal EM(N) defines the on / off times of the light emitting element EL.During the sampling period Ts, a pulse of the EM signal EM(N) may be generated as the gate off voltage VGH to block a current path between the first node n 1 and the third power supply line 63 and to block a current path of the light emitting element EL. The EM signal EM(N) may be inverted to the gate off voltage VGH when the second scan signal SCAN 2 is inverted to the gate on voltage VGL, and may be inverted to the gate on voltage VGL after the first scan signal SCAN 1 and the second scan signal SCAN 2 are inverted to the gate off voltage VGH. To accurately express the luminance of low grayscales, the EM signal EM(N) may oscillate between the gate turn-on voltage VGL and the gate turn-off voltage VGH at a predetermined duty cycle during the emission period Tem.The fourth switching element T 4 switches the current path of the light emitting element EL in response to the EM signal EM(N). The fourth switching element T 4 has a gate connected to the third gate line 123. The fourth switching element T 4 has a first electrode connected to the third node N 3 and a second electrode connected to the fourth node N 4.The fifth switching element T 5 is turned on according to the gate-on voltage VGL of the first scan signal SCAN 1 to supply the reference voltage Vref to the fourth node N 4 during the initialization period Ti and the sampling period Ts. During the initialization period Ti and the sampling period Ts, the anode voltage of the light emitting element EL is discharged to the reference voltage Vref. In this case, the light emitting element EL does not emit light because a voltage between the anode and the cathode is lower than the threshold voltage of the light emitting element EL. The fifth switching element T 5 includes a gate connected to the first gate line 121, a first electrode connected to the third power supply line 63, and a second electrode connected to the fourth node N 4.The driving element DT drives the light emitting element EL by adjusting the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n 2, a first electrode connected to the first power supply line 61, and a second electrode connected to the third node N 3. The pixel driving voltage VDD is supplied to the pixels P through the first power supply line 61.In FIG. 12, a pixel circuit according to a second embodiment of the present disclosure includes a light emitting element EL, a plurality of transistors T 11 to T 16 and DT, a capacitor CST, and so on.Each of the transistors T 11 to T 16 and DT may be implemented as a P-channel transistor, but is not limited thereto. The transistors T 11 to T 16 and DT include the switching elements T 11 to T 16 and a driving element DT.A gate signal applied to this pixel circuit includes an (N-1)th scan signal SCAN(N-1), an Nth scan signal SCAN(N), and an EM signal EM(N). The (N-1)th scan signal SCAN(N-1) is synchronized with a data voltage Vdata of an (N-1)th pixel line. The Nth scan signal SCAN(N) is synchronized with a data voltage Vdata of an Nth pixel line. A pulse of the N-th scan signal SCAN(N) is generated with the same pulse width as that of the (N-1)-th scan signal SCAN(N-1), and is generated later than a pulse of the (N-1)-th scan signal SCAN(N-1).The capacitor CST is connected between a first node n 11 and a second node n 12. The pixel driving voltage VDD is supplied to the pixel circuit through the first power supply line 61. The first node n 11 is connected to the first power supply line 61, the first electrode of the third switching element T 13, and the first electrode of the capacitor CST.The second node n 12 is connected to the second electrode of the capacitor CST, the gate of the driving element DT, the first electrode of the first switching element T 11, and the first electrode of the fifth switching element T 15.The first switching element T 11 is turned on according to the gate turn-on voltage VGL of the Nth scan signal SCAN(N) to connect the gate and the second electrode of the driving element DT. The first switching element T 11 includes a gate connected to the second gate line 125, a first electrode connected to the second node n 12, and a second electrode connected to the third node n 13. The Nth scan signal SCAN(N) is supplied to the pixels P through the second gate line 125. The third node n 13 is connected to the gate of the driving element DT, the second electrode of the first switching element T 11, and the first electrode of the fourth switching element T 11.The second switching element T 12 is turned on according to the gate turn-on voltage VGL of the Nth scan signal SCAN(N) to apply the data voltage Vdata to the first electrode of the driving element DT. The second switching element T 12 includes a gate connected to the second gate line 125, a first electrode connected to a fifth node n 15, and a second electrode connected to the data line 131. The fifth node n 15 is connected to the first electrode of the driving element DT, to the first electrode of the second switching element T 12, and to the second electrode of the third switching element T 13.The third switching element T 13 supplies the pixel driving voltage VDD to the first electrode of the driving element DT in response to the EM signal EM(N). The third switching element T 13 includes a gate connected to a third gate line 126, a first electrode connected to the first power supply line 61, and a second electrode connected to the fifth node n 15. The EM signal EM(N) is supplied to the pixels P through the third gate line 126.The fourth switching element T 14 is turned on according to the gate turn-on voltage VGL of the EM signal EM(N) to connect the second electrode of the driving element DT and the anode of the light emitting element EL. The fourth switching element T 14 has a gate connected to the third gate line 126. The fourth switching element T 14 has a first electrode connected to the third node n 13 and a second electrode connected to the fourth node n 14. The fourth node n 14 is connected to the anode of the light emitting element EL, the second electrode of the fourth switching element T 14, and the second electrode of the sixth switching element T 16.The fifth switching element T 15 is turned on according to the gate turn-on voltage VGL of the (N- 1)th scan signal SCAN(N- 1) to connect the second node n 12 to the third power supply line 63 so that the gate of the driving element DT and the capacitor CST are initialized during the initialization period Ti. The fifth switching element T 15 includes a gate connected to the first gate line 124, a first electrode connected to the second node n 12, and a second electrode connected to the third power supply line 63.The (N-1)th scan signal SCAN(N-1) is supplied to the pixels P through the first gate line 124. The initialization voltage Vini is supplied to the pixels P through the third power supply line 63.The sixth switching element T 16 is turned on according to the gate turn-on voltage VGL of the (N- 1)th scan signal SCAN(N- 1) to connect the third power supply line 63 to the anode of the light emitting element EL during the initialization period Ti. During the initialization period Ti, the anode voltage of the light emitting element EL is discharged to the initialization voltage Vini through the sixth switching element T 16. In this case, the light emitting element EL does not emit light because a voltage between the anode and the cathode is lower than the threshold voltage of the light emitting element EL. The sixth switching element T 16 includes a gate connected to the first gate line 124, a first electrode connected to the third power supply line 63, and a second electrode connected to the fourth node n 14.The driving element DT drives the light emitting element EL by adjusting the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n 12, a first electrode connected to the fifth node n 15, and a second electrode connected to the third node n 13.Figs. 13A to 15B are graphs showing stepwise the operation of the pixel circuit shown in Fig. 11. FIG. 13A is a graph showing a path of the current flowing through the pixel circuit during the initialization period Ti. FIG. 14A is a graph showing a path of the current flowing through the pixel circuit during the sampling period Ts. FIG. 15A is a graph showing a path of the current flowing through the pixel circuit during the emission period Tem. The transistors weakly shown in FIGS. 13A, 14A, and 15A are turned off. FIGS. 13B, 14B and 15B are waveforms showing the gate signals applied to the pixel circuit shown in FIG. 11.In FIGS. 13A and 13B, the voltages of the EM signal EM(N) and the first scan signal SCAN 1 during the initialization period Ti are the gate turn-on voltages VGL. The second to fifth switching elements T 2 to T 5 are turned on during the initialization period Ti to discharge the voltages of the first node n 1, the second node n 2, and the fourth node N 4 to the reference voltage Vref. As a result, during the initialization period Ti, the capacitor CST, the gate voltage of the driving element DT, and the anode voltage of the light emitting element EL are initialized to the reference voltage Vref.In FIGS. 14A and 14B, the voltages of the first scan signal SCAN 1 and the second scan signal SCAN 2 during the scan period Ts are the gate on voltages VGL. The first, second and fifth switching elements T1, T2 and T5 are turned on during the sampling period Ts. In this case, the data voltage Vdata is applied to the first node n 1, and the voltage of the second node n 2 is changed to VDD+ Vth. As a result, during the sampling period Ts, the threshold voltage Vth of the driving element DT is sampled, and the second node n 2 is charged with the threshold voltage Vth. The capacitor CST is charged with the data voltage Vdata for which the threshold voltage Vth of the driving element DT is compensated during the sampling period Ts.In FIGS. 15A and 15B, the voltage of the EM signal EM(N) during the emission period Tem is the gate turn-on voltage VGL. The third and fourth switching elements T 3 and T 4 are turned on during the emission period Tem. In this case, the voltage of the first node n 1 is changed to the reference voltage Vref, while the voltage of the second node n 2 is changed to Vref-Vdata+ VDD+ Vth. The light emitting element EL may emit light during the emission period Tem due to the current flowing through the driving element DT through the light emitting element EL.The current flowing through the light emitting element EL may be adjusted according to the gate-source voltage Vgs of the driving element DT. The gate-source voltage Vgs of the driving element DT is Vref-Vdata+ Vth during the emission period Tem.Figs. 16A to 18B are graphs showing stepwise the operation of the pixel circuit shown in Fig. 12. FIG. 16A is a graph showing a path of the current flowing through the pixel circuit during the initialization period Ti. FIG. 17A is a graph showing a path of the current flowing through the pixel circuit during the sampling period Ts. FIG. 18A is a graph showing a path of the current flowing through the pixel circuit during the emission period Tem. The transistors weakly shown in FIGS. 16A, 17A, and 18A are off. FIGS. 16B, 17B and 18B are waveforms showing the gate signals applied to the pixel circuit shown in FIG. 12.In FIGS. 16A and 16B, the voltage of the (N- 1)th scan signal SCAN(N- 1) during the initialization period Ti is the gate on voltage VGL. The fourth and fifth switching elements T 14 and T 15 are turned on during the initialization period Ti, so that the voltages of the second and fourth nodes n 12 and n 14 are discharged to the initialization voltage Vini. As a result, during the initialization period Ti, the capacitor CST, the gate voltage of the driving element DT, and the anode voltage of the light emitting element EL are initialized to the initialization voltage Vini.In FIGS. 17A and 17B, the voltage of the Nth scan signal SCAN(N) during the scan period Ts is the gate on voltage VGL. The first and second switching elements T 11 and T 12 are turned on during the sampling period Ts. In this case, the data voltage Vdata is applied to the fifth node n 15, while the voltage of the second node n 12 is changed to Vdata+ Vth. As a result, during the sampling period Ts, the threshold voltage Vth of the driving element DT is sampled, and the second node n 12 is charged with the threshold voltage Vth. The capacitor CST is charged with the data voltage Vdata for which the threshold voltage Vth of the driving element DT is compensated during the sampling period Ts.In FIGS. 18A and 18B, the voltage of the EM signal EM(N) during the emission period Tem is the gate turn-on voltage VGL. The third and fourth switching elements T 13 and T 14 are turned on during the emission period Tem. The light emitting element EL may emit light during the emission period Tem due to the current flowing through the driving element DT through the light emitting element EL.The current flowing through the light emitting element EL may be adjusted according to the gate-source voltage Vgs of the driving element DT. The gate-source voltage Vgs of the driving element DT is Vdata+ Vth-VDD during the emission period Tem.The present inventors have measured different luminance values of an organic light emitting display device at the same grayscale level and revealed a cause thereof depending on the positions on the screen of the display panel 100. This will be described in conjunction with Figs. 19 to 22.FIG. 19 is a graph showing a position of luminance measurement on the screen AA of the display panel 100 according to the embodiments of the present disclosure. FIG. 20 shows the luminance values based on the gray levels measured at the positions "top", "center", and "bottom" shown in FIG. 19. In FIG. 20, 255G indicates a gray level value of 255 of the pixel data. 127G indicates a gray level value of 277 of the pixel data, and 31G indicates a gray level value of 31 of the pixel data.In FIGS. 19 and 20, the voltage of the shift clock GCLK and the pixel driving voltage VDD output from the driving IC 300 may be changed by the IR drop depending on the positions above, center, and below of the screen AA. The pixel driving voltage VDD and the shift clock GCLK affect the gate-source voltage Vgs and the drain-source voltage Vdas of the driving elements DT. The shift clock GCLK affects the sampling period Ts defined by a scan signal supplied to the gate lines of the pixels P.A sample used in this experiment is an organic light emitting display device in which the VDD and GCLK outputs from the driver IC 300 are fixed. Because the position at the bottom is close to the driver IC 300, the amount of IR drop is small. Because the position is located at the top far from the driver IC 300, the amount of IR drop is the largest. The result of luminance measurement is that the current I of the pixels P is large in the case of a high grayscale level (255G). Consequently, due to a difference in the amount of IR drop, the luminance decreases toward the upper position. However, the current of the pixels P is small in the case of a low gray level (31G). Consequently, the effect of the IR drop is reduced, and luminance in a direction away from the driver IC 300 tends to increase due to other causes. In FIG. 20, the luminance of the low grayscale level (31G) measured at the lower position close to the driver IC 300 is 4.80 [Nit], while the luminance of the lower grayscale level (31G) measured at the upper position far from the driver IC 300 is increased to 6.20 [Nit].The inventors of the present invention have confirmed that, in the case of low gray level levels, the difference in the sampling period Ts has a greater effect on luminance unevenness than the effect of IR drop of VDD. The sampling period Ts is defined by the pulse width of the sampling signal. However, due to an RC delay of the shift clock GCLK(n) input to the gate driver unit 120, a delay of the shift clock waveform causes a delay of the scan signal. As a result, at low grayscale levels, the gate-source voltage Vgs of the driving element increases in the pixels far from the driving IC 3, and thus the luminance increases in the pixels far from the driving IC 300 more than in pixels near the driving IC 300.In FIG. 21, the waveforms of the scan signals SCAN(up) and SCAN(down) supplied to the gate lines of the position up and the position down on the screen AA have different RC delays. Because the resistance and parasitic capacitance of the shift clock lines 51 at the top position are large, the RC delay of the shift clock GCLK(n) increases. Consequently, the delay of the waveform of the scan signal SCAN(upper) supplied to the gate line at the upper position increases. As a result, the sampling period Ts(up) actually applied to the pixels at the top position is smaller than the sampling period Ts(down) at the bottom position.FIG. 22 is a graph showing the change in gate-source voltage of a driving element measured according to the positions and the gray level levels on a screen.In FIG. 22, for high gray level levels HIGH GRAY, the amount of current flowing through the pixels P is large, and thus the amount of IR drop from VDD to the maximum in a direction further from the driver IC 300 increases. Therefore, for high gray level HIGH GRAY, a decrease in luminance is larger than an increase in luminance due to a decrease in the sampling period Ts, and the measurement result thus shows that the luminance decreases in a direction further from the position above.For low gray level levels LOW GRAY, the amount of current flowing through pixels P is small, thus minimizing the IR drop of VDD. For the low gray level levels LOW GRAY, an increase in luminance due to a decrease in the sampling period Ts is greater than a decrease in luminance due to the IR drop of VDD in a direction further from the driver IC 300. In the result of luminance measurement shown in FIG. 20, it was confirmed that luminance tends to increase toward the upper position far from the driver IC 300. Although the effect of the IR drop of VDD is minimized in a screen AA to which an internal compensation technique is applied, luminance may increase in pixels remote from the driver IC 300 at low grayscale levels.According to the present disclosure, the voltage of the pulse and / or the pulse width of the shift clock GCLK(n), i.e., the gate on voltage VGL, is changed in real time in consideration of the RC delay scan result of the shift clock GCLK(n) according to the position on the screen AA. The pulse width and voltage of the scan signal defining the scan signal are substantially the same as those of the shift clock GCLK. According to the present disclosure, the pulse width or the voltage of the scan signal is changed by changing the voltage of the pulse of the shift clock GCLK, i.e., the gate on voltage VGL, or the pulse width of the shift clock GCLK.According to the present disclosure, by modulating the voltage of the pulse and / or the pulse width of the shift clock GCLK(n), control is performed for each position on the screen AA so that the sampling periods of the pixels of the entire screen are the same. As a result, the problem of luminance unevenness at the low grayscale levels, which cannot be solved only using a technique for compensating the IR drop of the pixel driving voltage VDD, can be solved according to the present disclosure.FIG. 23 is a diagram showing a sensing device according to a first embodiment of the present disclosure.In FIG. 23, the sensing device includes a feedback transistor M 9 connected to a gate driving unit 120, a feedback line 52 connected to the feedback transistor M 9, and a sensing unit 230.The gate driving unit 120 includes the stages ST 1 to ST(n) connected in cascade.The feedback transistor M 9 is connected to each of the stages ST 1 to ST(n), or is connected to at least two stages spaced apart from each other by a predetermined distance. As shown in FIG. 24, the feedback transistor M 9 is turned on according to the gate on voltage VGL of the Q node to connect a shift clock line 51 to the feedback line 52. For example, as shown in FIGS. 19 and 24, the feedback transistor M 9 may be connected to a stage connected to a gate line at the upper position and a stage connected to a gate line at the lower position.The sensing unit 230 compares the feedback signals or voltages GCLKOFB and GCLKEFB in the feedback line 52 with a predetermined reference voltage REF, and detects a voltage interval having voltages less than or equal to the reference voltage level REF as a pulse width from the feedback voltages GCLKOFB and GCLKEFB.Whenever the shift clock GCLK(n) is input to the shift clock line 51 while the Q node is being charged with the gate turn-on voltage VGL, the sensing unit 230 may measure the pulse widths of the feedback signals or the feedback voltages GCLKOFB and GCLKEFB of the shift clock at a corresponding position and sense an RC delay of the shift clock GCLK(n). Accordingly, the sensing unit 230 may sense the amount of RC delay of the shift clock GCLK(n) for each position on the screen AA in real time. In other words, the feedback signals received by the feedback line 52 are based on the shift clock GCLK(n) input to the shift clock line 51.The timing controller 303 may determine an actual sampling period Ts applied for each position on the screen AA using the output signal of the sampling unit 230, i.e., the pulse width of the shift clock GCLK(n) actually applied to the gate lines of the screen AA. The timing controller 303 may perform control so that the sampling periods TS of all pixels of the screen AA are equal by changing the voltage VGL of the pulse and / or the pulse width of the shift clock GCLK(n) for each position on the screen AA based on the pulse width of the shift clock GCLK(n) for each position input from the sampling unit 230.FIG. 24 is a circuit diagram specifically showing an Nth stage in the gate driver unit shown in FIG. 23.In FIG. 24, the feedback transistor M 9 is turned on according to the gate turn-on voltage VGL of the Q node at a corresponding stage to connect the shift clock line 51 to the feedback line 52.The feedback transistor M9 shares the Q node with the sixth transistor M6 in the corresponding stage to sample the pulse width of the shift clock Gout(n) actually applied to the gate lines. The feedback transistor M 9 includes a gate connected to the Q node, a first electrode connected to the shift clock line 51, and a second electrode connected to the feedback line 52.The feedback transistor M9 should be connected to a separate feedback line 52 which is separate from the output node of the stage so that the output nodes of the stages are not shorted.FIGS. 25 and 26 are graphs of comparing sensing operations according to the presence or absence of a ninth transistor shown in FIG. 24.In FIG. 25, the feedback transistor M 9 is turned on to supply the voltage of the shift clock GCLK(n) to the feedback line 52 only when the voltage of the Q node is the gate-on voltage VGL. In other stages, the feedback transistors M 9 connected to the other stages at other positions are turned off because the voltage of the Q node is the gate-off voltage VGH. For example, when the feedback transistor M 9 connected to the first stage ST 1 is turned on to supply the voltage of the shift clock GCLK input to the first stage STA to the feedback line 52, the feedback transistors M 9 connected to the other stages ST 2 to ST(n) are turned off.In order to prevent the output nodes through which the gate signals Gout(n) are output from the stages ST 1 to ST(n) through the feedback line 52 from being short-circuited, the feedback transistors M 9 should be connected to the feedback line 52 that is separated from the output nodes. The sensing device using the feedback transistor M 9 may sense the RC delay of the shift clock GCLK(n) in an active interval (see FIG. 30 ) in which an input image is displayed on the screen AA in real time.When a feedback transistor M9 shares the output node with the sixth transistor M6, as shown in Fig. 26, the output nodes of all stages to which the feedback transistor M9 is connected are short-circuited by the feedback line 52, and thus the gate signals cannot be sequentially outputted.The sensing device of the present disclosure may use a pixel array test circuit formed in the display panel 100. An automatic probe inspection process can inspect signal line defects or thin film pattern defects of a substrate by performing electrical tests on the wirings of the pixel array using an AP inspection circuit formed in the display panel 100 before a process of mounting the driver IC 300. According to the present disclosure, an RC delay of an enable signal corresponding to the shift clock GCLK(n) may be sampled in real time using an AP test circuit in the display panel 100 to which the driver IC 300 is attached.FIG. 27 is a diagram showing an AP test circuit in a display panel connectable to a sensing device of the present disclosure.In FIG. 27, the AP test circuit may be disposed in a surrounding area of the display panel 100 that is present outside the screen AA on which an image is displayed. In FIG. 27, "DL" indicates the data lines connected to the pixels P.The AP test circuit includes an AP pad (APPAD), the AP lines 271 to 274, and an AP switching element APTR.The AP lines include an enable line 271, a first test data line 272, a second test data line 273, and a third test data line 274. The AP pads APPAD and the AP switching elements APR may be disposed on opposite sides to each other, and a screen AA displays an image on the display panel 100. For example, the AP pads APPAD may be disposed closer to the driver IC 300. In this case, the AP switching elements APR may be disposed in an upper casing region far from the mounting position of the driver IC 300.The AP switching elements APR may include a first transistor MA 1, a second transistor MA 2, and a third transistor MA 3. The transistors MA 1, MA 2, and MA 3 may be implemented as P-channel TFTs like the transistors T 1 to T 16 (see FIGS. 11 and 12 ) constituting the pixel array. The first transistor MA 1 includes a gate connected to the enable line 271, a first electrode connected to the first test data line 272, and a second electrode connected to a first data line. The first data line may be connected to the red sub-pixels. The second transistor MA 2 includes a gate connected to the enable line 271, a first electrode connected to the second test data line 273, and a third electrode connected to a second data line. The second data line may be connected to the green sub-pixels. The third transistor MA 3 includes a gate connected to the enable line 271, a first electrode connected to the third test data line 274, and a second electrode connected to a third data line. The third data line may be connected to the blue sub-pixels.In an automatic probe testing process, the first transistor MA1 supplies a first test data signal to the first data line in response to an enable signal EN. The first test data signal may be supplied to a test device of the first test data line 272 through a needle in the automatic probe test process. The second transistor MA 2 supplies a second test data signal to the second data line DL in response to an enable signal EN. In the automatic probe test process, the second test data signal is supplied to a test device of the second test data line 273 through a needle. The third transistor MA 3 supplies a third test data signal to the third data line DL in response to an enable signal EN. The third test data signal is supplied to a test device of the third test data line 274 through a needle in the automatic probe test process.The test apparatus may supply an enable signal and an RGB test data signal through the AP pads APPAD, and may supply a gate test signal through gate pads (not shown) to the gate lines. In the automatic probe inspection process, whether the pixel array has a defect may be inspected without attaching the driver IC (DIC) to the display panel 100.As shown in FIG. 28, the sensing device of the present disclosure may be connected to the AP test circuit when the driver IC 300 is mounted on the display panel 100.In FIGS. 28 and 29, the scanning device includes the scanning unit 230 which is connected to the data line via a multiplexer MUX.The multiplexer MUX connects the output buffer AMP of the data driving unit 306 to the data line DL when the data voltage Vdata is output from the data driving unit 306, that is, during an active interval AT of FIG. 30, the multiplexer MUX connects the sensing unit 230 to the data line DL during a blanking period during which the data voltage Vdata is not output from the data driving unit 306, for example, during a vertical blanking period VB of FIG. 30.The driver IC 300 supplies the data voltage Vdata of the pixel data to the data line DL during the active interval AT. The driver IC 300 supplies a signal output from the timing controller 303 during the vertical blanking period VB to the enable line 271 and the test data line 272 to 274 in the form of a pulse signal. A pulse signal of the gate-on voltage VGL for turning on the AP switching elements MA1 to MA3 is applied as the enable signal EN to the enable line 271, and a pulse signal is applied to the test data lines 272 to 274. These pulse signals may be generated as pulse signals that swing between the gate turn-on voltage VGL and the gate turn-off voltage VGH like the shift clock GCLK(n). These pulse signals are supplied through the timing controller 303 and the level shifter 307 to the enable line 271 and the test data lines 272 to 274.The AP switching elements MA1 to MA3 are turned on according to the gate turn-on voltage VGL of the enable signal EN during the vertical blanking period VB to connect the test data lines 272 to 274 to the data line DL. As a result, the feedback signals for the pulse signals applied to the test data lines 272 to 274 during the vertical blanking period VB are supplied through the data line DL to the sampling unit 230. In other words, the feedback signal received through the data line DL is based on the pulse signals applied to the test data lines 272 to 274.The sensing unit 230 compares the voltage of each of the feedback signals received through the data line DL during the vertical blanking period VB with the predetermined reference voltage REF, and detects a voltage period or a voltage interval of the voltage of the feedback signal that is less than or equal to the data reference voltage REF as the pulse width.The timing controller 303 receives the raw data output from the sampling unit 230 during the vertical blanking period VB. The timing controller 303 knows the pulse widths of the pulse signals supplied to the test data lines 272 to 274 using register set values. The raw data output from the sensing unit 230 indicates a pulse width value delayed by reflecting an RC delay due to the resistance and parasitic capacitance of the test data lines 272- 274. Accordingly, the timing controller 303 may compare the pulse width of the pulse signal generated during the vertical blanking period VB and the pulse width of the feedback signal received through the data line DL and in which the RC delay is reflected, and may determine a deviation of the RC delay of the pulse signal on the screen AA.The pulse signal output from the timing controller 303 has no RC delay, while the feedback signal received from the sampling unit 230 has the maximum amount of RC delay. In order to compensate for the deviation of the RC delay of the pulse signal on the screen AA, the timing controller 303 gradually increases the pulse width of the shift clock GCLK(n) or the timing controller 303 gradually decreases the pulse voltage of the shift clock GCLK(n) in a direction toward the top position that is farthest from the driver IC 300. Accordingly, during the vertical blanking period VB, the timing controller 303 may perform the control by modulating the pulse voltage and / or the pulse width of the shift clock GCLK(n) based on the deviation of the RC delay of the screen AA sampled by the feedback signals of the pulse signals so that the sampling periods of all pixels of the screen AA are equal. The pulse voltage of the shift clock GCLK(n) is the gate turn-on voltage VGL.The sampling device shown in FIGS. 28 and 29 can measure the RC delay of the shift clock Gout(n) without a separate design change because the sampling device uses an AP test circuit. Specifically, this sampling device measures the RC delay of the shift clock Gout(n) every frame in real time, and thus it is possible to compensate for a state change of the display panel 100 such as pixel degradation in real time.FIG. 30 is a diagram specifically showing a vertical blanking period and an active interval in one frame period.In Fig. 30, a frame period is divided into an active interval in which pixel data is input and a vertical blanking period VB in which pixel data is not input.During the active interval AT, the pixel data corresponding to a frame to be written in all pixels on the screen AA of the display panel 100 is received by the driver IC 300 and written into the pixels P.The vertical blanking period VB is a blanking period that is between the active interval AT of an (N-1)-th frame period (N is a natural number) and the active interval AT of an N-th frame period and in which no pixel data is received by the driver IC 300. The vertical blanking period VB includes a vertical synchronizing time VS, a vertical front blanking interval FP and a vertical rear blanking interval BP.The vertical blanking period VB is a time period from the falling edge of the last pulse in a data enable signal DE received during the (N-1)th frame period to the rising edge of the first pulse in a data enable signal DE received during the Nth frame period. The start point of the Nth frame period is a rising timing of the first pulse of the data enable signal DE.The vertical synchronizing signal VSYNC defines a frame period. The horizontal synchronizing signal HSYNC defines a horizontal period (1H). The data enable signal DE defines a valid data period including the pixel data to be displayed on one screen. A pulse of the data enable signal DE is synchronized with the pixel data to be written in the pixels of the display panel 100. A pulse period of the data enable signal DE is a horizontal period (1H).Fig. 31 is a waveform diagram showing a sampling method of one sampling period for each position on a screen.In FIG. 31, the scan signals SCAN(top) and SCAN(bottom) define the scan periods TS(top) and TS(bottom) of the pixels. The pulse width of the scan signals SCAN(up) and SCAN(down) is determined according to the pulse width of the shift clock GCLK.The waveform of the shift clock GCLK is delayed due to the resistance and parasitic capacitance of the shift clock line 51 according to a position on the shift clock line 51. The shift clock GCLK applied to the shift clock line 51 in the display panel 100 causes delay of the waveforms of the scan signals SCAN(up) and SCAN(down) depending on the position on the screen AA. Accordingly, the deviation of the RC delay of the shift clock GCLK causes a difference in the sampling periods TS(up) and TS(down) between the positions on the screen AA.The sensing unit 230 receives the shift clock GCLK through a line on the display panel 100 as a feedback input or signal, and compares the received shift clock GCLK with the predetermined reference voltage REF. The sampling unit 230 may output the raw data, which is digital data, by an analog-to-digital converter (hereinafter referred to as an "ADC").The sampling unit 230 converts a low level interval of the feedback input voltage, i.e., the feedback signal voltage less than or equal to the reference voltage REF, into a first logic value by the ADC, and converts a high level interval of the feedback input voltage, i.e., the feedback signal voltage higher than the reference voltage REF, into a second logic value to generate a one-bit signal indicating a pulse width. The first logical value may be HIGH (= 1) or LOW (= 0), and the second logical value may be opposite to the first logical value.The sampling unit 230 may convert the variation of the pulse width caused by the RC delay of the shift clock GCLK into digital data by counting the low level logic interval as a clock CLK in the one-bit signal. Accordingly, the sampling unit 230 can accurately quantify the pulse width deviation of the shift clock GCLK for each screen position in one clock CLK period.According to the present disclosure, the RC delay of the shift clock GCLK for each position in the screen AA is sampled in real time, and the voltage and / or the pulse of the shift clock GCLK are automatically adjusted based on the sampling result. Accordingly, according to the present disclosure, it is possible to perform self-compensation of the sensing periods TS(upper) and TS(lower) adaptively to a condition change of the display panel 100 even though the conditions such as the ambient temperature and the element degradation of the display panel 100 are changed.FIGS. 32 to 36 are graphs showing a screen position-based sampling period control method according to a first embodiment of the present disclosure.FIG. 32 is a waveform diagram showing an example of a pulse width modulation method of a shift clock GCLK for reducing a variation of a sampling period Ts in each of the pixels P of the screen AA.In FIG. 32, the timing controller 303 may receive the raw data from the sensing unit 230 and determine a difference between the sensing periods TS for the positions on the screen AA.The timing controller 303 may change the pulse width of the sampling signal supplied to the pixels based on a result obtained by sampling the sampling period Ts in real time. In response to the raw data received from the sampling unit 230, the timing controller 303 decreases the pulse width of the shift clock GCLK synchronized with the sampling signal supplied to the pixels close to the driver IC 300 to be smaller than the pulse width of the shift clock GCLK synchronized with the sampling signal supplied to the pixels far from the driver IC 300.The position of a pixel with the smallest sampling period Ts may be the furthest from the driver IC 300 and may be the position above the screen AA where the RC delay of the shift clock GCLK is the greatest. Conversely, the position of a pixel with the largest sampling period Ts may be closest to the driver IC 300, and may be the position below the screen AA where the RC delay of the shift clock GCLK is the smallest. The timing controller 303 gradually decreases the pulse width of the shift clock GCLK in a direction from the top position of the screen AA to the bottom position of the screen AA. The pulse width of shift clock GCLK defines the sampling period Ts. Accordingly, by receiving a sampling result of the sampling period input from the sampling unit 230 and changing the pulse width of the shift clock GCLK, the timing controller 303 can execute the control such that the sampling periods TS of all pixels of the screen AA are equal.The level shifter 307 converts the low-level voltage of the shift clock GCLK input from the timing controller 303 into the gate-on voltage VGL, converts the high-level voltage of the shift clock GCLK into the gate-off voltage VGH, and supplies the shift clock GCLK to the shift clock line 51. When the shift clock GCLK is input through the shift clock line 51, the gate driving unit 120 outputs a gate signal to the gate lines. The gate signal includes a scan signal defining the scan period Ts.The timing controller 303 may change the pulse width of the shift clock GCLK using a look-up table (LUT).FIGS. 33 and 34 are diagrams showing a device that modulates the pulse width of a shift clock GCLK using the look-up table LUT and the sampling unit 230.In FIGS. 33 and 34, the timing controller 303 may include the look-up table LUT.The raw data output from the sampling unit 230 indicates the pulse width of the shift clock GCLK in which the RC delay is reflected. In FIG. 34, "SCAN" represents the input and output of the scan unit 230. The x-axis represents a screen position, while the y-axis represents the raw data output from the sampling unit 230.The raw data has the smallest value at the top position because the low level interval of the shift clock GCLK is the smallest at the top position where the RC delay is the largest. The raw data has the largest value at the bottom position because the low level interval of the shift clock GCLK is the largest at the bottom position where the RC delay is the smallest. Accordingly, the raw data input from the sampling unit 230 to the look-up table LUT has a smaller value because the raw data is farther from the driver IC 300.As shown in FIG. 34, the look-up table LUT receives the raw data from the sampling unit 230 and outputs a compensation pulse width. In a diagram defining the input and output of the look-up table LUT, the x-axis represents the raw data input to the look-up table LUT, while the y-axis represents a compensation pulse width output from the look-up table LUT.When the raw data is input from the sampling unit 230, the look-up table LUT outputs a compensation pulse width indicated by the value of the raw data. Because the pulse of the shift clock GCLK has substantially the same pulse width as the scan signal SCAN, the sampling periods TS of the pixels P are sampled. Accordingly, the look-up table LUT outputs a compensation pulse width in response to the sampling periods TS of the pixels P sampled by the sampling unit 230 in real time to execute the control so that the sampling periods TS of all the pixels P of the screen AA are equal. The timing controller 303 may generate the shift clock GCLK having the compensation pulse width output from the look-up table LUT.Fig. 35 is a waveform diagram showing an example of a shift clock having a pulse width modulated for each position on a screen during one frame period.In FIG. 35, during the active interval AT defining the vertical period of the screen AA in one frame period, the timing controller 303 changes the pulse width of the shift clock GCLK so that the sampling periods TS of the pixels P are equal. The shift clock GCLK further increases in one direction from the driver IC 300. The pulse width of the shift clock GCLK is smallest at the bottom position, for example, and increases in a direction toward the top position, as shown in FIGS. 32 and 35.Fig. 36 is a waveform diagram showing the sampling periods A, B and C of the positions on the screen AA and the shift clock GCLK applied to the pixels P. In FIG. 36, an upper waveform is an output waveform of the shift clock GCLK measured at the output node of the level shifter 307 having no RC delay. A lower waveform is a waveform of the shift clock GCLK applied to the shift clock line 51 and in which the RC delay is reflected. A, B and C indicate the sampling periods TS for the screen positions corresponding to the change in the pulse width of the shift clock GCLK.As seen in FIG. 36, according to the present disclosure, by adaptively changing the pulse width of the shift clock GCLK based on a result of sampling the feedback signal in real time, it is possible to perform control so that the sampling periods A, B, and C of all the pixels P of the screen AA are substantially equal even when the deviation of the RC delay of the shift clock GCLK on the display panel 100 is large. Accordingly, according to the present disclosure, it is possible to reduce an increase in luminance in a direction further from the driver IC 300 in the screen AA.By changing the gate-on voltage VGL of the shift clock GCLK based on a result of sampling the feedback signal in real time, the timing controller 303 can accurately sample the threshold voltage Vth of the driving element DT in all the pixels P of the screen AA even if the sampling periods TS are insufficient.FIGS. 37 to 42 are graphs showing a screen position-based sampling period control method according to a second embodiment of the present disclosure.FIG. 37 is a waveform diagram showing a change in the gate turn-on voltage VGL applied to the display panel 100 along the time axis. The waveform of FIG. 37 indicates the input of the gate turn-on voltage VGL to the level shifter 307.In FIG. 37, when the gate turn-on voltage VGL of the shift clock GCLK decreases, the turn-on current of the switching elements T 2 and T 11 increases as shown in FIGS. 14A and 17A. As a result, in FIGS. 14A and 17A, the voltages of the second nodes n 2 and n 12 quickly reach the threshold voltage Vth of the driving element DT, so that the threshold voltage Vth of the driving element DT can be sampled even if the sampling period Ts is insufficient. In addition, when the gate turn-on voltage VGL of the shift clock GCLK decreases, the rising edge time, i.e., the time taken to reach the gate turn-on voltage VGL decreases, and thus the sampling period Ts may increase. Accordingly, according to the present disclosure, by decreasing the gate on voltage VGL of the shift clock GCLK, it is possible to sample the threshold voltage Vth of the driving element DT for all pixels of the screen AA within the sampling period Ts even if there is a deviation in the sampling period Ts for each position on the screen AA.The timing controller 303 gradually decreases (or increases) the gate on voltage VGL of the shift clock GCLK within one frame period. The amount of RC delay of the shift clock GCLK increases, and thus the sampling period in one direction further from the driver IC 300 decreases. Consequently, the gate turn-on voltage VGL may be the lowest voltage V 1 at the upper position. Because there is no RC delay of the shift clock GCLK at a position closest to the driver IC 300, the gate turn-on voltage VGL at the position below may be the highest voltage V 2. In this example, a voltage difference ΔVGL of the gate turn-on voltage VGL input to the level shifter 307 is a maximum of V2-V1 within one frame period.Depending on the scanning direction of the screen AA, the gate turn-on voltage VGL may gradually increase or decrease within one frame period. When the pixels of the screen AA are scanned from the lower position to the upper position, the gate turn-on voltage VGL may gradually decrease from V2 to V1 during a frame period as shown in FIG. 37, and the change may be performed in the same manner for each frame. When the pixels of the screen AA are scanned from the upper position to the lower position, the gate turn-on voltage VGL may gradually increase from V 1 to V 2 during a frame period, and the change may be performed in the same manner for each frame.FIG. 38A is a waveform diagram showing a shift clock GCLK measured at an output node of the level shifter 307. FIG. 38B is a waveform diagram showing a waveform of the shift clock GCLK in which an RC delay is reflected when the shift clock GCLK is applied to the shift clock line 51 of the display panel 100 as shown in FIG. 38A.In FIGS. 38A and 38B, the timing controller 303 may receive the raw data from the sensing unit 230 and determine a difference between the sensing periods TS for the positions on the screen AA.The timing controller 303 performs control so that the gate on voltage VGL of the shift clock GCLK synchronized with a scan signal supplied to the pixels having the smallest scan period Ts is the lowest voltage based on the result of sampling the scan period Ts in real time. The timing controller 303 performs control so that the gate on voltage VGL of the shift clock GCLK synchronized with a scan signal supplied to the pixels having large sampling periods Ts is a relatively high voltage.The position of a pixel with the smallest sampling period Ts may be the furthest from the driver IC 300 and may be the position above the screen AA where the RC delay of the shift clock GCLK is the greatest. Conversely, the position of a pixel with the largest sampling period Ts may be closest to the driver IC 300, and may be the position below the screen AA where the RC delay of the shift clock GCLK is the smallest. The timing controller 303 gradually decreases the gate on voltage VGL of the shift clock GCLK in a direction from the bottom position of the screen AA to the top position of the screen AA. The timing controller 303 receives a result of sampling the sampling period input from the sampling unit 230 and changes the gate on voltage VGL of the shift clock GCLK. As a result, the threshold voltage Vth of the driving element DT can be sampled within the sampling period Ts, and the sampling periods TS of all pixels of the screen AA can be the same as shown in FIG. 38B.The timing controller 303 may change the gate on voltage VGL of the shift clock GCLK using the look-up table LUT and the DAC.FIGS. 39 and 40 are diagrams showing a device that modulates the gate on voltage of the shift clock using a look-up table and a sampling unit.In FIGS. 39 and 40, the driver IC 300 may further include a DAC connected between the timing controller 303 and the level shifter 307. The timing controller 303 may include a look-up table LUT.The sampling unit 230 converts a feedback signal received through the feedback line 52 into digital data by an ADC, and outputs the raw data. The raw data output from the sampling unit 230 indicates the pulse width of the shift clock GCLK in which the RC delay is reflected. The raw data has the smallest value at the top position because the low level interval of the shift clock GCLK is the smallest at the top position where the RC delay is the largest. The raw data has the largest value at the bottom position because the low level interval of the shift clock GCLK is the largest at the bottom position where the RC delay is the smallest. Accordingly, the raw data input from the sampling unit 230 to the look-up table LUT has a smaller value because the raw data is farther from the driver IC 300.Because the pulse of the shift clock GCLK has substantially the same pulse width as the scan signal SCAN, the sampling periods TS of the pixels P are defined.As shown in FIG. 40, the look-up table LUT receives the raw data from the sampling unit 230, and outputs the VGL data defining the voltage level of the gate turn-on voltage VGL. In a diagram defining the input and output of the look-up table LUT shown in FIG. 40, the x-axis represents the raw data input from the sampling unit 230 to the look-up table LUT, while the y-axis represents the VGL data output from the look-up table LUT. When the raw data is input from the sampling unit 230, the look-up table LUT outputs the VGL data indicated by the value of the raw data.The DAC converts the VGL data input from the look-up table LUT into an analog voltage. The analog voltage includes a high level voltage and a low level voltage that is lower than the high level voltage. The low level voltage has a voltage level within a voltage range corresponding to a data range of the VGL data output from the look-up table.The level shifter 307 converts the low level voltage of an input voltage received from the DAC into a variable gate turn-on voltage VGL. The level shifter 307 outputs a voltage closer to V 1 when the low-level voltage of the input voltage is lower, and outputs a voltage closer to V 2 when the low-level voltage of the input voltage is higher. The level shifter 307 converts the high level voltage of the input voltage into the gate off voltage VGH that is higher than V 2, and supplies the gate off voltage VGH to the shift clock line 51. When the shift clock GCLK is input through the shift clock line 51, the gate driving unit 120 outputs a gate signal to the gate lines. The gate signal includes a scan signal defining the scan period Ts.FIGS. 41 and 42 are diagrams illustrating a gate turn-on voltage having a voltage level that varies depending on a screen position.In Fig. 41, the vertical count of the left column represents a pixel row number of the vertical resolution.In Figs. 41 and 42, A, B and C are the sampling periods TS for the positions on a screen. The gate turn-on voltage VGL of the scan signal applied to the pixels P varies depending on the position on the screen AA. The gate turn-on voltage VGL of the scan signal is substantially the same as the gate turn-on voltage VGL of the shift clock GCLK. According to the present disclosure, by changing the gate turn-on voltage VGL of the shift clock GCLK based on a feedback signal according to a sampling period sampled in real time for each positioning of the screen AA, the pulse width and the gate turn-on voltage VGL of the sampling signal are changed.The gate turn-on voltage VGL applied to the pixels at the position farthest from the driver IC 300 at the top is the lowest voltage V 1. The gate turn-on voltage VGL applied to the pixels at the lower most position in the driver IC 300 is a relatively high voltage V 2. The gate turn-on voltage VGL of the scan signal may gradually decrease in a direction from the bottom position of the screen AA to the top position of the screen AA. In FIG. 41, V1 and V2 may be -8.00 V and -7.50 V, respectively. However, the present disclosure is not limited thereto.According to the present disclosure, by adaptively changing the gate on voltage VGL of the shift clock GCLK based on a result of sampling a feedback signal in real time, it is possible to minimize the deviations of the sampling periods A, B, and C for all pixels P of the screen AA even if a deviation of the RC delay of the shift clock GCLK in the display panel 100 is significantly large. Accordingly, according to the present disclosure, it is possible to reduce an increase in luminance in a direction further from the driver IC 300 in the screen AA.According to another embodiment of the present disclosure, by changing the pixel driving voltage VDD depending on the grayscale levels as well as changing the voltage and / or the pulse width of the scan signal or the shift clock for each position on the screen AA, it is possible to further improve the uniformity of luminance.FIG. 43 is a graph showing an example in which the pixel driving voltage VDD varies depending on the gray level.In FIG. 43, in the case of the high grayscale level of 255G in the organic light emitting display device, the amount of IR drop of VDD increases because the amount of current flowing through the pixels P is large. At the high gray level of 255G, the amount of IR drop of VDD increases in a direction toward the top position furthest from the driver IC 300. At the high gray level of 255G, the deviation of the amount of IR drop on the screen AA is large.In order to compensate for the deviation of the amount of IR drop from VDD, the power supply unit 304 increases the voltage VDD in a direction toward the upper position as shown in the upper diagram of FIG. 43 under the control of the timing controller 303. The timing controller 303 may control the voltage output from the power supply unit 304 using the gain of the VDD. The timing controller 303 may increase the voltage VDD by increasing the gain multiplied by the VDD and decrease the voltage VDD by decreasing the gain.At the average gray level of 127G, the amount of IR drop of VDD increases in a direction toward the position furthest from the driver IC 300 at the top. The deviation of the amount of IR drop on the screen AA is smaller at the average gray level of 127G than at the high gray level of 255G. In order to compensate for the deviation of the amount of IR drop of the VDD, the power supply unit 304 increases the voltage VDD in a direction toward the upper position as shown in the middle diagram of FIG. 43 under the control of the timing controller 303. The timing controller 303 may control the voltage output from the power supply unit 304 using the gain of the VDD. The variable range of the gain is set to be smaller at the average gray level of 127G than at the high gray level of 255G.At the high gray level of 255G and the medium gray level of 127G, the VDD output from the power supply unit 304 varies within one frame period. Accordingly, the gain used to adjust the voltage VDD varies within a frame period at the high gray level of 255G and the medium gray level of 127G.In the case of the low grayscale level of 0G in the organic light emitting display device, the amount of IR drop of the VDD is small because the amount of current flowing through the pixels P is small. Particularly, in the case of a gray level 0 (0G), the IR drop of the VDD is minimized. At the low gray level of 0G, the VDD output from the power supply unit 304 does not vary. Accordingly, in the case of the low gray level of 0G, the gain is set to a specific value.FIG. 44 is a luminance measurement result graph showing improvement in luminance uniformity of a screen at higher grayscale levels when the pixel driving voltage (VDD) and the gate turn-on voltage (VGL) are modulated in the same manner as an embodiment of the present disclosure. FIG. 45 is a luminance measurement result graph showing improvement in luminance uniformity of a screen at lower grayscale levels when the pixel driving voltage (VDD) and the gate turn-on voltage (VGL) are modulated in the same manner as an embodiment of the present disclosure. FIG. 46 is a graph showing luminance measurement positions of FIGS. 44 and 45 on a screen. In Figs. 44 and 45, x and y are the xy color coordinate values.In Figs. 44 to 46, the inventor of the present invention has measured the luminance (Nit) and the color coordinates of the first and second target samples at nine positions P1 to P6 of the screen.In FIGS. 44 and 45, "VDD and VGL fixation" represents a first target sample (a comparative sample). "VDD+ VGL modulation" represents a second target sample (a sample to which the present disclosure has been applied). The first and second target samples are display panels of the organic light emitting display device. FIG. 44 shows the luminance and color coordinates measured at nine positions P1 to P9 when a white image pattern of the high gray level of 255G is displayed on a screen. FIG. 44 shows the luminance and color coordinates measured at the nine positions P1 to P9 when a high gray level image pattern of 255G is displayed on a screen. Fig. 45 shows the luminance and color coordinates measured at nine positions P1 to P9 when a low gray level image pattern of 31G is displayed on a screen.For the first target sample, the gate on voltage VGL of the scan signal and the pixel driving voltage VDD were set regardless of the position and the gray level of the screen.For the second target sample, the pixel driving voltage VDD varies depending on the positions and the gray level on the screen AA as shown in FIG. 43. For the second target sample, moreover, the gate turn-on voltage VGL of the scan signal varies depending on the positions and the gray level on the screen AA in the same manner as shown in Figs. 37 to 42. The luminance was measured at nine positions P 1 to P 6 of a sample to be used for luminance measurement.As can be seen from FIG. 44, the uniformity of luminance on the screen AA in the case of a comparative example at the high gray level (VDD and VGL fixation) is 85.30 %. On the other hand, in the case of the present disclosure (VDD+VL modulation), the uniformity of luminance was increased to 95.02%. The uniformity of luminance is a value obtained by dividing a minimum luminance value MIN by a maximum luminance value MAX.As can be seen from FIG. 45, in the case of a comparative example, the uniformity of luminance on the screen AA is at the low grayscale level (VDDu. VGL fixation) 71.39%. On the other hand, in the case of the present disclosure (VDD+VL modulation), the uniformity of luminance was increased to 95.05%. In particular, according to the present disclosure, it was possible to obtain an image enhancement effect in which luminance uniformity for the grayscale levels was almost similar.The display device and its driving method according to the present disclosure may be described as follows.The display device of the present disclosure includes a display panel in which the data lines and the gate lines cross each other and in which the pixels are arranged in a matrix form; a gate driving unit formed on the display panel and configured to supply a scan signal to the gate lines; a shift clock line formed on the display panel and configured to supply a shift clock to the gate driving unit; a sensing device configured to receive a feedback signal for a pulse signal supplied to the display panel and sense a pulse width of the scan signal; and a driving device configured to supply a data voltage to the data lines and generate the shift clock. The driving means changes one or both of a pulse width of the shift clock and a pulse voltage of the shift clock for each screen position of the display panel in response to a pulse width of the feedback signal sampled by the sampling means in real time.The pulse voltage of the shift clock and a pulse voltage of the scan signal are the same gate turn-on voltage. Each of the pixels includes one or more pixel MOSs that are turned on according to the gate turn-on voltage.The pulse signal supplied to the display panel includes the shift clock supplied to the shift clock line.The sensing device includes a feedback line connected to the gate driving unit, and includes a sensing unit configured to compare the feedback signal input through the feedback line with a predetermined reference voltage, detect a voltage interval having voltages less than or equal to the reference voltage from the feedback signal as the pulse width of the feedback signal, and output the digital data indicating the pulse width of the feedback signal.The gate driving unit includes a shift register configured to receive a start pulse and the shift clock, and sequentially shift and output the scan signal. The shift register includes cascaded stages. The stages include a pull-up transistor that is turned on according to a voltage of a Q node and is configured to charge an output node connected to the gate lines with a gate turn-on voltage. The pixels include one or more pixel switching elements that are turned on according to the gate turn-on voltage.The sensing device further includes a feedback transistor that is turned on according to the voltage of the Q node and is configured to connect the shift clock line to the feedback line.The feedback transistor is connected to each of the stages or connected to at least two stages spaced a predetermined distance apart.The display panel further includes an enable line configured to receive an enable signal from the driver unit; a test data line configured to receive a pulse signal from the driver unit; and a switching element that is turned on in response to the enable signal and is configured to supply the pulse signal to one of the data lines.The pulse signal supplied to the display panel includes the pulse signal supplied to the test data line.The sensing device includes a data line through which the pulse signal is supplied through a switching element, and includes a sensing unit configured to compare the pulse signal input through the data line with a predetermined reference voltage, detect a voltage interval having a voltage less than or equal to the reference voltage from the feedback signal as the pulse width of the feedback signal, and output the digital data indicating the pulse width of the feedback signal.The driving device includes a timing controller configured to, in response to the digital data received from the sensing device, reduce the pulse width of the shift clock synchronized with the sensing signal supplied to the pixels close to the driving device to be smaller than the pulse width of the shift clock synchronized with the sensing signal supplied to the pixels far from the driving device.The driving device includes a level shifter configured to convert the pulse voltage of the shift clock output from the timing controller into a gate turn-on voltage. The pixels include one or more pixel switches that are turned on according to the gate turn-on voltage.The driving means changes the pulse width of the shift clock using a look-up table in which a compensation pulse width corresponding to a pulse width value of the digital data received from the sampling means is defined.The driving device reduces, in response to the digital data received from the sensing device, a voltage of the shift clock synchronized with the sensing signal supplied to the pixels close to the driving device to be lower than a voltage of the shift clock synchronized with the sensing signal supplied to the pixels far from the driving device.The driving device includes a timing controller configured to output, in response to the digital data received from the sensing device, the digital data that changes the pulse voltage of the shift clock according to the positions of the pixels.The driving device includes a digital-to-analog converter configured to convert the digital data received from the timing controller into an analog voltage, and a level shifter configured to convert a voltage received from the digital-to-analog converter into a gate turn-on voltage. The pixels include one or more pixel switches that are turned on according to the gate turn-on voltage.Each of the pixels includes a light emitting element, a driving element configured to adjust the current flowing through the light emitting element according to a gate-source voltage, and an internal compensation circuit configured to sample a threshold voltage of the driving element in a sampling period defined by a pulse of the sampling signal and configured to supply the threshold voltage to a capacitor.The internal compensation circuit includes a capacitor connected to a gate of the driving element, and includes one or more switching elements configured to connect the capacitor, the driving element, and the light emitting element. The switching element is turned on according to the pulse voltage of the scan signal.The driving element changes the pixel driving voltage according to the positions of the pixels.At a high grayscale level and an intermediate grayscale level of the pixel data written into the pixels, the driving device increases and outputs a pixel driving voltage supplied to the pixels far from the driving device to be larger than a pixel driving voltage supplied to the pixels close to the driving device.At a low gray level of the pixel data written into the pixels, the driving device outputs the pixel driving voltage supplied to the pixels far from the driving device so as to be equal to the pixel driving voltage supplied to the pixels close to the driving device.A driving method of a display device including a display panel in which the data lines and the gate lines cross each other and in which the pixels are arranged in a matrix form, a gate driving unit formed in the display panel and configured to supply a scan signal to the gate lines, and a shift clock line formed in the display panel and configured to supply a shift clock to the gate driving unit includes receiving a feedback signal for a pulse signal supplied to the display panel and sampling a pulse width of the scan signal in real time; and changing one or both of a pulse width of the shift clock and a pulse voltage of the shift clock for each screen position of the display panel in response to the pulse width of the feedback signal sampled in real time.The driving method further includes, at a high grayscale level and a medium grayscale level of the pixel data written in the pixels, supplying a pixel driving voltage to the pixels and increasing a pixel driving voltage supplied to the pixels far from the driving device to be larger than a pixel driving voltage supplied to the pixels close to the driving device.The driving method further includes, at a low grayscale level of the pixel data written into the pixels, making the pixel driving voltage supplied to the pixels far from the driving device equal to the pixel driving voltage supplied to the pixels close to the driving device.The display device of the present disclosure samples a pulse width of a feedback signal for a pulse applied to a screen in real time, and changes one or both of a pulse voltage and a pulse width of a shift clock according to the detection result. As a result, by accurately sampling the electric characteristics of the driving element in all pixels of a planar display panel with an RC delay of a shift clock line, it is possible to realize uniform image quality over the screen.It should be noted that the advantageous effects of the present disclosure are not limited to the above-described effects, and that other effects not described herein will be apparent to those skilled in the art from the following claims.While the embodiments of the present disclosure have been described above in detail with reference to the accompanying drawings, the present disclosure is not limited to the embodiments, and various changes and modifications may be made without departing from the scope of the present disclosure. Accordingly, the embodiments disclosed herein are to be considered as illustrative and not restrictive of the scope of the present disclosure, the scope of the present disclosure not being limited by the embodiments. Therefore, it should be understood that the above embodiments are illustrative rather than restrictive in all respects. The scope of the disclosure should be construed by the appended claims, with all equivalents being construed as being included within the scope of the disclosure.

Claims

A display device, comprising: a display panel (100) comprising a screen (AA) having data lines (DL1 to D6) and gate lines (GL1, GL2) crossing each other, and pixels (P) arranged in a matrix form defined by the data lines (DL1 to D6) and the gate lines (GL1, GL2); a gate driving unit (120) configured to supply a scan signal (SCAN) to the gate lines (GL1, GL2); a driving device (300) configured to supply a data voltage (Vdata) to the data lines (DL1 to D6) and generate a shift clock (GCLK); a shift clock line (51) configured to supply the shift clock (GCLK) to the gate driving unit (120); and a sampling device (M9, 52, 230) configured to detect a pulse width of a feedback signal supplied to the display panel (100), wherein the sampling device (M9, 52, 230) is configured to compare the feedback signal with a predetermined reference voltage (Vref) and detect an interval of the feedback signal in which a voltage of the feedback signal is less than or equal to the reference voltage (Vref) as the pulse width of the feedback signal, wherein the driving device (300) is configured to:, a pulse width of the shift clock (GCLK) and / or a pulse voltage of the shift clock (GCLK) depending on a pixel position on the screen in response to the pulse width of the feedback signal detected by the sampling device, wherein the gate driving unit (120) includes a shift register configured to receive a start pulse (VST) and the shift clock (GCLK), and sequentially shift and output the sampling signal (SCAN), and the shift register includes cascade-connected stages, each of the stages including a pull-up transistor turned on according to a voltage of a Q node, wherein the sampling device (M9, 52, 230) further includes at least one feedback transistor (M9), which is turned on according to the voltage of the Q node of a stage of the shift register, wherein the feedback transistor (M9) is configured to connect the shift clock line (51) to a feedback line (52) to supply the feedback signal to the sampling device.The display device according to claim 1, wherein a pulse signal supplied to the display panel (100) includes the shift clock (GCLK) supplied to the shift clock line (51).The display device according to any one of the preceding claims, wherein a feedback transistor (M9) is provided for each of the stages or a feedback transistor (M9) is provided for at least two stages.The display device according to any one of the preceding claims, wherein the display panel (100) further comprises: an enable line (271) configured to receive an enable signal from the driver unit (300); a test data line (272 to 274) configured to receive a pulse signal from the driver unit (300); and a switching element (MA1, MA2, MA3) configured to be turned on in response to the enable signal and configured to supply the pulse signal to one of the data lines (DL, DL1 to DL6) to supply the feedback signal to the sensing device.The display device according to claim 4, wherein the pulse signal supplied to the display panel (100) includes the pulse signal supplied to the test data line (272 to 274).The display device according to claim 4 or 5, wherein the feedback signal is received via the one data line (DL, DL1 to DL6).The display device according to any one of the preceding claims, wherein the driving device (300) is configured to, in response to the pulse width of the feedback signal detected by the sensing device, reduce the pulse width of the shift clock (GCLK) for the sensing signal (SCAN) supplied to the pixels disposed adjacent to the driving device (300) to be smaller than the pulse width of the shift clock (GCLK) for the sensing signal (SCAN) supplied to the pixels disposed farther from the driving device (300).The display device according to any one of the preceding claims, wherein the driving device (300) is configured to change the pulse width of the shift clock (GCLK) using a look-up table (LUT) in which a compensation pulse width corresponding to a pulse width value detected by the sampling device is defined.The display device according to any one of the preceding claims, wherein the pulse voltage of the shift clock (GCLK) and a pulse voltage of the scan signal (SCAN) have the same gate turn-on voltage.The display device according to any one of the preceding claims, wherein the driving device (300) is configured to convert the pulse voltage of the shift clock (GCLK) into a gate turn-on voltage.The display device according to any one of the preceding claims, wherein the driving device (300) is configured to, in response to the pulse width of the feedback signal detected by the sensing device, decrease a pulse voltage of the shift clock (GCLK) for the sensing signal (SCAN) supplied to the pixels adjacent to the driving device (300) to be lower than a voltage of the shift clock for the sensing signal supplied to the pixels farther from the driving device (300).The display device according to any one of the preceding claims, wherein each of the pixels (P) comprises: a light emitting element (EL); a driving element (DT) configured to control the current flowing through the light emitting element (EL) according to a gate-source voltage; and an internal compensation circuit for sampling a threshold voltage of the driving element (DT) in a sampling period defined by a pulse of the sampling signal (SCAN), the internal compensation circuit comprising: a capacitor (Cst) connected to a gate of the driving element (DT); and at least one switching element configured to connect the capacitor (Cst), the driving element (DT), and the light emitting element (EL), the at least one switching element being turned on according to the pulse voltage of the scan signal (SCAN).The display device according to any preceding claim, wherein when a high gray level and an intermediate gray level of the pixel data are to be written into the pixels, the driving device (300) is configured to control a pixel driving voltage supplied to the pixels arranged far from the driving device (300) to be larger than a pixel driving voltage supplied to the pixels close to the driving device (300).The display device according to any one of the preceding claims, wherein when a low grayscale level of the pixel data is to be written into the pixels, the driving device (300) is configured to control a pixel driving voltage supplied to the pixels far from the driving device (300) to be equal to the pixel driving voltage supplied to the pixels close to the driving device (300).The driving method for a display device according to any one of the preceding claims, wherein the driving method comprises: supplying a pulse signal to the display panel (100); receiving the feedback signal via the feedback line (52) and detecting a pulse width of the feedback signal; comparing the feedback signal with a predetermined reference voltage (Vref), and detecting an interval of the feedback signal in which a voltage of the feedback signal is less than or equal to the reference voltage (Vref) as the pulse width of the feedback signal; and changing a pulse width of the shift clock (GCLK) and / or a pulse voltage of the shift clock (GCLK) depending on a pixel position (P) on the screen in response to the pulse width of the feedback signal.

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