SPACE REQUIREMENTS FOR MULTI-BIT FLIP-FLOP

Abstract

Integrated circuit comprising: a first plurality of cell rows (ROW1, ROW3); a second plurality of cell rows (ROW2, ROW4) arranged adjacent to the first plurality of cell rows (ROW1, ROW3), wherein a first number of fins in the first plurality of cell rows (ROW1, ROW3) differs from a second number of fins (141, 142) in the second plurality of cell rows (ROW2, ROW4); a first and a second clock inverter (251, 252; 811, 812) arranged in the second plurality of cell rows (ROW2, ROW4), wherein a first clock signal generated by the first clock inverter (251; 811) and a second clock signal generated by the second clock inverter (252; 812) have different phases; and a plurality of flip-flops (202, 204, 501) arranged in the first plurality of cell rows (ROW1, ROW3) and the second plurality of cell rows (ROW2, ROW4), the plurality of flip-flops (202, 204, 501) comprising a first plurality of flip-flops configured to operate in response to the first and second clock signals.

Description

BACKGROUNDMulti-bit flip-flop circuits are used in electronic systems for storing digital data. Scan flip-flops included in the multi-bit flip-flop are operable to store many bits of data in response to clock signals. In some approaches, the multi-bit flip-flop circuits are based on circuitry with similar circuit topology and dimensioning.U.S. Pat. No. 8,723,574 B2 discloses a semiconductor integrated circuit.U.S. Pat. No. 9,966,936 B2 disclosed a semiconductor integrated circuit.U.S. Pat. No. 8,856,704 B2 discloses a layout library for layouts in which identical flip-flop circuits are implemented.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description when read with the accompanying figures. It should be appreciated that, in accordance with standard practices in the industry, various elements are not drawn to scale. In fact, for clarity, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1A is a plan view diagram of a portion of a semiconductor device, in accordance with some embodiments. FIG. 1B is a sectional diagram illustrating a structure of some cell rows along a section line in FIG. 1A, in accordance with some embodiments. FIG. 2A is a schematic diagram of a portion of a scan flip-flop, in accordance with some embodiments. FIG. 2B is a layout view of the scan flip-flop in FIG. 2A, in accordance with some embodiments. FIGS. 3A to 3F are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B included in 4-bit flip-flop circuits in the semiconductor device in FIG. 1A, according to some embodiments. FIGS. 4A to 4B are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B included in 8-bit flip-flop circuits in the semiconductor device in FIG. 1A, according to some embodiments. FIG. 5A is a schematic diagram of a portion of a scan flip-flop, in accordance with some embodiments. FIG. 5B is a layout view of the scan flip-flop in FIG. 5A, in accordance with some embodiments. FIGS. 6A to 6C are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B and a plurality of the scan flip-flops in FIGS. 5A to 5B included in 4-bit flip-flop circuits in the semiconductor device in FIG. 1A, according to some embodiments. FIGS. 7A to 7B are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B and a plurality of the scan flip-flops in FIGS. 5A to 5B included in 8-bit flip-flop circuits in the semiconductor device in FIG. 1A, according to some embodiments. FIG. 8A is a schematic diagram of a portion of a first set of scan flip-flops corresponding to the scan flip-flop in FIG. 2A, in accordance with some embodiments. FIG. 8B is a schematic diagram of a portion of a second set of scan flip-flops corresponding to the scan flip-flop in FIG. 5A, in accordance with some embodiments. FIGS. 9A to 9C are layout views of the first set of scan flip-flops and the second set of scan flip-flops included in 4-bit flip-flop circuits in the semiconductor device in FIG. 1A, according to some embodiments. FIG. 10 are layout views of the first set of scan flip-flops and the second set of scan flip-flops included in an 8-bit flip-flop circuit in the semiconductor device in FIG. 1A, in accordance with some embodiments. FIG. 11 is a flow diagram of a method for generating a layout design for manufacturing the integrated circuit. FIG. 12 is a block diagram of a system for designing the layout design of the integrated circuit according to some embodiments of the present disclosure. FIG. 13 is a block diagram of an integrated circuit fabrication system and an integrated circuit fabrication flow associated therewith, in accordance with some embodiments.DETAILED DESCRIPTIONThe invention is defined by the claims. The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Hereinafter, concrete examples of the components and arrangements will be described in order to simplify the present disclosure. The formation of a first element over or on a second element in the following description may include, for example, embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which the respective term is used. The use of examples in this specification, including the examples of terms discussed herein, is illustrative only and does not in any way limit the scope and meaning of the disclosure or an exemplary term. Also, the present disclosure is not limited to various embodiments listed in this specification.As used herein, the terms "comprising," "including," "having," "including," "including," and the like are open-ended, i.e., to mean "including, but not limited to.".References throughout this specification to "one (1) embodiment," "one embodiment," or "some embodiments" mean that a / e particular / s feature, structure, implementation, or characteristic described in connection with the embodiment / s is included in at least one embodiment of the present disclosure. Thus, use of the phrases "in one (1) embodiment," or "in one embodiment," or "in some embodiments," at different places throughout the specification does not necessarily always refer to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments.Further, spatially relative terms such as "below," "below," "lower," "over," "upper," and the like may be used herein to facilitate the description to describe the relationship of an element or feature to one or more other element(s) or feature(s) as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein may also be interpreted accordingly. As used herein, the phrase "and / or" includes any and all combinations of one or more of the associated listed items.As used herein, terms such as "about", "about", "about" or "substantially" generally refer to any approximate value of a given value or range in which it varies depending on various compartments to which it relates and the scope of which is attributable to the broadest interpretation understood by those skilled in the art to which it relates, so as to encompass all such modifications and similar structures. In some embodiments, this generally means within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate. That is, the terms "about", "about", "about" or "substantially" may be inferred unless expressly stated or denote other approximate values.Reference is now made to FIG. 1A. FIG. 1A is a plan view diagram of a portion of a semiconductor device 10 in accordance with some embodiments. As illustratively shown in FIG. 1A, the semiconductor device 100 includes a plurality of cell rows ROW1-ROW4. In some embodiments, cells, for example the cells illustrated in FIGS. 3A-3F, 4A-4B, 6A-7B, 9A-10, are implemented by integrated circuits arranged in these cell rows ROW1-ROW4. The number of cell rows ROW1-ROW4in the semiconductor device 10 in FIG. 1A is given for illustrative purposes. Different numbers of cell rows ROW1-ROW4 are within the contemplated scope of the present disclosure. In some embodiments, the number of cell rows in the semiconductor device 10 is more than 4, for example.For illustration, the cell rows ROW1-ROW4 extend along an x-direction and parallel to each other. In some embodiments, the cell rows ROW1-ROW4 are arranged along a y-direction that is substantially perpendicular to the x-direction.In some embodiments, there are two groups of cell rows among the rows ROW1-ROW4 with respect to their row height. As illustratively shown in FIG. 1A, each of the cell rows ROW 1 and ROW 3 is configured to have a row height H 1, and each of the cell rows ROW 2 and ROW 4 is configured to have a different row height H 2 that is shorter than the row height H 1. The cell rows ROW 1 and ROW 3 having the row height H 1 are regarded as a first group "A" of the cell rows ROW 1- ROW 4, and the cell rows ROW 2- ROW 4 are regarded as a second group "B" of the cell rows ROW 1- ROW 4. In some embodiments, as shown in FIG. 1A, the first group A of the cell rows and the second group B of the cell rows are interleaved.By way of illustration, the row of cells ROW1 having row height H1 in the first group "A" includes two active regions 110- 120, and the row of cells ROW2 having row height H2 in the second group "B" includes two active regions 130- 140. Similarly, cell row ROW3 includes two active regions 150-160 and cell row ROW4 includes two active regions 170-180. Illustratively, the active regions 110- 180 extend along an x-direction and are separated from each other in a y-direction. The configurations of the active regions 110- 180 will be explained in the following paragraphs with reference to FIG. 1B.In some embodiments, active regions 110 and 140 have a P-type conductivity while active regions 120 and 130 have an N-type conductivity. The configurations of the active regions 150 and 180 are similar to the active regions 110 and 140, and the configurations of the active regions 160 and 170 are similar to the active regions 120 and 130. In other words, the cell rows ROW1-ROW4 are interleaved in a periodic sequence along a y-direction. The configurations of the active regions 110- 180 are provided for illustrative purposes. Various implementations of the active regions 110- 180 are included within the contemplated scope of the present disclosure. In some embodiments, active regions 110, 140, 150, and 180 are, for example, N-type and active regions 120, 130, 160, and 170 are, for example, P-type.The configurations of the semiconductor device 10 in FIG. 1A are given for illustrative purposes. Various implementations of the semiconductor device 10 are included within the contemplated scope of the present disclosure. In some embodiments explained in the following paragraphs, for example, the cell rows are arranged in a sequence different from that of the cell rows ROW 1 to ROW 4, such as in sequences ROW 1, ROW 2, ROW 4, and ROW 3. In other words, the cell rows having the same height are arranged abutting each other.Reference is now made to FIG. 1B. FIG. 1B is a sectional diagram illustrating a structure of the cell rows ROW3-ROW4 along a section line AA' in FIG. 1A, in accordance with some embodiments. Referring to the embodiments in FIG. 1A, like elements in FIG. 1B are denoted by like reference numerals for better understanding.As illustratively shown in FIG. 1B, the cell row ROW 1 having the row height H 1 in the second group "A" includes two active regions 110- 120 on the substrate Sub. The active region 110 of the cell row ROW 1 includes a first fin-shaped structure and the active region 120 of the cell row ROW 1 includes a second fin-shaped structure. In other words, each of the active regions 110- 120 includes a fin-shaped structure.As illustratively shown in FIG. 1B, the cell row ROW 2 having the row height H 1 in the first group "B" includes the active regions 130- 140 on a substrate Sub. The active region 130 of the cell row ROW 2 includes two fin-shaped structures 131 and 132 and the active region 140 of the cell row ROW 2 includes two further fin-shaped structures 141 and 142. In other words, each of the active regions 130- 140 includes two fin-shaped structures, such as 131 and 132 or 141 and 142.In some embodiments, fin structures 131 and 132 are n-type fin structures and fin structures 141 and 142 are p-type fin structures. In some other embodiments, fin-shaped structures 131 and 132 are p-type fin-shaped structures and fin-shaped structures 141 and 142 are n-type fin-shaped structures.The aforementioned fins may be patterned by any suitable method. The fins may be patterned using, for example, one or more photolithography processes, including dual-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithography and self-aligning processes, which allows structures to be created that have, for example, smaller pitches than what otherwise can be achieved using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed and patterned over a substrate using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins.In some embodiments, such an active region may include one or more fin-shaped structures of one or more three-dimensional field effect transistors (e.g., FinFETs, gate-all-around (GAA) transistors), or an oxide definition (OD) regions of one or more planar metal oxide semiconductor field effect transistors (MOSFETs). The active region may serve as a source feature or a drain feature of the respective transistor(s).In some embodiments, the active region 130 of the cell row ROW 2 includes two fin-shaped structures 131 and 132 together as an active region for forming an integrated circuit component (such as a transistor) such that an equivalent width of the active region of the integrated circuit component disposed on the active region 130 is wider than another integrated circuit component disposed on the active region 110 including the first one fin-shaped structure. In other words, in some embodiments, integrated circuit components disposed on the cell row ROW 2 have better performance than integrated circuit components disposed on the cell row ROW 1.Reference is now made to FIG. 2A. FIG. 2A is a schematic diagram of a portion of a scan flip-flop 200 and corresponding inverters 251- 252, in accordance with some embodiments. In some embodiments, the scan flip-flop 200 is formed in the semiconductor device 10 in FIG. 1A. To illustrate, the scan flip-flop 200 includes a mux input circuit 210, a first latch circuit 220, a second latch circuit 230, and an output stage 240. Mux input circuit 210 is coupled to first latch circuit 220. The first latch circuit 220 is coupled to the second latch circuit 230. The second latch circuit 230 is coupled to the output stage 230.In operation, the mux input circuit 210 is configured to receive a sample data input SI, a data input Di, and a sample enable signal SE, and output the sample data input SI or the normal data input Di. The first and second latch circuits 220- 230 are configured to receive clock signals CLKB and CLKBB and to be cross-coupled for storing a data state. The clock signal CLKB is generated by the inverter 251 inverting a clock signal CP1, and the clock signal CLKBB is generated by the inverter 252 inverting the clock signal CLKB. The output stage 240 is configured to generate an output data signal Qi based on the output of the second latch circuit 230. In some embodiments, the output signal Qi is associated with the output signal of mux input circuit 210, the data state stored in first and second latch circuits 220- 230, and clock signals CLKB and CLKBB.Mux input circuit 210 specifically includes a multiplexer (MUX) 211. The MUX 211 is configured to output the scan data input SI or the data input Di according to the scan enable signal SE. In some embodiments, there are a plurality of scan flip-flops configured with respect to the scan flip-flop 200 and configured to receive a multi-bit data signal, and the data input Di corresponds to the i-th bit data of the multi-bit data signal. The scan flip-flops receive, for example, a 4-bit signal and, accordingly, data inputs D1 to D4 correspond to the first to fourth bit data of the 4-bit signal.In some embodiments, scan enable signal SE received from MUX 211 switches scan flip-flop 200 between a normal operation mode and a scan test mode. For example, when the scan enable signal SE is raised to a high logic level (i.e., logic 1) and the scan flip-flop 200 operates in the scan test mode, the scan data input SI is output from the MUX 211. When the scan enable signal SE is pulled down to a logic low level (i.e., logic 0) and the scan flip-flop 200 operates in the normal operation mode, the data input Di is output from the MUX 211.To illustrate, the first latch circuit 220 includes transfer gates 221 and 223 and inverters 222 and 224. The transmission gate 221 receives the clock signals CLKB and CLKBB. The inverters 222 and 224 and transmission gate 223 form a latch including the inverter 222 coupled in a forward path between the transmission gate 221 and an output terminal of the first latch circuit 220 and the inverter 224 coupled in a feedback configuration and the transmission gate 223 activated and deactivated by the clock signals CLKB and CLKBB.Similarly, the second latch circuit 230 includes transfer gates 231 and 233 and inverters 232 and 234. The transfer gate 231 receives the clock signals CLKB and CLKBB. The inverters 232 and 234 and the transmission gate 233 form a latch including the inverter 232 coupled in a forward path between the transmission gate 231 and an output terminal of the second latch circuit 230 and the inverter 234 coupled in a feedback configuration and the transmission gate 233 activated and deactivated by the clock signals CLKB and CLKBB.The output stage 240 includes an inverter 241. The inverter 241 is coupled to an output of the second latch circuit 230. The inverter 241 is configured to output the output signal of the second latch circuit 230 and generate the output data signal Qi.As mentioned above, in some embodiments, the data input Di corresponds to the i-th bit data of the multi-bit data signal. Accordingly, the output data signal Qi corresponds to ith bit data of the multi-bit data signal. Moreover, in alternative embodiments, the output data signal Qi of the i-th bit flip-flop is input to the (i+1)-th bit flip-flop as the sample data input SI(i+1) along with the data input D(i+1), etc. In some embodiments, all of the scan flip-flops in a multi-bit flip-flop circuit receive the same sample data input.In some embodiments, the "flips" and "flops" of the output data signal Qi may be between a "1" and a "0" in a manner that depends on the output of the mux input circuit 210 and the clock signal CP 1. Generally, the stored data state in the scan flip-flop 200 is output as the output data signal Qi until a logic state of the clock signal CP 1 changes. When the logic state of the clock signal CP1 changes, the current status of the output signal of the mux input circuit 210 is stored and supplied as the output data signal Qi. In some embodiments, the initially stored status in the scan flip-flop is, for example, "1.". When the status of the clock signal CP1 changes and the status of the output signal of the mux input circuit 210 is still "1", status "1" is stored for another clock cycle. On the other hand, when the status of the clock signal CP1 changes and the status of the output signal of the mux input circuit 210 is "0", status "0" is stored for the subsequent clock cycle, and accordingly, the output signal Qi having a status "0" is output.The configurations in FIG. 2A are provided for illustrative purposes. Various implementations of FIG. 2A are within the intended scope of the present disclosure. For example, in some embodiments, the transfer gate 223 of the first latch circuit 220 and the transfer gate 233 of the second latch circuit 230 are omitted.Reference is now made to FIG. 2B. FIG. 2B is a layout view of the scan flip-flop 200 in FIG. 2A, in accordance with some embodiments. Referring to FIG. 2A, like elements in FIG. 2B are denoted by like reference numerals for better understanding.In some embodiments, a cell 201 is configured in forming the scan flip-flop 200 in FIG. 2A. As illustratively shown in FIG. 2B, cell 201 includes mux input circuit 210, first latch circuit 220, second latch circuit 230, and output stage 240 arranged along a cell boundary direction 250. The configurations of the cell 201 corresponding to the scan flip-flop 200 are provided for illustrative purposes. Various implementations of the cell 201 are within the contemplated scope of the present disclosure. For example, in some embodiments, mux input circuit 210, first latch circuit 220, second latch circuit 230, and output stage 240 are arranged along both cell boundary directions 250 and 260.FIGS. 3A to 3F are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B included in 4-bit flip-flop circuits 31- 33 in the semiconductor device 10 in FIG. 1A according to some embodiments. In some embodiments, cells included in the multi-bit flip-flop circuits 31- 36 have a cell height H 1 and are arranged in rows, such as cell rows ROW 1 and ROW 3 in FIG. 1A. Similarly, the cells included in the multi-bit flip-flop circuits 31- 36 have a cell height H 2 and are arranged in rows, such as cell rows ROW 2 and ROW 4 in FIG. 1A. In other words, the cells having cell height H 1 are implemented in the high fin rows (including at least two fins in an active region) and the cells having cell height H 2 are implemented in the low fin rows (including a fin in an active region).In some embodiments, the cell rows ROW1-ROW4 are arranged in sequences different from FIG. 1A to implement the corresponding flip-flop circuits 31-36.Reference is now made to FIG. 3A. The 4-bit flip-flop circuit 31 includes cells 201-204 and 253-254. For example, cells 202- 204 are configured with respect to cell 201. In some embodiments, cells 201- 204 comprise a same equivalent circuit including, for example, scan flip-flop 200 of FIG. 2A.Cells 201-204 correspond to bit 1 through bit 4 scan flip-flops separately (as shown in Figure 3A). In alternative embodiments, the output data signal Qi is input to the cell 201 of bit 1 as the sample data input SI for the cell 202 of bit 2. The output data signal Qi in the cell 202 of bit 2 is input as the sample data input SI for the cell 203 of bit 3. The output data signal Qi in the cell 203 of bit 3 is input as the sample data input SI for the cell 204 of bit 4. Cells 253 and 254 correspond to inverters 251 and 252 of FIG. 2A, respectively. In some embodiments, the scan flip-flops of cells 201-204 operate in response to clock signal CLKB generated by inverter 251 of cell 253 and clock signal CLKBB generated by inverter 252 of cell 254.For illustration, the cell 201 of bit 1 is arranged in the cell row ROW 1 and has a width W 1. The cells 202 of bit 2 and 253 are arranged in the row of cells ROW2. The cell 202 of bit 2 has a width W 2 that is less than the width W 1 and abuts the cell 253. The cells 203 of bit 3 and 254 are arranged in the row of cells ROW3. Cell 203 of bit 3 has width W2 and abuts cell 254. The cell 204 of bit 4 is arranged in the cell row ROW 4 and has the width W 1. The cells 253- 254 abut each other.In some embodiments, transistors of cells 201- 204 included in scan flip-flop circuit 31 share gate structures in the layout view. For example, in various embodiments, at least one gate structure is configured to be in the formation of inverter 222 in cell 201 and transfer gate 223 in cell 202. In other words, cells in the cell row with a lower cell height, such as cell rows ROW 1 and ROW 3, save routing resources for connecting gates due to the shared gate structures, and the cells are further capable of containing complex circuits (more circuit elements) within a relatively smaller range of cells compared to cells in the cell rows with a larger row height. The above-mentioned configurations are for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, inverters in cells 253- 254 share, for example, gate or other layout patterns (i.e., conductive patterns MD configured as drain or source terminals of transistors) with elements in cells 201- 204.Moreover, in some approaches, each bit of a multi-bit flip-flop circuit has a similar circuit topology and dimensioning. Accordingly, the functionality of each bit is the same and the timing characteristics are very similar. Compared to the approaches with the configurations of the present disclosure, bits of the multi-bit flip-flop circuit are arranged in mixed row height structures, and thereby flexibility of topology and device dimensioning is provided. Moreover, because the constraints due to the same topology and sizing for bits of a multi-bit flip-flop circuit are eliminated, the space requirement for implementing the multi-bit flip-flop circuit in a mixed row cell architecture is also eliminated. Accordingly, better performance, performance, and area usage are achieved with the present disclosure compared to some approaches.Reference is now made to FIG. 3B. Referring to FIG. 3A, like elements in FIG. 3B are denoted by like reference numerals for better understanding.As compared to FIG. 3A, instead of arranging the cell 254 in the cell row ROW 3, the cell 254 of the multi-bit flip-flop circuit 32 is arranged in the cell row ROW 4 and abuts the cell 202 of bit 4.In the configurations in FIG. 3B, scan flip-flops that operate at higher computational speed because the cells 202 of bit 2 and 202 of bit 4 are arranged in the cell rows ROW 2 and ROW 4 having a 2-fin structure as mentioned in FIG. 1A formed in cell rows ROW 2 and ROW 4 operate at lower computational speed compared to scan flip-flops formed in the cell rows ROW 1 and ROW 3. In other words, the scan flip-flops in the multi-bit flip-flop circuit operate at different speeds. In some embodiments, the speed of the multi-bit flip-flops is not dominated by the scan flip-flops operating at lower computational speed.Reference is now made to FIG. 3C. Referring to FIGS. 3A-3B, like elements in FIG. 3C are designated with like reference numerals for ease of understanding.In comparison with FIG. 3A, instead of the cell 201 of bit 1 in the cell row ROW 1 and the cell 202 of bit 2 in the cell row ROW 2, the multi-bit flip-flop circuit 33 includes the cell 204 of bit 2 arranged in the cell row ROW 2 and the cell 203 of bit 1 in the cell row ROW 1. Cell 203 of bit 1 abuts cell 253. In other words, cells 203 of bit 1 and 203 of bit 3 are arranged between cells 204 of bit 2 and 204 of bit 4. To explain it in another way, cell rows ROW1 and ROW3 are arranged lying between cell rows ROW2 and ROW4.Reference is now made to FIG. 3D. Referring to FIGS. 3A-3C, like elements in FIG. 3D are designated with like reference numerals for ease of understanding.As compared with FIG. 3A, instead of arranging the cells of bit 3 and bit 4 vertically in the cell of the multi-bit flip-flop circuit 31, the multi-bit flip-flop circuit 34 includes the cell 202 of bit 3 and the cell 254 arranged in the cell row ROW 2. In other words, cells 253- 254 are arranged between cells 202 of bit 2 and 202 of bit 3. The multi-bit flip-flop circuit 34 further includes the cell 201 of bit 4 in the cell row ROW 1. Cell 201 of bit 4 abuts cell 201 of bit 1. In some embodiments, the cells from bit 1 to bit 4 are arranged clockwise in the cell corresponding to the multi-bit flip-flop circuit 34.Reference is now made to FIG. 3E. Referring to FIGS. 3A-3D, like elements in FIG. 3E are designated with like reference numerals for ease of understanding.In comparison to FIG. 3D, instead of arranging cells 253- 254 in cell row ROW 2, multi-bit flip-flop circuit 35 includes cells 253- 254 that are in cell row ROW 1 and are arranged between cells 203 of bit 1 and 203 of bit 4. As shown in FIG. 3D, the multi-bit flip-flop circuit 35 further includes the cells 204 of bit 2 and 204 of bit 3 that are in the cell row ROW 2 and abut each other.Reference is now made to FIG. 3F. Referring to FIGS. 3A-3E, like elements in FIG. 3F are designated with like reference numerals for ease of understanding.As compared to FIG. 3E, instead of the cells 253- 254 in the same cell row, the multi-bit flip-flop circuit 36 includes the cell 253 in the cell row ROW 1 and the cell 254 in the cell row ROW 2. As shown in FIG. 3F, the multi-bit flip-flop circuit 36 includes the cells 203 of bit 1 and 203 of bit 4 in the cell row ROW 1 and the cells 202 of bit 2 and 202 of bit 3 in the cell row ROW 2. Cell 253 is located between cells 203 of bit 1 and 203 of bit 4 and cell 254 is located between cells 202 of bit 2 and 202 of bit 3. The cells 253- 254 abut each other.FIGS. 4A to 4B are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B included in 8-bit flip-flop circuits 41- 42 in the semiconductor device in FIG. 1A, according to some embodiments. Referring to FIGS. 3A-3F, like elements in FIGS. 4A-4B are designated by like reference numerals for ease of understanding.Reference is now made to FIG. 4A. As compared to FIG. 3B, the multi-bit flip-flop 41 includes cells corresponding to bits 5 to bit 8. Illustratively, multi-bit flip-flop 41 includes cells 205 of bit 1, 205 of bit 3, 205 of bit 6, and 205 of bit 8, each having a width W 3 that is less than width W 1 and greater than width W 2, and cell height H 1. In some embodiments, cells 205 of bit 1, 205 of bit 3, 205 of bit 6, and 205 of bit 8 are configured with respect to, for example, cell 201 in FIG. 2B. In some embodiments, cells 205 of multi-bits have the same equivalent circuit, including, for example, scan flip-flop 200 in FIG. 2A.Specifically, the cell 205 of bit 1 and the cell 205 of bit 8 are arranged in the cell row ROW 1. Cell 202 of bit 2, cell 253 and cell 202 of bit 7 are arranged in cell row ROW 2. The cell 205 of bit 3 and the cell 205 of bit 6 are arranged in the cell row ROW 3. Cell 202 of bit 4, cell 254, and cell 202 of bit 5 are arranged in cell row ROW4. In some embodiments, the cells from bit 1 to bit 8 are arranged clockwise in the cell corresponding to the multi-bit flip-flop circuit 41.Reference is now made to FIG. 4B. As compared to FIG. 4A, cells 253- 254 abut each other. Illustratively, multi-bit flip-flop 42 includes cells 206 of bit 4 and 206 of bit 5, each having width W3 and cell height H2. In some embodiments, cells 206 of bit 4 and 206 of bit 5 are configured with respect to, for example, cell 201 in FIG. 2B. In some embodiments, cells 206 of multi-bits have the same equivalent circuit, including, for example, scan flip-flop 200 in FIG. 2A.The cell 203 of bit 2, the cell 254, and the cell 203 of bit 7 are arranged in the cell row ROW 3. Cell 202 of bit 3, cell 253 and cell 202 of bit 6 are arranged in cell row ROW 2. Cell 202 of bit 3, cell 253 and cell 202 of bit 6 are arranged in cell row ROW 2.The configurations in FIGS. 4A-4B are provided for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. For example, in some embodiments, instead of cells 203 of bit 2 and 203 of bit 7, multi-bit flip-flop circuit 42 includes cell 202 of bit 2, cell 254 and cell 202 of bit 7 in cell row ROW2, and cells 205 of bit 4 and 205 of bit 5 in cell row ROW4.Reference is now made to FIG. 5A. FIG. 5A is a schematic diagram of a portion of a scan flip-flop 500, in accordance with some embodiments. Referring to the embodiments in FIG. 2A, like elements in FIG. 5A are denoted by like reference numerals for ease of understanding. The specific operations of similar elements already explained in detail in the above paragraphs are omitted here for brevity, unless there is a need to present the cooperation relationship with the elements shown in FIG. 5B.As illustratively shown in FIG. 5A, scan flip-flop 500 includes mux input circuit 510, first latch circuit 520, second latch circuit 530, and output stage 540. In some embodiments, mux input circuit 510 is configured with respect to, for example, mux input circuit 210 in FIG. 2A. The first latch circuit 520 is configured with respect to, for example, the first latch circuit 220 in FIG. 2A. The second latch circuit 530 is configured with respect to the second latch circuit 230 in FIG. 2A, for example. Output stage 540 is configured, for example, with respect to output stage 240 in FIG. 2A.As compared to the scan flip-flop 200 in FIG. 2A, the scan flip-flop 500 includes, instead of the inverters 222 and 234, a NOR gate 522 in the first latch circuit 520 and a NOR gate 534 in the second latch circuit 530. As illustratively shown in FIG. 5A, a first input terminal of the NOR gate 522 is coupled to the transmission gates 221 and 223, and a second input terminal of the NOR gate 522 is coupled to a control signal CD. A first input terminal of the NOR gate 534 is coupled to the inverters 232 and 241, and a second input terminal of the NOR gate 534 is coupled to a control signal CD. In some embodiments, the control signal CD is configured as a "reset" signal that resets the output of the scan flip-flops to a particular logic state (i.e., logic 1) at corresponding clock cycles.In some embodiments, scan flip-flop 500 in FIG. 5A, having NOR gates 522 and 534, occupies a larger space than scan flip-flop 200 in FIG. 2A.Reference is now made to FIG. 5B. Referring to FIG. 5A, like elements in FIG. 5B are denoted by like reference numerals for better understanding. As illustratively shown in FIG. 2B, cell 510 includes mux input circuit 510, first latch circuit 520, second latch circuit 530, and output stage 540, which are arranged along a cell boundary direction 550. The configurations of the cell 501 corresponding to the scan flip-flop 500 are provided for illustrative purposes. Various implementations of the cell 501 are within the contemplated scope of the present disclosure. For example, in some embodiments, mux input circuit 510, first latch circuit 520, second latch circuit 530, and output stage 540 are arranged along both cell boundary directions 550 and 560.FIGS. 6A to 6C are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B and a plurality of the scan flip-flops in FIGS. 5A to 5B included in 4-bit flip-flop circuits 61- 63 in the semiconductor device in FIG. 1A according to some embodiments.Reference is now made to FIG. 6A. As compared to FIG. 3B, as shown in FIG. 6A, instead of the cells 201 of bit 1 and 201 of bit 3, the multi-bit flip-flop 61 includes the cell 501 of bit 1 in the cell row ROW 1, the cell 501 of bit 3 in the cell row ROW 3, wherein the cells 501 of bit 1 and 501 of bit 3 have the width W 1 and the cell height H 1.Reference is now made to FIG. 6B. As compared with FIG. 6A, the cell rows ROW 2 and ROW 4 having a larger cell height are arranged lying between the cell rows ROW 1 and ROW 3 having a smaller cell height in the multi-bit flip-flop circuit 62, instead of the cell rows having different cell heights which are arranged in an interleaved manner. In other words, cell 501 of bit 4 in cell row ROW3 is replaced with cell 202 of bit 3 and cell 254 arranged in cell row ROW4, and cells 253- 254 abut each other.Reference is now made to FIG. 6C. As compared to FIG. 6B, instead of the cell rows having a larger cell height and being arranged between the cell rows having a smaller cell height, the cell rows ROW 1 and ROW 3 are arranged lying between the cell rows ROW 2 and ROW 4.The configurations in FIGS. 6A-6C are provided for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. The scan flip-flops, which correspond to bits in a multi-bit flip-flop circuit, for example, are arranged in sequence along one of the cell boundaries which extends in a direction perpendicular to the direction in which the cells extend.FIGS. 7A to 7B are layout views of a plurality of the scan flip-flops in FIGS. 2A to 2B and a plurality of the scan flip-flops in FIGS. 5A-5B included in 8-bit flip-flop circuits 71- 72 in the semiconductor device in FIG. 1A, according to some embodiments. Referring to FIGS. 2A-6C, like elements in FIGS. 7A-7B are designated with like reference numerals for ease of understanding.Reference is now made to FIG. 7A. In comparison to FIG. 4 a, instead of cells 205 of bit 1, 205 of bit 3, 205 of bit 6, and 205 of bit 8, multi-bit flip-flop circuit 71 includes cells 502 of bit 1, 502 of bit 3, 502 of bit 6, and 502 of bit 8. In some embodiments, cells 502 of bit 1, 502 of bit 3, 502 of bit 6, and 502 of bit 8 are configured with respect to, for example, cell 501 in FIG. 5B. In some embodiments, cells 502 of multi-bits have the same equivalent circuit, including, for example, scan flip-flop 500 in FIG. 5A.Reference is now made to FIG. 7B. As compared with FIG. 7A, the cell row ROW 3 is replaced with the cell row ROW 4. In particular, cell 202 of bit 4 is disposed between cell 202 of bit 2 and cell 502 of bit 3. Cell 202 of bit 5 is located between cell 202 of bit 7 and cell 502 of bit 6. The cells 253- 254 abut each other.With the configurations in FIGS. 6A-7B, clock drivers, such as the inverters in clock cells 253- 254, are centralized in the multi-bit flip-flop circuit and abut some scan flip-flops. In other words, instead of each scan flip-flop having its own pair of clock drivers, signals of the clock drivers centralized in the multi-bit flip-flop circuit are shared by all scan flip-flops in the multi-bit flip-flop circuit. Accordingly, the total area of the multi-bit flip-flop circuit is reduced.Moreover, in the configurations in FIGS. 6A-7B, scan flip-flops corresponding to bits of the multi-bit flip-flop are integrated together with different flop functions in different cell architectures. In some embodiments, different cell architectures have a different computational speed. Accordingly, the timing path is characterized separately for each bit and the EDA tools perform optimization and place a timing critical path into the faster cell architecture and a less timing critical path into a power optimized cell.Reference is now made to FIG. 8A. FIG. 8A is a schematic diagram of a portion of a first set of scan flip-flops 801- 802 corresponding to scan flip-flop 500 in FIG. 5A, in accordance with some embodiments. Referring to FIGS. 2A-7B, elements in FIG. 8A are designated with the same reference numerals for ease of understanding. The specific operations of similar elements already explained in detail in the above paragraphs are omitted here for brevity, unless there is a need to present the cooperation relationship with the elements shown in FIG. 8A.In some embodiments, each scan flip-flop in the first set of scan flip-flops 801- 802 is configured with respect to, for example, scan flip-flop 500 in FIG. 5A. Inverters 811- 812 are configured with respect to, for example, inverters 251- 252 in FIG. 2A. As illustratively shown in FIG. 8A, the scan flip-flops 801- 802 are configured to operate in response to an output signal CLKB 1 of the inverter 811 and an output signal CLKBB 1 of the inverter 812, while the scan flip-flop 802 receives the signal data input SI 1. The clock signal CLKB1 is generated by the inverter 811 inverting the clock signal CP1, and the clock signal CLKBB1 is generated by the inverter 812 inverting the clock signal CLKB1. In some embodiments, the output data signal Q 2 of the scan flip-flop 802 is received by the scan flip-flop 801, and the scan flip-flop 801 outputs the output data signal Q 4.Reference is now made to FIG. 8B. FIG. 8B is a schematic diagram of a portion of a second set of scan flip-flops 803- 804 corresponding to scan flip-flop 200 in FIG. 2A, in accordance with some embodiments. Referring to FIGS. 2A-8A, like elements in FIG. 8B are designated with like reference numerals for ease of understanding. The specific operations of similar elements already explained in detail in the above paragraphs are omitted here for brevity, unless there is a need to present the cooperation relationship with the elements shown in FIG. 8B.In some embodiments, each scan flip-flop in the second set of scan flip-flops 803- 804 is configured with respect to, for example, scan flip-flop 200 in FIG. 2A. Inverters 813- 814 are configured with respect to, for example, inverters 251- 252 in FIG. 2A. As illustratively shown in FIG. 8B, the scan flip-flops 803- 804 are configured to operate in response to an output signal CLKB 2 of the inverter 813 and an output signal CLKBB 2 of the inverter 814, while the scan flip-flop 804 receives the signal data input SI 2. Clock signal CLKB2 is generated by inverter 813, which inverts clock signal CP2, and clock signal CLKBB2 is generated by inverter 814, which inverts clock signal CLKB2. In some embodiments, the output data signal Q 1 of the scan flip-flop 804 is received by the scan flip-flop 803, and the scan flip-flop 803 outputs the output data signal Q 3.In some embodiments, clock signals CP 1 and CP 2 are different. Accordingly, the first set of scan flip-flops 801- 802 and the second set of scan flip-flops 803- 804 have different timing characteristics. In other words, in some embodiments, the first set of scan flip-flops 801- 802 and the second set of scan flip-flops 803- 804 are configured to be in two independent multi-bit flip-flop circuits.The configurations in FIGS. 8A-8B are provided for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. The clock signals CP1 and CP2 are, for example, the same. In various embodiments, the output data signals Q 1-Q 2 are not received by the scan flip-flops 801 and 803. Each of the scan flip-flops 801-804 receives the same signal data input SI.FIGS. 9A to 9C are layout views of the first set of scan flip-flops 801- 802 and the second set of scan flip-flops 803- 804 included in 4-bit flip-flop circuits 91- 93 in the semiconductor device in FIG. 1A, according to some embodiments. Referring to FIGS. 2A-8B, like elements in FIGS. 9A-9C are designated by like reference numerals for ease of understanding.Reference is now made to FIG. 9A. The multi-bit flip-flop circuit 91 includes cells 202-203, 503-504, a first pair of clock cells 815-816, and a second pair of clock cells 817-818. The cells 503- 504 have a width W 4 that is greater than the width W 1 and the cell height H 1. In some embodiments, scan flip-flops 801- 802 in the first set of scan flip-flops are arranged in cells 504 of bit 4 and 503 of bit 2, respectively. The scan flip-flops 803-804 in the second set of scan flip-flops are located in cells 202 of bit 3 and 203 of bit 1, respectively. Illustratively, 4-bit flip-flop 91 includes cells 815- 818. Cells 815- 816 correspond to inverters 813- 814 in FIG. 8B, respectively. Cells 817- 818 correspond to inverters 811- 812 in FIG. 8A, respectively.As shown in FIG. 9A, the cells 203 of bit 1 and the first pair of clock cells 815- 816 are arranged in the cell row ROW 1. The cells 202 of bit 3 and the second pair of clock cells 817- 818 are arranged in the row of cells ROW 2. The cell 503 of bit 2 is arranged in the cell row ROW3. Cell 504 of bit 4 is arranged in cell row ROW4.Reference is now made to FIG. 9B. In comparison to FIG. 9A, rather than the cell 503 of bit 2 abutting the cell 202 of bit 3 and the second pair of clock cells 817- 828, the cell 504 of bit 4 is arranged abutting the cell 202 of bit 3 and the second pair of clock cells 817- 818, while the cell 503 of bit 2 is arranged on the opposite side of the cell 504 of bit 4.Reference is now made to FIG. 9C. In comparison to FIG. 9A, rather than having cell 202 of bit 3 and the second pair of clock cells 817-818 arranged abutting cell 503 of bit 2, cell 203 of bit 1 and the first pair of clock cells 815-816 of multi-bit flip-flop circuit 93 are arranged abutting cell 503 of bit 2, while cell 202 of bit 3 and the second pair of clock cells 817-818 are arranged on the opposite side of cell 203 of bit 1.The configurations in FIGS. 9A-9C are provided for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, the sequence of the cell rows ROW1-ROW4 is different from what was shown in the embodiments of FIGS. 9A-9C, for example.Reference is now made to FIG. 10. FIG. 10 is a layout view of a plurality of first sets of scan flip-flops and a plurality of second sets of scan flip-flops included in an 8-bit flip-flop circuit 101 in the semiconductor device 10 in FIG. 1A, according to some embodiments. Referring to FIGS. 2A-9C, like elements in FIG. 10 are designated with like reference numerals for ease of understanding.As shown in FIG. 10, in comparison to FIG. 9A, instead of cells 503 of bit 2 and 504 of bit 4, multi-bit flip-flop circuit 101 includes cells 501 of bit 2, 505 of bit 4, 505 of bit 8 and 501 of bit 6. To illustrate, cells 505 of bit 4 and 505 of bit 8 are arranged in cell row ROW 4 and cells 501 of bit 2 and 501 of bit 6 are arranged in cell row ROW 3.In some embodiments, one of the first set of scan flip-flops 801- 802 corresponding to bit 2 and bit 4 is located in cells 501 of bit 2 and 505 of bit 4 and the other one corresponding to bit 6 and bit 8 is located in cells 501 of bit 6 and 505 of bit 8.As illustratively shown in FIG. 10, multi-bit flip-flop circuit 101 further includes cells 203 of bit 5 and 202 of bit 7. In some embodiments, one of the second set of scan flip-flops 803- 804 corresponding to bit 1 and bit 3 is located in cells 203 of bit 1 and 202 of bit 3 and the other one corresponding to bit 5 and bit 7 is located in cells 203 of bit 5 and 202 of bit 7.The configurations in FIG. 10 are given for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, the sequence of the cell rows ROW1-ROW4 is different from what is shown in the embodiments in FIG. 10, for example.With the configurations in FIGS. 9A-10, by utilizing two pairs of clock cells in a mixed cell row architecture, the flexibility of arranging two independent multi-bit flip-flop circuits is provided, and further the overall area of the multi-bit flip-flop circuits is reduced.FIG. 11 is a flow diagram of a method 1100 of generating a layout design for fabricating an integrated circuit including multi-bit flip-flop circuits 31- 36, 41- 42, 61. It should be appreciated that additional operations may be provided before, during, and after the processes shown in FIG. 11, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable. In the various views and illustrative embodiments, like reference numerals are used to designate like elements. The method 1100 includes operations 1110- 1120, which are described below with reference to the multi-bit flip-flop circuit 61 in FIG. 6A.In operation 1110, cells 501 of bit 1, 501 of bit 3, 202 of bit 2, and 204 of bit 4 are arranged in cell rows ROW1-ROW4. As shown in the embodiments of FIG. 6A, cells 501 of bit 1, 501 of bit 3 have width W 1, and cells 202 of bit 2 and 204 of bit 4 have width W 2, which is different from width W 1.In some embodiments, width W 2 is less than width W 1.In some embodiments, the scan flip-flops corresponding to cells 501 and 202 have different functions as mentioned above with reference to FIG. 6A. For example, compared to the scan flip-flop in cell 202, the scan flip-flop in cell 501 is further configured to operate in response to the control signal CD.In some embodiments, cell rows ROW 1 and ROW 3 have row height H 1, and cell rows ROW 2 and ROW 4 have row height H 2, where row height H 1 is less than row height H 2.In some embodiments, as shown in FIG. 6A, cells 501 of bit 1 and 501 of bit 3 are arranged in cell rows ROW 1 and ROW 3. The cell 202 of bit 2 and 204 of bit 4 are arranged in the cell rows ROW2 and ROW4.In operation 1120, clock cells 253- 254 are arranged in cell rows ROW 2 and ROW 4. In the embodiments of FIG. 6A, clock cell 253 abuts cell 202 of bit 2 and clock cell 254 abuts cell 204 of bit 4.In various embodiments, as shown in FIG. 9A, the first pair of clock cells 815- 816 are arranged in the cell row ROW 1 and the second pair of clock cells 817- 818 are arranged in the cell row ROW 2, wherein the cell height is different from that of the cell row ROW 1.In some embodiments, as shown in FIG. 6A, cells 501 of bit 1, 501 of bit 3, 202 of bit 2, 204 of bit 4 are included in clock cells 253- 254 in a standard cell that operates as multi-bit flip-flop circuit 61.Reference is now made to FIG. 12. FIG. 12 is a block diagram of an electronic design automation (EDA) system 1200 for designing the integrated layout design, according to some embodiments of the present disclosure. EDA system 1200 is configured to implement one or more operations of method 110 disclosed in FIG. 11 and will be discussed in more detail in connection with FIGS. 1A-10. In some embodiments, EDA system 1200 includes an APR system.In some embodiments, EDA system 1200 is a general purpose computing device that includes a hardware processor 1202 and a non-transitory computer readable storage medium 1204. Storage medium 1204 is encoded, i.e., stores, by, among other things, computer program code(s) 1206, i.e., a set of executable instructions. Execution of the instructions 1206 by hardware processor 1202 represents (at least in part) an EDA tool that implements a portion or all of, for example, the method 1200.Processor 1202 is electrically coupled to computer readable storage medium 1204 via bus 1208. Processor 1202 is also electrically coupled to an I / O interface 1210 and a manufacturing tool 1216 via bus 1208. A network interface 1212 is also electrically connected to processor 1202 via bus 1208. Network interface 1212 is connected to network 1214 such that processor 1202 and computer readable medium 1204 are capable of connecting to external elements via network 1214. The processor 1202 is configured to execute computer program code 1206, encoded in computer readable storage medium 1204, for causing EDA system 1200 to be usable to perform part or all of the recited processes and / or methods. In one or more embodiments, processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.In one or more embodiments, the computer readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). The computer readable storage medium 1204 includes, for example, a semiconductor or solid state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments using optical disks, computer readable storage medium 1204 includes a compact disk read-only memory (CD-ROM), a compact disk read / write memory (CD-R / W), and / or a digital video disk (DVD).In one or more embodiments, storage medium 1204 stores computer program code 1206 configured to cause EDA system 1200 (where such execution represents (at least in part) the EDA tool) to be usable to perform part or all of the recited processes and / or methods. In one or more embodiments, storage medium 1204 also stores information that enables part or all of the recited processes and / or methods to be performed. In one or more embodiments, storage medium 1204 stores an IC layout diagram 1220 of standard cells, including those standard cells disclosed herein, where cells correspond to, for example, the multi-bit flip-flop circuits 31- 36, 41- 42, 61- 63, 71- 72, 91- 93, and 101 discussed above with reference to FIGS. 1A-10.EDA system 1200 includes I / O interface 1210. I / O interface 1210 is coupled to external circuitry. In one or more embodiments, I / O interface 1210 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or arrow keys for communicating information and commands to processor 1202.EDA system 1200 also includes network interface 1212 coupled to processor 1202. Network interface 1212 enables EDA system 1200 to communicate with network 1214 to which one or more other computer systems are connected. Network interface 1212 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1264. In one or more embodiments, a portion or all of the recited processes and / or methods are implemented in two or more systems 1200.EDA system 1200 also includes manufacturing tool 1216 coupled to processor 1202. The fabrication tool 1216 is configured to fabricate integrated circuits, such as the multi-bit flip-flop circuits 31- 36, 41- 42, 61- 63, 71- 72, 91- 93, and 101 discussed above with reference to FIGS. 1A-10, in accordance with the design files processed by the processor 1202.EDA system 1200 is configured to receive information through I / O interface 1210. The information received by I / O interface 1210 includes one or more instructions, data, drop rules, libraries of standard cells, and / or other parameters for processing by processor 1202. The information is transmitted to processor 1202 via bus 1208. EDA system 1200 is configured to receive information related to a UI through I / O interface 1210. The information is stored in computer readable medium 1204 as design specification 1222.In some embodiments, some or all of the recited processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the recited processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the recited processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of said processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the recited processes and / or methods are implemented as a software application used by the EDA system 1200. In some embodiments, a layout diagram including standard cells is generated using a suitable layout generation tool.In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external / removable and / or internal / built-in storage units, for example one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, a RAM, a memory card, and the like.FIG. 13 is a block diagram of an IC manufacturing system 1300 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, (A) one or more semiconductor masks and / or (B) at least one component is fabricated in a layer of a semiconductor integrated circuit using IC fabrication system 1300.In FIG. 13, IC manufacturing system 1300 includes entities such as a design house 1320, a mask house 1330, and an IC paver / fab ("Fab") 1350 that interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1360. The entities in the IC manufacturing system 1300 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a plurality of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and / or receives services from one or more of the other entities. In some embodiments, two or more of design house 1320, mask house 1330, and IC fab 1350 belong to a single, larger entity. In some embodiments, two or more of design house 1320, mask house 1330, and IC fab 1350 coexist in a common facility and share common resources.Design house (or design team) 1320 generates an IC design layout diagram 1322. IC design layout diagram 1322 includes various geometric structures, such as an IC layout design illustrated in FIGS. 3A-4B, 6A-7B, and / or 9A-10, designed for an IC device 1360, such as integrated circuits 100 and 700 discussed above with reference to FIGS. 3A-4B, 6A-7B, and / or 9A-10. The geometric patterns correspond to patterns of the metal, oxide, or semiconductor layers that form the various components of the IC device 1360 to be fabricated. The various layers connect to form various IC features. A portion of the IC design layout diagram 1322 includes, for example, various IC features such as an active region, gate electrode, source and drain, conductive segments or vias of an interlayer connection to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers disposed on the semiconductor substrate. Design house 1320 implements a suitable design method for forming IC design layout diagram 1322. The design method includes one or more logic designs, physical design, or placement and routing. IC design layout diagram 1322 is presented in one or more data files containing geometric pattern information. IC design layout diagram 1322 may be expressed in, for example, a GDSII file format or a DFII file format.Mask house 1330 includes data preparation 1332 and mask fabrication 1344. Mask house 1330 uses IC design layout diagram 1322 to fabricate one or more masks 1345 to be used to fabricate the various layers of IC device 1360 in accordance with IC design layout diagram 1322. Mask house 1330 performs mask data editing 1332, where IC design layout diagram 1322 is translated into a representative data file ("RDF"). Mask data preparation 1332 provides the RDF to mask fabrication 1344. Mask fabrication 1344 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1345 or a semiconductor wafer 1353. The IC design layout diagram 1322 is manipulated by mask data handler 1332 to conform to certain characteristics of the mask writer and / or requirements of the IC fab 1350. In FIG. 13, data preparation 1332 and mask fabrication 1344 are illustrated as separate elements. In some embodiments, data preparation 1332 and mask fabrication 1344 may be collectively referred to as mask data preparation.In some embodiments, data conditioning 1332 includes Optical Proximity Correction (OPC) that uses lithography enhancement techniques to compensate for image errors, such as those that may result from diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 1322. In some embodiments, data preparation 1332 further includes resolution enhancement techniques (RET) such as off-axis illumination, sub-resolution auxiliary functions, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, Inverse Lithography Technology (ILT) is also used that deals with OPC as an inverse imaging problem.In some embodiments, data preparation 1332 includes a mask rule checker (MRC) that checks the IC design layout diagram 1322 that has undergone processes in the OPC with a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 1322 to compensate for restrictions during mask fabrication 1344, which undo some of the modifications made by OPC to meet mask generation rules.In some embodiments, data preparation 1332 includes lithography process checking (LPC) that simulates processing implemented by IC Fab 1350 to fabricate IC device 1360. LPC simulates this processing based on IC design layout diagram 1322 to produce a simulated fabricated device, such as IC device 1360. The processing parameters in LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors such as aerial contrast, depth of field ("DOF"), mask defect enhancement factor ("MEEF"), other suitable factors and the like, or combinations thereof. In some embodiments, after a simulated fabricated device is created by LPC, if the simulated device is not sufficiently close in shape to meet design rules, OPC and / or MRC are repeated to further refine IC design layout diagram 1322.It is to be understood that the above description of data preparation 1332 has been simplified for the sake of clarity. In some embodiments, data preparation 1332 includes additional features, such as a logic operation (LOP) for modifying IC design layout diagram 1322 according to manufacturing rules. Moreover, the processes applied to IC design layout diagram 1322 during data preparation 1332 may be performed in a variety of different orders.After data preparation 1332 and during mask fabrication 1344, a mask 1345 or a set of masks 1345 is fabricated based on the modified IC design layout diagram 1322. In some embodiments, mask fabrication 1344 includes performing one or more lithographic exposures based on IC design layout diagram 1322. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on a mask (photomask or reticle) 1345 based on the modified IC design layout diagram 1322. Mask 1345 may be formed in various technologies. In some embodiments, mask 1345 is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and transmitted through the transparent regions. In one example, a binary mask version of mask 1345 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, mask 1345 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1345, various features in the structure formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and image quality. In various examples, the phase shift mask may be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 1344 are used in a plurality of processes. Such one or more mask(s) are employed, for example, in an ion implantation process to form various doped regions in semiconductor wafers 1353, an etching process to form various etching regions in semiconductor wafers 1353, and / or other suitable processes.IC Fab 1350 includes wafer fabrication 1352. IC fab 1350 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a plurality of different IC products. In some embodiments, IC Fab 1350 is a semiconductor foundry. For example, there may be one fabrication facility for front-end manufacturing a plurality of IC products (front-end-of-line (FEOL) manufacturing), while a second fabrication facility may provide back-end manufacturing for connection and packaging of the IC products (back-end-of-line (BEOL) manufacturing), and a third fabrication facility may provide other services for the foundry store.IC Fab 1350 uses mask(s) 1345 manufactured by mask house 1330 to fabricate IC device 1360. Thus, IC Fab 1350 at least indirectly uses IC design layout diagram 1322 to fabricate IC device 1360. In some embodiments, semiconductor wafer 1353 is fabricated from IC Fab 1350 using mask(s) 1345 to form IC device 1360. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram 1322. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1353 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent fabrication steps).As described above, integrated circuits in the present disclosure provide multi-bit flip-flop architecture arranged in hybrid cell rows. By placing cells with different cell architectures and functions in cell rows with different cell heights, space requirements are reduced and flexibility of timing characteristics is provided.In some embodiments, an integrated circuit is disclosed that includes a first plurality of cell rows; a second plurality of cell rows arranged abutting the first plurality of cell rows, in which a first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows; first and second clock inverters are arranged in the second plurality of cell rows, wherein a first clock signal generated by the first clock inverter and a second clock signal generated by the second clock inverter have different phases; and a plurality of flip-flops arranged in the first plurality of cell rows and the second plurality of cell rows, the flip-flops comprising a first plurality of flip-flops configured to operate in response to the first and second clock signals. In some embodiments, the first number of fins is less than the second number of fins. In some embodiments, the first number of fins is equal to one and the second number of fins is equal to two. In some embodiments, the second plurality of cell rows abuts each other and is disposed between at least two of the first plurality of cell rows. In some embodiments, the plurality of flip-flops further comprises: a second plurality of flip-flops different from the first plurality of flip-flops, the second plurality of flip-flops configured to operate in response to the first clock signal and the second clock signal; wherein the first plurality of flip-flops are arranged in the second plurality of cell rows and the second plurality of flip-flops are arranged in the first plurality of cell rows. In some embodiments, the integrated circuit further comprises third and fourth clock inverters arranged in a first row of the first plurality of cell rows, wherein the third clock inverter is abutting, arranged in the first row of the first plurality of cell rows, on one of the first plurality of flip-flops. In some embodiments, the plurality of flip-flops further comprises a second plurality of flip-flops; wherein the second plurality of flip-flops is configured to respond to output signals of the third and fourth inverters.An integrated circuit is also disclosed that includes a first flip-flop disposed in a first cell and a second flip-flop disposed in a second cell; a third flip-flop disposed in a third cell and a fourth flip-flop disposed in a fourth cell; and a first inverter disposed in a first clock cell and a second inverter disposed in a second clock cell; wherein the first and second cells have a first height and the third and fourth cells and the first and second clock cells have a second height that is greater than the first height; wherein the first clock cell abuts the third cell and the third cell abuts the first cell, the fourth cell, or the combination thereof. In some embodiments, the second clock cell abuts the fourth cell. In some embodiments, the first and second clock cells abut each other. In some embodiments, the first and third flip-flops include different circuit configurations, wherein the first flip-flop is configured to be activated in response to a reset signal. In some embodiments, the integrated circuit further includes a third inverter disposed in a third clock cell and a fourth inverter disposed in a fourth clock cell; wherein the third and fourth clock cells have the first height and abut each other. In some embodiments, the first and second clock cells and the third cell are arranged in a first cell row having the second height, and the third and fourth clock cells and the first cell are arranged in a second cell row having the first height. In some embodiments, the first and third flip-flops are configured to operate in response to output signals of the first and second inverters, and the second and fourth flip-flops are configured to operate in response to output signals of the third and fourth inverters. In some embodiments, the integrated circuit further includes a fifth flip-flop disposed in a fifth cell and a sixth flip-flop disposed in a sixth cell, the fifth and sixth cells having the first height; and a seventh flip-flop disposed in a seventh cell and an eighth flip-flop disposed in an eighth cell, the seventh and eighth cells having the second height; wherein the first clock cell is disposed intermediate the third and seventh cells and the second clock cell is disposed intermediate the fourth and eighth cells. In some embodiments, the first inverter is configured to generate a first inverted signal from a clock signal and the second inverter is configured to generate a second inverted signal from the first inverted signal; wherein the first through eighth flip-flops are configured to operate in response to the first and second inverted signals.A method is also disclosed that includes arranging a first plurality of cells, a second plurality of cells, and a plurality of clock cells in a plurality of cell rows. Each of the first plurality of cells has a first width and each of the second plurality of cells has a second width different from the first width. Each of the plurality of clock cells abuts at least one of the first plurality of cells. The first and second pluralities of cells and the plurality of clock cells are included in a standard cell that operates as a multi-bit flip-flop circuit. In some embodiments, the first width is less than the second width, and the first and second pluralities of cells have different functions. In some embodiments, the plurality includes a first plurality of cell rows each having a first height and a second plurality of rows each having a second height less than the first height; the method further comprising arranging the first plurality of cells having a first type of function in the first plurality of cell rows; and arranging the second plurality of cells having a second type of function in the second plurality of cell rows. In some embodiments, the plurality of clock cells includes a first pair of clock cells and a second pair of clock cells, and the plurality of cell rows includes a first plurality of cell rows each having a first height and a second plurality of rows each having a second height less than the first height; the method further comprising: arranging the first pair of clock cells and a cell of the first plurality of cells in one of the first plurality of cell rows; and arranging the second pair of clock cells and another cell of the first plurality of cells in one of the second plurality of cell rows.

Claims

An integrated circuit comprising: a first plurality of cell rows (ROW1, ROW3); a second plurality of cell rows (ROW2, ROW4) arranged in abutment with the first plurality of cell rows (ROW1, ROW3), wherein a first number of fins in the first plurality of cell rows (ROW1, ROW3) is different from a second number of fins (141, 142) in the second plurality of cell rows (ROW2, ROW4); first and second clock inverters (251, 252; 811, 812) arranged in the second plurality of cell rows (ROW2, ROW4), wherein a first clock signal generated by the first clock inverter (251; 811), and a second clock signal generated by the second clock inverter (252; 812) having different phases; and a plurality of flip-flops (202, 204, 501) disposed in the first plurality of cell rows (ROW1, ROW3) and the second plurality of cell rows (ROW2, ROW4), the plurality of flip-flops (202, 204, 501) comprising a first plurality of flip-flops configured to operate in response to the first and second clock signals.The integrated circuit of claim 1, wherein a row of cells of the first plurality of rows of cells (ROW1, ROW3) comprises active regions (110, 120) each having the first number of fins, wherein a row of cells of the second plurality of rows of cells (ROW2, ROW4) comprises active regions (130, 140) each having the second number of fins (141, 142, 131, 132).The integrated circuit of claim 1 or claim 2, wherein the first number of fins is less than the second number of fins (141, 142, 131, 132).The integrated circuit of any of claims 1 to 3, wherein the first number of fins is equal to one and the second number of fins (141, 142, 131, 132) is equal to two.The integrated circuit of any preceding claim, wherein the second plurality of cell rows (ROW2, ROW4) abut each other and are disposed between at least two of the first plurality of cell rows (ROW1, ROW3).The integrated circuit of any preceding claim, wherein the plurality of flip-flops further comprises: a second plurality of flip-flops different from the first plurality of flip-flops, the second plurality of flip-flops configured to operate in response to the first clock signal and the second clock signal; wherein the first plurality of flip-flops are disposed in the second plurality of cell rows (ROW2, ROW4), and the second plurality of flip-flops are disposed in the first plurality of cell rows (ROW1, ROW3).The integrated circuit of claim 1 to claim 5, further comprising: third and fourth clock inverters (813; 814) arranged in a first row of the first plurality of cell rows (ROW1, ROW3), wherein the third clock inverter (813) is arranged in abutment with a flip-flop in the first plurality of flip-flops arranged in the first row of the first plurality of cell rows (ROW1, ROW3).The integrated circuit of claim 7, wherein the plurality of flip-flops further comprises: a second plurality of flip-flops; wherein the second plurality of flip-flops are configured to operate in response to inputs from the third and fourth clock inverters (813, 814).The integrated circuit of any preceding claim, wherein each of the first plurality of cell rows has a first width (W1) and each of the second plurality of cell rows has a second width (W2) different from the first width (W1).The integrated circuit of claim 9, wherein the first width (W1) is less than the second width (W2), and the first and second pluralities of cells have different functions.An integrated circuit comprising: a first flip-flop disposed in a first cell (501 of bit1) and a second flip-flop disposed in a second cell (501 of bit3); a third flip-flop disposed in a third cell (202 of bit2) and a fourth flip-flop disposed in a fourth cell (202 of bit4); and a first inverter (251) disposed in a first clock cell (253) and a second inverter (252) disposed in a second clock cell (254); wherein the first and second cells (501 of bit1 and bit2) have a first height (H1) and the third and fourth cells (202 of bit3 and bit4) and the first and second clock cells (253, 254) have a second height (H2) greater than the first height, wherein the first and second cells (501 of bit1 and bit2) having the first height each comprise a first number of fins, wherein the third and fourth cells (202 of bit3 and bit4) having the second height each comprise a second number of fins (131, 132, 141, 142), and wherein the first number of fins is different than the second number of fins (141, 142); and wherein the first clock cell (253) abuts the third cell (501 of bit3) and the third cell (501 of bit3) abuts the first cell (501 of bit1) and / or the fourth cell (202 of bit4).The integrated circuit of claim 11, wherein the second clock cell (254, 816) abuts the fourth cell (202 of bit4).The integrated circuit of claim 11 or 12, wherein the first and second clock cells (253, 254) abut each other.The integrated circuit of any of claims 11 to 13, wherein the first and third flip-flops comprise different circuit configurations, the first flip-flop being configured to be activated in response to a reset signal.The integrated circuit of any of claims 11 to 14, further comprising: a third inverter (251) disposed in a third clock cell (815) and a fourth inverter (252) disposed in a fourth clock cell (816); wherein the third and fourth clock cells (815, 816) have the first height and abut each other.The integrated circuit of claim 15, wherein the first and second clock cells (253, 254) and the third cell are arranged in a first cell row having the second height, and the third and fourth clock cells (815, 816) and the first cell are arranged in a second cell row having the first height.The integrated circuit of claim 15 or 16, wherein the first and third flip-flops are configured to operate in response to output signals of the first and second inverters (251, 252), and the second and fourth flip-flops are configured to operate in response to output signals of the third and fourth inverters (251, 252).The integrated circuit of any of claims 11 to 17, further comprising: a fifth flip-flop disposed in a fifth cell and a sixth flip-flop disposed in a sixth cell, wherein the fifth and sixth cells have the first height; and a seventh flip-flop disposed in a seventh cell and an eighth flip-flop disposed in an eighth cell, wherein the seventh and eighth cells have the second height; wherein the first clock cell (253) is disposed between the third and seventh cells and the second clock cell (254) is disposed between the fourth and eighth cells.The integrated circuit of claim 18, wherein the first inverter (251) is configured to generate a first inverted signal from a clock signal and the second inverter (252) is configured to generate a second inverted signal from the first inverted signal; wherein the first through eighth flip-flops are configured to operate in response to the first and second inverted signals.The integrated circuit of any of claims 11 to 19, wherein said cells and said clock cells (254) are included in a standard cell that operates as a multi-bit flip-flop circuit.

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