DISPLAY DEVICE

Abstract

Display device (10), comprising: a display panel (100) comprising a display area (AA) and a first to fourth non-display area (NA1, NA2, NA3, NA4) surrounding the display area (AA), wherein the display area (AA) comprises a plurality of pixels (P1, P2, P3) connected to a plurality of gate lines (GL) numbered consecutively; a pad section (170) located in the first non-indication area (NA1); a first gate driver circuit (310) located in the second non-display area (NA2) for driving a first group of gate lines under the plurality of gate lines (GL); a second gate driver circuit (320) located in the third non-display area (NA3) for driving a second group of gate lines under the plurality of gate lines (GL); wherein each gate line (GL) of the first group of gate lines is an odd-numbered gate line (GL) from the plurality of gate lines (GL), and each gate line (GL) of the second group of gate lines is an even-numbered gate line (GL) from the plurality of gate lines (GL), and a third gate driver circuit (330) located in the fourth non-display area (NA4) for driving the first and second groups of gate lines, wherein the display panel (100) further comprises a plurality of connecting lines (CL1, CL2) which connect the gate lines (GL) of the first and second group of gate lines to the third gate driver circuit (300).

Description

BACKGROUND Area of ​​the invention

[0001] The present invention relates to a display device. Discussion of related technology

[0002] Display devices are widely used as screens in laptop computers, tablet computers, smartphones, portable display devices, and portable information devices, in addition to display devices in televisions (TVs) and monitors. Examples of display devices include liquid crystal displays (LCDs) and light-emitting displays. Because light-emitting displays project an image using a self-emissive device, they offer fast response times, low power consumption, and good viewing angles, thus attracting considerable attention as next-generation display devices.

[0003] The display devices can each include a gate driver that supplies a gate pulse to a plurality of gate lines, and by using a shift register, the gate driver can sequentially shift the gate pulse applied to the plurality of gate lines. Furthermore, since the shift register and a pixel array are provided on a substrate of a display panel, the display devices can each have a gate-in-panel (GIP) structure.

[0004] In a display device of the related technology, since the shift register is arranged in each of a left and a right non-display region of the substrate, the gate pulse can be fed by a dual-feed method or an interlaced method. In this case, the dual-feed method has the problem that one design region of the shift register increases, so that the left and right non-display regions also increase. Similarly, when the interlaced method is applied to a large display panel, it has the problem that the delay of the gate pulse increases in the direction away from an input terminal where the gate pulse is applied.

[0005] Furthermore, the display device of the related technology does not have a structure for reducing parasitic capacitance between metal conductors contained in a display panel.

[0006] Furthermore, the display device of the related technology should have a structure for covering a pad portion exposed on a front surface of the display panel. Therefore, in the display device of the related technology, at least one of the four side surfaces of a front cover supporting the display panel should surround the display panel on a front area of ​​the display panel. Therefore, it is difficult to reduce the size of a front bezel of a front cover of a display device.

[0007] From US 2019 / 0114981 A1, a display device is known in which each gate line is connected at its two ends to a respective gate driver located on the left or right side of a display panel, and each gate line is connected to another gate driver located on the top and / or bottom of the display panel. SUMMARY

[0008] Accordingly, the present invention is directed to providing a display device that substantially overcomes one or more of the problems caused by limitations and disadvantages of the related technology.

[0009] One aspect of the present invention is directed to providing a display device in which a gate driver circuit is arranged in all non-display areas except one non-display area which has a pad part, from a plurality of non-display areas, and a plurality of connecting lines are provided which are provided on a layer which is distinct from a plurality of gate lines and are connected to the gate lines.

[0010] Further advantages and features of the invention are partly set forth in the following description and partly become apparent to those with average familiarity with the technology upon studying the following or can be discovered by carrying out the invention. The objectives and other advantages of the The invention can be realized and achieved through the structure, which is particularly highlighted in the written description and the claims thereto, as well as the accompanying drawings.

[0011] To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and described in detail herein, a display device according to claim 1 is provided. Further embodiments are described in the dependent claims.

[0012] Details of other embodiments are included in the detailed description and drawings.

[0013] It should be understood that both the preceding general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide a further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated into and form part of this application, represent embodiments of the invention and, together with the description, serve to explain the principle of the invention. The following applies to the drawings: Fig. 1 is a top view showing a display device according to an embodiment of the present invention; Fig. 2 is a diagram that represents a connection relationship between a plurality of stages and a plurality of gate lines in a display device according to a first embodiment of the present invention; Fig. Figure 3 is a diagram showing a first gate driver circuit in the Fig. 2 represents the display device shown; Fig. 4 is a diagram showing a second gate driver circuit in the Fig. 2 represents the display device shown; Fig. 5 is a diagram showing a third gate driver circuit in the Fig. 2 represents the display device shown; Fig. Figure 6 is a waveform diagram showing a gate start signal, a gate shift clock, and a common gate signal in the Fig. The display device shown in section 2 is shown; Fig. 7 is a circuit diagram showing an internal configuration of a Fig. The first stage is shown in section 3; Fig. Figure 8 is a diagram describing the effect of reducing the size of a non-display area in the Fig. 2 display device shown; Fig. Figure 9 is a diagram describing the effect of reducing the delay of a gate pulse in the Fig. 2 display device shown; Fig. 10 is a diagram that represents a connection relationship between a plurality of stages and a plurality of gate lines in a display device according to a second embodiment of the present invention; Fig. 11 is a diagram showing a first gate driver circuit in the Fig. 10 represents the display device shown; Fig. 12 is a diagram showing a second gate driver circuit in the Fig. 10 represents the display device shown; Fig. 13 is a diagram showing a third gate driver circuit in the Fig. 10 represents the display device shown; Fig. Figure 14 is a diagram describing the effect of reducing the size of a non-display area in the Fig. 10 display device shown; Fig. 15 is an example diagram showing a cross-sectional area of ​​a Fig. 2 and Fig. schematically represents the 10 display panels shown; Fig. Figure 16 is another example diagram showing the cross-sectional area of ​​the Fig. 2 and Fig. schematically represents the 10 display panels shown; Fig. Figure 17 is another example diagram showing the cross-sectional area of ​​the Fig. 2 and Fig. schematically represents the 10 display panels shown; Fig. Figure 18 is another example diagram showing the cross-sectional area of ​​the Fig. 2 and Fig. schematically represents the 10 display panels shown; Fig. Figure 19 is an exemplary diagram to describe the principle that a parasitic capacitance decreases in a display device according to the present invention; Fig. Figure 20 is an exemplary diagram to describe a method of attaching a circuit film to a display panel in a display device according to the present invention; Fig. 21 is an exemplary diagram that presents an example where the in Fig. 20 display panels are attached to a front cover; and Fig. 22 is an exemplary diagram showing a frontal area of ​​the in Fig. 21 display panels are shown. DETAILED DESCRIPTION OF THE INVENTION

[0015] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings to denote the same or similar parts.

[0016] Advantages and features of the present invention, and methods of its realization, are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the present invention can be embodied in various forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided to ensure that this invention is thoroughly and completely explained and to fully convey its scope to those familiar with the technology. Furthermore, the present invention is defined only within the scope of the claims.

[0017] A shape, size, ratio, angle, and number disclosed in the drawings to describe embodiments of the present invention are merely examples, and thus the present invention is not limited to the details shown. The same reference numerals refer to the same elements throughout. In the following description, if a detailed description of a corresponding known function or configuration is considered to unnecessarily obscure the important point of the present invention, the detailed description is omitted. In a case where 'have', 'have', and 'contain' are used in the present description, a further part may be added unless 'only' is used. Singular expressions may include plural forms unless otherwise indicated.

[0018] When designing an element, the element is designed to include an error range, even though this is not explicitly described.

[0019] When describing a positional relationship, for example when a positional relationship between two parts is described as 'on-', 'above-', 'below-', and 'next to-', one or more other parts may be positioned between the two parts unless 'exactly' or 'directly' is used.

[0020] When describing a temporal relationship, for example when the temporal sequence is described as 'after', 'subsequent', 'next', and 'before', the non-continuous case may be included unless 'exactly' or 'immediately' is used.

[0021] It is to be understood that, although the terms "first," "second," etc., may be used herein to describe different elements, these elements are not intended to be limited by these terms. These terms are used only to distinguish one element from another and do not necessarily define any order. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present invention.

[0022] In describing elements of the present invention, the terms "first," "second," etc., may be used. These terms serve only to distinguish one element from another, and the nature, sequence, arrangement, or number of any such element should not be limited by these terms. It is to be understood that when an element or layer is described as "connected," "coupled," or "adhered" to another element or layer, the element or layer may be directly connected or adhered to the other element or layer, but the other element or layer may be "arranged" between elements or layers, or elements or layers may be "connected," "coupled," or "adhered" to each other by means of the other element or layer.

[0023] Features of different embodiments of the present invention can be partially or completely coupled or combined with one another and can interact and be operated in various ways, as those familiar with the technology will readily understand. The embodiments of the present invention can be carried out independently of one another or together in a mutually dependent relationship.

[0024] The following describes in detail embodiments of a light-emitting display device according to the present invention with reference to the accompanying drawings. When adding reference numerals to elements from each of the drawings, even if the same elements are shown in other drawings, the same reference numerals may denote the same elements.

[0025] Fig. Figure 1 is a top view showing a display device 10 according to an embodiment of the present invention, and Fig. Figure 2 is a diagram illustrating the connection between a plurality of stages and a plurality of gate lines in a display device according to a first embodiment of the present invention. All components of the display device according to all embodiments of the present invention are operationally coupled and configured.

[0026] Referring to Fig. 1 and Fig. 2 The display device 10 can have a display panel 100, a display driver 200 and a gate driver 300.

[0027] The display panel 100 can have a display area AA and a non-display area NA. The display panel 100 can be a liquid crystal display panel or an organic light-emitting display panel, but is not limited to either and can be various types of panels.

[0028] If the display panel 100 is a liquid crystal display panel, a color filter for realizing a color may be provided in an upper substrate, which is arranged with a liquid crystal between the upper substrate and a thin-film transistor (TFT) substrate (a lower substrate) which has a transistor.

[0029] However, the color filter can be provided in a planarization layer covering the transistor. For example, the transistor can be located within the transistor substrate, the planarization layer can be placed on top of the transistor to eliminate any step difference, a pixel electrode can be placed on the planarization layer, and a liquid crystal layer can be placed on top of both the planarization layer and the pixel electrode. In this case, the planarization layer can be configured with at least two layers, and the color filter can also function as a planarization layer. Since a color filter is not located within the top substrate in this case, the fabrication process and structure of the top substrate can be simplified. This will be discussed in detail below. Fig. Described in sections 17 to 19.

[0030] The display area AA can be an area that displays an image and can be defined in a central region of any substrate. Here, the display area AA can correspond to an active region of a pixel array layer. For example, the display area AA can contain a multitude of pixels, which are accordingly provided in a multitude of pixel regions defined by the intersections of a multitude of data lines DL and a multitude of gate lines GL. Each of these multiple pixels can be defined as a minimum-unit region that emits light.

[0031] The display area AA can have a first display area AA1 and a second display area AA2.

[0032] The first display area AA can correspond to a left area of ​​the display area AA and can be adjacent to a first gate driver circuit 310. For example, one end (for example, a left end) of the first display area AA1 can face the first gate driver circuit 310, and the other end (for example, a bottom end) perpendicular to one end of the first display area AA1 can face the even stages ST2 to ST(2n) (where n is a natural number equal to or greater than four) of a third gate driver circuit 330.Therefore, one end of each of the odd gate lines GL1 to GL(2n-1) (where n is a natural number equal to or greater than four), which are arranged in the first display area AA1, can be connected to the first gate driver circuit 310 and can receive a gate pulse, and even gate lines GL2 to GL(2n) (where n is a natural number equal to or greater than four), which are arranged in the first display area AA1, can be connected to even stages ST2 to ST(2n) of the third gate driver circuit 330 by means of the second connecting line CL2 and can receive the gate pulse.

[0033] The first and second interconnects CL1 and CL2 and the gate leads can be provided on different layers, with an insulating layer in between. In this case, each interconnect and a corresponding gate lead can be electrically connected to each other via a contact hole.

[0034] If the display panel 100 is a liquid crystal display panel, the first and second interconnect lines in the TFT substrate can be provided by the same process as one of transistors contained in each pixel and metals contained in the pixel electrode.

[0035] For example, if the display panel 100 is a liquid crystal display panel, the first and second interconnects can be embedded in the TFT substrate and covered by the insulating layer, and the transistors can be placed on top of the insulating layer. That is, the first and second interconnects can be located beneath the transistors, thus isolating them. In this case, since there is no parasitic capacitance between the metal traces forming the transistors and the first and second interconnects, the driver efficiency of the transistors can be improved, and the load on both the first and second interconnects can be reduced. This will be explained in detail below with reference to... Fig. 15 and Fig. 16 described.

[0036] The second display area AA2 can correspond to a right-hand area of ​​display area AA and can be adjacent to a second gate driver circuit 320. For example, one end (for example, a right-hand end) of the second display area AA2 can face the second gate driver circuit 320, and the other end (for example, a bottom-hand end) perpendicular to one end of the second display area AA2 can face odd-numbered stages ST1 to ST(2n-1) (where n is a natural number equal to or greater than four) of the third gate driver circuit 330.Therefore, one end of each of the even gate lines GL2 to GL(2n) arranged in the second display area AA2 can be connected to the second gate driver circuit 320 and can receive the gate pulse, and odd gate lines GL1 to GL(2n-1) arranged in the second display area AA2 can be connected to odd stages ST1 to ST(2n-1) of the third gate driver circuit 330 by means of the first connecting line CL1 and can receive the gate pulse.

[0037] The non-display area NA can be an area that does not display an image and can be defined in a boundary region of any substrate surrounding the display area AA. Furthermore, the non-display area NA can have first to fourth non-display areas NA1 to NA4, which face a top, left, right, and bottom end of the display area AA.

[0038] The first non-display area NA1 can be located on the display area AA and can be connected to the display driver 200, and can furthermore have a pad part that is electrically connected to the display driver 200. For example, the pad part of the first non-display area NA1 can be connected to a plurality of circuit films 210 of the display driver 200.

[0039] The second non-display area NA2 can be located at the left end of the display area AA and can accommodate the first gate driver circuit 310. Specifically, the second non-display area NA2 can accommodate the odd-numbered stages ST1 to ST(2n-1) of the first gate driver circuit 310. Here, the odd-numbered stages ST1 to ST(2n-1) can correspond to any number of stages. Furthermore, the second non-display area NA2 can accommodate one end of each of the odd-numbered gate lines GL1 to GL(2n-1) or a first group of gate lines connected to the odd-numbered stages ST1 to ST(2n-1) of the first gate driver circuit 310. Furthermore, the second non-display area NA2 can extend from the display driver 200 and can accommodate a common signal line CGS and an odd clock line CLK_ODD, each connected to the first gate driver circuit 310.

[0040] The third non-display area NA3 can be located at the right end of the display area AA and can accommodate the second gate driver circuit 320. Specifically, the third non-display area NA3 can accommodate the even-numbered stages ST2 to ST(2n) of the second gate driver circuit 320. Here, the even-numbered stages ST2 to ST(2n) can correspond to the even-numbered stages ST2 to ST(2n) of the plurality of stages. Furthermore, the third non-display area NA3 can accommodate one end of each of the even-numbered gate lines GL2 to GL(2n), or a second group of gate lines, connected to the even-numbered stages ST2 to ST(2n) of the second gate driver circuit 320. Additionally, the third non-display area NA3 can extend from the display driver 200 and can accommodate the common signal line CGS and an even clock line CLK_EVEN, each connected to the second gate driver circuit 320.

[0041] The fourth non-display area NA4 can be located at the lower end of the display area AA and can accommodate the third gate driver circuit 330. Specifically, the fourth non-display area NA4 can accommodate the odd-numbered stages ST1 to ST(2n-1) and the even-numbered stages ST2 to ST(2n) of the third gate driver circuit 330. Furthermore, the fourth non-display area NA4 can accommodate one end of the first interconnect line CL1, which is connected to the odd-numbered gate lines GL1 to GL(2n-1), and one end of the second interconnect line CL2, which is connected to the even-numbered gate lines GL2 to GL(2n). Furthermore, the fourth non-display area NA4 can extend from the second or third non-display area NA2 or NA3 and can accommodate the common signal line CGS, the odd clock line CLK_ODD and the even clock line CLK_EVEN, each connected to the third gate driver circuit 320.

[0042] The display panel 100 can further feature the multitude of gate lines, the multitude of data lines DL, and the first and second connecting lines CL1 and CL2.

[0043] The multiple gate lines GL can extend lengthwise in a first direction and can be separated from each other along a second direction that intersects the first. Specifically, the multiple gate lines GL can comprise a first group of gate lines GL1 to GL(2n-1) and a second group of gate lines GL2 to GL(2n). The first group of gate lines can include the odd-numbered gate lines GL1 to GL(2n-1), and the second group of gate lines can include the even-numbered gate lines GL2 to GL(2n). The multiple gate lines GL can receive the gate pulse from the gate driver 300 and can sequentially drive the multiple pixels.

[0044] According to one embodiment, one end of each of the odd gate lines GL1 to GL(2n-1) can be directly connected to the first gate driver circuit 310 and can receive the gate pulse, and the odd gate lines GL1 to GL(2n-1) can be connected to the first connecting line CL1 in the second display area AA2 and can receive the gate pulse from the odd stages ST1 to ST(2n-1) of the third gate driver circuit 330.

[0045] According to one embodiment, one end of each of the straight gate lines GL2 to GL(2n) can be directly connected to the second gate driver circuit 320 and can receive the gate pulse, and the straight gate lines GL2 to GL(2n) can be connected to the second connecting line CL2 in the first display area AA1 and can receive the gate pulse from the straight stages ST2 to ST(2n) of the third gate driver circuit 330.

[0046] The multiple data lines DL can extend lengthwise in the second direction and can be separated from each other along the first direction. Each multiple data line DL can receive a data voltage from the display driver 200 to control the luminance of a light-emitting device contained in a corresponding pixel of the multiple pixels.

[0047] The first connecting line CL1 can be provided as a plurality, and the plurality of first connecting lines CL1 can extend lengthwise in the second direction and can be separated from each other along the first direction. The plurality of first connecting lines CL1 can be directly connected to the odd stages ST1 to ST(2n-1) of the third gate driver circuit 330 and can extend to the second display area AA2. Therefore, the first connecting line CL1 can connect positions of the odd gate lines GL1 to GL(2n-1) of the second display area AA2 to the odd stages ST1 to ST(2n-1) of the third gate driver circuit 330.

[0048] The second connecting line CL2 can be provided as a plurality, and the plurality of second connecting lines CL2 can extend lengthwise in the second direction and can be separated from each other along the first direction. The plurality of second connecting lines CL2 can be directly connected to the even stages ST2 to ST(2n) of the third gate driver circuit 330 and can extend to the first display area AA1. Therefore, the second connecting line CL2 can connect locations of the even gate lines GL2 to GL(2n) of the first display area AA1 to the even stages ST2 to ST(2n) of the third gate driver circuit 330.

[0049] Each of the plurality of pixels can be provided in a corresponding pixel area, defined by a corresponding gate line GL and a corresponding data line DL, each located in the display area AA. According to one embodiment, each of the plurality of pixels can have a pixel circuit comprising a driver transistor and a light-emitting device connected to the pixel circuit.

[0050] The display driver 200 can be connected to the pad portion provided in the non-display area NA of the display panel 100 and can display an image on each pixel, corresponding to video data supplied by a display driver system. According to one embodiment, the display driver 200 can comprise a plurality of circuit films 210, a plurality of integrated data driver circuits (ICs) 220, a printed circuit board (PCB) 230, and a timing controller 240.

[0051] Input terminals provided on one side of each of the plurality of circuit films 210 can be attached to the PCB 230 by a film attachment process, and output terminals provided on the other side of each of the plurality of circuit films 210 can be attached to the pad part by a film attachment process. According to one embodiment, each of the plurality of circuit films 210 can be implemented as a flexible circuit film and can be bent so that the enclosing area of ​​the display device 10 is reduced. For example, each of the plurality of circuit films 210 can be configured as a tape carrier package (TCP) or a chip-on-film (or chip-on-film board) (COF).

[0052] Each of the multiple data driver ICs 220 can be individually mounted on a corresponding circuit film of the multiple circuit films 210. Each of the multiple data driver ICs 220 can receive a data control signal and pixel data, each provided by the timing controller 240, convert the pixel data into a pixel-based analog data signal according to the data control signal, and feed the analog data signal to a corresponding data line.

[0053] The PCB 230 can carry the timing controller 240 and can transmit signals and power between the elements of the display driver 200. The PCB 230 can provide a signal and driver power, each supplied by the timing controller 240, to the data driver ICs 220 and a variety of scan driver ICs to display an image on each pixel. For this purpose, a signal transmission line and various power lines can be provided on the PCB 230. For example, the PCB 230 can be provided as one or more, based on the number of circuit films 210.

[0054] The timing controller 240 can be mounted on the PCB 230 and, via a user interface provided on the PCB 230, can receive video data and a timing synchronization signal, both supplied by the display driver system. The timing controller 240 can align the video data to generate pixel data that conforms to a pixel array structure, based on the timing synchronization signal, and can supply the generated pixel data to a corresponding data driver IC 220. Furthermore, the timing controller 240 can generate the data control signal and a gate control signal based on the timing synchronization signal, control the drive timing of each of the multiple data driver ICs 220 using the data control signal, and control the drive timing of the gate driver 300 using the gate control signal.In this case, the gate control signal can be supplied to the gate driver 300 through the first non-display area NA1 and a first and / or last flexible circuit film of the plurality of circuit films 210.

[0055] The gate driver 300 can be connected to the plurality of gate lines GL provided in the display panel 100. Specifically, the gate driver 300 can generate the gate pulse in a predefined sequence based on the gate control signal supplied by the timing controller 240 and can supply the gate pulse to a corresponding gate line GL. According to one embodiment, the gate driver 300 can include the first to third gate driver circuits 310 to 330.

[0056] The first gate driver circuit 310 can have the odd stages ST1 to ST(2n-1), which correspond to the odd gate lines GL1 to GL(2n-1). Specifically, the first gate driver circuit 310 can be integrated into a left edge (or the second non-display area NA2) of the display panel 100 by a TFT manufacturing process and can be connected to the odd gate lines GL1 to GL(2n-1). According to one embodiment, the first gate driver circuit 310 can have the odd stages ST1 to ST(2n-1) located in the second non-display area NA2 and provide the gate pulse to the odd gate lines GL1 to GL(2n-1).

[0057] The second gate driver circuit 320 can comprise the even stages ST2 to ST(2n), which correspond to the even gate lines GL2 to GL(2n). Specifically, the second gate driver circuit 320 can be integrated into a right edge (or the third non-display area NA3) of the display panel 100 through a TFT manufacturing process and can be connected to the even gate lines GL2 to GL(2n). According to one embodiment, the second gate driver circuit 320 can comprise the even stages ST2 to ST(2n), which are located in the third non-display area NA3, and provide the gate pulse accordingly to the even gate lines GL2 to GL(2n).

[0058] The third gate driver circuit 330 can have the odd stages ST1 to ST(2n-1), which correspond accordingly to the odd gate lines GL1 to GL(2n-1), and the even stages ST2 to ST(2n), which correspond accordingly to the even gate lines GL2 to GL(2n). In detail, the third gate driver circuit 330 can be integrated into a lower edge (or the fourth non-display area NA4) of the display panel 100 by a TFT manufacturing process and can be connected to the plurality of first connection lines CL1 and the plurality of second connection lines CL2.For example, the odd stages ST1 to ST(2n-1) of the third gate driver circuit 330 can be connected to the odd gate lines GL1 to GL(2n-1) by the first connecting line CL1, and the even stages ST2 to ST(2n) of the third gate driver circuit 330 can be connected to the even gate lines GL2 to GL(2n) by the second connecting line CL2.

[0059] Fig. Figure 3 is a diagram showing a first gate driver circuit in the Fig. 2 represents the display device shown.

[0060] Referring to Fig. The first gate driver circuit 310 can have odd stages ST1 to ST(2n-1), which supply a gate pulse to odd gate lines GL1 to GL(2n-1). That is, the first gate driver circuit 310 can have the odd stages ST1 to ST(2n-1) corresponding to the total number of odd gate lines GL1 to GL(2n-1). In detail, the first gate driver circuit 310 can be supplied with a first and a second driver voltage VDD and VSS via a common signal line CGS, which runs through a second non-display area NA2, and can receive an odd clock signal via an odd clock line CLK_ODD. Here, the odd clock signal can correspond to a first, third, fifth, and seventh gate clock CLK1, CLK3, CLK5, and CLK7. Furthermore, each of the first, third, fifth and seventh gate clocks CLK1, CLK3, CLK5, and CLK7 can have a phase which is sequentially shifted.In this case, the odd clock line CLK_ODD can send the first gate clock CLK1 to a 2k-7. te Stage ST(2k-7) (where k is a multiple of 4 equal to or less than n) transmits the third gate clock CLK3 to a 2k-s te Stage ST(2k-5) is transferred, the fifth gate clock CLK5 to a 2k-3 te Stage ST(2k-3) is transferred, and the seventh gate clock CLK7 is sent to a 2k-1 te Stage ST(2k-1) transferred.

[0061] The first and third stages, ST1 and ST3, can be activated by a first and third gate start signal, Vst1 and Vst3, and can receive the first and third gate clock signals, CLK1 and CLK3, to deliver gate pulses Gout1 and Gout3 to the first and third gate lines, GL1 and GL3. Furthermore, the first and third stages, ST1 and ST3, can be reset by output signals (or gate pulses) Gout5 and Gout7 from the fifth and seventh stages, ST5 and ST7.

[0062] In this way, the fifth to 2n-5 can be calculated. te Stages ST5 to ST(2n-5) of the odd-numbered stages ST1 to ST(2n-1) are activated by an output signal from a preceding fourth stage and can accordingly receive the corresponding gate clocks CLK1, CLK3, CLK5, and CLK7 to supply gate pulses Gout5 to Gout(2n-5) to the odd-numbered gate lines GL5 to GL(2n-5). Furthermore, the fifth to 2n-5 te Stages ST5 to ST(2n-5) are reset by an output signal from the next fourth stage.

[0063] Furthermore, the 2n-3 te and 2n-1 te Stages ST(2n-3) and ST(2n-1) are activated by an output signal from a preceding fourth stage and can accordingly receive the corresponding gate clocks CLK5 and CLK7 in order to send gate pulses Gout(2n-3) and Gout(2n-1) to the 2n-3 te and 2n-1 te To supply the gate line GL(2n-3) and GL(2n-1). Furthermore, the 2n-3 teand 2n-1 te Stages ST(2n-3) and ST(2n-1) are reset by a first and third reset step.

[0064] In this way, each of the output signals Goutl to Gout(2n-5) of the first to 2n-5 can be used. ten Stages ST1 to ST(2n-5) are fed as a gate start signal to a next fourth stage, and each of the output signals Gout5 to Gout(2n-1) of the fifth to 2n-1 ten Stage ST5 to ST(2n-1) can be supplied as a reset step of a previous fourth stage.

[0065] Fig. 4 is a diagram showing a second gate driver circuit in the Fig. 2 represents the display device shown.

[0066] Referring to Fig. The second gate driver circuit 320 can have even stages ST2 to ST(2n), which supply a gate pulse to even gate lines GL2 to GL(2n). That is, the second gate driver circuit 320 can have the number of even stages ST2 to ST(2n) corresponding to the total number of even gate lines GL2 to GL(2n). In detail, the second gate driver circuit 320 can be supplied with a first and second driver voltage VDD and VSS via a common signal line CGS, which runs through a third non-display area NA3, and can receive an even clock signal via an even clock line CLK_EVEN. This even clock signal can correspond to a second, fourth, sixth, and eighth gate clock CLK2, CLK4, CLK6, and CLK8, respectively. Furthermore, each of the second, fourth, sixth and eighth gate clocks CLK2, CLK4, CLK6, and CLK8 can have a phase that is sequentially shifted.In this case, the straight clock line CLK_EVEN can send the second gate clock CLK2 to a 2k-6. te Stage ST(2k-6) (where k is a multiple of 4 equal to or less than n) transmits the fourth gate clock CLK4 to a 2k-4 te Stage ST(2k-4) is transferred, the sixth gate clock CLK6 to a 2k-2 te Stage ST(2k-2) is transferred, and the eighth gate clock CLK8 is sent to a 2k te Stage ST(2k) transferred.

[0067] The second and fourth stages, ST2 and ST4, can be activated by a second and fourth gate start signal, Vst2 and Vst4, respectively, and can receive the second and fourth gate clock signals, CLK2 and CLK4, to supply gate pulses Gout2 and Gout4 to the second and fourth gate lines, GL2 and GL4. Furthermore, the second and fourth stages, ST2 and ST4, can be reset by output signals (or gate pulses) Gout6 and Gout8 from the sixth and eighth stages, ST6 and ST8.

[0068] In this way, the sixth to 2n-4 can be calculated. te Stages ST6 to ST(2n-4) of the even stages ST2 to ST(2n) are activated by an output signal from a preceding fourth stage and can accordingly receive the corresponding gate clocks CLK2, CLK4, CLK6, and CLK8 to supply gate pulses Gout6 to Gout(2n-4) to the even gate lines GL6 to GL(2n-4). Furthermore, the sixth stage up to 2n-4 te Stages ST6 to ST(2n-4) are reset by an output signal from the next fourth stage.

[0069] Furthermore, the 2n-2 te and 2n te Stages ST(2n-2) and ST(2n) are activated by an output signal from a preceding fourth stage and can accordingly receive the corresponding gate clocks CLK6 and CLK8 in order to send gate pulses Gout(2n-2) and Gout(2n) to the 2n-2 te and 2n te To supply the gate line GL(2n-2) and GL(2n). Additionally, the 2n-2 te and 2n teStages ST(2n-2) and ST(2n) are reset by a second and a fourth reset step.

[0070] In this way, each of the output signals Gout2 to Gout(2n-4) of the second to 2n-4 can be ten Stages ST2 to ST(2n-4) are fed as a gate start signal to a next fourth stage, and each of the output signals Gout6 to Gout(2n) of the sixth to 2n ten Stage ST6 to ST(2n) can be supplied as a reset step of a previous fourth stage.

[0071] Fig. 5 is a diagram showing a gate driver circuit in the Fig. 2 represents the display device shown.

[0072] Referring to Fig. 5 The third gate driver circuit 330 can have odd stages ST1 to ST(2n-1), which supply a gate pulse to odd gate lines GL1 to GL(2n-1) by means of a first connecting line CL1, and can have even stages ST2 to ST(2n), which supply the gate pulse to even gate lines GL2 to GL(2n) by means of a second connecting line CL2.

[0073] This means that the third gate driver circuit 330 can have the odd stages ST1 to ST(2n-1) corresponding to the total number of odd gate lines GL1 to GL(2n-1) and the even stages ST2 to ST(2n) corresponding to the total number of even gate lines GL2 to GL(2n). In detail, the third gate driver circuit 330 can receive a first and a second driver voltage VDD and VSS via a common signal line CGS passing through a fourth non-display area NA4, can receive a first, third, fifth and seventh gate clock CLK1, CLK3, CLK5, and CLK7 via an odd clock line CLK_ODD, and can receive a second, fourth, sixth and eighth gate clock CLK2, CLK4, CLK6, and CLK8 via an even clock line CLK_EVEN. In this process, each of the first to eighth gate clock cycles, CLK1 to CLK8, can have a phase that is sequentially shifted.In this case, the odd-clock line CLK_ODD can transmit the first, third, fifth and seventh gate clocks CLK1, CLK3, CLK5, and CLK7 to the odd stages ST1 to ST(2n-1), and the even-clock line CLK_EVEN can transmit the second, fourth, sixth and eighth gate clocks CLK2, CLK4, CLK6, and CLK8 to the even stages ST2 to ST(2n).

[0074] The odd stages ST1 to ST(2n-1) of the third gate driver circuit 330 can generate the same output signals Gout1 to Gout(2n-1) with the same timing as the odd stages ST1 to ST(2n-1) of the first gate driver circuit 310.

[0075] According to one embodiment, the odd stages ST1 to ST(2n-1) of the third gate driver circuit 330 can be connected to positions of the odd gate lines GL1 to GL(2n-1) of the second display area AA2 by means of the first connecting line CL1. Therefore, the odd stages ST1 to ST(2n-1) of the third gate driver circuit 330 can provide output signals Gout1 to Gout(2n-1) to the odd gate lines GL1 to GL(2n-1) of the second display area AA2 by means of the first connecting line CL1.

[0076] The even stages ST2 to ST(2n) of the third gate driver circuit 330 can generate the same output signals Gout2 to Gout(2n) with the same timing as the even stages ST2 to ST(2n) of the second gate driver circuit 320.

[0077] According to one embodiment, the even stages ST2 to ST(2n) of the third gate driver circuit 330 can be connected to positions of the even gate lines GL2 to GL(2n) of the first display area AA1 by means of the second connecting line CL2. Therefore, the even stages ST2 to ST(2n) of the third gate driver circuit 330 can provide output signals Gout2 to Gout(2n) to the even gate lines GL2 to GL(2n) of the first display area AA1 by means of the second connecting line CL2.

[0078] Fig. Figure 6 is a waveform diagram showing a gate start signal, a gate shift clock, and a common gate signal in the Fig. The display device shown in section 2 is shown. Fig. 7 is a circuit diagram showing the internal configuration of a Fig. The first stage is shown in section 3.

[0079] Referring to Fig. 6 and Fig. 7 can have a first stage ST1, a first TFT T1, a third TFT T3, a thirty-first TFT T31, a fourth TFT T4, a fifty-first TFT T51, a fifty-second TFT T52, a sixth TFT T6, a seventh TFT T7, and a boot capacitor CB.

[0080] The first TFT T1 can have a gate terminal that receives a first gate start signal Vst1, a second terminal that receives the first gate start signal Vst1, and a third terminal connected to a first node Q. This means that the first TFT T1 can be switched on based on the first gate start signal Vst1 and can supply the first gate start signal Vst1 to the first node Q. The first node Q can be connected to a gate terminal of the sixth TFT T6, and the first stage ST1 can supply an output signal (or gate pulse) Gout1 to a first gate line GL1 based on a voltage at the first node Q. Furthermore, the output signal Gout1 can be supplied as a gate start signal to a subsequent fourth stage.

[0081] According to one embodiment, the first TFTs T1 of the second to fourth stages ST2 to ST4 can be switched on accordingly based on a second to fourth gate start signal Vst2 to Vst4, and the second to fourth stages ST2 to ST4 can accordingly provide the second to fourth gate start signal Vst2 to Vst4 to first nodes Q. Furthermore, a first TFT T1 of an i ten Stage STi (where i is a natural number from five to 2n) can be switched on based on an output signal Gout(i-4) of a preceding fourth stage and can provide the output signal Gout(i-4) of the preceding fourth stage to a first node Q.

[0082] The third TFT T3 can have a gate connection connected to a second node QB, a first connection connected to the first node Q, and a second connection that receives the second driver voltage VSS. This means that the third TFT T3 can be switched on based on a voltage at the second node QB and can discharge the voltage of the first node Q to the second driver voltage VSS. The voltage at the second node QB can be an opposite voltage to the voltage at the first node Q.

[0083] The thirty-first TFT T31 can have a gate terminal that receives an output signal Gout5 of the fifth stage ST5 or an output signal of the next fourth stage, a first terminal connected to the first node Q, and a second terminal that receives the second driver voltage VSS. That is, the thirty-first TFT T31 can be switched on based on the output signal Gout5 of the fifth stage ST5 and can discharge the voltage of the first node Q to the second driver voltage VSS.

[0084] According to one embodiment, a thirty-first TFT T31 of a j ten Stage STj (where j is a natural number from one to 2n-4) can be switched on based on an output signal Gout(j+4) of a subsequent fourth stage and can discharge a voltage of a first node Q onto the second driver voltage VSS. Additionally, a thirty-first TFT T31 can be selected from each of the 2n-3 ten up to 2n tenStage ST(2n-3) to ST2n can be switched on by a first to fourth reset clock and can discharge a voltage of a first node Q to the second driver voltage VSS.

[0085] As described above, multiple stages of the Gate Driver 300 can each include a third TFT T3 and a thirty-first TFT T31, and thus can have multiple routes through which the voltage of the first node Q is discharged. Accordingly, the discharge characteristic of the voltage of the first node Q can be improved, thereby enhancing the reliability of the Gate Driver 300.

[0086] The fourth TFT T4 can have a gate terminal that receives the first driver voltage VDD, a first terminal that receives the first driver voltage VDD, and a second terminal that is connected to the second node QB. This means that the fourth TFT T4 can be switched on based on the first driver voltage VDD and can supply the first driver voltage VDD to the second node QB.

[0087] The fifty-first TFT T51 can have one gate terminal that receives the first gate start signal Vst1, one terminal connected to the second node QB, and one terminal connected to the second driver voltage VSS. That is, the fifty-first TFT T51 can be switched on based on the first gate start signal Vst1 and can discharge the voltage of the second node QB to the second driver voltage VSS.

[0088] According to one embodiment, fifty-first TFTs T51 of the second to fourth stages ST2 to ST4 can be switched on accordingly based on a second to fourth gate start signal Vst2 to Vst4 and can each discharge a voltage of a second node QB onto the second driver voltage VSS. Furthermore, a fifty-first TFT T51 of an i ten Stage STi (where i is a natural number from five to 2n) is switched on based on an output signal Gout(i-4) of a preceding fourth stage and can discharge a voltage of a second node QB onto the second driver voltage VSS.

[0089] The fifty-second TFT T52 can have a gate terminal connected to the first node Q, a first terminal connected to the second node QB, and a second terminal connected to the second driver voltage VSS. That is, the fifty-second TFT T52 can be turned on based on the voltage of the first node Q and can discharge the voltage of the second node QB to the second driver voltage VSS.

[0090] As described above, the multiple stages ST1 to ST2n of the gate driver 300 can each have a fifty-first TFT T51 and a fifty-second TFT T52, and can thus have a multitude of routes through which the voltage of the second node QB is discharged. Accordingly, the discharge characteristic of the voltage of the second node QB can be improved, thereby enhancing the reliability of the gate driver 300.

[0091] The sixth TFT T6 can have a gate terminal connected to the first node Q, a first terminal that receives a first gate clock CLK1, and a second terminal connected to an output node. This means that the sixth TFT T6 can be switched on based on the voltage of the first node Q and can provide an output signal (or gate pulse) Gout1 to the first gate line GL1. Furthermore, the output signal Gout1 can be used as a gate start signal for a subsequent fourth stage.

[0092] The seventh TFT T7 can have a gate terminal connected to the second node QB, a first terminal connected to an output node, and a second terminal connected to the second driver voltage VSS. This means the seventh TFT T7 can be turned on based on the voltage of the second node QB and can discharge a voltage from the output node to the second driver voltage VSS.

[0093] Furthermore, one end of the boot capacitor CB can be connected to the first node Q, and the other end of the boot capacitor CB can be connected to the output node. Accordingly, the boot capacitor CB can store a differential voltage between the first node Q and the output node.

[0094] The following describes the operation of a first ST1 according to an embodiment of the present disclosure with reference to Fig. 6 and Fig. 7.

[0095] First, when the first gate start signal Vst1 reaches a high level, the first TFT T1 and the fifty-first TFT T51 of a first stage ST1 can be switched on. Therefore, a voltage VQ1 of a first node Q, which is one end of a boot capacitor, can be precharged with a first driver voltage VDD supplied by the first TFT T1, and a voltage of a second node QB can be discharged to a second driver voltage VSS by the fifty-first TFT T51. In this process, the rise time of a first gate clock CLK1 can be delayed by four horizontal periods compared to the rise time of the first gate start signal Vst1, and the first gate start signal Vst1 can remain at a high level until the rise time of the first gate clock CLK1.Therefore, a sixth TFT T6 can be switched on based on the first gate start signal Vst1, which has a high level and is charged into the first node Q, and can provide the first gate clock CLK1 with a low level to a first gate line GL1 via an output node. At this time, the voltage of the second node QB can be discharged to the driver voltage VSS by each of the fifty-first TFT T51 and a fifty-second TFT T52, and a seventh TFT T7 can remain in a switched-off state.

[0096] Subsequently, when the first gate start signal Vst1 has a low level and the first gate clock CLK1 has a high level, the first gate clock CLK1 can be applied to the output node, which is the other end of the boot capacitor CB, via the sixth TFT T6, which is still in a switched-on state. Therefore, the first node Q, which is one end of the boot capacitor CB, can be bootstrapped so that it has a high-level voltage. Consequently, the sixth TFT T6 can be switched to a fully switched-on state and can provide the first gate clock CLK1 as a first gate pulse Gout1 to the first gate line GL1 without any voltage drop.At this time, the voltage of the second node QB can be discharged to the second driver voltage VSS by each of the fifty-first TFT T51 and the fifty-second TFT T52, and the seventh TFT T7 can maintain a switched-off state.

[0097] Finally, if a high-level output signal Gout5 is applied from a fifth stage ST5 or the next fourth stage to a gate terminal of a thirty-first TFT T31, the thirty-first TFT T31 can be switched on and can discharge the voltage VQ1 of the first node Q to the second driver voltage VSS. Therefore, the sixth TFT T6 can be switched off and cannot provide the first gate clock CLK1 to the output node, and the fifty-second TFT T52 can be switched off and cannot discharge the voltage of the second node QB to the second driver voltage VSS. Accordingly, the voltage of the second node QB can be high, based on the first driver voltage VDD supplied by the fourth TFT T4, and the seventh TFT T7 can be switched on and can discharge an output node voltage to the second driver voltage VSS.As a result, when the output node voltage is discharged to the second driver voltage VSS, the first stage ST1 can supply a gate-off voltage to the first gate line GL1.

[0098] Furthermore, apart from the descriptions given above (for example, second to fourth gate start signal Vst2 to Vst4 and first to fourth clock cycles), a configuration and operation of each of the second to 2n ten Stages ST2 to ST2n are the same as the first stage ST1 described above, and therefore their description is omitted.

[0099] Fig. Figure 8 is a diagram describing the effect of reducing the size of a border area in the display device, which is in Fig. 2 is shown. Fig. Figure 9 is a diagram describing the effect of reducing the delay of a gate pulse in the display device, which is in Fig. 2 is shown.

[0100] Referring to Fig. 8 and Fig. 9 In a display device of the related technology, which has a large display panel, a gate pulse is supplied to a plurality of gate lines by using a double supply method or an interlaced scanning method.

[0101] In Fig. In a display device of related technology, driven by the dual-feed method, a plurality of stages are arranged in each of a left non-display region and a right non-display region of a substrate. In this case, a problem of the display device of related technology is that the left non-display region and the right non-display region increase due to a width w1 of a clock line CLK, which has a first to eighth gate clock CLK1 to CLK8, and a width w2 of each of the plurality of stages. The display device of related technology has a problem in that a non-display region increases when a gate driver is driven at high speed (or high frequency).

[0102] To solve such a problem, in a display device 10 according to the present disclosure, odd stages ST1 to ST(2n-1) of a first gate driver circuit 310 can be arranged in a left edge (or a second non-display area NA2) of a display panel 100, even stages ST2 to ST(2n) of a second gate driver circuit 320 can be arranged in a right edge (or a third non-display area NA3) of the display panel 100, and odd stages ST1 to ST(2n-1) and even stages ST2 to ST(2n) of a third gate driver circuit 330 can be arranged in a lower edge (or a fourth non-display area NA4) of the display panel 100.Accordingly, in the first gate driver circuit 310, a width w3 of a clock line CLK, which has a first, third, fifth and seventh gate clock CLK1, CLK3, CLK5, and CLK7, and a width w4 of each of the odd stages ST1 to ST(2n-1) can be smaller compared with the display device of the related technique.

[0103] For example, in the display device of the related technique, which is driven by the dual-feed method, a second width w2 increases so that a first to fourth stage ST1 to ST4 is provided within a certain distance h1. On the other hand, in the first gate driver circuit 310 according to the present disclosure, the width w4 of each of the odd stages ST1 and ST3 can be reduced by decreasing the number of stages provided within the certain distance h1. Accordingly, since in the first gate driver circuit 310 according to the present disclosure only the odd stages ST1 and ST3 are provided within the certain distance h1, a non-display area can be reduced in size even when a large display panel is driven.

[0104] In Fig. In a related display device driven by interlaced scanning, an odd-numbered stage ST(2n-1) of the plurality of stages is located in the left non-display region of the substrate, and an even-numbered stage ST(2n) of the plurality of stages is located in the right non-display region of the substrate. In this case, the related display device, which has a large display panel, experiences the problem that a gate clock signal Gout is delayed with increasing distance of a gate line GL(2n) from a stage. Therefore, an output difference occurs in the related display device between one end of the gate line GL(2n), which receives a gate clock signal directly from a stage, and the other end of the gate line GL(2n), which is further away from the stage.Furthermore, in the display device of the related technology, a delay occurs in the gate clock Gout, which causes the problem that an image defect occurs during high-speed (or high-frequency) control.

[0105] To solve such a problem, in the display device 10 according to the present disclosure, odd stages ST1 to ST(2n-1) of the first gate driver circuit 310 can be arranged at one end of a first display area AA1, and odd stages ST1 to ST(2n-1) of the third gate driver circuit 330 can be arranged at the other end of a second display area AA2. Furthermore, in the display device 10 according to the present disclosure, even stages ST2 to ST(2n) of the second gate driver circuit 320 can be arranged at one end of the second display area AA2, and even stages ST2 to ST(2n) of the third gate driver circuit 330 can be arranged at the other end of the first display area AA1.

[0106] Therefore, the odd-numbered stages ST1 to ST(2n-1) of the first gate driver circuit 310 can supply a gate pulse directly to one end of odd-numbered gate lines GL1 to GL(2n-1), and the odd-numbered stages ST1 to ST(2n-1) of the third gate driver circuit 330 can supply the gate pulse via a first connecting line CL1 to positions on the odd-numbered gate lines GL1 to GL(2n-1) of the second display area AA2. Similarly, the even-numbered stages ST2 to ST(2n) of the second gate driver circuit 320 can supply the gate pulse directly to one end of even-numbered gate lines GL2 to GL(2n), and the even-numbered stages ST2 to ST(2n) of the third gate driver circuit 330 can supply the gate pulse via a second connecting line CL2 to positions on the even-numbered gate lines GL2 to GL(2n) of the first display area AA1.

[0107] Therefore, the display device 10 according to the present disclosure can prevent a delay in the gate clock Gout, thereby preventing an output difference between the two ends of the gate line GL(2n). Accordingly, the display device 10 according to the present disclosure can prevent a delay during high-speed (or high-frequency) driving and can thus easily perform high-speed driving of a large display panel, thereby improving image quality.

[0108] As a result, since the display device 10 according to the present disclosure comprises the first to third gate driver circuits 310 to 330, the left and right border regions can be reduced, and the delay of the gate pulse can be eliminated, thus easily achieving high-speed drive operation. In other words, since in the display device 10 according to the present disclosure the first to third gate driver circuits 310 to 330 are individually and appropriately arranged in the second to fourth non-display regions NA2 to NA4, excluding the first non-display region NA1 with the pad section provided therein, the area of ​​each of the second and third non-display regions NA2 and NA3 can be reduced, and it can be prevented that an output difference between gate pulses occurs in the display region AA.

[0109] Fig. Figure 10 is a diagram that represents a connection relationship between a plurality of stages and a plurality of gate lines in a display device according to a second embodiment. Fig. Figure 11 is a diagram showing a first gate driver circuit in the display device, which is in Fig. 10 is shown, represents. Fig. 12 is a diagram showing a second gate driver circuit in the display device, which is in Fig. 10 is shown, represents. Fig. 13 is a diagram showing a third gate driver circuit in the display device, which is in Fig. 10 is shown. Here, a display device according to a second embodiment, which is shown in Fig. As shown in Figures 10 to 13, this can be implemented by modifying only the configurations of a first and a second odd-clock line CLK_ODD1 and CLK_ODD2 and a first and a second even-clock line CLK_EVEN1 and CLK_EVEN2, and thus the same configuration as the one described above is either briefly described or omitted.

[0110] Referring to Fig. From 10 to 13, the first odd clock line CLK_ODDI1 can extend from a display driver 200 to a second non-display area NA2 and can be connected to odd stages ST1 to ST(2n-1) of a first gate driver circuit 310.

[0111] The second odd clock line CLK_ODD2 can pass through a third non-display area NA3 and can extend from the display driver 200 to a fourth non-display area NA4 and can be connected to odd stages ST1 to ST(2n-1) of a third gate driver circuit 330.

[0112] The first straight clock line CLK_EVEN1 can extend from the display driver 200 to the third non-display area NA3 and can be connected to even stages ST2 to ST(2n) of a second gate driver circuit 320.

[0113] The second straight clock line CLK_EVEN2 can pass through the second non-display area NA2 and can extend from the display driver 200 to the fourth non-display area NA4 and can be connected to even stages ST2 to ST(2n) of a third gate driver circuit 330.

[0114] As described above, since the display device 10 is implemented according to the second embodiment by modifying a configuration of each clock line of the display device according to the first embodiment, a load on each clock line can be reduced, and the first to eighth gate clock CLK1 to CLK8 can be easily transferred to each stage of the gate driver 300.

[0115] Fig. Figure 14 is a diagram describing the effect of reducing the size of a non-display area in the display device, which is in Fig. 10 is shown.

[0116] Referring to Fig. In the display device of the related technique, which is driven by the dual-feed method, a plurality of stages are arranged in each of a left and a right non-display region of a substrate. In this case, the display device of the related technique has the problem that the left and right non-display regions increase due to a clock line CLK with a width w1, which includes a first to eighth gate clock CLK1 to CLK8, and a width w2 of each of the plurality of stages. The display device of the related technique has the problem that a non-display region increases when a gate driver is driven at high speed (or high frequency).

[0117] To solve such a problem, in a display device 10 according to the present disclosure, odd stages ST1 to ST(2n-1) of a first gate driver circuit 310 can be arranged in a left edge (or a second non-display area NA2) of a display panel 100, even stages ST2 to ST(2n) of a second gate driver circuit 320 can be arranged in a right edge (or a third non-display area NA3) of the display panel 100, and odd stages ST1 to ST(2n-1) and even stages ST2 to ST(2n) of a third gate driver circuit 330 can be arranged in a lower edge (or a fourth non-display area NA4) of the display panel 100. Accordingly, in the first gate driver circuit 310, the width w4 of each of the odd stages ST1 to ST(2n-1) can be reduced compared to the display device of the related technology.

[0118] As a result, since the display device 10 according to the present disclosure has a first to third gate driver circuit 310 to 330, the left and right non-display areas can be reduced in size, and the delay of the gate pulse can be eliminated, thus easily achieving high-speed drive operation. In other words, since in the display device 10 according to the present disclosure the first to third gate driver circuit 310 to 330 are individually and appropriately arranged in the second to fourth non-display areas NA2 to NA4, excluding the first non-display area NA1 with the pad section provided therein, the area of ​​each of the second and third non-display areas NA2 and NA3 can be reduced, and it can be prevented that an output difference between gate pulses occurs in the display area.

[0119] Furthermore, if the display panel 100 is a liquid crystal display panel, the lower substrate, which has transistors, may be exposed on the outside of the display device 10, and thus the width of a bezel of a front cover, which covers or supports the first to fourth non-display area, may be reduced.

[0120] For example, a pad component, generally located in the first non-display area, can be placed on the lower substrate. An upper substrate can be connected to the lower substrate with a liquid crystal in between, and the upper substrate can be exposed on the outside of the display device. That is, a user operating the display device can see an image projected through the upper substrate. In this case, since the pad component should be exposed, the size of the upper substrate can be implemented such that it is smaller than that of the lower substrate. Therefore, the pad component can also be exposed in a direction visible to the user, and thus the pad component can be covered by the front cover so that it is not visible to the user.Accordingly, according to the present disclosure, even if an area of ​​each of the second to fourth non-indication area is reduced, an area of ​​the first non-indication area cannot be reduced, and in particular, a width of the border of the front cover covering the first non-indication area cannot be reduced.

[0121] However, if the lower substrate is arranged in an outer direction (i.e., a direction seen by the user) of the display device 10 and the upper substrate is provided in an inner direction (i.e., a direction towards a backlight unit) of the display device 10, the width of the bezel of the front cover which covers or supports the first non-display area may be reduced.

[0122] This means that, according to the arrangement structure described above in the present disclosure, even if the size of the first non-display area is not substantially reduced, the pad portion in the outer direction of the display device 10 may not be exposed, and thus the width of the front cover's edging for covering the first non-display area with the pad portion provided therein may be reduced. In this case, according to the present disclosure, since the area of ​​each of the second and third non-display areas is reduced, the widths of the front cover edgings that cover or support the second and third non-display areas may be reduced. Accordingly, according to the present disclosure, the widths of the front cover edgings that cover or support the first through fourth non-display areas may be reduced. This will be explained in detail below with reference to Fig. described in sections 20 to 22.

[0123] In the following description, "connection line CL" can be a generic name for the first connection line CL1 and the second connection line CL2. The following describes a connection structure of a gate line and a connection line. Descriptions that are the same as or similar to those given above are omitted or abbreviated.

[0124] Fig. 15 is an example diagram showing a cross-sectional area of ​​the display panel that is in Fig. 2 and Fig. Figure 10 is shown schematically. In particular, (a) represents Fig. Figure 15 schematically represents a cross-sectional area, taken along the first pixel P1, which is in Fig. 2 and Fig. 10 is shown, parallel to the gate line GL, (b) of Fig. Figure 15 schematically represents a cross-sectional area, taken along the second pixel P2, which is in Fig. 2 and Fig. 10 is shown parallel to the gate line GL, and (c) of Fig. Figure 15 schematically represents a cross-sectional area, taken along the third pixel P3, which is in Fig. 2 and Fig. Figure 10 shows the gate line GL parallel to it. For the sake of simplicity, elements not directly depicted in the cross-sectional areas shown in (a), (b), and (c) are included in the cross-sectional areas. To provide further clarification: The cross-sectional areas shown in (a), (b), and (c) illustrate an arrangement of the gate line GL and the second connecting line CL2, while the other elements are shown schematically for clarity.

[0125] Firstly, referring to (a) of Fig. 15, since the first pixel P1 only has the gate line GL, as in Fig. 2 and Fig. As shown in Figure 10, the second connecting line CL2 is not included in the cross-sectional area of ​​the first pixel P1.

[0126] In this case, as in (a) of Fig. As shown in Figure 15, the first pixel P1 of the display panel 100 can have: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate line GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, a planarization layer 108 provided on the passivation layer 107, and a pixel electrode 110,which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108.

[0127] If the display panel 100 is a liquid crystal display panel, as in Fig. As shown in Figure 15, a common electrode 111 can further be provided on the planarization layer 108 and can be covered by an insulating layer 109. In this case, the pixel electrode 110 can be provided on the insulating layer 109 and can be electrically connected to the second electrode 106 by a contact hole formed in the insulating layer 109 and the planarization layer 108. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate conductor GL can each perform the function of a transistor (a TFT) (in particular, a switching transistor) for controlling the light transmittance of the liquid crystal contained in the liquid crystal panel. Such a description can be applied to a display panel 100 shown in Figures (b) and (c) of Figures (b). Fig. 15 is shown.

[0128] If the display panel 100 is an organic light-emitting display panel, the common electrode 111 and the insulating layer 109 can be omitted. In this case, the pixel electrode 110 can be an anode of an organic light-emitting diode (OLED), a light-emitting layer contained in the OLED can be provided on the pixel electrode 110, and a cathode contained in the OLED can be provided on the light-emitting layer. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate lead GL can each perform a transistor (TFT) function (in particular, a driver transistor) for controlling the amount of light emitted by the OLED contained in the organic light-emitting display panel. Such a description can be applied to the display panel 100 shown in (b) and (c) of Fig. As shown in section 15, it can be applied.

[0129] Referring to (b) of Fig. In the second pixel P2, the gate line GL can cross the second connecting line CL2, as shown in Fig. 2 and Fig. 10 is shown.

[0130] In this case, as in (b) of Fig. Figure 15 shows the second pixel P2 of the display panel 100 comprising: a substrate 101, the second interconnect CL2 provided on the substrate 101, a high-temperature-resistant planarization layer 102 covering the second interconnect CL2, a gate GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, and a planarization layer. 108, which is provided on the passivation layer 107,and a pixel electrode 110, which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108.

[0131] That is, in the present disclosure, as shown in (b), the first connecting line CL1 and the second connecting line CL2 can be provided on the substrate 101 and can be covered by the high heat-resistant planarization layer 102.

[0132] Finally, with reference to (c) of Fig. 15, in which the third pixel P3 is connected to the gate line GL with the second connecting line CL2, as in Fig. 2 and Fig. 10 is shown.

[0133] In this case, as in (c) of Fig. Figure 15 shows the third pixel P3 of the display panel 100 comprising: a substrate 101, the second interconnect CL2 provided on the substrate 101, a high-temperature-resistant planarization layer 102 covering the second interconnect CL2, a gate GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, and a planarization layer. 108, which is provided on the passivation layer 107,and a pixel electrode 110, which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108.

[0134] That is to say, in the present revelation, as in (b) of Fig. Figure 15 shows that the first connecting line CL1 and the second connecting line CL2 are provided on the substrate 101 and can be covered by the high heat-resistant planarization layer 102.

[0135] In particular, as in (c) of Fig. As shown in Figure 15, the second connecting line CL2 can be connected to the gate line GL through a contact hole formed in the high-temperature resistant planarization layer 102, and furthermore, the first connecting line CL1 can be connected to the gate line GL through a contact hole formed in the high-temperature resistant planarization layer 102.

[0136] To provide an additional description: As in Fig. 1, Fig. 2, and Fig. As shown in Figure 10, the connecting lines CL can extend in one direction (i.e., the second direction) from the fourth non-display area NA4 of the display panel 100 to the first non-display area NA1, and the gate lines GL can extend in one direction (in particular, the first direction perpendicular to the second direction) which differs from the connecting lines CL.

[0137] In this case, as in Fig. As shown in Figure 15, the connecting lines CL are provided on the substrate 101, insulated from the gate line GL by the high-temperature resistant planarization layer 102, and electrically connected to the gate line GL by a contact hole formed in the high-temperature resistant planarization layer 102.

[0138] The reason why, as described above, the connecting lines CL are contained in the substrate 101 and the substrate 101 is covered by the high-temperature-resistant planarization layer 102 is to reduce the load on the connecting line CL and to reduce the parasitic capacitance that occurs between the connecting line CL and at least one of the various metals (for example, the first electrode 105, the second electrode 106, the common electrode 111, and the data line) contained in the display panel 100.

[0139] In particular, increasing the thickness of the high-temperature-resistant planarization layer 102 can increase the distance between the metals applied to the high-temperature-resistant planarization layer 102 and the connecting conductor CL, thereby reducing the magnitude of any parasitic capacitance occurring between the connecting conductor CL and the metals. That is, the high-temperature-resistant planarization layer 102 can perform the function of planarizing the upper end of the connecting conductor CL and reducing the parasitic capacitance occurring between the connecting conductor CL and other metals.

[0140] In this case, since the gate line GL, the semiconductor 104, the first electrode 105, and the second electrode 106, all of which require a high-temperature process, are provided on the high-temperature-resistant planarization layer 102, the high-temperature-resistant planarization layer 102 should therefore use a high-temperature-resistant material.

[0141] Therefore, the permittivity of the high-temperature planarization layer 102 should be greater than 2 and less than 4, the uniformity (max-min) of the high-temperature planarization layer 102 should be greater than 0 and less than 0.2 µm, the weight loss of the high-temperature planarization layer 102 in a high-temperature process carried out on oxide at a temperature above 400°C should be greater than 0.1% and less than 1%, the high-temperature planarization layer 102 should be chemically stable so that no weight loss or deformation of a material property occurs due to metal etching, and the contact characteristics with another layer should be good. That is, the weight loss, the permittivity, and the uniformity should be as small as possible.

[0142] Furthermore, if a display panel that incorporates the high-temperature-resistant planarization layer 102 is a liquid crystal display panel, the high-temperature-resistant planarization layer 102 should have a transmittance of 70% to 100%.

[0143] This means that the high-temperature resistant planarization layer 102 can have a material that has a physical property similar to that of silicon dioxide (SiO2).

[0144] Fig. Figure 16 is another exemplary diagram that schematically shows the cross-sectional area of ​​the display panel that is in Fig. 2 and Fig. 10 is shown, represents. In particular, (a) of Fig. Figure 16 schematically represents a cross-sectional area, taken along the first pixel P1, which is in Fig. 2 and Fig. 10 is shown, parallel to the gate line GL, (b) of Fig. Figure 16 schematically represents a cross-sectional area, taken along the second pixel P2, which is in Fig. 2 and Fig. 10 is shown parallel to the gate line GL, and (c) of Fig. Figure 16 schematically represents a cross-sectional area, taken along the third pixel P3, which is in Fig. 2 and Fig. Figure 10 shows the gate line GL parallel to it. For the sake of simplicity, elements not directly depicted in the cross-sectional areas shown in (a), (b), and (c) are included in the cross-sectional areas. To provide further clarification: The cross-sectional areas shown in (a), (b), and (c) illustrate an arrangement of the gate line GL and the second connecting line CL2, while the other elements are shown schematically for clarity.

[0145] Firstly, referring to (a) of Fig. 16, since the first pixel P1 only has the gate line GL, as in Fig. 2 and Fig. As shown in Figure 10, the second connecting line CL2 is not included in the cross-sectional area of ​​the first pixel P1.

[0146] In this case, as in (a) of Fig. Figure 16 shows the first pixel P1 of the display panel 100 comprising: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate line GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, a planarization layer 108 provided on the passivation layer 107, and a pixel electrode 110,which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108.

[0147] If the display panel 100 is a liquid crystal display panel, then, as in Fig. As shown in Figure 16, a common electrode 111 may be provided on the planarization layer 108 and may be covered by an insulating layer 109. In this case, the pixel electrode 110 may be provided on the insulating layer 109 and may be electrically connected to the second electrode 106 by a contact hole formed in the insulating layer 109 and the planarization layer 108. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate conductor GL may each perform the function of a transistor (a TFT) (in particular, a switching transistor) for controlling the light transmittance of the liquid crystal contained in the liquid crystal display panel. Such a description can be applied to a display panel 100 shown in Figures (b) and (c) of Figures (b) and (c). Fig. As shown in section 16, they can be applied.

[0148] If the display panel 100 is an organic light-emitting display panel, the common electrode 111 and the insulating layer 109 can be omitted. In this case, the pixel electrode 110 can be an anode of an OLED, a light-emitting layer contained in the OLED can be provided on the pixel electrode 110, and a cathode contained in the OLED can be provided on the light-emitting layer. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate lead GL can each perform a transistor (TFT) function (in particular, a driver transistor) for controlling the amount of light emitted by the OLED contained in the organic light-emitting display panel. Such a description can be applied to the display panel 100 shown in (b) and (c) of Fig. As shown in section 16, they can be applied.

[0149] Referring to (b) of Fig. In the second pixel P2, the gate line GL can cross the second connecting line CL2, as shown in Fig. 2 and Fig. 10 shown.

[0150] In this case, as in (b) of Fig. Figure 16 shows the second pixel P2 of the display panel 100 comprising: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, a second interconnection line CL2 provided on the gate insulation layer 103, a passivation layer 107 covering the second interconnection line CL2 and the gate insulation layer 103, a planarization layer 108 provided on the passivation layer 107, and a pixel electrode 110 provided on the planarization layer 108.

[0151] That is, in the present disclosure, as shown in (b), the first connecting line CL1 and the second connecting line CL2 can be provided on the gate insulation layer 103.

[0152] In this case, the connecting line CL can be formed by the same process as the first and second electrodes 105 and 106, which are provided on the gate insulation layer 103 and together form the transistor (the TFT).

[0153] That is, a first electrode 105 and an electrode 106, both forming a transistor contained in the pixel, can be provided on the gate insulation layer 103, and the connecting lines CL can be formed on the same layer as the first electrode 105 and the second electrode 106 at an upper end of the gate insulation layer 103.

[0154] Furthermore, since the first electrode 105 and the second electrode 106 are provided on the semiconductor 104, the connecting line CL can be provided on another semiconductor 104a, which is formed by the same process as the semiconductor 104.

[0155] This means that the connecting line CL can be formed by the same process as the first and second electrodes 105 and 106, which together form the TFT. In this case, the connecting line CL can be provided directly on the gate insulation layer 103, or it can be provided on the other semiconductor 104a, which is formed by the same process as the semiconductor 104 that together form the transistor (the TFT), in order to have the same structure as each of the first electrode 105 and the second electrode 106.

[0156] Finally, with reference to (c) of Fig. 16, in which the third pixel P3 is connected to the gate line GL with the second connecting line CL2, as in Fig. 2 and Fig. 10 shown.

[0157] In this case, as in (c) of Fig. Figure 16 shows the third pixel P3 of the display panel 100 comprising: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, the other semiconductor 104a provided on the gate insulation layer 103 and electrically connected to the gate line GL by a contact hole formed in the gate insulation layer 103, the second interconnect CL2 provided on the other semiconductor 104a, a passivation layer 107 covering the second interconnect CL2 and the other semiconductor 104a, a planarization layer 108 provided on the passivation layer 107, and a pixel electrode 110 provided on the planarization layer 108.

[0158] As described above, the second connecting line CL2 can be provided directly on the gate insulation layer 103, and in this case the second connecting line CL2 can be electrically connected to the gate line GL through a contact hole formed in the gate insulation layer 103.

[0159] If the connecting lines CL are contained in the substrate 101 as described above, the connecting lines CL can even be formed without an additional process.

[0160] In the above description, the high-temperature-resistant planarization layer 102 can be provided on the substrate 101, or in an embodiment described above with reference to Fig. As described in section 16, the high-temperature resistant planarization layer 102 can be omitted.

[0161] However, in one embodiment, the above with reference to Fig. As described in Figure 16, if a different metal is provided on the substrate 101 instead of the connecting conductor CL, the high-temperature-resistant planarization layer 102 performs the function of reducing a parasitic capacitance between various metals provided on the high-temperature-resistant planarization layer 102 and the other metal.

[0162] In this case, the high-temperature-resistant planarization layer 102 can exhibit a physical property which, as above with reference to Fig. 15 is described.

[0163] The following describes the structure of a display panel for reducing parasitic capacity with reference to Fig. 17 to 19. In the following description, descriptions that are the same as or similar to descriptions given above are omitted or given briefly.

[0164] Fig. Figure 17 is another exemplary diagram that schematically shows the cross-sectional area of ​​the display panel that is in Fig. 2 and Fig. 10 is shown, represents. In particular, (a) of Fig. Figure 17 schematically represents a cross-sectional area, taken along the first pixel P1, which is in Fig. 2 and Fig. 10 is shown, parallel to the gate line GL, (b) of Fig. Figure 17 schematically represents a cross-sectional area, taken along the second pixel P2, which is in Fig. 2 and Fig. 10 is shown parallel to the gate line GL, and (c) of Fig. Figure 17 schematically represents a cross-sectional area, taken along the third pixel P3, which is in Fig. 2 and Fig. Figure 10 shows the gate line GL parallel to it. For the sake of simplicity, elements not directly depicted in the cross-sectional areas shown in (a), (b), and (c) are included in the cross-sectional areas. To provide further clarification: The cross-sectional areas shown in (a), (b), and (c) illustrate an arrangement of the gate line GL and the second connecting line CL2, while the other elements are shown schematically for simplicity.

[0165] Firstly, referring to (a) of Fig. 17, since the first pixel P1 only has the gate line GL, as in Fig. 2 and Fig. As shown in Figure 10, the second connecting line CL2 is not included in the cross-sectional area of ​​the first pixel P1.

[0166] In this case, as in (a) of Fig. Figure 17 shows the first pixel P1 of the display panel 100 comprising: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate line GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, a color filter CF provided on the passivation layer 107, and a planarization layer. 108, which is provided on the CF color filter, and a pixel electrode 110,which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108 and the color filter CF.

[0167] If the display panel 100 is a liquid crystal display panel, then, as described in Fig. As shown in Figure 17, a common electrode 111 is provided on the planarization layer 108 and may be covered by an insulating layer 109. In this case, the pixel electrode 110 can be provided on the insulating layer 109 and can be electrically connected to the second electrode 106 by a contact hole formed in the insulating layer 109, the planarization layer 108, the color filter CF, and the passivation layer 107. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate lead GL can each perform the function of a transistor (a TFT) (in particular, a switching transistor) for controlling the light transmittance of the liquid crystal contained in the liquid crystal display panel.

[0168] In particular, the color filter CF can be provided on the passivation layer 107 in the display panel 100. The color filter CF can perform the function of defining the color of light emitted by the pixel.

[0169] This means that if the display panel 100 is the liquid crystal panel, light emitted by a backlight unit provided beneath the substrate 101 can pass through the color filter CF, the insulating layer 109, the liquid crystal provided on the insulating layer 109, and an upper substrate provided on the liquid crystal. Accordingly, a user can see colored light emitted through the upper substrate.

[0170] Such a description can be applied to the display panel 100, which is shown in (b) and (c) of Fig. As shown in 17, they can be applied.

[0171] If the display panel 100 is an organic light-emitting diode (OLED) display panel, the common electrode 111 and the insulating layer 109 can be omitted. In this case, the pixel electrode 110 can be an anode of an OLED, a light-emitting layer contained in the OLED can be provided on the pixel electrode 110, and a cathode contained in the OLED can be provided on the light-emitting layer. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate lead GL can each perform the function of a transistor (a TFT) (in particular, a driver transistor) for controlling the amount of light emitted by the OLED contained in the organic light-emitting diode display panel.

[0172] That is, if the display panel 100 is the organic light-emitting display panel, the pixel electrode 110 can be connected to the second electrode 106 by a contact hole formed in the passivation layer 107, the color filter CF and the planarization layer 108, and the color filter CF can be provided under the pixel electrode 110. Fig. Figure 17 shows a cross-sectional area of ​​the organic light-emitting display panel, and the color filter CF is not shown below the pixel electrode 110. However, in a top view, the color filter CF may be provided below the pixel electrode 110 on a partial area of ​​the pixel electrode 110, excluding the partial area in which the contact hole is formed.

[0173] In this case, the pixel electrode 110 can perform the function of an anode electrode of the organic light-emitting display panel, and thus, as described above, a light-emitting layer can be provided on the pixel electrode 110 and a cathode can be provided on the light-emitting layer.

[0174] Light emitted by the light-emitting layer can pass through the color filter CF, the gate insulation layer 103, the high-temperature-resistant planarization layer 102, and the substrate 101 to the outside. Accordingly, a user can see colored light emitted through the substrate 101.

[0175] Such a description can be applied to the display panel 100, which is shown in (b) and (c) of Fig. 17 is applied. Referring to (b) of Fig. In the second pixel P2, the gate line GL can cross the second connecting line CL2, as shown in Fig. 2 and Fig. 10 shown.

[0176] In this case, as in (b) of Fig. Figure 17 shows the second pixel P2 of the display panel 100 comprising: a substrate 101, the second interconnect CL2 provided on the substrate 101, a high-temperature-resistant planarization layer 102 covering the second interconnect CL2, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate line GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, and a color filter CF provided on the passivation layer 107 is provided, a planarization layer 108,which is provided on the color filter CF, and a pixel electrode 110, which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108, the color filter CF and the passivation layer 107.

[0177] That is to say, in the present revelation, as in (b) of Fig. As shown in Figure 17, the first connecting line CL1 and the second connecting line CL2 are provided on the substrate 101 and can be covered by the high-temperature-resistant planarization layer 102. Finally, with reference to (c) of Fig. 17, in which the third pixel P3 is connected to the gate line GL with the second connecting line CL2, as in Fig. 2 and Fig. 10 shown.

[0178] In this case, as in (c) of Fig. Figure 17 shows the third pixel P3 of the display panel 100 comprising: a substrate 101, the second interconnect CL2 provided on the substrate 101, a high-temperature-resistant planarization layer 102 covering the second interconnect CL2, a gate conductor GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate conductor GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate conductor GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, and a color filter CF provided on the passivation layer 107 is provided, a planarization layer 108,which is provided on the color filter CF, and a pixel electrode 110, which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108, the color filter CF and the passivation layer 107.

[0179] That is to say, in the present revelation, as in (b) of Fig. Figure 17 shows that the first connecting line CL1 and the second connecting line CL2 are provided on the substrate 101 and can be covered by the high heat-resistant planarization layer 102.

[0180] In particular, as in (c) of Fig. Figure 17 shows that the second connecting line CL2 can be connected to the gate line GL through a contact hole formed in the high-temperature resistant planarization layer 102, and furthermore, the first connecting line CL1 can be connected to the gate line GL through a contact hole formed in the high-temperature resistant planarization layer 102.

[0181] To provide an additional description: As in Fig. 1, Fig. 2, and Fig. As shown in Figure 10, the connecting lines CL can extend in one direction (i.e., the second direction) from the fourth non-display area NA4 of the display panel 100 to the first non-display area NA1, and the gate lines GL can extend in one direction (in particular, the first direction perpendicular to the second direction) which differs from the connecting lines CL.

[0182] In this case, as in Fig. As shown in Figure 17, the connecting lines CL are provided on the substrate 101, insulated from the gate line GL by the high-temperature resistant planarization layer 102, and electrically connected to the gate line GL by a contact hole formed in the high-temperature resistant planarization layer 102.

[0183] The reason why, as described above, the connecting lines CL are contained in the substrate 101 and the substrate 101 is covered by the high-temperature-resistant planarization layer 102 is to reduce the load on the connecting line CL and to reduce the parasitic capacitance that occurs between the connecting line CL and at least one of the various metals (for example, the first electrode 105, the second electrode 106, the common electrode 111 and the data line) contained in the display panel 100.

[0184] In particular, increasing the thickness of the high-temperature-resistant planarization layer 102 can increase the distance between the metals provided on the high-temperature-resistant planarization layer 102 and the connecting conductor CL, thus reducing the magnitude of any parasitic capacitance occurring between the connecting conductor CL and the metals. That is, the high-temperature-resistant planarization layer 102 can perform the function of planarizing the upper end of the connecting conductor CL and reducing the parasitic capacitance occurring between the connecting conductor CL and other metals.

[0185] In this case, since the gate line GL, the semiconductor 104, the first electrode 105 and the second electrode 106, all of which require a high-temperature process, are provided on the high-temperature-resistant planarization layer 102, the high-temperature-resistant planarization layer 102 should therefore use a high-temperature-resistant material.

[0186] Therefore, the permittivity of the high-temperature planarization layer 102 should be greater than 2 and less than 4, the uniformity (max-min) of the high-temperature planarization layer 102 should be greater than 0 and less than 0.2 µm, the weight loss of the high-temperature planarization layer 102 in a high-temperature process carried out on oxide at a temperature above 400°C should be greater than 0.1% and less than 1%, the high-temperature planarization layer 102 should be chemically stable so that no weight loss or deformation of a material property occurs due to metal etching, and the contact characteristics with another layer should be good. That is, the weight loss, the permittivity, and the uniformity should be as small as possible.

[0187] Furthermore, if a display panel featuring the high-temperature-resistant planarization layer 102 is a liquid crystal display panel, the high-temperature-resistant planarization layer 102 should have a transmittance of 70% to 100%.

[0188] This means that the high-temperature resistant planarization layer 102 can have a material that has a physical characteristic similar to that of silicon dioxide (SiO2).

[0189] Furthermore, as described above, since the color filter CF is provided between the passivation layer 107 and the planarization layer 108, parasitic capacitance occurring between metal conductors provided on the planarization layer 108 and metal conductors provided below the passivation layer 107 can be reduced. This will be discussed in more detail below. Fig. 19 described.

[0190] Fig. Figure 18 is another exemplary diagram that schematically shows the cross-sectional area of ​​the display panel that is in Fig. 2 and Fig. 10 is shown, represents. In particular, (a) of Fig. Figure 18 schematically represents a cross-sectional area, taken along the first pixel P1, which is in Fig. 2 and Fig. 10 is shown, parallel to the gate line GL, (b) of Fig. Figure 18 schematically represents a cross-sectional area, taken along the second pixel P2, which is in Fig. 2 and Fig. 10 is shown parallel to the gate line GL, and (c) of Fig. Figure 18 schematically represents a cross-sectional area, taken along the third pixel P3, which is in Fig. 2 and Fig. Figure 10 shows the gate line GL parallel to it. For the sake of simplicity, elements not directly depicted in the cross-sectional areas shown in (a), (b), and (c) are included in the cross-sectional areas. To provide further clarification: The cross-sectional areas shown in (a), (b), and (c) illustrate an arrangement of the gate line GL and the second connecting line CL2, while the other elements are shown schematically for clarity.

[0191] Firstly, referring to (a) of Fig. 18, since the first pixel P1 only has the gate line GL, as in Fig. 2 and Fig. As shown in Figure 10, the second connecting line CL2 is not included in the cross-sectional area of ​​the first pixel P1.

[0192] In this case, as in (a) of Fig. Figure 18 shows the first pixel P1 of the display panel 100 comprising: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate conductor GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate conductor GL, a semiconductor 104 provided on the gate insulation layer 103 such that it overlaps the gate conductor GL, a first electrode 105 provided on the semiconductor 104, a second electrode 106 provided on the semiconductor 104 such that it is separated from the first electrode 105, a passivation layer 107 covering the first electrode 105, the second electrode 106 and the semiconductor 104, a color filter CF provided on the passivation layer 107, and a planarization layer. 108, which is provided on the CF color filter, and a pixel electrode 110,which is provided on the planarization layer 108 and is electrically connected to the second electrode 106 by a contact hole formed in the planarization layer 108, the color filter CF and the passivation layer 107.

[0193] If the display panel 100 is a liquid crystal display panel, then, as described in Fig. As shown in Figure 18, a common electrode 111 is provided on the planarization layer 108 and may be covered by an insulating layer 109. In this case, the pixel electrode 110 may be provided on the insulating layer 109 and may be electrically connected to the second electrode 106 by a contact hole formed in the insulating layer 109, the planarization layer 108, the color filter CF, and the passivation layer 107. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate lead GL may each perform the function of a transistor (a TFT) (in particular, a switching transistor) for controlling the light transmittance of the liquid crystal contained in the liquid crystal display panel.

[0194] In particular, the color filter CF can be provided on the passivation layer 107 in the display panel 100. The color filter CF can perform the function of defining the color of light emitted by the pixel.

[0195] This means that if the display panel 100 is the liquid crystal display panel, light emitted by a backlight unit provided beneath the substrate 101 can pass through the color filter CF, the insulating layer 109, the liquid crystal provided on the insulating layer 109, and an upper substrate provided on the liquid crystal. Accordingly, a user can see colored light emitted through the upper substrate.

[0196] Such a description can be applied to the display panel 100, which is shown in (b) and (c) of Fig. As shown in section 18, they can be applied.

[0197] If the display panel 100 is an organic light-emitting diode (OLED) display panel, the common electrode 111 and the insulating layer 109 can be omitted. In this case, the pixel electrode 110 can be an anode of an OLED, a light-emitting layer contained in the OLED can be provided on the pixel electrode 110, and a cathode contained in the OLED can be provided on the light-emitting layer. The first electrode 105, the second electrode 106, the semiconductor 104, the gate insulating layer 103, and the gate lead GL can each perform the function of a transistor (a TFT) (in particular, a driver transistor) for controlling the amount of light emitted by the OLED contained in the organic light-emitting diode display panel.

[0198] That is, if the display panel 100 is the organic light-emitting display panel, the pixel electrode 110 can be connected to the second electrode 106 through a contact hole formed in the passivation layer 107, the color filter CF, and the planarization layer 108, and the color filter CF can be provided under the pixel electrode 110. Fig. Figure 18 shows a cross-sectional area of ​​the organic light-emitting display panel, and the color filter CF is not shown below the pixel electrode 110. However, in a top view, the color filter CF may be provided below the pixel electrode 110 on a portion of the pixel electrode 110, except for the portion containing the contact hole.

[0199] In this case, the pixel electrode 110 can perform the function of an anode electrode of the organic light-emitting display panel, and thus, as described above, a light-emitting layer can be provided on the pixel electrode 110, and a cathode can be provided on the light-emitting layer.

[0200] Light emitted by the light-emitting layer can pass through the color filter CF, the gate insulation layer 103, the high-temperature-resistant planarization layer 102, and the substrate 101 to the outside. Accordingly, a user can see colored light emitted through the substrate 101.

[0201] Such a description can be applied to the display panel 100, which is shown in (b) and (c) of Fig. As shown in section 18, they can be applied.

[0202] Referring to (b) of Fig. In the second pixel P2, the gate line GL can cross the second connecting line CL2, as shown in Fig. 2 and Fig. 10 shown.

[0203] In this case, as in (b) of Fig. Figure 18 shows the second pixel P2 of the display panel 100 comprising: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, a second connecting line CL2 provided on the gate insulation layer 103, a passivation layer 107 covering the second connecting line CL2 and the gate insulation layer 103, a color filter CF provided on the passivation layer 107, a planarization layer 108 provided on the color filter CF, and a pixel electrode 110 provided on the planarization layer 108.

[0204] That is, in the present disclosure, as shown in (b), the first connecting line CL1 and the second connecting line CL2 can be provided on the gate insulation layer 103.

[0205] In this case, the connecting line CL can be formed by the same process as the first and second electrodes 105 and 106, which are provided on the gate insulation layer 103 and together form the transistor (the TFT).

[0206] Furthermore, since the first electrode 105 and the second electrode 106 are provided on the semiconductor 104, the connecting line CL can be provided on another semiconductor 104a, which is formed by the same process as the semiconductor 104.

[0207] This means that the connecting line CL can be formed by the same process as the first and second electrodes 105 and 106, which together form the TFT. In this case, the connecting line CL can be provided directly on the gate insulation layer 103, or it can be provided on the other semiconductor 104a, which is formed by the same process as the semiconductor 104 that together form the transistor (the TFT), in order to have the same structure as each of the first electrode 105 and the second electrode 106.

[0208] Finally, with reference to (c) of Fig. 18, in the third pixel P3, the gate line GL can be connected to the second connecting line CL2, as in Fig. 2 and Fig. 10 shown.

[0209] In this case, as in (c) of Fig. Figure 18 shows the third pixel P3 of the display panel 100 comprising: a substrate 101, a high-temperature-resistant planarization layer 102 provided on the substrate 101, a gate line GL provided on the high-temperature-resistant planarization layer 102, a gate insulation layer 103 provided on the gate line GL, the other semiconductor 104a provided on the gate insulation layer 103 and electrically connected to the gate line GL by a contact hole formed in the gate insulation layer 103, the second interconnection line CL2 provided on the other semiconductor 104a, a passivation layer 107 covering the second interconnection line CL2 and the other semiconductor 104a, a color filter CF provided on the passivation layer 107, a planarization layer 108 provided on the color filter CF, and a pixel electrode 110.which is provided on the planarization layer 108.

[0210] As described above, the second connecting line CL2 can be provided directly on the gate insulation layer 103, and in this case the second connecting line CL2 can be electrically connected to the gate line GL through a contact hole formed in the gate insulation layer 103.

[0211] If, as described above, the connecting lines CL are contained in the substrate 101, the connecting lines CL can even be formed without an additional process. In the above description, the high-temperature-resistant planarization layer 102 can be provided on the substrate 101, or in an embodiment described above with reference to Fig. As described in section 18, the high-temperature resistant planarization layer 102 can be omitted.

[0212] However, in one embodiment, the above with reference to Fig. As described in Figure 18, when a different metal is provided on the substrate 101 instead of the connecting conductor CL, the high-temperature-resistant planarization layer 102 performs a function of reducing a parasitic capacitance between various metals provided on the high-temperature-resistant planarization layer 102 and the other metal.

[0213] In this case, the high-temperature-resistant planarization layer 102 can exhibit a physical characteristic which, as above with reference to Fig. 17 is described.

[0214] Furthermore, as described above, since the color filter CF is provided between the passivation layer 107 and the planarization layer 108, a parasitic capacitance that occurs between metals provided on the planarization layer 108 and metals provided below the passivation layer 107 can be reduced. This will be discussed below with reference to Fig. 19 described.

[0215] Fig. Figure 19 is an exemplary diagram to describe the principle that a parasitic capacitance decreases in a display device according to the present disclosure. Here, (a) is of Fig. 19 a cross-sectional view of a display panel of the related technology, (b) of Fig. Figure 19 is a cross-sectional view of the display panel, which is shown above in relation to Fig. 17 described, and (c) of Fig. Figure 19 is a cross-sectional view of the display panel, which is shown above in relation to Fig. 18 was described.

[0216] As described above with reference to Fig. 17 and Fig. 18, can be provided in the display panel of the color filter CF on the passivation layer 107.

[0217] The color filter CF can reduce parasitic capacitance that occurs between metal or metal conductors provided on the planarization layer 108 and metal or metal conductors provided below the passivation layer 107.

[0218] For example, if the display panel is a liquid crystal display panel, a distance between a gate line GL and a common electrode 111 in a liquid crystal display panel in which no color filter is provided between a passivation layer 107 and a planarization layer 108, as in (a) of Fig. 19 shown, be smaller than a distance between a gate line GL and a common electrode 111 in a liquid crystal display panel in which a color filter is provided between a passivation layer 107 and a planarization layer 108, as shown in (b) of Fig. 19 is shown, and can also be smaller than the distance between a connecting line CL and the common electrode 111. A parasitic capacitance is generally inversely proportional to a distance, and thus a parasitic capacitance can decrease with increasing distance between two electrodes.

[0219] Therefore, a parasitic capacitance can exist between the gate line GL and the common electrode 111 in the liquid crystal display panel in which the color filter is provided between the passivation layer 107 and the planarization layer 108, as shown in (b) of Fig. 19 shown, be smaller than a parasitic capacitance between the gate line GL and the common electrode 111 in a liquid crystal display panel of related technology in which the color filter is not provided between the passivation layer 107 and the planarization layer 108, as in (a) of Fig. 19 shown. Furthermore, as in (b) of Fig. Figure 19 shows that in the liquid crystal display panel, in which a connecting line CL is provided between the passivation layer 107 and a high-temperature-resistant planarization layer 102, the distance between the connecting line CL and the common electrode 111 increases more strongly based on the color filter CF provided between the passivation layer 107 and the planarization layer 108, and thus a parasitic capacitance between the connecting line CL and the common electrode 111 can be reduced.

[0220] Furthermore, a parasitic capacitance between a connecting line CL and a common electrode 111 in a liquid crystal display panel of the present disclosure, which is shown in (c) of Fig. 19 is shown to be smaller than a parasitic capacitance between a connecting line CL and a common electrode 111 in a liquid crystal display panel of the related technology in which a color filter CF is not provided between the connecting line CL and the planarization layer 108.

[0221] In this case, according to the disclosure described above, a feature has been described that a parasitic capacitance between the gate line GL or the connecting line CL, which is provided under the color filter CF, and the common electrode 111, which is provided on the color filter CF, can be reduced.

[0222] However, the present disclosure is not limited to that.

[0223] For example, in the display panel used in the present disclosure, since the color filter CF is provided between the passivation layer 107 and the planarization layer 108, a parasitic capacitance between various metals (for example, a common electrode, a pixel electrode, an anode electrode, a cathode electrode, and various power supply lines) provided on the planarization layer 108 and various metals (for example, a gate line, a connecting line, a data line, a touch electrode, and various power supply lines) provided below the color filter CF can decrease compared with a parasitic capacitance of a display panel of the related technology in which the color filter CF is not provided between the passivation layer 107 and the planarization layer 108.

[0224] To provide a further description: In the present disclosure, the color filter CF can perform a function of reducing a parasitic capacitance between metals provided under and on top of the color filter CF.

[0225] Fig. Figure 20 is an exemplary diagram to describe a method of attaching a circuit film to a display panel in a display device according to the present disclosure. Fig. 21 is an example diagram that illustrates an example in which the display panel, which is in Fig. 20 is shown, attached to a front cover. Fig. 22 is an example diagram showing a front section of the display panel, which is in Fig. 21 is shown, represents.

[0226] Firstly, with regard to Fig. 20, the display panel 100 can have a lower substrate 180 and an upper substrate 190. If the display panel 100 is a liquid crystal display panel, the liquid crystal can be implanted in a region between the lower substrate 180 and the upper substrate 190.

[0227] The lower substrate 180 can be formed in various ways, as described above with reference to Fig. 15 to 19.

[0228] If the display panel 100 is a liquid crystal display panel, the upper substrate 190 together with the lower substrate 180 can perform a function of holding implanted liquid crystal.

[0229] If the display panel 100 is an organic light-emitting display panel, the upper substrate 190 can perform a function of covering the lower substrate 180 to prevent water from entering an OLED contained in the lower substrate 180.

[0230] A pad part 170, as described above, can be provided in the lower substrate 180, and a circuit film 210 can be connected to the pad part 170, and can then be bent and arranged at a lower end of the display panel.

[0231] In particular, a display panel of the related technology, as in (a) of Fig. 20 shows that the circuit film 210, which is connected to the pad part 170 contained in the lower substrate 180, is bent along a side surface of the lower substrate 180 and can be arranged at a lower end of the lower substrate 180.

[0232] However, in a display panel used in the present disclosure, as in (b) of Fig. Figure 20 shows a circuit film 210 connected to a pad part 170 contained in a lower substrate 180, bent along a side surface of the upper substrate 190 and can be provided at a lower end of the upper substrate 190.

[0233] That is, in a display device of the related technology, an image I can be output through the upper substrate 190 to the outside, as in (a) of Fig. 20, and in a display device according to the present disclosure, an image I can be output through the lower substrate 180 to the outside, as shown in (b) of Fig. 20 shown.

[0234] In this case, it is possible that in the display device according to the present disclosure, as in Fig. Figure 21 shows that a multitude of pads 171 contained in the pad part 170 are not exposed to the outside, and that therefore a front cover 160 to support the display panel does not need to cover the pad part 170.

[0235] The front cover 160 can serve to support the display panel 100 or to form an external appearance of the display device. In a case where the front cover 160 serves to support the display panel 100, an external housing of the display device may cover more of the front cover 160. However, the external appearance of the external housing of the display device may be based on the external appearance of the front cover 160, and thus, even in a case where the display device further comprises an external housing, the description and the following description can be applied identically. For the sake of simplicity, a display device in which the front cover 160 forms an external appearance of the display device is described below as an example of the present disclosure.

[0236] For example, if a user opens the front of the display device according to the present disclosure, as in Fig. 21 and Fig. As shown in Figure 22, the entire front surface of the display panel 100 and only side panel areas 161 of the front cover 160 are exposed. In this case, the pads 171 contained in the pad part 170 can be covered by the lower substrate 180 and thus cannot be exposed on the outside.

[0237] That is to say, in the display device according to the present disclosure, since the pads 171 contained in the pad part 170 are not exposed on the outside, a front surface front cover part, which is used in the display device of the related technology, cannot be provided.

[0238] Therefore, the entire front surface of the display panel 100 and only side area 161 of the front cover 160 can be exposed to a user. Furthermore, even if edge area of ​​the front surface of the display panel 100 is covered and supported by the front cover 160, the portion covered by the front cover 160 can be designed to be as small as possible to fulfill the purpose of supporting the display panel 100.

[0239] Therefore, in the display device according to the present disclosure, a width B of a frame can be set such that it is equal to a width of each of the side sections 161 of the front cover 160, or it can be set such that it is as small as possible to fulfill the purpose of supporting the display panel 100.

[0240] Furthermore, in the display device according to the present disclosure, the widths of the bezels contained in the four side faces of the display panel 100 can be the same. Accordingly, the aesthetic appearance of the display device can be improved.

[0241] To provide an additional description: In the display device according to the present disclosure, a TFT substrate (i.e., the lower substrate 180) having transistors may be exposed on the outside of the display device 10, and thus the width of a bezel of a front cover for covering or supporting each of the first to fourth non-display areas may be reduced.

[0242] For example, according to the arrangement described above, although the size of the first non-display area is not substantially reduced in the present disclosure, the pad portion may not be exposed in a direction towards the exterior of the display device 10, and thus the width of a front cover's border for covering the first non-display area containing the first pad portion may be reduced. In this case, since an area of ​​each of the second and third non-display areas is reduced, the width of a front cover's border for covering or supporting each of the second and third non-display areas may be reduced, according to the present disclosure. Accordingly, the widths of front cover borders for covering or supporting the first through fourth non-display areas may all be reduced, according to the present disclosure.

[0243] Features of the present revelation described above are briefly described.

[0244] Firstly, since in the present disclosure the gate driver circuit is arranged in a non-display area of ​​each of three surfaces, except for a pad portion, a left bounding area and a right bounding area can be reduced in size, and the delay of a gate pulse can be eliminated, thereby making high-speed driving easily achievable.

[0245] Secondly, in the present disclosure, the connecting line CL can be arranged on the substrate 101, and the high-temperature-resistant planarization layer 102 can be arranged between the connecting line CL and the gate line GL, thereby reducing a parasitic capacitance that occurs between the metals provided on the high-temperature-resistant planarization layer 102 and the connecting line CL.

[0246] Furthermore, parasitic capacity can be reduced, and thus the widths of metal conduits containing the metals can be reduced, thereby reducing the widths of metal conduits located in non-indicating areas. Consequently, the widths of the non-indicating areas can be reduced further.

[0247] Thirdly, in the present disclosure, the color filter CF can be arranged between the passivation layer 107 and the planarization layer 108, thereby reducing a parasitic capacitance between metals provided on the planarization layer 108 and metals provided below the passivation layer 107.

[0248] Furthermore, parasitic capacity may be reduced, thus reducing the widths of metal conduits containing the metals, which in turn reduces the widths of metal conduits deployed in non-indicating areas. Consequently, the widths of the non-indicating areas can be reduced even further.

[0249] Fourthly, in the present disclosure, the lower substrate 180, which has the pad part 170, can be arranged from the lower substrate 180 and the upper substrate 190, which both form the display panel 100, such that it faces the outside of the display device according to the present disclosure, and thus the widths of four borders corresponding to four non-display areas of the display device can be reduced compared with the display device of the related technology, and in particular, the widths of four borders can be equal.

[0250] Furthermore, in the present disclosure, the first feature can be combined in various ways with at least one of the second to fourth features.

[0251] In the display device according to the present disclosure, since a plurality of gate driver circuits are distributed over and arranged in a second to fourth non-display area, excluding a first non-display area where a pad section is arranged, the width of each of the second to fourth non-display areas can be reduced, and the delay of a gate pulse can be eliminated to easily implement high-speed driving, thereby preventing an output difference between gate pulses in a display area.

[0252] Furthermore, the display device according to the present disclosure can reduce a parasitic capacitance that occurs between metals which are contained in different layers.

[0253] Furthermore, in the display device according to the present disclosure, the width of a border can be minimized, thereby improving the aesthetic appearance of the display device.

[0254] The feature, structure, and effect described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, the feature, structure, and effect described in at least one embodiment of this disclosure can be implemented by those familiar with the technology through combination or modification of other embodiments. Therefore, content associated with such combination and modification should be interpreted as falling within the scope of this disclosure.

Claims

[1] Display device (10) comprising: a display panel (100) comprising a display area (AA) and a first to fourth non-display area (NA1, NA2, NA3, NA4) surrounding the display area (AA), wherein the display area (AA) comprises a plurality of pixels (P1, P2, P3) connected to a plurality of gate lines (GL) numbered consecutively; a pad section (170) located in the first non-indication area (NA1); a first gate driver circuit (310) located in the second non-display area (NA2) for driving a first group of gate lines under the plurality of gate lines (GL); a second gate driver circuit (320) located in the third non-display area (NA3) for driving a second group of gate lines under the plurality of gate lines (GL); wherein each gate line (GL) of the first group of gate lines is an odd-numbered gate line (GL) from the plurality of gate lines (GL), and each gate line (GL) of the second group of gate lines is an even-numbered gate line (GL) from the plurality of gate lines (GL), and a third gate driver circuit (330) located in the fourth non-display area (NA4) for driving the first and second groups of gate lines, wherein the display panel (100) further comprises a plurality of connecting lines (CL1, CL2) which connect the gate lines (GL) of the first and second group of gate lines to the third gate driver circuit (300). [2] Display device (10) according to claim 1, wherein the multitude of connecting lines (CL1, CL2) are provided on a substrate (101) which is contained in the display panel (100), the multitude of connecting lines (CL1, CL2) are covered by a highly heat-resistant planarization layer (102), the multitude of gate lines (GL) are provided on the high-temperature-resistant planarization layer (102), and Each of the multiple connecting lines (CL1, CL2) is connected to a corresponding gate line (GL) by a contact hole formed in the high-temperature resistant planarization layer (102). [3] Display device (10) according to claim 1, wherein the multitude of interconnection lines (CL1, CL2) are provided on a gate insulation layer (103) that covers the multitude of gate lines (GL), and Each of the multiple connecting lines (CL1, CL2) is connected to a corresponding gate line (GL) by a contact hole formed in the gate insulation layer (103). [4] Display device (10) according to claim 3, wherein a first electrode (105) and a second electrode (106), each forming a transistor contained in each of the plurality of pixels (P1, P2, P3), are provided on the gate insulation layer (103), and the multitude of connecting lines (CL1, CL2) on the same layer as the first electrode (105) and the second electrode (106) are provided on the gate insulation layer (103). [5] Display device (10) according to claim 4, wherein the transistor has a semiconductor (104) and another semiconductor (104a) having the same material as the semiconductor (104) is provided between the gate insulation layer (103) and each of the plurality of connecting lines (CL1, CL2). [6] Display device (10) according to claim 3, wherein a metal conductor is provided on a substrate (101) contained in the display panel (100), the metal conduit is covered by a high-temperature resistant planarization layer (102), the multitude of gate lines (GL) are formed on the high-temperature resistant planarization layer (102). [7] Display device (10) according to claim 1, further comprising: a color filter (CF) provided on a passivation layer (107) covering a transistor contained in each of the plurality of pixels (P1, P2, P3); and a planarization layer (108) provided on the color filter (CF). [8] Display device (10) according to claim 7, wherein the multitude of connecting lines (CL1, CL2) are provided on a substrate (101) which is contained in the display panel (100), the multitude of connecting lines (CL1, CL2) are covered by a highly heat-resistant planarization layer (102), the multitude of gate lines (GL) are provided on the high-temperature-resistant planarization layer (102), Each of the multiple connecting lines (CL1, CL2) is connected to a corresponding gate line (GL) by a contact hole formed in the high-temperature resistant planarization layer (102), and the passivation layer (107) is provided on the multitude of gate lines (GL). [9] Display device (10) according to claim 7, wherein the multitude of interconnection lines (CL1, CL2) are provided on a gate insulation layer (103) which covers the multitude of gate lines (GL), Each of the multiple connecting lines (CL1, CL2) is connected to a corresponding gate line (GL) by a contact hole formed in the gate insulation layer (103), and the passivation layer (107) is provided on the gate insulation layer (103). [10] Display device (10) according to claim 1, wherein the display panel (100) further comprises a lower substrate (180) having the plurality of pixels (P1, P2, P3), and an upper substrate (190) covering the lower substrate (180), and an image generated by the display panel (100) is output to the outside through the lower substrate (180). [11] Display device (10) according to claim 10, wherein a plurality of pads (171) contained in the pad part (170) are covered by the lower substrate (180) and are not exposed. [12] Display device (10) according to any one of claims 1 to 11, wherein the first gate driver circuit (310) has an odd stage (ST1 to ST(2n-1)) which corresponds to an odd numbered gate line of the plurality of gate lines. [13] Display device (10) according to any one of claims 1 to 12, wherein the second gate driver circuit (320) has an even stage (ST2 to ST(2n)) which corresponds to an even numbered gate line (GL) of the plurality of gate lines. [14] Display device (10) according to any one of claims 1 to 13, wherein the third gate driver circuit (330) has an odd stage (ST1 to ST(2n-1)) corresponding to the first group of gate lines and an even stage (ST2 to ST(2n)) corresponding to the second group of gate lines. [15] Display device (10) according to claim 14, wherein the plurality of connecting lines (CL1, CL2) comprises: a first connecting line (CL1) that connects the odd stage (ST1 to ST(2n-1)) of the third gate driver circuit (330) to the first group of gate lines; and a second connecting line (CL2) that connects the straight stage (ST2 to ST(2n)) of the third gate driver circuit (330) to the second group of gate lines. [16] Display device (10) according to any one of claims 1 to 15, wherein the display area (AA) comprises: a first display area (AA1) adjacent to the first gate driver circuit (310); and a second display area (AA1) adjacent to the second gate driver circuit (320). [17] Display device (10) according to claim 2, 6 or 8, wherein a relative dielectric constant of the high-temperature-resistant planarization layer (102) is greater than 2 and less than 4, a uniformity of the high-temperature resistant planarization layer (102) greater than 0 and less than approximately 0.2 µm, and a weight loss of the high heat-resistant planarization layer (102) is greater than 0.1% and less than 1%.

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