Semiconductor device with complementary field-effect transistor of the type with buried logic conductors, layout diagram, manufacturing method and system for it

By integrating buried logic conductors beneath the active zones of CFETs, the semiconductor device addresses inefficiencies in signal routing, enhancing routing capacity and conduction efficiency in the M0 layer.

DE102020125647B4Active Publication Date: 2026-06-03TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Filing Date
2020-10-01
Publication Date
2026-06-03

AI Technical Summary

Technical Problem

Existing semiconductor devices face challenges in efficiently routing logic signals due to limited routing resources in the metallization layer, particularly in complementary field-effect transistors (CFETs) where the metallization layer beneath the active zones is absent, leading to inefficiencies in signal conduction.

Method used

Incorporating buried logic conductors (BLC) in a metallization layer beneath the active zones of CFETs, which allows for increased routing resources in the M0 layer by routing logic signals through these conductors, thereby optimizing signal conduction.

Benefits of technology

This approach enhances the routing capacity in the M0 layer, providing improved signal conduction and resource utilization compared to traditional CFET designs that rely solely on the M0 layer for logic signal routing.

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Abstract

Semiconductor device (100) comprising a CFET with buried logic conductors, BLC, wherein the BLC-CFET comprises: with respect to a first direction (Z) a first and a second active zone (208(2), AAN, 210(2), AAP), which are arranged in a stack according to a CFET configuration; a first (214(1), MDN, 214(3)(1), MDP) and a second contact structure (216(1), 216(3)(1), 316(5)(1), 316(5)(1)'-(4)', MDP, 332(1), 332(1)', VMDPB), which are electrically connected to the first active zone (208(2), AAN); a third (214(4)(1), MDN) and a fourth contact structure (216(2), 216(4)(1), MDP), which are electrically connected to the second active zone (210(2), AAP); a first metallization layer, M_1st layer (220(1), 220(2), 320(3), 420(4), M0) above the stack, which has: Alpha logic conductors (222(2), 222(7)', 322(11)', 422(15), OUT, 222(3), 222(8)', 322(12)', 422(16), IN), configured for logic signals; and Supply current conductor, PG conductor (222(1), 222(6)', 322(10)', 422(14), VDD, 222(4), 222(9)', 322(13)', 422(17), VSS); where the Alpha logic ladders (222(2), 222(7)', 322(11)', 422(15), 222(3), 222(8)', 322(12)', 422(16)) and the PG ladders (222(1), 222(6)', 322(10)', 422(14), VDD, 222(4), 222(9)', 322(13)', 422(17), VSS) do not overlap; and a metallization layer below the stack, M_B layer (224(1), 224(2), 324(3), 422(4), MB), which has non-overlapping beta logic conductors (226(1)-226(4), 226(5)'-226(6)', 326(7)'-326(8)', 426(9)-426(12)); and wherein, with respect to a second direction perpendicular to the first direction (Z), each of the alpha logic ladders (222(2), 222(7)', 322(11)', 422(15), 222(3), 222(8)', 322(12)', 422(16)), the PG ladder (222(1), 222(6)', 322(10)', 422(14), VDD, 222(4), 222(9)', 322(13)', 422(17), VSS) and the beta logic ladder (226(1)-226(4), 226(5)'-226(6)', 326(7)'-326(8)', 426(9)-426(12)) at least partially forms one or Several of the first, second, third and fourth contact structures overlap.
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