Switching power converter with adaptive pulse frequency modulation

Abstract

A control device (300; 305) for controlling switching of a power switching transistor in a switching power converter, the control device (300; 305) comprising: a feedback loop circuit comprising an error amplifier (400) configured to generate an error signal in response to an error between an output voltage and a desired value, and a loop filter (405) configured to filter the error signal to form a control voltage signal; and a logic circuit (410) configured to generate a proportionality constant in response to the control voltage signal, wherein for each cycle of the power switching transistor, the logic circuit (410) is configured to turn on the power switching transistor for an on-time and turn off the power switching transistor during a reset period followed by a delay period, and wherein the logic circuit (410) is further configured to time the delay period to be equal to a product of the sum of the on-time and the reset period and the proportionality constant minus the sum of the on-time and the reset period.

Description

TECHNICAL AREA

[0001] This application relates to switching power converters and in particular to a switching power converter with adaptive pulse frequency modulation. BACKGROUND

[0002] Single-stage AC-DC power conversion is a cost-effective and therefore widely used power supply topology for applications such as solid-state lighting. An important parameter for a single-stage AC-DC switching power converter is its power factor, which is the ratio of the real power delivered from the AC mains to the single-stage AC-DC switching power converter compared to the apparent power delivered to the single-stage AC-DC switching power converter. Apparent power is insensitive to the phase shift between the input current and voltage, unlike real power. The power factor (PF) is thus reduced when the input current and input voltage are out of phase. The rectified input voltage to a single-stage AC-DC switching power converter transitions from approximately zero volts to the peak line voltage (e.g., 120 V * 1.414 in the US) at twice the AC mains frequency.Given this sinusoidal pulsing or cycling of the rectified input voltage, the input current should have a similar profile to achieve high PF, such as by using a suitably modified peak current or a constant on-time control method.

[0003] In each of these techniques, the switching power converter regulates the cycling, or switching, of the power switching transistor so that, during periods of high load, the input current to the switching power converter has a profile that is in phase with the profile, or envelope, for the rectified input voltage. Each cycle of the rectified input voltage begins at a relatively low voltage (e.g., zero volts) to reach a peak voltage in the middle of the cycle, and then decays back to the relatively low voltage. To achieve a high PF, the peak value for each cycle of the input current to the switching power converter has a profile, or threshold envelope, similar to the envelope of the rectified input voltage.The peak input current thus changes in phase with the rectified input voltage, so that the peak input current is relatively small at the beginning of a cycle, peaks in the middle of the cycle, and then falls back to a relatively small value at the end of each cycle.

[0004] To achieve high efficiency, it is also common for the controller to change the modulation mode of switching the power switching transistor depending on the load. During periods of high load, a pulse-width modulation mode may be used. However, when the load drops, it is common to switch to a pulse-frequency modulation mode. While pulse-frequency modulation is used, the switching frequency drops when the load decreases and increases when the load increases. The resulting drop in the pulse switching frequency during pulse-frequency modulation operation at low load can cause a number of problems. For example, the switching frequency for switching the power switching transistor may enter the audible range. Additionally, the switching frequency is independent of the AC mains cycle, which drives the sinusoidal profile for the rectified input voltage.At the beginning and end of each rectified input voltage cycle, it is desirable that the peak current for each power switching transistor cycle be relatively small so that the input current profile to the switching power converter is in phase with the rectified input voltage envelope. However, the peak current must also be responsive to the output voltage. To keep the output voltage in regulation, the peak current at the beginning and end of each rectified input voltage cycle (zero-crossing times for the AC mains input voltage) must be undesirably high. Conventional pulse frequency modulation during light load conditions therefore suffers from a reduced power factor due to the need to increase the peak current to the power switch near the zero-crossing times for the AC mains input voltage.

[0005] Accordingly, there is a need in the art for single-stage power converters with robust power factor correction during pulse frequency modulation operation.

[0006] DE 10 2017 102 676 A1 relates to a device and a method for voltage control of a switching converter in quasi-resonant mode, in particular a power factor correction converter.

[0007] US 9 154 030 B2 relates to a digital control device of a switching power supply.

[0008] US 2008 / 0 246 444 A1 relates to integrated circuits, in particular devices for controlling the power supply.

[0009] US 7 064 527 B2 relates to a transition operating device for correcting the power factor in switching power supplies.

[0010] US 2011 / 0 317 459 A1 relates to a controller for a power factor correction circuit, in particular a controller for the operation of a switch in a power factor correction circuit.

[0011] US 2018 / 0 054 113 A1 concerns electronic circuits that provide power factor correction for a load. SUMMARY

[0012] To improve the power factor while maintaining the output voltage in regulation, adaptive pulse frequency modulation is provided, in which the switching frequency is reduced as the cycles of the power switching transistor progress from the beginning of a rectified input voltage cycle to a midpoint of the rectified input voltage cycle. The switching frequency then increases from the midpoint of the rectified input voltage to the end of the cycle in a symmetrical manner, as was the case in the first half of the cycle. Due to the increase in switching frequency near the zero-crossing times that mark the beginning and end of the cycle, the corresponding relatively small pulses of input current to the switching power converter are relatively numerous compared to conventional pulse frequency modulation.The envelope for the input current to the switching power converter can thus be proportional to the envelope for the rectified input voltage, but the output voltage for the switching power converter is kept in regulation.

[0013] As is common with pulse frequency modulation of a switching power converter, a feedback loop generates a control signal based on an error between the output voltage and a desired value for the output voltage. In a conventional switching power converter, the resulting control signal would be mapped to a switching frequency that would be relatively static over the cycle of the rectified input voltage. In the switching power converters disclosed here, the control signal is instead mapped to a proportionality constant, which is used as follows. During each cycle of the power switching transistor, the on-time of the power switching transistor is followed by a reset time during which the total output current from the inductor in a DC-DC switching power converter (or from a secondary winding in a transformer for an isolated switching power converter, such as a flyback converter) decreases to zero.The reset time is followed by an idle delay period during which the power switching transistor is not switched, since the conduction mode disclosed here is discontinuous. To generate an instantaneous switching frequency for each cycle of the power switching transistor, a controller for the switching power converter may observe the on-time and reset time and then set the subsequent idle delay period such that a ratio of the sum of the on-time and reset time is equal to the proportionality constant.

[0014] These advantageous features can be better appreciated by considering the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A shows the sinusoidal envelope of the rectified input voltage over two consecutive cycles of the rectified input voltage. Fig. Figure 1B shows the peak input current envelope over one cycle of the rectified input voltage, in which the peak input current envelope is proportional to the rectified input voltage envelope and in which pulse frequency modulation is used to switch the power switching transistor at a relatively low switching frequency due to low load conditions. Fig. 2 shows the peak input current envelope for one cycle of the rectified input voltage in which adaptive pulse frequency modulation is used to switch the power switching transistor, and also shows the switching frequency for the cycle of the rectified input voltage according to one aspect of the disclosure. Fig. 3 shows an exemplary boost converter with a controller configured to implement an embodiment of adaptive pulse frequency modulation according to one aspect of the disclosure. Fig. 4 shows the control device of Fig. 3 in more detail.

[0015] Embodiments of the present disclosure and their advantages are best understood by reference to the following detailed description. It should be noted that like reference numerals are used to identify like elements illustrated in one or more of the figures. DETAILED DESCRIPTION

[0016] To improve the power factor during low-load pulse frequency modulation, it is common practice for the peak input current to the switching power converter during each cycle of the power switching transistor to be proportional to the rectified input voltage to the switching power converter. For brevity, the rectified input voltage will be referred to simply as the input voltage in the following discussion. At the beginning of an input voltage cycle, the input voltage is relatively low. The peak input current at this time would thus also be relatively low. In the middle of the input voltage cycle, the input voltage reaches a peak value. The peak input current would thus also be at its highest value in the middle of the cycle, while the peak input current would again be relatively low at the end of the cycle.

[0017] The switching power converter controllers disclosed herein also switch the power switching transistor such that the peak input current is proportional to the input voltage. As noted above, such proportionality must typically be violated during light-load pulse frequency modulation (PFM) operation. During such light-load PFM operation, the switching frequency is relatively slow, as it decays proportionally with the load. Thus, there are relatively few pulses of the power switching transistor over one input voltage cycle during light-load PFM operation. In a conventional switching power converter, the peak current would have to be increased for the power switching cycles near the zero-crossing times of the AC mains (the beginning and end of each input voltage cycle), which reduces the power factor.To solve this problem, a switching power converter is disclosed that implements adaptive pulse frequency modulation operation in the presence of relatively light loads. In this adaptive pulse frequency modulation, the switching period for the power switching transistor is shortened near the zero-crossing times for the input voltage of the AC grid.

[0018] The resulting adaptive pulse frequency modulation is quite advantageous because the output voltage can remain regulated near zero-crossing times due to the increased number of pulses from the power switching transistor, yet these pulses can have lower peak input currents, improving the power factor. Additionally, varying the pulse frequency modulation across the input voltage cycle helps prevent or reduce switching frequencies in the audible noise bandwidth.

[0019] An example of the input voltage profile or envelope 110 over two cycles is shown in Fig. 1A. In each cycle, the input voltage rises to a maximum value in the middle of the cycle. A zero-crossing time 115 separates the two cycles. The peak input current for each cycle of the power switching transistor should match the envelope 110 for improved power factor. However, with a conventional PFM, the switching frequency would be essentially constant and relatively slow over each input voltage cycle for low-load operation, so conventional shaping of the peak input current to match the envelope 110 cannot keep the output voltage regulated. This shaping of the peak input current, together with conventional pulse frequency modulation, is shown in Fig. 1B for a single input current cycle (which also corresponds to an input voltage cycle). Since the switching frequency for switching the power switching transistor is essentially constant over the cycle, the switching period Tp between current pulses is constant. Due to the relatively low switching frequency, the switching period Tp is relatively large, so there are relatively few pulses of input current over the input current cycle. There is thus only one pulse within the first approximately 20% of the cycle and one pulse 125 within the last approximately 20% of the cycle. Due to the current shaping to the input voltage profile, pulses 120 and 125 are relatively weak, so that the output voltage for the corresponding switching power converter can be kept in regulation because only two relatively weak input current pulses are carried out over approximately 40% of the input current cycle.

[0020] To provide a robust power factor and still be able to keep the output voltage regulated, the adaptive pulse frequency modulation disclosed herein increases the switching frequency at the zero-crossing times (beginning and end of each input voltage cycle) as for a peak input current envelope 200 in Fig. 2. The switching period Tp thus becomes relatively large near the middle of the cycle, but decreases at the beginning and end of the cycle. The resulting switching frequency (fsw) profile 200 for the input voltage cycle is also shown in Fig. 2. The switching frequency is inversely related to the switching period Tp, so that the switching frequency increases as the time to the beginning or end of the cycle decreases. Conversely, the switching frequency decreases to a minimum value in the middle of the cycle.

[0021] Any suitable switching power converter can implement the adaptive pulse frequency modulation disclosed herein. An exemplary boost converter 300 is shown in Fig. 3, which has a control device 305 configured for an embodiment of adaptive pulse frequency modulation, in Fig. 3. A bridge rectifier 310 rectifies an AC mains input voltage (V_INAC) to form the rectified input voltage (Vin) on an input voltage supply rail. For each half cycle of the AC mains input voltage, the rectified input voltage has one cycle, as shown in Fig. 1A. An input capacitor Cin stores and filters the rectified input voltage. The controller 305 regulates an output voltage (V_OUT) by modulating the switching of a power switching transistor S. One terminal (e.g., a source terminal) of the power switching transistor is connected to ground, while a remaining terminal (e.g., a drain terminal) is coupled to the input voltage rail via an inductor L. While the power switching transistor is turned on, an input current (In) flows through the inductor and through the power switching transistor to ground. During this on-time, an output diode D1 is reverse biased to prevent an output current (Iout) from flowing out of the boost converter to charge an output capacitor Cout with the output voltage.When the power switching transistor is turned off, the output diode is forward biased, allowing the inductor to run freely to drive the output current and charge the output voltage. In alternative embodiments, the output diode can be replaced by a synchronous rectifying switching transistor.

[0022] An embodiment of the control device 300 is shown in Fig.4 is shown in more detail. An error amplifier 400 compares the output voltage to a desired value of the output voltage (Vref) to generate an error signal, which is filtered by a loop filter 405 to form a control signal voltage Vc. The error amplifier 400 and the loop filter 405 form a feedback loop circuit that can be implemented either in the analog domain or in the digital domain. In an implementation in the digital domain, the output voltage and the reference voltage are digitized. The error amplifier would then be replaced by an adder that subtracts the digitized reference voltage from the digitized output voltage to form a digital error signal. The loop filter would then be a digital loop filter in such a digital implementation.Regardless of whether the feedback loop circuit is implemented in the digital or analog domain, the control signal voltage would be mapped to a switching frequency for pulse frequency modulation operation in a conventional controller (note that the power converters disclosed herein are assumed to drive relatively light loads, so pulse frequency modulation is invoked). However, in controller 300, a logic circuit 410 maps the control signal voltage to a proportionality constant instead of a switching frequency. In one embodiment, logic circuit 410 is a microcontroller.

[0023] Logic circuit 410 also generates an on-time for the power switching transistor, which is timed by a timer, as implemented by a counter 420 that counts in response to cycles of a clock signal from a clock source 415. Those skilled in the art will appreciate that the detection of the reset time may be performed using any of several known techniques. The detection of the reset time by a reset time detection circuit 425 will therefore not be discussed in detail here. Counter 420 counts both the on-time period for the power switching transistor and the reset time. Based on the proportionality constant, logic circuit 410 calculates the delay period (T DELAY ) after the reset time as follows: TDELAY=(TON+TRESET)×Ratio−(TON−TRESET) where T ON the one-time, T RESET is the reset time and Ratio is the proportionality constant.

[0024] The delay period calculation can be performed on a pulse-by-pulse basis over the input current cycle. Alternatively, the delay period can be applied to a group of pulses (e.g., a pair of pulses) and then updated for a subsequent group of pulses. Regardless of how the delay period is updated, logic circuit 410 can use a constant on-time to achieve an input current envelope proportional to the rectified input voltage envelope. Alternatively, logic circuit 410 can calculate a peak current for each cycle of the power switching transistor as a function of the input voltage (Vin). The input voltage is thus an optional parameter for logic circuit 410.

Claims

[1] A control device (300; 305) for controlling switching of a power switching transistor in a switching power converter, the control device (300; 305) comprising: a feedback loop circuit comprising an error amplifier (400) configured to generate an error signal in response to an error between an output voltage and a desired value, and a loop filter (405) configured to filter the error signal to form a control voltage signal; and a logic circuit (410) configured to generate a proportionality constant in response to the control voltage signal, wherein for each cycle of the power switching transistor, the logic circuit (410) is configured to turn on the power switching transistor for an on-time and turn off the power switching transistor during a reset period followed by a delay period, and wherein the logic circuit (410) is further configured to time the delay period to be equal to a product of the sum of the on-time and the reset period and the proportionality constant minus the sum of the on-time and the reset period. [2] The control device (300; 305) according to claim 1, wherein the switching power converter is a boost converter. [3] The control device (300; 305) according to claim 1 or 2, wherein the control device (300; 305) further comprises a reset detection circuit configured to detect the reset period. [4] The control device (300; 305) of any one of claims 1 to 3, wherein the logic circuit (410) is further configured such that the on-time for each cycle of the switching power transistor is a constant. [5] The control device (300; 305) of any one of claims 1 to 4, wherein the logic circuit (410) is further configured to calculate a peak current proportional to an input voltage for each cycle of the switching power transistor. [6] Control device (300; 305) according to one of claims 1 to 5, wherein the logic circuit (410) comprises a microcontroller. [7] The control device (300; 305) according to any one of claims 1 to 6, wherein a switching frequency for the power switching transistor has a minimum in a middle of a cycle of the rectified input voltage. [8] A method for controlling switching of a power switching transistor in a switching power converter, comprising: Generating a proportionality constant in response to an error between an output voltage for the switching power converter and a desired value for the output voltage; Turning on the power switching transistor for an on time for a first cycle of the power switching transistor; after the on-time, measuring a reset time for the switching power converter; Calculating a delay period in response to a product of a sum of the on-time and the reset time and the proportionality constant and a subtraction of the sum of the on-time and the reset time from the product; Waiting for the delay period to expire after the reset time before beginning a second cycle of the power switching transistor. [9] The method of claim 8, wherein the on-time is constant for the first cycle of the power switching transistor and for the second cycle of the power switching transistor. [10] The method of claim 8 or 9, wherein generating the proportionality constant comprises generating an error signal in an error amplifier (400) in response to the error between the output voltage and the desired value for the output voltage. [11] The method of claim 10, wherein generating the proportionality constant further comprises: Filtering the error signal in a loop filter (405) to form a control voltage signal; and Mapping the control voltage signal into the proportionality constant. [12] The method of any one of claims 8 to 11, wherein measuring the reset time comprises measuring when an inductor current drops to zero after the on time.

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