TRANSCEIVER FRONT END WITH RECEIVER BRANCH ADAPTATION NETWORK INCLUDING INTEGRATED ELECTROSTATIC DISCHARGE PROTECTION
The transceiver front-end design with a switch and impedance matching network for FDSOI or FinFET technologies reduces noise figure by disconnecting low-noise amplifiers during transmission, addressing high noise figures in conventional designs and enhancing reliability and efficiency.
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- GLOBALFOUNDRIES US INC
- Filing Date
- 2020-08-19
- Publication Date
- 2026-06-18
AI Technical Summary
Conventional transceiver front-ends have high noise figures due to the combination of ESD protection structures and low-noise amplifiers, particularly in technologies optimized for fully depleted transistors, which is exacerbated in 5G mmWave transceivers.
A transceiver front-end design that includes a switch to disconnect the low-noise amplifier from the input/output pad during transmit mode, using series-connected n-type FDSOI or FinFET transistors, and a common impedance matching network for both impedance matching and ESD protection, eliminating switches between power amplifiers and the input/output pad.
This configuration reduces noise figure by minimizing signal degradation and power losses, ensuring reliable operation without requiring negative bias voltages in the off state, and providing effective ESD protection for low-noise amplifiers.
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Abstract
Description
Background / Area of the invention
[0001] The present invention relates to transceiver front ends and in particular to embodiments of a transceiver front end with a reduced noise figure (NF). Description of the state of the art
[0002] The person skilled in the art will recognize in particular that a transceiver is a device comprising both a transmitter and a receiver that share a common antenna or antenna arrangement. The front end of the transceiver refers to the circuitry within the transceiver from the antenna up to and including a power amplifier in the transmitter branch and also up to and including a low-noise amplifier in the receiver branch. In a conventional transceiver front-end architecture, the antenna is connected to an input / output pad, and a switch selectively connects either the transmitter branch or the receiver branch to the input / output pad and thus to the antenna. Typically, an electrostatic discharge (ESD) protection structure is located between the input / output pad and the switch (e.g., a protective layer).A shunt coil or other ESD protection structure is integrated to protect the switch and other components in the front end. An impedance matching network is typically integrated into the receiver branch between the switch and the low-noise amplifier. The estimated noise figure (LF) for a transceiver front end configured in this way can be relatively high due to the ESD protection structure and the switch in combination with the low-noise amplifier. Therefore, there is a need in the field for an improved transceiver front end configured to exhibit a reduced LF.
[0003] Document US 2009 / 0115549A1 shows an input circuit of the wireless transceiver, consisting of an antenna unit comprising an antenna and a first impedance matching circuit, a receiver connected to the antenna unit, and a transmit block connected to the antenna unit and the receiver, comprising a transmitter and a first switch, wherein the receiver and the transmit block are integrated in a single chip.
[0004] Document US 2016 / 0197643A1 describes a high-frequency module consisting of a first transmit / receive circuit that transmits and receives a first communication signal in a first frequency band, a second transmit / receive circuit that transmits and receives a second communication signal in a second frequency band that differs from the first frequency band, a common terminal to be connected to an antenna commonly used for the first and second communication signals, a connection point where the first transmit / receive circuit, the second transmit / receive circuit, and the common terminal are connected, and a phaser circuit comprising a circuit element connected to the connection point and the first transmit / receive circuit that performs phase matching to align the second side of the transmit / receive circuit, as seen from the connection point,The phase circuit is designed to keep the first frequency band open at a high frequency and to keep the first side of the transmit / receive circuit, as viewed from the connection point, open at a high frequency in the second frequency band. The phase circuit includes a band-cutting filter connected between the connection point and the first transmit / receive circuit. The band-cutting filter has an attenuation band containing a harmonic of a specific frequency band within the first frequency band, as well as passbands on the high-frequency and low-frequency sides at the outer edges of the attenuation band. The first frequency band is located within the passband on the low-frequency side.
[0005] According to document CN 1 09 004 925 A, an electronic circuit for an antenna is known, the electronic circuit comprising: a first amplifier coupled to the antenna via a first path, a second amplifier coupled to the antenna via a second path, a first transistor coupled to the first path at a first node, the first transistor having a back gate, and a bias circuit for the back gate coupled to the back gate of the first transistor, the bias circuit being configured to supply a bias voltage to the back gate of the first transistor, thereby reducing the first threshold voltage of the transistor.
[0006] Document US 2015 / 0070096A1 describes a power amplifier consisting of a semiconductor substrate, an input node, amplifying transistors arranged on the semiconductor substrate that amplify a signal from the input node and output an amplified signal to an output node, a bias circuit that applies a bias voltage to the signal input of the amplifying transistors, a filter circuit comprising at least one chip inductor and one chip capacitor that removes noise from the signal input of the amplifying transistors, and an impedance matching circuit comprising an impedance matching resistor, the impedance matching resistor being arranged on the semiconductor substrate between the input node and the signal input of the amplifying transistors.
[0007] Document US 6,356,536 B1 discloses a front-end circuit for a radio transceiver comprising a receiver, a transmitter, and an antenna, wherein this front-end circuit includes a common signal path connected to the antenna and shared by the transmitter and receiver of the radio transceiver, an RF transmit / receive (T / R) switch for alternately coupling the transmitter and receiver to the common signal path, wherein the T / R switch has a first state that couples the transmitter to the common signal path and a second state that couples the receiver to the common signal path via a receive signal path, and a shunt switch connected between the receive signal path and an electrical ground, wherein the shunt switch is distinct from the T / R switch and is located on the receive signal path downstream of the T / R switch, and wherein the shunt switch has a first shunt state.The shunt switch has two states: one that couples the receive signal path to ground, and a second that does not couple the receive signal path to ground. The shunt switch is switched to the first shunt state during transmit operation and to the second shunt state during receive operation.
[0008] Document US 10 116 347 B1 discloses an integrated front-end module (FEM) comprising at least one power amplifier (PA) coupled to an antenna, without the FEM including a switching element in a transmit signal path between an output of the PA and the antenna, at least one shunt transistor connected to an input of the at least one PA, at least one first low-noise amplifier (LNA), and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the first LNA, wherein the switching circuit is configured in a first mode to activate the at least one shunt transistor, thereby deactivating the PA and connecting the input of the first LNA to the antenna to receive signals from the antenna, and wherein the switching circuit is configured in a second mode toto disconnect the input of the first LNA from the antenna and to deactivate at least one shunt transistor, thereby activating the PA to send signals to the antenna.
[0009] Document US 2019 / 0371891A1 describes a high-frequency integrated circuit switch comprising a semiconductor chip containing a transistor having a gate on the front face of the semiconductor chip, a first deep trench isolation region extending from the front face to the back face of the semiconductor chip opposite the front face, a body contact layer on the back face of the semiconductor chip connected to the back face of the transistor body, the body comprising a first P-type region and the body contact layer having a conductive material over the entire length of the back face of the semiconductor chip, and a back face dielectric layer on a surface of the body contact layer opposite the transistor body. Summary
[0010] In view of the above, embodiments of a transceiver front end according to independent claim 1, wherein advantageous embodiments are defined in dependent claims 2 and 3, or according to independent claim 4, wherein advantageous embodiments are defined in dependent claims 5 to 7, are provided here.
[0011] More specifically, these are generally embodiments of a transceiver front-end that can operate in both transmit and receive modes and is configured for reduced noise (LF). The transceiver front-end can include an antenna, a transmit branch, and a receive branch, all connected to an input / output pad. The transmit branch can include a power amplifier and an impedance transformer. In transmit mode, the power amplifier can generate output signals. The impedance transformer can couple the power amplifier to the input / output pad so that the antenna can carry the output signals. The receive branch can include a low-noise amplifier, a switch, and a matching network. The switch can alternatively disconnect the low-noise amplifier from the input / output pad or connect the low-noise amplifier to the input / output pad.When the low-noise amplifier is disconnected from the input / output pad by the switch, the transceiver front end operates in transmit mode, where the switch protects the low-noise amplifier from the output signals from the power amplifier. When the low-noise amplifier is connected to the input / output pad by the switch, the transceiver front end operates in receive mode, where the switch allows input signals received from the antenna to be amplified by the low-noise amplifier. The matching network can be operationally connected to both the switch and the low-noise amplifier to provide impedance matching and electrostatic discharge protection for both the switch and the low-noise amplifier.
[0012] A special embodiment of the transceiver front-end described here is designed for integration into FDSOI technologies. This transceiver front-end can include an antenna, a transmitter branch, and a receiver branch, all connected to an input / output pad. The transmitter branch can include a power amplifier and an impedance transformer. In transmitter mode, the power amplifier can generate output signals. The impedance transformer can couple the power amplifier to the input / output pad so that the antenna can transmit the output signals. The receiver branch can include a low-noise amplifier, a switch, and a matching network. In this case, the switch can specifically include several series-connected n-type FDSOI transistors.This means the switch can include several series-connected, fully depleted n-type field-effect transistors on a relatively thin buried insulating layer over a semiconductor substrate. The switch can alternatively disconnect the low-noise amplifier from the input / output pad or connect the low-noise amplifier to the input / output pad. When the low-noise amplifier is disconnected from the input / output pad by the switch, the transceiver front end operates in transmit mode, in which the switch protects the low-noise amplifier from the output signals sent by the transmit branch. When the low-noise amplifier is connected to the input / output pad by the switch, the transceiver front end operates in receive mode, in which the switch allows input signals received from the antenna to be amplified by the low-noise amplifier.The matching network can be operationally connected to both the switch and the low-noise amplifier to provide both impedance matching and protection against electrostatic discharge for the switch and the low-noise amplifier.
[0013] Another special embodiment of the transceiver front-end presented here is designed for integration into FinFET technologies. This transceiver front-end can include an antenna, a transmitter branch, and a receiver branch, all connected to an input / output pad. The transmitter branch can include a power amplifier and an impedance transformer. In transmitter mode, the power amplifier can generate output signals. The impedance transformer can couple the power amplifier to the input / output pad so that the antenna can transmit the output signals. The receiver branch can include a low-noise amplifier, a switch, and a matching network. In this case, the switch can specifically include several n-type fin field-effect transistors (FinFETs) connected in series (e.g., on a semiconductor bulk substrate).The switch can either disconnect the low-noise amplifier from the input / output pad or connect the low-noise amplifier to the input / output pad. When the low-noise amplifier is disconnected from the input / output pad by the switch, the transceiver front end operates in transmit mode, in which the switch protects the low-noise amplifier from the output signals of the transmit branch. When the low-noise amplifier is connected to the input / output pad by the switch, the transceiver front end operates in receive mode, in which the switch allows input signals received from the antenna to be amplified by the low-noise amplifier. The matching network can be connected to both the switch and the low-noise amplifier to provide impedance matching and electrostatic discharge protection for both the switch and the low-noise amplifier. Brief description of some views in the drawings
[0014] The present invention is better understood with reference to the following detailed description and the drawings, which are not necessarily drawn to scale and in which: Fig. 1 is a schematic drawing representing a conventional transceiver front end; Fig. 2 is a schematic drawing that generally represents embodiments of a transceiver front end; Fig. 3A is a schematic drawing that represents an embodiment of a transceiver front-end, and which Fig. 3B and Fig. 3C cross-sectional views are shown, representing an exemplary switch and an exemplary shunt device that are installed in the transceiver front end of Fig. 3A could be installed; and Fig. 4A is a schematic drawing showing one embodiment of a transceiver front-end, and the Fig. 4B and Fig. 4C cross-sectional views are shown, respectively, representing an exemplary switch and an exemplary shunt device installed in the transceiver front end of Fig. 4A could be installed. Detailed description
[0015] As mentioned above, a transceiver is a device comprising both a transmitter and a receiver that share a common antenna or antenna array. The front end of the transceiver refers to the circuitry within the transceiver from the antenna up to and including a power amplifier in the transmitter branch and also up to and including a low-noise amplifier in the receiver branch.
[0016] Fig. Figure 1 is a schematic drawing depicting a conventional architecture for a transceiver front end 100. This transceiver front end 100 comprises an antenna 150, a transmitter branch 101 with a power amplifier 110, and a receiver branch 102 with a low-noise amplifier 120. The antenna 150 is electrically connected to an input / output pad 151. A switch 180 selectively and alternately connects either the transmitter branch 101 or the receiver branch 102 electrically to the input / output pad 151 and thus to the antenna 150. An ESD protection structure 155 (e.g., a shunt coil or other ESD protection structure) is integrated into the transceiver front end 100 between the input / output pad 151 and the switch 180 to protect the switch 180 and other components in the front end. An impedance matching network 130 is typically integrated into the receiver branch 102 between the switch 180 and the low-noise amplifier 120.
[0017] The person skilled in the art will recognize that the noise figure (NF) of a receiver refers to the difference in decibels (dB) between the noise output of an actual receiver and the noise output of an "ideal" receiver with the same overall gain and bandwidth when the receivers are connected to matched sources at the standard noise temperature. In other words, the NF represents a measure of signal-to-noise degradation. For optimal receiver performance, the receiver's gain stages should exhibit low NF values. Unfortunately, due to the ESD protection structure and the switch, in combination with the low-noise amplifier, the estimated noise figure (NF) for receiver branch 102 in a transceiver front end, as described above and in Fig. The ESD self-protection (ESD) level, as shown in Figure 1, can be relatively high. This is particularly noteworthy for technology nodes optimized for the formation of fully depleted transistors. With partially depleted transistors, at least some ESD self-protection can be implemented via their shunt branch. Fully depleted transistors (e.g., fully depleted fin-type field-effect transistors (FD-FinFETs) or fully depleted silicon-on-insulator field-effect transistors (FDSOI-FETs)) do not have a shunt branch. In this case, the estimated noise figure (NF) for a 5G mmWave transceiver (e.g., a 30GHz transceiver) can be approximately 3.8 dB (including 2 dB for the ESD structure and switch, and 1.8 dB for the low-noise amplifier).
[0018] In light of the above, embodiments of a transceiver front end configured for a reduced noise figure (LF) are described here. Generally, each embodiment described here includes an antenna, a transmit branch, and a receive branch, all connected to an input / output pad. The transmit branch is coupled to the input / output pad (and thus to the antenna) via an impedance transformer. Only the receive branch is selectively electrically connected to the input / output pad (and thus to the antenna) via a switch. A common matching network upstream of the switch provides both impedance matching and protection against electrostatic discharge for the switch and the low-noise amplifier, thereby reducing the LF. Special embodiments for integration into specific technologies (e.g.,Completely depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies are described. In each case, the transceiver's front-end configuration has the additional advantages that the switch is located away from the transmitter branch (thus avoiding power losses in the output signals) and that no negative bias voltage is required on the switch in the off state (i.e., when the transceiver is in transmitter mode).
[0019] More precisely Fig. 2 a schematic representation which generally depicts embodiments of a transceiver front end 200 with reduced NF. Fig. 3A is a schematic representation that depicts a special embodiment of a reduced LF transceiver front end 300 and includes specific features that enable integration into fully depleted silicon-on-insulator (FDSOI) technologies. Fig. Figure 4A is a schematic representation illustrating another special embodiment of a Transceiver Front End 400 configured to have a reduced LF and specific features that enable integration into Fin Field Effect Transistor (FinFET) technologies.
[0020] The transceiver front end 200, 300, 400 can include: an antenna 250, 350, 450; a transmitter branch 201, 301, 401; and a receiver branch 202, 302, 402.
[0021] The antenna 250, 350, 450 can be a single antenna. Alternatively, the antenna 250, 350, 450 can represent an antenna array functioning as a single antenna. Such antennas are well known in the art, and their details have therefore been omitted from this description to allow the reader to focus on the essential aspects of the described embodiments. As already mentioned, a transceiver is a device comprising both a transmitter and a receiver that share a common antenna or antenna array. The transceiver front end refers to the circuitry within a transceiver from the antenna up to and including a power amplifier in the transmitter branch, and also up to and including a low-noise amplifier in the receiver branch.The transmit branch refers to the section of the transceiver front end that is part of the transmitter, and the receive branch refers to the section of the transceiver front end that is part of the receiver. In each case, the antennas 250, 350, 450, the transmit branch 201, 301, 401, and the receive branch 202, 302, 402 can all be connected to an input / output pad 251, 351, 451.
[0022] The transmitter branch 201, 301, 401 can include a power amplifier 210, 310, 410 and an impedance transformer 211, 311, 411, which couples the power amplifier 210, 310, 410 to the input / output pad 251, 351, 451 and thus to the antenna 250, 350, 450. In transmitter mode, the power amplifier 210, 310, 410 can generate high-power RF signals from low-power RF output signals (i.e., it can be adapted, configured, etc., to generate them). In exemplary embodiments, the high-power RF output signals can be millimeter wave (mmWave) RF output signals (i.e., between 24 GHz and 100 GHz, e.g., at 30 GHz) for 5G applications. Alternatively, the high-power RF output signals can also be RF signals in any other part of the radio spectrum.In exemplary embodiments, the power amplifier 210, 310, 410 can exhibit a swing of the output voltage with a peak between 2.0 and 5 volts (e.g. at 2.5V, at 3V, at 3.5V, at 4V, etc.).
[0023] The impedance transformer 211, 311, 411 can comprise a pair of inductors arranged back-to-back (in particular, a primary winding 214, 314, 414 and a secondary winding 212, 312, 412). In transmitter mode, the power amplifier 210, 310, 410 can apply the generated output signals to the primary winding 214, 314, 414. Due to inductive coupling, the corresponding output signals appear at the secondary winding 212, 312, 412 and are transferred to the input / output pad 251, 351, 451 for subsequent transmission by the antenna 250, 350, 450. Depending on the turns ratio between the two windings, the impedance transformer 211, 311, 411 provides a required impedance matching between the output of the power amplifier 210, 310, 410 and the input of the antenna 250, 350, 450.
[0024] It should be noted that, as shown, there is no switch between the power amplifiers 210, 310, 410 and the input / output pad 251, 351, 451 in the transmitter branch 201, 301, 401. That is, only the impedance transformer 211, 311, 411 is connected in series between the power amplifiers 210, 310, 410. By eliminating a switch between the power amplifiers 210, 310, 410, the signal degradation between the power amplifiers 210, 310, 410 and the antenna 250, 350, 450 is minimized.
[0025] The receiver branch 202, 302, 402 comprises: a switch 280, 380, 480; a low-noise amplifier 220, 320, 420; a common impedance matching network 230, 330, 430; several bias resistors 271 and 272, 371, 471-472; and optionally a shunt device 260, 360, 460.
[0026] Switch 280, 380, 480 includes an input terminal 285, 385, 485 and an output terminal 286, 386, 486. Switch 280, 380, 480 can be configured (i.e., adapted) to selectively and alternately disconnect the low-noise amplifier 220, 320, 420 from the input / output pad 251, 351, 451, or connect the low-noise amplifier 220, 320, 420 to the input / output pad 251, 351, 451. When the low-noise amplifier 220, 320, 420 is disconnected from the input / output pad 251, 351, 451 by the switch 280, 380, 480, the transceiver front end operates in transmitter mode, in which the switch 280, 380, 480 protects the low-noise amplifier 220, 320, 420 from the output signals sent through the transmitter branch.When the low-noise amplifier 220, 320, 420 is connected to the input / output pad 251, 351, 451 via the switch 280, 380, 480, the transceiver front end operates in receiver mode, in which the switch 280, 380, 480 allows input signals received from the antenna to be amplified by the low-noise amplifier 220, 320, 420.
[0027] In particular, the switch 280, 380, 480 can selectively switch off and, in particular, respond to a control signal to selectively disconnect the low-noise amplifier 220, 320, 420 from the input / output pad 251, 351, 451 when the transceiver front end is operating in transmit mode. By disconnecting the low-noise amplifier 220, 320, 420 from the input / output console 251, 351, 451 in transmit mode, the switch 280, 380, 480 prevents high power and, in particular, high voltage output signals that can pass from the transmit branch 201, 301, 401 into the receiver branch 202, 302, 402 from ever reaching and damaging the low-noise amplifier 220, 320, 420. The switch 280, 380, 480 can also connect selectively and, in particular, respond to the switching of the control signal to selectively connect the low-noise amplifier 220, 320, 420 to the input / output pad 251, 351, 451 when the transceiver front end is operating in receiver mode.By connecting the input / output pad 251, 351, 451 to the low-noise amplifier 220, 320, 420 in receiver mode, the switch 280, 380, 480 enables the processing of input signals received by the antenna 250, 350, 450 in receiver mode by the low-noise amplifier 220, 320, 420.
[0028] In exemplary embodiments, the switch 280, 380, 480 can comprise several stacked n-type field-effect transistors (NFETs) or, in particular, several NFETs connected in series, wherein the gates of all NFETs are connected to the same node and respond to a control signal (i.e., an applied gate voltage) at that node to either turn on (e.g., in response to a relatively high applied gate voltage) or turn off (e.g., in response to a low applied gate voltage, such as a discharge to ground). It should be noted that the specific characteristics of such a switch may vary depending on the technologies used (see the detailed explanations below for switch 380 in receiver branch 302 of the transceiver front end 300; see also the detailed explanations below for switch 480 in receiver branch 402 of the transceiver front end 400).
[0029] Alternatively, any other suitable switch configuration could be used. However, it should be noted that, regardless of the type of switch and its characteristics, the switch 280, 380, 480 should be configured so that it does not fail (e.g., does not switch from an off state to an on state) when exposed to the high-voltage output signals of the power amplifier 210, 310, 410 in transmit mode. In the exemplary embodiments where the switch includes stacked NFETs, for example, the sum of all maximum drain-source voltages (VDS) in the switch should be greater than the maximum output voltage of the power amplifier to ensure reliable operation of all NFETs and prevent switch failure in transmit mode.If, in one example, the power amplifier 210, 310, 410 has a maximum output voltage of 2 volts and the NFETs each have a maximum VDS of 1.6 volts, then the switch ideally comprises at least two stacked NFETs that should be able to apply 2 times 1.6 volts (i.e., 3.2 volts, which is greater than the maximum output voltage of the power amplifier of 2V) to its input terminal in transmitter mode without the switch failing. If, in another example, the power amplifier 210, 310, 410 has a maximum output voltage of 3-4 volts and the NFETs each have a maximum VDS of 1.6 volts, then the switch ideally comprises at least three stacked NFETs that should be able to apply three times 1.6 volts (i.e.,4.8 volts, which is greater than the maximum output voltage of the power amplifier (3-4V), applied to its input terminal in transmitter mode, to process without failure, etc.
[0030] The low-noise amplifier 220, 320, 420 of the receiver branch 202, 302, 402 can, in receiver mode, receive weak (i.e., low-power) RF input signals via the switch 280, 380, 480 and amplify these RF input signals (i.e., it can be adapted, configured, etc., to amplify them) to increase the power without increasing the existing noise (i.e., without degrading the signal-to-noise ratio). Such low-noise amplifiers 220, 320, 420 are well known in the art, and therefore the details have been omitted from this description to allow the reader to focus on the outstanding aspects of the described embodiments. In transmitter mode, the low-noise amplifier 220, 320, 420 is switched off.
[0031] The common impedance matching network 230, 330, 430 of the receiver branch 202, 302, 402 can be operationally connected to both the switch 280, 380, 480 and the low-noise amplifier 220, 320, 420 to provide both impedance matching and protection against electrostatic discharge (ESD) for the switch 280, 380, 480 and the low-noise amplifier. In particular, the common impedance matching network 230, 330, 430 comprises at least one inductor and one capacitor 231, 331, 431, which are electrically connected in series between ground and an input terminal 285, 385, 485 of the switch 280, 380, 480.
[0032] The inductance of the common impedance matching network 230, 330, 430 can, as shown, be a discrete inductance 235, 335, 435 connected to the receiver branch 202, 302, 402 downstream of the input / output pad 251, 351, 451. Alternatively, the secondary winding 212, 312, 412 (i.e., the proximal inductor part) of the impedance transformer 211, 311, 411 within the transmitter branch 201, 301, 401 in receiver mode could also act as the inductance of the common matching network. A dual use of the secondary winding 212, 312, 412 is possible because there is no switch in the transmitter branch, and the secondary winding 212, 312, 412 is therefore an inductor connected directly in series between ground and the matching capacitor 231, 331, 431. In any case, the inductor of the common impedance matching network 230, 330, 430 can perform impedance matching to the low-noise amplifier 220, 320, 420.The inductor can also provide protection against electrostatic discharge (ESD) for the switch 280, 380, 480 and the low-noise amplifier 220, 320, 420.
[0033] The capacitor 231, 331, 431 of the common impedance matching network 230, 330, 430 can be connected in series between the inductor and the input terminal 285, 385, 485 of the switch 280, 380, 480, and can also be connected in series between the input / output pad 251, 351, 451 and the input terminal 285, 385, 485 of the switch 280, 380, 480. The capacitor 231, 331, 431 can provide capacitance matching for the switch 280, 380, 480. It should be noted that this capacitor 231, 331, 431 also supports the bias voltage of the input terminal 285, 385, 485 of the switch 280, 380, 480, thus making it unnecessary to apply a negative bias voltage to the gate terminal of the switch 280, 380, 480 in the off state in transmitter mode.
[0034] It should be noted that in some embodiments, the common impedance matching network may also include a second capacitor that is electrically connected to the output terminal of the switch. This is referred, for example, to the optional second capacitor 232 in the common impedance matching network 230 of the transceiver front end 200 in Fig. 2. It also refers to the second capacitor 432 in the common impedance matching network 430 of the transceiver front end 400 in Fig. 4A refers to which can be integrated into FDSOI technologies and which is described in more detail below.
[0035] As mentioned above, the receiver branch 202, 302, 402 also includes one or more bias resistors. In each of the embodiments described here, the receiver branch 202, 302, 402 includes at least one first bias resistor 271, 371, 471, which is electrically connected to the input terminal 285, 385, 485 of the switch 280, 380, 480, thus making it possible to apply different first bias voltages to the input terminal 285, 385, 485 of the switch 280, 380, 480 in transmitter mode and receiver mode, respectively. In some of the embodiments described here, the receiver branch may also include a second bias resistor. For example, the optional second bias resistor 272 in the receiver branch 202 of the [description of embodiment] is mentioned. Fig. Reference is made to the 2 transceiver front ends 200 shown. Reference is also made to the second bias resistor 472 in the receiver branch 402 of the [unclear text]. Fig. Reference is made to the transceiver front-end 400 shown in Figure 4A, which can be integrated into FDSOI technologies and is described in more detail below. Such a second bias resistor 272, 472 can be electrically connected to the input terminal 225, 425 of the low-noise amplifier 220, 420, making it possible to apply at least a second bias voltage to the input terminal of the low-noise amplifier in transmit and / or receive mode.
[0036] The shunt device 260, 360, 460 can be integrated into the receiver branch after the switch 280, 380, 480 and before the low-noise amplifier 220, 320, 420 (i.e., between the switch and the low-noise amplifier). The shunt device 260, 360, 460 can have an "on" state, which occurs whenever the transceiver front end 200, 300, 400 is in transmit mode, and an "off" state, which occurs whenever the transceiver front end 200, 300, 400 is in receive mode. The shunt device 260, 360, 460 can be configured to provide a low-resistance path for current flow when it is turned on in transmit mode.Therefore, if the switch 280, 380, 480, which should be in the off state in transmitter mode, allows current to pass through, the current is bypassed by the shunt device 260, 360, 460, thus bypassing the low-noise amplifier 220, 320, 420 and preventing damage to the low-noise amplifier. In particular, the shunt device 260, 360, 460 provides a low impedance for the large signal at the ESD input and thus eliminates the large swing at the LNA input. The LNAs are switched off by cascade components (not shown in the figure). The shunt device 260, 360, 460 can further be configured such that, when switched off in receiver mode, the current flowing through the switch is not interrupted, but can flow to the input terminal 225, 325, 425 of the low-noise amplifier 220, 320, 420 for processing. The shunt device 260, 360, 460 can, for example, be a single field-effect transistor.It should be noted that the specific characteristics of such a shunt device may vary depending on the technology used (see the detailed explanation below about the 360 shunt device in the 302 receiver branch of the 300 transceiver front end, see also the detailed explanation below about the 460 shunt device in the 402 receiver branch of the 400 transceiver front end).
[0037] As mentioned above, represents Fig. Figure 3A shows a schematic representation illustrating a special embodiment of a transceiver front end 300 configured to have a reduced NF and incorporating specific features that enable integration into fully depleted silicon-on-insulator (FDSOI) technologies. Fig. Figure 3B is a cross-sectional view showing an exemplary switch 380 that may be installed in this transceiver front end 300, and Fig. Figure 3C is a cross-sectional view illustrating an exemplary 360° shunt device that may be incorporated into the 300° transceiver front end.
[0038] In FDSOI technology, a silicon-on-insulator wafer is used with an ultrathin silicon layer (e.g., a silicon layer with a thickness of 25 nm or less, e.g., 22 nm, 12 nm, etc.) on top of a thin buried insulator layer (e.g., a thin buried oxide layer) over a semiconductor substrate. The ultrathin silicon layer is used to form fully depleted planar field-effect transistors. Optionally, well regions can be formed in the semiconductor substrate, aligned beneath the transistors, and these well regions can be contacted, thus forming substrate gates in combination with the buried insulator layer.
[0039] As explained above, the transceiver front end 300 can include an antenna 350, a transmitter branch 301 and a receiver branch 302, all connected to an input / output pad 351.
[0040] The transmitter branch 301 can include a power amplifier 310, which is connected via an impedance transformer 311 to the input / output pad 351 and thus to the antenna 350. In exemplary embodiments, the power amplifier 310 can exhibit a swing of the output voltage with a peak between 2.0 and 5 volts (e.g., at 2.5V, at 3V, at 3.5V, at 4V, etc.).
[0041] The receiver branch 302 may include: a low-noise amplifier 320, which can be connected to the input / output pad 351 via a switch 380; a common impedance matching network 330 with an inductor and a single capacitor 331 connected in series between ground and the input terminal 385 of the switch 380; a single bias resistor 371 connected to the input terminal 385 of the switch 380; and a shunt device 360 connected downstream of the switch 380 and upstream of the low-noise amplifier 320.
[0042] As mentioned above, the inductance of the common impedance matching network 330 can be a discrete inductor 335. Alternatively, the secondary winding 312 of the impedance transformer 311 can serve as the inductor for the common impedance matching network.
[0043] In this embodiment, the switch 380 can comprise planar, series-connected FDSOI-NFETs 381(a)-381(c) (as e.g. in Fig. 3B), which are configured to selectively disconnect the low-noise amplifier 320 from the input / output pad 351 in transmitter mode and to selectively connect the low-noise amplifier 320 to the input / output pad 351 in receiver mode. Each FDSOI NFET 381(a)-381(c) can comprise N+ source / drain regions 382 and a channel region 383 (e.g., an undoped channel region) located laterally between the N+ source / drain regions 382 within a thin semiconductor layer 393 (e.g., a thin silicon layer) above a buried insulator layer 392 (e.g., a buried oxide layer). Adjacent NFETs can share a source / drain region to provide a series connection. The NFETs 381(a)-381(c) can further comprise gate structures 384 (each with a dielectric gate layer and a gate conductor layer) on the top of the thin silicon layer 393 over the channel regions 383.These gate structures 384 can be electrically connected at a common gate node 387. To minimize parasitic capacitance, the FDSOI-NFETs 381(a)-381(c) of switch 380 can be BFMOAT-FDSOI-NFETs. That is, during the fabrication of FDSOI-NFETs, a doping implantation process is often performed to form one or more P-wells (i.e., regions doped with P+) in the semiconductor substrate, which are located beneath one or more FDSOI-FETs. Such P-wells can optionally be contacted and, in combination with the buried insulator layer, act as a substrate gate. However, the presence of a P-well can lead to an increase in parasitic capacitance. To avoid this parasitic capacitance, BFMOAT FDSOI-FETs can be formed.“BFMOAT” refers to a degree of masking performed during manufacturing to block the implantation of dopants, thus preventing the formation of a p-well in a desired region of the semiconductor substrate and making that region a high-resistance area. As shown in [reference]. Fig. 3B thus contains a high-resistance region 397 (i.e., a region without a P-well) within the semiconductor substrate 391, which is aligned under the FDSOI-NFETs 381(a)-381(c), and a P-well ring region 396 borders (in particular surrounds) the high-resistance region 397.
[0044] It should be noted that the switch 380 shown above is described for illustrative purposes as comprising three NFETs 381(a)-381(c) connected in series. However, it should be understood that the figures and the described exemplary embodiments are not to be considered limiting. Alternatively, any number of one or more BFMOAT-FDSOI NFETs could be used to form the switch 380, provided that the combined maximum VDS of all NFETs in the switch 380 is sufficient to ensure that the switch 380 does not fail in transmitter mode when the maximum output voltage of the power amplifier 310 is applied to the input terminal 385 of the switch 380. If, in an example, the power amplifier 310 has a maximum output voltage of 2 volts and the NFETs each have a maximum VDS of 1.6 volts, then the switch 380 ideally comprises at least two stacked NFETs that should be able to supply twice 1.6 volts (i.e.,3.2 volts, which is greater than the maximum output voltage of the power amplifier (2V), applied to its input terminal in transmitter mode without failure. In another example, if the power amplifier 310 has a maximum output voltage of 3-4 volts and the NFETs each have a maximum VDS of 1.6 volts, then the switch ideally has at least three stacked NFETs that should be able to handle three times 1.6 volts (i.e., 4.8 volts, which is greater than the maximum output voltage of the power amplifier (3-4V)) applied to its input terminal in transmitter mode without failure, and so on.
[0045] In this embodiment, the shunt device 360 can be a very low threshold voltage (SLVT) FDSOI PFET integrated into the receiver branch 302 after the switch 380 and before the low-noise amplifier 320. The PFET shunt device 360 can have an on state, which occurs whenever the transceiver front end 300 is in transmit mode, and an off state, which occurs whenever the transceiver front end 300 is in receive mode. As shown in Fig. 3C could comprise an exemplary PFET shunt device 360, which may be incorporated into the receiver branch 302, within a thin silicon layer 393 above a buried insulating layer 392 (e.g., a buried oxide layer), P+ source / drain regions 362, and a channel region 363 (e.g., an undoped channel region) located laterally between the P+ source / drain regions 362. The PFET shunt device 360 may include a gate structure 364 (including a dielectric gate layer and a gate conductor layer) on the top surface of the thin silicon layer 393 above the channel region 363 and may also include a P-well ring region 396 within the semiconductor substrate 391 and adjacent to (in particular surrounding) the high-resistance region 397. The P-tub ring area 396 can be contacted and can function as a substrate gate in combination with the buried insulator layer 392.
[0046] Such a 300-series transceiver front-end can be operated in transmitter mode and receiver mode as follows.
[0047] In transmitter mode, the power amplifier 310 in the transmitter branch 301 can be switched on and output high-power signals via the impedance transformer 311 to the input / output pad 351 and thus to the antenna 350. In transmitter mode, the NFETs 381(a)-381(c) of the switch 380 and the low-noise amplifier 320 in the receiver branch 302 can be switched off, and the PFET shunt device 360 can be switched on. This can be achieved by applying 0.0 V to the common gate node 387 for the switch 380 and to the front gate, and optionally to the rear gate, of the PFET shunt device 360. In transmitter mode, additional bias conditions in the receiver branch 302 can include applying a positive bias (VBIAS) (e.g. 0.8V) to the input terminal 385 of the switch 380 via the bias resistor 371 and applying the same first positive bias to the drain area of the PFET shunt device 360.As a result, the voltage level at input terminal 325 of the low-noise amplifier 320 will be 0.8V, but the low-noise amplifier can still be switched off using the cascade bias. It should be noted that the impedance transformer 311 in the transmitter branch 301 and the common impedance matching network 330 in the receiver branch 302 should be designed together with respect to the input impedance to the receiver branch (Zin_rx) in the intended transmitter mode. Additionally, it should be noted that the output voltage of the power amplifier 310 in transmitter mode is applied to the receiver branch 302 and, in particular, to the capacitor 331 of the common impedance matching network, where it is only slightly amplified (e.g., by about 10 percent) before reaching the input terminal 385 of the switch 380. At the output terminal 386, however, the swing is completely attenuated.
[0048] In receiver mode, the power amplifier 310 in the transmitter branch 301 is switched off (e.g., the power amplifier's supply voltage is grounded and the power amplifier's bias voltage is switched on). It should be noted that the impedance transformer 311 in the transmitter branch 301 and the common impedance matching network 330 in the receiver branch 302 should be designed together with respect to the input impedance of the transmitter branch (Zin_tx) in the intended receiver mode, and in particular, designed so that Zin_tx does not affect the receiver audio frequency (AF). Zin_tx can, for example, be connected in parallel to a larger resistor (e.g., a resistor of several hundred ohms) in the form of a large inductor (i.e., an inductor larger than the inductor 335) (not shown).In receiver mode, the NFETs 381(a)-381(c) of switch 380 and the low-noise amplifier 320 can be switched on in receiver branch 302, and the PFET shunt device 360 can be switched off. To switch on switch 380, a high gate voltage (VGG) can be applied to the common gate node 387 for switch 380. VGG can be equal to the optimal input voltage (VG0) for the low-noise amplifier plus the positive bias voltage (VBIAS) (e.g., 0.8 V) or a higher positive bias voltage (VBIAS+) (e.g., 1.0 V). Those skilled in the art will recognize that the optimal input voltage (VG0) for the low-noise amplifier can vary depending on the technology node. For FDSOI at 22 nm, this optimal input voltage could be, for example, 0.3-0.4 V. Thus, VGG could be equal to 1.2 V or higher. To switch off the PFET shunt device 360, a high positive supply voltage (VDD) can be applied to the front gate and optionally to the substrate gate.In receiver mode, additional bias conditions in the receiver branch 302 can include applying VDD to the drain region of the PFET shunt device 360 and applying a lower positive bias (VBIAS-) to the input terminal 385 of the switch 380 via the bias resistor 371. VBIAS- can be equal to the optimal input voltage (VG0) for the low-noise amplifier (see above). Note that the BFMOAT FDSOI NFETs do not provide a bias for a substrate gate due to the high-impedance region 397.
[0049] As already mentioned, Fig. 4A is a schematic representation of a special embodiment of a transceiver front end 400 with reduced LF and specific features that enable integration into bulk-type fin field-effect transistor (FinFET) technologies. Fig. Figure 4B is a cross-sectional view illustrating an exemplary switch 480 that can be fitted into this transceiver front end 400. Fig. Figure 4C is a cross-sectional view illustrating an exemplary shunt device 460 that can be installed in the transceiver front end 400.
[0050] It is evident to those skilled in the art that bulk FinFET technologies utilize a semiconductor bulk substrate (e.g., a silicon bulk substrate). One or more semiconductor fins (i.e., one or more elongated, relatively tall and thin, essentially rectangular semiconductor bodies) are structured in the upper part of the substrate. Within each semiconductor fin, a channel region is arranged laterally between source / drain regions. Adjacent to the upper surface and the opposite side walls of the semiconductor fin, a gate structure is located at the corresponding channel region. Such a FinFET represents a fully depleted structure exhibiting multidimensional field effects compared to the one-dimensional field effects of a planar FET, thus providing improved gate control via the channel region. Isolation from the lower part of the semiconductor substrate is provided by one or more doped well regions.Optionally, multiple semiconductor fins can be integrated into a single FinFET to increase operational reliability.
[0051] As explained above, the transceiver front end 400 can include an antenna 450, a transmitter branch 401 and a receiver branch 402, all connected to an input / output pad 451.
[0052] The transmitter branch 401 can include a power amplifier 410, which is connected via an impedance transformer 411 to the input / output pad 451 and thus to the antenna 450. In exemplary embodiments, the power amplifier 410 can exhibit a swing of the output voltage with a peak between 2.0 and 5 volts (e.g., at 2.5V, at 3V, at 3.5V, at 4V, etc.).
[0053] The receiver branch 402 may include: a low-noise amplifier 420, which may be connected to the input / output pad 451 via a switch 480; a common impedance matching network 330 with an inductor and a first capacitor 431 connected in series between ground and the input terminal 485 of the switch 480, and with a second capacitor 432 connected to the output terminal 486 of the switch 480; a first bias resistor 471 connected to the input terminal 485 of the switch 480, and a second bias resistor 472 connected to the input terminal 425 of the low-noise amplifier 420; and a shunt device 460 connected downstream of the switch 480 and upstream of the low-noise amplifier 420.
[0054] As mentioned above, the inductance of the common impedance matching network 430 can be a discrete inductor 435. Alternatively, the secondary winding 412 of the impedance transformer 411 can serve a dual function as the inductor for the common impedance matching network. It should be noted that the second capacitor 432 is required to provide isolation between the output terminal 486 of the switch 480 and the second bias resistor 472.
[0055] In this embodiment, the switch 480 can comprise N-type FinFETs 481(a)-481(c) connected in series (e.g. as in Fig. 4B), which are configured to selectively disconnect the low-noise amplifier 420 from the input / output pad 451 in transmitter mode and to selectively connect the low-noise amplifier 420 to the input / output pad 451 in receiver mode. The NFETs 481(a)-481(c) can, for example, be configured as a semiconductor fin 499 structured in the upper portion of a p-type semiconductor substrate 491. The semiconductor fin 499 can comprise N+ source / drain regions 482 and a p-channel region 483 for each NFET, arranged laterally between the N+ source / drain regions 482. Adjacent NFETs can, as illustrated, share a source / drain region to provide a series connection. The NFETs 481(a)-481(c) can further comprise gate structures 484 (each with a dielectric gate layer and a gate conductor layer) on the top and opposite side walls of the semiconductor fin 499 next to the channel regions 483.It should be noted that multiple semiconductor fins may be incorporated into the NFETs of the switch to improve operational reliability. In any case, these gate structures 484 may be electrically connected at a common gate node 487. The NFETs 481(a)-481(c) may be triple-well NFETs. That is, a P-well 493 may be located in the P-semiconductor substrate 491 below the NFETs, and an N-well 492 may be located in the P-semiconductor substrate 491 between the P-well 493 and a P-region (located between the N-well 492 and the bottom surface of the substrate 491).
[0056] For illustration, it should be noted that the switch 480 is described above as comprising three NFETs 481(a)-481(c) connected in series. However, it should be understood that the figures and the exemplary embodiments described are not intended to be limiting. Alternatively, any number of one or more triple-dish N-FinFETs could be used to form the switch 480, provided that the combined maximum VDS of all NFETs in the switch 480 is sufficient to ensure that the switch 480 does not fail in the off state in transmitter mode when the maximum output voltage of the power amplifier 410 is applied to the input terminal 485 of the switch 480.If, in one example, the power amplifier 410 has a maximum output voltage of 2 volts and the NFETs each have a maximum VDS of 1.6 volts, then the switch 480 ideally has at least two stacked NFETs that should be able to handle 2 times 1.6 volts (i.e., 3.2 volts, which is greater than the maximum output voltage of the power amplifier of 2V) at its input terminal in transmitter mode without failure. If, in another example, the power amplifier 410 has a maximum output voltage of 3-4 volts and the NFETs each have a maximum VDS of 1.6 volts, then the switch 480 ideally has at least three stacked NFETs that should be able to handle three times 1.6 volts (i.e., 4.8 volts, which is greater than the maximum output voltage of the power amplifier of 3-4V) applied to its input terminal in transmitter mode without failure, and so on.
[0057] In this embodiment, the shunt device 460 can be an N-type FinFET integrated into the receiver branch 402 after the switch 480, the second capacitor 432, and the second bias resistor 472, and before the low-noise amplifier 420. This NFET shunt device 460 can have an on state, which occurs whenever the transceiver front end 400 is in transmit mode, and an off state, which occurs whenever the transceiver front end 400 is in receive mode. As shown in Fig.4C can include an exemplary PFET shunt device 460, which can be incorporated into the receiver branch 402, within a semiconductor fin 498 (e.g., a silicon fin) structured in the upper section of a p-type semiconductor substrate, comprising N+ source / drain regions 462 and a p-channel region 463 arranged laterally between the N+ source / drain regions 462. The PFET shunt device 460 can further include a gate structure 464 (including a dielectric gate layer and a gate conductor layer) adjacent to the upper surface and on opposite sides of the semiconductor fin 498 in the channel region 463. It should be noted that multiple semiconductor fins can be integrated into the PFET of the shunt device 460 to improve its operational robustness.
[0058] Such a 400-series transceiver front-end can be operated in transmitter mode and receiver mode as follows.
[0059] In transmitter mode, the power amplifier 410 in the transmitter branch 401 can be switched on and output high-power signals via the impedance transformer 411 to the input / output pad 451 and thus to the antenna 450. In transmitter mode, the NFETs 481(a)-481(c) of the switch 480 and the low-noise amplifier 420 in the receiver branch 402 can be switched off, and the NFET shunt device 460 can be switched on. This can be achieved by applying 0.0 V to the common gate node 487 for the switch 480 and an initial positive bias voltage (e.g., 0.8 V) to the gate of the NFET shunt device 460. Switching on the NFET shunt device 460 pulls the voltage level at the input terminal of the low-noise amplifier 420 down and switches it off completely. In transmitter mode, additional bias conditions in receiver branch 402 can apply the first positive bias (VBIAS1) (e.g.The operation includes applying 0.8V to the input terminal 485 of the switch 480 via the first bias resistor 471 and applying 0.0V to the input terminal 425 of the low-noise amplifier 420 via the second bias resistor 472. It should be noted that the impedance transformer 411 in the transmitter branch 401 and the common impedance matching network 430 in the receiver branch 402 should be designed with the same input impedance to the receiver branch (Zin_rx) in the intended transmitter mode. Additionally, it should be noted that the output voltage of the power amplifier 410 in transmitter mode is applied to the receiver branch 402, and in particular to the first capacitor 431 of the common impedance matching network 430, where it is amplified only slightly (e.g., by about 10 percent) before reaching the input terminal 485 of the switch 480. However, the swing is completely damped at output terminal 486.
[0060] In receiver mode, the power amplifier 410 in the transmitter branch 401 is switched off (e.g., the power amplifier's supply voltage is grounded and the power amplifier's bias voltage is switched on). It should be noted that the impedance transformer 411 in the transmitter branch 401 and the common impedance matching network 430 in the receiver branch 402 must also be designed with respect to the input impedance to the transmitter branch (Zin_tx) during receiver mode, and in particular, designed so that Zin_tx does not affect the receiver audio frequency (AF). Zin_tx can, for example, be connected in parallel to a larger resistor (e.g., a resistor of several hundred ohms) in the form of a large inductor (i.e., an inductor larger than the inductor 435) (not shown).
[0061] In receiver mode, the NFETs 481(a)-481(c) of switch 480 and low-noise amplifier 420 in receiver branch 402 can be switched on, and the NFET shunt device 460 can be switched off. To switch on switch 480, a high gate voltage (VGG) can be applied to the common gate node 487 for switch 480. VGG can be equal to a slightly higher positive bias voltage (VBIAS+) (e.g., 1.0 V or more). VGG can, for example, be equal to the optimal input voltage (VG0) (e.g., 0.3–0.4 V) for the low-noise amplifier plus the positive bias voltage (VBIAS) (e.g., 0.8 V). That is, VGG could be equal to 1.2 V or higher. To switch off the NFET shunt device 460, the gate is discharged to ground. In receiver mode, additional bias conditions can be applied in receiver branch 402, e.g., for the 20dBm power input, by applying the positive bias voltage (VBIAS) (e.g.The switching operation may include applying a 0.8V voltage to the input terminal 485 of switch 480 via the first bias resistor 471, applying a zero voltage (VPW) to the P-socket 493 below NFETs 481(a)-481(c) (e.g., discharging the P-socket 493 to ground), and applying a significantly higher positive voltage (VNW, e.g., 2.5V) to the N-socket 492, which is located below the P-socket and above the P-substrate 491. Additionally, a lower positive bias voltage (VBIAS-) may be applied to the input terminal 425 of the low-noise amplifier 420 via the second bias resistor 472. VBIAS- may be equal to the optimal input voltage (VG0) for the low-noise amplifier (see above).
[0062] Therefore, the embodiments of a transceiver front end configured for reduced audio frequency (AF) are described above. Generally, each embodiment includes an antenna, a transmit branch, and a receive branch, all connected to an input / output pad. The transmit branch is coupled to the input / output pad (and thus to the antenna) via an impedance transformer. Only the receive branch is selectively electrically connected to the input / output pad (and thus to the antenna) via a switch. A common matching network upstream of the switch provides both impedance matching and electrostatic discharge protection for the switch and the low-noise amplifier, thereby reducing the AF. Special embodiments for integration into various technologies are also described (e.g., fully depleted silicon-on-insulator (FDSOI) and field-effect transistor (FinFET) technologies).In any case, the front-end configuration of the transceiver has the additional advantages that the switch is located away from the transmitter branch (thus avoiding power losses of the output signals) and that no negative bias voltage is required on the switch in the off state (i.e. when the transceiver is in transmitter mode).
[0063] It is important to understand that, in the structures described above, a semiconductor material refers to a material whose conductivity can be modified by doping with an impurity. Examples of semiconductor materials include silicon-based semiconductors (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and gallium nitride-based semiconductors. A pure semiconductor material, and especially one that is not doped with an impurity to increase conductivity (i.e., an undoped semiconductor), is referred to in technical terms as an intrinsic semiconductor. A semiconductor material that is doped with an impurity to increase conductivity (i.e., a doped semiconductor) is referred to in technical terms as an extrinsic semiconductor and is more conductive than an intrinsic semiconductor made from the same base material.This means that extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. Furthermore, it is important to understand that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and that the dopants can vary depending on the specific semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, while a silicon-based semiconductor material is typically doped with a group V dopant, such as arsenic (As), phosphorus (P), or antimony (Sb), to achieve N-type conductivity.A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve p-type conductivity or with silicon (Si) to achieve n-type conductivity. The person skilled in the art will also recognize that different conductivity levels depend on the relative concentration levels of the dopant(s) in a given semiconductor region.
[0064] Furthermore, it should be understood that the terminology used here serves to describe the structures and procedures described and is not intended as a limitation. For example, the singular forms "ein, eine, einer" and "der, die, das" used here are also intended to include the plural forms unless the context clearly indicates otherwise. Additionally, as used here, the terms "umfasst," "umfassend," "einschlusst," and / or "einschlussd" specify that the given features, integers, steps, operations, elements, and / or components are present, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.Furthermore, relative terms such as "right," "left," "vertical," "horizontal," "above," "below," "below," "underneath," "below," "over," "above," "parallel," "perpendicular," etc., are intended to describe arrangements as they are oriented and represented with respect to the drawings (unless otherwise specified). Terms such as "touching," "in direct contact," "affecting," "directly adjacent," "immediately adjoining," etc., are intended to indicate that at least one element physically touches another element (without other elements separating the described elements). The term "lateral" is used here to describe the relative positions of the elements and, in particular, to indicate that one element is positioned laterally to another element and not above or below the other element, as these elements are oriented and represented in the drawings. For example,An element positioned laterally next to another element will lie next to the other element; an element positioned laterally immediately next to another element will lie directly next to the other element; and an element that laterally surrounds another element will abut and define the outer side walls of the other element. The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims shall comprise any structure, material, or action for fulfilling the function in combination with other claimed elements, as specifically claimed.
Claims
[1] Transceiver front end (200; 300; 400), comprising: an antenna (250; 350; 450); a transmitter branch (201; 301; 401) and a receiver branch (202; 302; 402), wherein the antenna (250; 350; 450), the transmitter branch (201; 301; 401) and the receiver branch (202; 302; 402) are connected to an input / output pad (251; 351; 451), wherein the transceiver front end (200; 300; 400) is operable in a transmitter mode and a receiver mode, and wherein the receiver branch (202; 302; 402) comprises: a low-noise amplifier (220; 320; 420); a switch (280; 380; 480), wherein the switch (280; 380; 480) alternately disconnects the low-noise amplifier (220; 320; 420) from the input / output pad (251; 351; 451) and connects the low-noise amplifier (220; 320; 420) to the input / output pad (251; 351; 451), wherein the transceiver front end (200; 300; 400) is operated in transmitter mode when the low-noise amplifier (220; 320; 420) is disconnected from the input / output pad (251; 351; 451) by the switch (280; 380; 480), wherein the transceiver front end (200; 300; 400) is operated in receiver mode when the low-noise amplifier (220; 320; 420) is connected to the input / output pad (251; 351; 451) via the switch (280; 380; 480), and wherein the low-noise amplifier (220; 320; 420) amplifies the input signals received from the antenna (250; 350; 450) when the transceiver front-end (200; 300; 400) is in receiver mode, and an matching network (230; 330; 430) that is operationally connected to the switch (280; 380; 480) and the low-noise amplifier (220; 320; 420), wherein the matching network (230; 330; 430) provides both impedance matching and protection against electrostatic discharge for the switch (280; 380; 480) and the low-noise amplifier (220; 320; 420), wherein the matching network (230; 330; 430) comprises an inductor (235; 335; 435) and a first capacitor (231; 331; 431) electrically connected in series between ground and an input terminal (285; 385; 485) of the switch (280; 380; 480), and further comprises a second capacitor (232; 432) electrically connected between an output terminal (286; 386; 486) of the switch (280; 380; 480) and the second bias resistor (272, 472). wherein the receiver branch (202; 302; 402) further comprises a bias resistor (271; 371; 471) which is electrically connected to an input terminal (285; 385; 485) of the switch (280; 380; 480), enabling different bias voltages to be applied to the input terminal (285; 385; 485) of the switch (280; 380; 480) accordingly in transmitter mode and receiver mode, and wherein the receiver branch (202; 302; 402) further comprises a second bias resistor (272; 472) which is electrically connected to an input terminal (225; 325; 425) of the low-noise amplifier (220; 320; 420). [2] Transceiver front-end (200; 300; 400) according to claim 1, wherein the transmitter branch (201; 301; 401) comprises a power amplifier (210; 310; 410) which generates output signals in transmitter mode, and wherein the transmitter branch (201; 301; 401) further comprises an impedance transformer (211; 311; 411) which couples the power amplifier (210; 310; 410) to the input / output pad (251; 351; 451), enabling the antenna (250; 350; 450) to transmit the output signals, and wherein the switch (280; 380; 480) comprises n-type field-effect transistors (381a-381c; 481a-481c) connected in series and wherein a sum of all drain-source voltages of the n-type field-effect transistors (381a-381c; 481a-481c) connected in series in the switch (280; 380; 480) is greater than a maximum output voltage of the power amplifier (210; 310; 410) to prevent the switch (280; 380; 480) from being turned on in transmitter mode. [3] Transceiver front end (200; 300; 400) according to claim 1, wherein the receiver branch (202; 302; 402) further comprises a shunt device (260; 360; 460) downstream of the switch (280; 380; 480) and upstream of the low-noise amplifier (220; 320; 420), and wherein the shunt device (260; 360; 460) is in an off state in receiver mode and in an on state in transmitter mode. [4] Transceiver front end (400), comprising: an antenna (450); a transmitter branch (401); and a receiver branch (402), wherein the antenna (450), the transmitter branch (401) and the receiver branch (402) are connected to an input / output pad (451), wherein the transceiver front end (400) is operable in a transmitter mode and a receiver mode, and wherein the receiver branch (402) comprises: a low-noise amplifier (420); a switch (480), wherein the switch (480) comprises series-connected n-type fin field-effect transistors (481a - 481c) on a semiconductor substrate (491), wherein the switch (480) alternately disconnects the low-noise amplifier (420) from the input / output pad (451) and connects the low-noise amplifier (420) to the input / output pad (451), wherein the transceiver front end (400) operates in a transmitter mode when the low-noise amplifier (420) is disconnected from the input / output pad (451) by the switch (480), wherein the transceiver front end (400) operates in a receiver mode when the low-noise amplifier (420) is connected to the input / output pad (451) via the switch (480), and wherein the low-noise amplifier (420) amplifies the input signals received by the antenna (450) when the transceiver front end (400) is in receiver mode; and an matching network (430) which is operationally connected to the switch (480) and the low-noise amplifier (420), wherein the matching network (430) provides both impedance matching and protection against electrostatic discharge for the switch (480) and the low-noise amplifier (420), wherein the matching network (430) further comprises an inductor (435) and a first capacitor (431) which are electrically connected in series between ground and an input terminal (485) of the switch (480), and a second capacitor (432) which is electrically connected between an output terminal (486) of the switch (480) and an input terminal (425) of the low-noise amplifier (420). [5] Transceiver front end (400) according to claim 4, wherein the transmitter branch (401) comprises a power amplifier (410) which generates output signals in transmitter mode, and wherein the transmitter branch (401) further comprises an impedance transformer (411) which couples the power amplifier (410) to the input / output pad (451), enabling the antenna (450) to transmit the output signals, and wherein a sum of all drain-source voltages of all n-type field-effect transistors (481a - 481c) in the switch (480) is greater than a maximum output voltage of the power amplifier (410) to prevent the switch (480) from being turned on in transmitter mode. [6] Transceiver front end (400) according to claim 4, wherein a substrate area (491) aligned below the switch (480) comprises a P-trough (493), an N-trough (492) below the P-trough (493) and a P-area between the N-trough (492) and a bottom surface of the substrate (491), and wherein the N-tub (492) is positively biased in receiver mode and the P-tub (493) is discharged to ground. [7] Transceiver front end (400) according to claim 4, wherein the receiver branch (402) further comprises a first bias resistor (471) which is electrically connected to the input terminal (485) of the switch (480), enabling a first bias voltage to be applied to the input terminal (485) of the switch (480) accordingly in transmitter mode and receiver mode, and wherein the receiver branch (402) further comprises a second bias resistor (472) which is electrically connected to the input terminal (425) of the low-noise amplifier (420), enabling a second bias voltage, equal to an optimal input voltage for the low-noise amplifier (420), to be applied to the input terminal (425) of the low-noise amplifier (420) in receiver mode. [8] Transceiver front end (400) according to claim 7, wherein the receiver branch (402) further comprises a shunt device (460) downstream of the second capacitor (432) and the second bias resistor (472) and upstream of the low-noise amplifier (420), wherein the shunt device (460) is in an on state in transmitter mode and in an off state in receiver mode. [9] Transceiver front end (400) according to claim 8, wherein the shunt device (460) comprises an n-type fin field-effect transistor, wherein in transmitter mode the n-type fin field-effect transistor is in the on state and pulls a voltage level at the input terminal (425) of the low-noise amplifier (420) to ground in order to effectively turn off the low-noise amplifier (420).