Semiconductor component and method for manufacturing a semiconductor component

Abstract

Method for fabricating a semiconductor device (100, 208A) based on a dual-architecture compatible design, the method comprising: forming (1202) one or more components of one or more transistors in a transistor layer, TR layer, of the semiconductor device (100, 208A); and performing one of: A) fabricating (1206) further components according to a buried busbar architecture type, BPR architecture type, for the semiconductor device (100, 208A), wherein the BPR architecture type comprises sub-transistor layers, sub-TR layers, and supra-TR layers; or B) fabricating (1236) further components according to a non-buried busbar architecture type, non-BPR architecture type, for the semiconductor device (100, 208A), wherein the non-BPR architecture type comprises supra-TR layers;and wherein: the dual-architecture compatible design is essentially equally suitable for adaptation to the BPR architecture type and for adaptation to the non-BPR architecture type; which A) fabricating (1206) further components according to a BPR architecture type comprises: in appropriate sub-TR layers, forming (1208) various non-dummy structures, non-dummy sub-TR structures, which are appropriately coupled to the transistor components; and, in appropriate supra-TR layers, forming (1210) various dummy structures, dummy supra-TR structures, which are appropriate artifacts resulting from the dual-architecture compatible design that is suitable for adaptation to the non-BPR architecture type;and B) Fabricating (1236) further components according to a non-BPR architecture type comprises: in corresponding supra-TR layers: forming (1238) various non-dummy structures, non-dummy supra-TR structures that are coupled accordingly with the transistor components; and forming (1240) various dummy structures, dummy supra-TR structures that are corresponding artifacts resulting from the dual-architecture compatible design suitable for adaptation to the BPR architecture type.;

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] The present application claims priority over the preliminary US application 63 / 031,409, filed on Thursday, May 28, 2020, which is hereby incorporated in its entirety by reference. BACKGROUND

[0002] An integrated circuit (IC) comprises one or more semiconductor devices. One way to represent a semiconductor device is by using a top view called a layout diagram. Layout diagrams are created within the context of design rules. A set of design rules imposes restrictions on the placement of corresponding structures in a layout diagram, such as geographical / spatial constraints, interconnection requirements, or the like. In general, a set of design rules includes a subset of design rules that relate to the spacing and other interactions between structures in adjacent or neighboring cells, where the structures represent conductors in a metallization layer.

[0003] Typically, a set of design rules is specific to a process / technology node, according to which a semiconductor device is manufactured based on a layout diagram. This set of design rules compensates for the variability of the corresponding process / technology node. Such compensation increases the likelihood that a real semiconductor device resulting from a layout diagram will be an acceptable counterpart to the virtual device on which the layout diagram is based. List of characters

[0004] Aspects of this disclosure are best understood by referring to the following detailed description, when read in conjunction with the accompanying figures. It should also be noted that, in accordance with standard industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as desired for the clarity of the discussion. Fig. Figure 1 is a block diagram of a semiconductor device. 100 according to some embodiments. Fig. 2A, Fig. 2B and Fig. 2C are corresponding cross-sections, Fig. 2D and Fig. 2E are corresponding layout diagrams and Fig. 2F and Fig. 2G are corresponding circuit diagrams according to some embodiments. Fig. 3A, Fig. 3B and Fig. 3C are corresponding cross-sections and Fig. 3D and Fig. 3E are corresponding layout diagrams according to some embodiments. Fig. 4A, Fig. 4B and Fig. 4C are corresponding cross-sections and Fig. 4D and Fig. 4E are corresponding layout diagrams according to some embodiments. Fig. 5A, Fig. 5B and Fig. 5C are corresponding cross-sections, Fig. 5D and Fig. 5E are corresponding layout diagrams according to some embodiments. Fig. 6A, Fig. 6B and Fig. 6C are corresponding cross-sections according to some embodiments. Fig. 7A, Fig. 7B and Fig. 7C are corresponding cross-sections and Fig. 7D and Fig. 7E are corresponding layout diagrams according to some embodiments. Fig. Figure 8 is a flowchart of a process for manufacturing a semiconductor device according to some embodiments. Fig. Figure 9 is a flowchart of a process for manufacturing a semiconductor device according to some embodiments. Fig. Figure 10 is a block diagram of an EDA (Electronic Design Automation) system according to some embodiments. Fig. Figure 11 is a block diagram of a manufacturing system for integrated circuits (ICs) and an associated IC manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or exemplary embodiments for implementing various features of the provided subject matter. Specific exemplary embodiments for components, values, processes, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely exemplary embodiments and are not intended to be limiting. Other components, values, processes, materials, arrangements, or the like are considered.For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves for simplicity and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the device in use or operation. The object may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptions used here can be interpreted accordingly.

[0007] In some embodiments, a layout diagram is generated that is compatible with dual architecture in the sense that selective pruning of structures from the layout diagram yields either a first single-architecture compatible layout diagram or a second single-architecture compatible layout diagram, wherein: the first single-architecture compatible layout diagram has a first architecture type, i.e., is compatible with it; and the second single-architecture compatible layout diagram has a second architecture type, i.e., is compatible with it. In some embodiments, the first architecture type is a non-buried power rail (non-BPR) architecture type, and the second architecture type is a buried power rail (BPR) architecture type.In some embodiments, selective trimming of the set of structures contained in the dual-architecture compatible layout diagram includes selective separation of structures, i.e., selective removal of structures from the dual-architecture compatible layout diagram.

[0008] In some embodiments, a dual-architecture compatible layout diagram representing a given circuit design has the advantage of facilitating the porting (adaptation) of the given circuit design to multiple architecture types. In particular, porting (adaptation) is facilitated because porting (adapting) the dual-architecture compatible layout diagram does not require adding new structures (shapes) to the dual-architecture compatible layout diagram, nor does it require extending or multiplying existing structures (shapes) of the dual-architecture compatible layout diagram, or anything of the sort. Rather, porting (adapting) the dual-architecture compatible layout diagram is a subtractive process in which structures are clipped (selectively removed) from the dual-architecture compatible layout diagram.

[0009] In some embodiments, a method (for fabricating a semiconductor device based on a dual-architecture compatible design) comprises forming transistor components in a transistor layer (TR layer) and performing one of (A) fabricating further components according to a buried busbar architecture type (BPR architecture type) comprising layers below the transistor layer (sub-TR layers) and layers above the transistor layer (supra-TR layers), or (B) fabricating further components according to an unburied busbar architecture type (non-BPR architecture type) comprising supra-TR layers; wherein: the dual-architecture compatible design is substantially equally suitable for adaptation to the BPR architecture type and for adaptation to the non-BPR architecture type;(A) Fabricating further components according to a BPR architecture type includes: in corresponding Sub-TR layers, forming various non-dummy structures (non-dummy Sub-TR structures), in corresponding Supra-TR layers, forming various dummy structures (dummy Supra-TR structures), which are corresponding artifacts resulting from the dual-architecture compatible design suitable for adaptation to the non-BPR architecture type; and (B) Fabricating further components according to a non-BPR architecture type includes: in corresponding Supra-TR layers, forming various non-dummy structures (non-dummy Supra-TR structures) and forming various dummy structures (dummy Supra-TR structures), which are corresponding artifacts resulting from the dual-architecture compatible design suitable for adaptation to the BPR architecture type.

[0010] Fig. Figure 1 is a block diagram of a semiconductor device. 100according to some embodiments.

[0011] In Fig. 1 includes the semiconductor device 100 including an area 104 and an area 106 The areas 104 and 106 are based on a corresponding layout diagram compatible with dual architecture.

[0012] The area 104 It features an architecture type with a non-buried power rail (non-BPR architecture type). With respect to a transistor layer (TR layer) and in corresponding layers above the transistor layer (supra-TR layers), the area exhibits 104 on: various non-dummy structures (non-dummy supra-TR structures) that are coupled with the transistor components and are included, since the area 104exhibits the non-BPR architecture type; and various dummy structures (dummy supra-TR structures) that are corresponding artifacts resulting from the dual-architecture compatible design suitable for adaptation to a buried busbar architecture type (BPR architecture type), incorporating the artifacts of the manufacturing of the area 104 is expedient. In other words, the artifacts are compatible with the area. 102 included, which is otherwise compatible with a buried busbar architecture type (BPR architecture type).

[0013] In some embodiments, the area includes 104 Furthermore, various dummy structures (dummy sub-TR structures) are corresponding artifacts resulting from the dual architecture-compatible design suitable for adaptation to the BPR architecture type, including the incorporation of manufacturing artifacts from the area. 104is expedient. In other words, the artifacts are compatible with the area. 104 included, which is otherwise compatible with the BPR architecture type.

[0014] The area 106 It features a buried busbar architecture (BPR architecture type). With respect to a transistor layer (TR layer), the area 106 on: in corresponding Supra-TR layers, various dummy structures (dummy Supra-TR structures) that are corresponding artifacts resulting from the dual architecture compatible design suitable for adapting to the architecture type with non-buried busbar, including the incorporation of the manufacturing artifacts of the area 104is useful; and, in corresponding transistor layer sub-TR layers, various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and contained therein, since the area 106 exhibits the BPR architecture type. In other words, the artifacts are for compatibility with the area. 106 included, which is otherwise compatible with the non-BPR architecture type.

[0015] In some embodiments, the area 102 in the semiconductor device 100 not present. In some embodiments, the area 104 in the semiconductor device 100 not present. In some embodiments, the area 106 in the semiconductor device 100 unavailable.

[0016] Fig. 2A is a cross-section of a layout diagram compatible with dual architecture. 208A, which represents a semiconductor device, according to some embodiments. Fig. 2B and Fig. 2C are cross-sections of corresponding layout diagrams compatible with simple architecture. 208B and 208C , the corresponding semiconductor components 208B and 208C represent, according to some embodiments. Fig. 2D and Fig. 2E are corresponding top views of layout diagrams compatible with simple architecture. 208D and 208E , which represent the corresponding semiconductor components, according to some embodiments. Fig. 2F and Fig. 2G are corresponding circuit diagrams 208F and 208G according to some embodiments.

[0017] In particular, they correspond Fig. 2B, Fig. 2D and Fig. 2F each other, and Fig. 2B is out Fig. 2A derived. Fig. 2C, Fig. 2E and Fig. 2G correspond to each other, and Fig. 2D is out Fig. 2A derived. In some embodiments, the layout diagrams are 208A-208E corresponding Fig. 2A-2E on a non-volatile, computer-readable medium (see Fig. 10) saved.

[0018] The layout diagram 208A It comprises a set of structures that represent components of a semiconductor device. Furthermore, the layout diagram... 208A compatible with dual architecture in the sense that selective trimming of structures from the layout diagram 208A This results either in a first layout diagram compatible with simple architecture, which exhibits a first architecture type, or in a second layout diagram compatible with simple architecture, which exhibits a second architecture type. In particular, trimming a first subset of structures from the layout diagram yields... 208A the layout diagram 208B out of Fig. 2B is the first layout diagram, where the latter represents a semiconductor device exhibiting the architecture type with an unburied busbar (again, a non-BPR architecture type). The process of extracting a second subset of structures from the layout diagram... 208A This results in a second layout diagram, which results in the layout diagram. 208C as a second layout diagram, the latter representing a semiconductor device that has the buried busbar architecture type (again BPR architecture type).

[0019] In some embodiments, selective trimming of the set of structures included in the layout diagram involves 208A Included, as noted above, is the selective separation of structures from the layout diagram. 208A , i.e., selective removal of structures from the layout diagram 208A In some embodiments, selective trimming of the set of structures in the layout diagram includes208A Included, as noted above, is selective cropping of the layout diagram. 208A , i.e., selective removal of structures from the layout diagram 208A In some embodiments, selective trimming of the set of structures in the layout diagram includes 208A Included, as noted above, is selective trimming of the layout diagram. 208A , i.e., selective removal of structures from the layout diagram 208A .

[0020] The layout diagram compatible with dual architecture 208A This is thus provided to facilitate the porting of a design between simple architecture-compatible non-BPR architecture layout diagrams and simple architecture-compatible BPR architecture layout diagrams. In some embodiments, the dual architecture-compatible layout diagram 208Atrimmed down so that the final semiconductor device, as represented in a corresponding final layout diagram, either has a non-BPR architecture type that does not have BPRs, or has a BPR architecture type that does not have non-BPRs.

[0021] The discussion of Fig. 2A-2C refers to structures in the layout diagrams. 208A-208C , as if these were components of corresponding semiconductor devices, which are shown on the corresponding layout diagrams 208A-208C based.

[0022] In some embodiments, a dummy structure is generally a structure that does not make a primary contribution to the functional purpose of a semiconductor device. In some embodiments, a dummy structure does not make a primary contribution to a logic function, memory function, amplification function, buffer function, current shaping function, or the like of a semiconductor device.

[0023] In some embodiments, a first type of dummy structure is included as a secondary contribution to the functional purpose of a semiconductor device, e.g. by arrangement between non-dummy structures, i.e. primary contributions to the functional purpose of a semiconductor device, and thereby reduces crosstalk (interference) between the non-dummy structures or the like.

[0024] In some embodiments, a second type of dummy structure is included as a tertiary contribution to the functional purpose of a semiconductor device, e.g., because the inclusion of the second type of dummy structure improves the results of a planarization process, e.g., chemical-mechanical polishing (CMP), performed during manufacturing, and the improved results of planarization by non-dummy structures, i.e., primary contributions to the functional purpose of the semiconductor device, promote improved performance.

[0025] In some embodiments, within the context of a semiconductor device based on a dual-architecture compatible design and configured with one of the two architectures of the dual-architecture design, a third type of dummy structure is included in the semiconductor device. This third type of dummy structure is included in the semiconductor device because it is an artifact resulting from the dual-architecture compatible design, suitable not only for adaptation to the first architecture but also for adaptation to the second architecture.

[0026] In some embodiments, the third type of dummy structure also makes a secondary or tertiary contribution to the functionality of a semiconductor device. However, the primary reason for including the third type of dummy structure in a semiconductor device is that its inclusion is expedient with regard to the manufacturing process. That is, in terms of process features / aspects / steps associated with manufacturing the third type of dummy structure, it is expedient to form the third type of dummy structure rather than to undertake process features / aspects / steps associated with not forming the third type of dummy structure.In some embodiments, the third type of dummy structure is included in a semiconductor device because process features / aspects / steps associated with manufacturing the third type of dummy structure are advantageous compared to the process features / aspects / steps that would otherwise be associated with not manufacturing the third type of dummy structure.

[0027] In Fig. 2A includes the layout diagram compatible with dual architecture. 208A a transistor layer (TR layer) which is shown extending in a first direction and having a thickness in a second direction perpendicular to the first direction. Fig. In 2A, the first direction runs along the X-axis and the second direction along the Z-axis. In some embodiments, the first and second directions are directions that do not run along the X-axis or the Z-axis, respectively.

[0028] In Fig. 2A includes the layout diagram 208AWith respect to the Z-axis and above the TR layer, further supra-TR layers, the supra-TR layers comprising: a contact-to-transistor component layer (MD / MG layer); a via-between-contact-and-metallization layer (VD / VG layer); a first metallization layer (M0 layer); a first interconnection layer (VIA0 layer); a second metallization layer (M1 layer); a second interconnection layer (VIA1 layer); a third metallization layer (M2 layer); a third interconnection layer (VIA2 layer); a fourth metallization layer (M3 layer); a fourth interconnection layer (VIA3 layer); a fifth metallization layer (M4 layer); a fifth interconnection layer (VIA4 layer); a sixth metallization layer (M5 layer); a sixth interconnection layer (VIA5 layer); a seventh metallization layer (M6 layer); a seventh interconnection layer (VIA6 layer); an eighth metallization layer (M7 layer);an eighth interconnection layer (VIA7 layer); a ninth metallization layer (M8 layer); a ninth interconnection layer (VIA8 layer); a tenth metallization layer (M9 layer); a tenth interconnection layer (VIA9 layer); an eleventh metallization layer (MIO layer); an eleventh interconnection layer (VIA10 layer); a twelfth metallization layer (M11 layer); a twelfth interconnection layer (VIA11 layer); a thirteenth metallization layer (M12 layer); a thirteenth interconnection layer (VIA12 layer); a fourteenth metallization layer (M13 layer); a fourteenth interconnection layer (VIA13 layer); a fifteenth metallization layer (M14 layer); a fifteenth interconnection layer (VIA14 layer); a sixteenth metallization layer (M15 layer); a sixteenth interconnection layer (VIA15 layer); a redistribution layer (RV layer); and a pad layer (AP layer).

[0029] In some embodiments, the layout diagram shows 208A a larger number of supra-TR metallization layers and a correspondingly larger number of supra-TR interconnection layers. In some embodiments, the layout diagram shows 208A fewer Supra-TR metallization layers and correspondingly fewer Supra-TR interconnection layers.

[0030] With respect to the Z-axis and below the TR layer, the layout diagram includes 208Afurthermore, Sub-TR layers, wherein the Sub-TR layers comprise: a buried contact-to-transistor component layer (BVD / BVG); a first buried metallization layer (BM0 layer); a first buried interconnection layer (BVIA0 layer); a second buried metallization layer (BM1 layer); a second buried interconnection layer (BVIA1 layer); a third buried metallization layer (BM2 layer); a third buried interconnection layer (BVIA2 layer); a fourth buried metallization layer (BM3 layer); a fourth buried interconnection layer (BVIA3 layer); a fifth buried metallization layer (BM4 layer); a fifth buried interconnection layer (BVIA4 layer); a sixth buried metallization layer (BM5 layer); a buried redistribution layer (BRV layer); and a buried pad layer (BAP layer).

[0031] With reference to Fig. 2A In some embodiments, the TR layer is a layer of semiconductor material comprising regions that have been appropriately doped to serve various corresponding purposes. In particular, the TR layer in Fig. 2A: a first type of doped region designated “G” and configured to serve as the gate terminal (G terminal) for a corresponding transistor structure; a second type of doped region designated “D” and configured to serve as the drain terminal (D terminal) for a corresponding transistor structure; a third type of doped region designated “S” and configured to serve as the source terminal (S terminal) for a corresponding transistor structure; a fourth type of doped region designated “B” and configured to serve as the body bias terminal (substrate bias terminal) (B terminal) for a corresponding transistor structure; and a fifth type of doped region designated with TTLV is designated and is configured to serve as a conductive section in an electrical coupling path between a given MD structure (discussed below) in the MD / MG layer and a corresponding BVD structure (discussed below) in the BVD / BVG layer, or in an electrical coupling path between a given MG structure (discussed below) in the MD / MG layer and a corresponding BVG structure (discussed below) in the BVD / BVG layer. The fifth type of doped region is designated as a transistor layer through-transistor via (TTLV). In some embodiments, a silicon through-silicon via structure is used instead of the fifth type of doped region.TSV structure) as a conductive section in an electrical coupling path between a given MD structure (discussed below) in the MD / MG layer and a corresponding BVD structure (discussed below) in the BVD / BVG layer, or in an electrical coupling path between a given MG structure (discussed below) in the MD / MG layer and a corresponding BVG structure (discussed below) in the BVD / BVG layer. For easier illustration, . Fig. 2A TSV structures instead of the fourth type of endowed area.

[0032] In some cases, an insulating region (IR) is provided between doped regions. An instance of the insulating region between the columns C4 and C5 is in Fig. 2A, denoted by IR. In some embodiments, one or more instances of the insulating region comprise dielectric material. In some embodiments, one instance of the insulating region is formed by converting the semiconductor material of the TR layer into a dielectric material. In some embodiments where the semiconductor material of the TR layer is silicon, a given instance of the insulating region comprises silicon dioxide grown from the silicon at the position of the insulating region in the TR layer.

[0033] In Fig. 2A comprises the contact-to-transistor component layer (MD / MG layer) with respect to the supra-TR layers: one or more contact structures of a first type, each of which is configured to be electrically coupled to a drain terminal (D), a source terminal (S), a body bias terminal (B) of a corresponding transistor structure in the TR layer or a corresponding TSV structure in the TR layer, the first type being referred to herein as the MD contact structure; and one or more contact structures of a second type, each of which is configured to be electrically coupled to a gate terminal (G) of a corresponding transistor structure in the TR layer, the second type being referred to herein as the MG contact structure.In some embodiments, the MD contact structure is not used to be electrically coupled with a corresponding TSV structure in the TR layer, but the MD / MG layer instead further comprises one or more contact structures of a third type (not shown) which is configured to be electrically coupled with a corresponding TSV structure in the TR layer.

[0034] The via-contact-to-metallization (VD / VG) layer comprises: one or more via-contact-to-metallization structures of a first type, each of which is configured to be electrically coupled to a corresponding MD contact structure, the first type being referred to herein as the VD structure; and one or more via-contact-to-metallization structures of a second type, each of which is configured to be electrically coupled to a corresponding MG contact structure, the second type being referred to herein as the VG contact structure.In some embodiments, where the VD / VG layer comprises one or more contact structures of the third type (not shown) configured to be electrically coupled to a corresponding TSV structure in the TR layer, the via-contact-and-metallization layer (VD / VG layer) further comprises one or more via-contact-and-metallization structures of a third type (not shown). The third type of via-contact-and-metallization structure is configured to be electrically coupled to a corresponding TSV structure in the TR layer.

[0035] In Fig. 2A includes each of the metallization layers M0-M15 one or more conductive segments. Each interconnection layer VIAO-VIA14 The layer comprises one or more via structures. The redistribution layer comprises one or more redistribution contact structures (RV contact structures). The pad layer AP comprises one or more pads.

[0036] In Fig. 2A comprises the buried contact-to-transistor component layer (BVD / BVG layer) with respect to the sub-TR layers: one or more contact structures of a first type, each of which is configured to be electrically coupled to a drain terminal (D), a source terminal (S), a body bias terminal (B) of a corresponding transistor structure in the TR layer or a corresponding TSV structure in the TR layer, respectively, the first type being referred to herein as the BVD contact structure; and one or more contact structures of a second type, each of which is configured to be electrically coupled to a gate terminal (G) of a corresponding transistor structure in the TR layer, the second type being referred to herein as the BVG contact structure.In some embodiments, the BVD contact structure is not used to be electrically coupled with a corresponding TSV structure in the TR layer, but the BVD / BVG layer instead further comprises one or more contact structures of a third type (not shown) which is configured to be electrically coupled with a corresponding TSV structure in the TR layer.

[0037] In Fig. 2A comprises one or more buried conductive segments in each of the buried metallization layers BM0-BM5. Each buried interconnection layer BVIA0-BVIA4 comprises one or more buried via structures. The buried redistribution layer BRV comprises one or more buried redistribution contact structures (BRV contact structures). The buried pad layer AP comprises one or more buried pads.

[0038] In Fig. 2A are exemplary pitch distances for each of the metallization layers. M0-M15 , the pad layer AP, each of the buried metallization layers BMO-BM5 and the buried pad layer BAP is listed, where each pitch is a multiple of a unit pitch d. For example, the pitch of the layer is M0 in Fig. 2A 22 d. In some embodiments, d is one nanometer. In some embodiments, d is a value other than one nanometer. In some embodiments, for one or more of the metallization layers M0-M15 Different division distances are used.

[0039] The layout diagram is for discussion purposes. 208A into the columns C1 , C2 , C3 , C4 and C5 structured. The column C2For example, it includes an electrically conductive path that electrically couples the pad in pad layer AP to the buried pad in layer BAP. The electrically conductive path in the column C2 includes: the pad in the pad layer AP to the buried pad in the layer BAP; an RV contact structure in the RV layer; a supra-TR single stack via (single stack or SS via) 210A ; a VD structure in the VD / VG layer; an MD contact structure in the MD / MG layer; a D connection in the TR layer; a BVD structure in the BVD / BVG layer; a Sub-TR-SS via; a BRV contact structure in the BRV layer; and the buried pad in the buried pad layer BAP.

[0040] In the column C2 in Fig. 2A includes the Supra-TR-SS through-hole connection 210A corresponding conductive segments in the metallization layers M0-M15 and corresponding via structures in each of the interconnection layers VIAO-VIA14 The Sub-TR-SS vias in the column C2 include corresponding buried conductive segments in the buried metallization layers BM0-BM5 and corresponding buried via structures in each of the interconnection layers VIAO-VIA14 .

[0041] What the column C2 As far as this is concerned, neither the pad in the pad layer AP nor the conductive structures in the metallization layers extend MO-M15 , the buried conductive segments in the buried metallization layers BMO-BM5 still the buried pad in the buried pads layer BAP related to the X-axis in the column C1 and not in the column either C3 .

[0042] The layout diagram 208A includes in each of the columns C1 , C3 , C4 and C5further SS vias. However, for the sake of simplifying the drawings, in Fig. 2A the further SS vias are not marked with corresponding reference symbols.

[0043] The column C1 It comprises a first electrically conductive path that electrically couples a pad in the AP pad layer to a B terminal in the TR layer. The first electrically conductive path of the column C1 includes: the pad in the pad layer AP, an RV contact structure in the RV layer; a supra-TR-SS through-hole (the metallization layers) M0-M15 and the corresponding interconnection layers VIAO-VIA14 span); a VD structure in the VD / VG layer; an MD contact structure in the MD / MG layer; and the B terminal in the TR layer.

[0044] The column C1 further includes a second electrically conductive path, which is a conductive segment in the buried metallization layer BM0 electrically connects to a buried pad in the buried pad layer BAP. The second electrically conductive path of the column C1 includes: a sub-TR-SS through-hole (the buried metallization layers) BMO-M5 and the corresponding buried interconnection layers VIA0-VTA4 (spanning); a BRV contact structure in the BRV layer; and the buried pad in the buried pad layer BAP. Regarding the column C1 As far as this is concerned, the buried conductive segment is located in the buried metallization layer. BM0 the column C1 electrically coupled to the buried pad in the buried pad layer BAP. However, since in the column C1 Since the BVD / BVG layer does not exhibit a BVD structure, the buried conductive segment is located in the buried metallization layer. BM0 Not electrically connected to the B terminal. Accordingly, the column shows C1The B-connection is not electrically coupled to the buried pad in the buried pad layer BAP.

[0045] What the column C1 As far as this is concerned, neither the pad in the pad layer AP nor the conductive structures in the metallization layers extend MO-M15 , the buried conductive segments in the buried metallization layers BMO-BM5 still the buried pad in the buried pad layer BAP related to the X-axis in the column C2 .

[0046] In Fig. 2A includes the column C3 a first electrically conductive path that electrically couples a pad in the AP pad layer to a G-terminal in the TR layer. The first electrically conductive path of the column C3 includes: the pad in the AP pad layer; an RV contact structure in the RV layer; a supra-TR-SS via (the metallization layers) M0-M15 and the corresponding interconnection layers VIAO-VIA14 span); a VG structure in the VD / VG layer; a MG contact structure in the MD / MG layer; and the G connection in the TR layer.

[0047] As for the sub-TR layers, the column comprises C3 a routing arrangement wherein the routing arrangement places corresponding conductive segments in the buried metallization layers BMO-BM5 and includes a buried pad within the buried pad layer (BAP). The conductive segments are located within the buried metallization layers. BMO-BM5 are used for routing signals to other structures (in Fig. (2A not shown) is available. It should be noted that the routing order of the column C3 no BVD structure in the BVD / BVG layer, no corresponding via structures in the buried interconnection layers BVIAO-BVIA4 and has no BRV contact structure in the BRV layer. Accordingly, the routing order in the column C3no second electrically conductive path in the column C3 that would otherwise have electrically coupled the terminal C in the TR layer to the buried pad in the buried pad layer BAP.

[0048] What the column C3 As far as this is concerned, neither the pad in the pad layer AP nor the conductive structures in the metallization layers extend M0-M7 , the buried conductive segments in the buried metallization layers BM0-BM5 still the buried pad in the buried pad layer BAP related to the X-axis in the column C2 and not in the column either C4 The conductive structures in the metallization layers M8 and M9 extend accordingly into the column with respect to the x-axis C4 , but not in the column C2 .

[0049] In the layout diagram 208A The column includes C4: a first electrically conductive path that forms a conductive segment in the layer M7 electrically couples with a buried pad in the buried pad layer BAP. The first electrically conductive path in the column C4 includes: a first supra-TR-SS through-hole (the metallization layers) MO-M7 and the corresponding interconnection layers VIAO-VIA6 span); a VD structure in the VD / VG layer; an MD contact structure in the MD / MG layer; an S connection in the TR layer; a BVD structure in the BVD / BVG layer; a sub-TR SS via; a BRV contact structure in the BRV layer; and the buried pad in the buried pad layer BAP. The column C4 further includes a second supra-TR-SS through-hole (the metallization layers). M8-M9 and the corresponding interconnection layer VIA8 (spanning).

[0050] The column C4It also includes conductive segments in the metallization layers. M8 and M9 and a corresponding via structure in the interconnection layer VIA8, which is in a via column 212A are included, which will be discussed below. The conductive structures in the metallization layers M8 and M9 extend accordingly into the column with respect to the x-axis C5 , but not in the column C3 .

[0051] The column C4 further comprises a routing arrangement, wherein the routing arrangement includes corresponding conductive segments in the metallization layers. M10-M15 and includes a pad in the AP pad layer. The conductive segments in the metallization layers. M10-M15 are used for routing signals to other structures (in Fig. (2A not shown) is available. It should be noted that the routing order of the column C4no corresponding via structures in the interconnection layers VIA9-VIA14 and has no RV contact structure in the RV layer. Accordingly, the routing arrangement in the column C4 no second electrically conductive path in the column C4 dar.

[0052] What the column C4 As far as the X-axis is concerned, neither the pad in the pad layer AP nor the conductive structures in the metallization layers extend MO-M7 , the buried conductive segments in the buried metallization layers BM0-BM5 the buried pad in the buried pad layer BAP accordingly into the column C3 and not in the column either C5 ; and the conductive structures in the metallization layers M8 and M9 extend accordingly into each of the columns C3 and C4 ; and the conductive structures in the metallization layers M10-M15 extend accordingly into the column C5 , but not in the column C3 .

[0053] In the layout diagram 208A The column includes C5 : a first electrically conductive path that forms a conductive segment in the layer M9 electrically couples with a buried pad in the buried pad layer BAP. The first electrically conductive path in the column C5 includes: a supra-TR-SS through-hole (the metallization layers) MO-M9 and the corresponding interconnection layers VIAO-VIA8 span); a VD structure in the VD / VG layer; an MD contact structure in the MD / MG layer; a TSV structure in the TR layer; a BVD structure in the BVD / BVG layer; a Sub-TR-SS via; a BRV contact structure in the BRV layer; and the buried pad in the buried pad layer BAP.

[0054] In the layout diagram 208Arepresent the second Supra-TR-SS through-connection of the column C4 (which are the metallization layers) M8-M9 and the corresponding interconnection layer VIA8 overspanned) and the Supra-TR-SS through-connection of the column C5 (which are the metallization layers) MO-M9 and the corresponding interconnection layers VIA0-VTA8 (spanning) together a supra-TR via pillar 212A dar.

[0055] In some embodiments, the term through-hole plating refers to, for example, the Supra-TR through-hole plating. 212A, on an arrangement of multiple SS vias connected in parallel. In some embodiments, the "legs" of a via pillar are symmetrical with respect to the length measured in the Y-direction. In some embodiments, the "legs" of a via pillar are asymmetrical with respect to the length measured in the Y-direction. In some embodiments, in a case where a via pillar replaces a single SS via within a given electrically conductive path, the use of a via pillar reduces the electrical resistance of the given electrically conductive path compared to using the single SS via, providing performance advantages, e.g., with respect to timing effects and signal propagation delays. However, a trade-off must be made regarding the use of via pillars, e.g.,Since a through-hole via requires additional space within the geometry of a semiconductor device compared to using a single SS through-hole, which can complicate routing and increase the overall size of the semiconductor device, the use of a through-hole via reflects the decision that the advantages outweigh the disadvantages.

[0056] In the column C5 The conductive structures extend into the metallization layers. M8 and M9 in the column C4 and across the column C4 out into the column C3 Therefore, the via pillar 212A Part of a larger via column, which includes not only the via column 212A includes, but also the Supra-TR-SS_via of the column C3 (which are the metallization layers) M0-M15 and the corresponding interconnection layers VIAO-VIA14 overstretched).

[0057] The column C5 further comprises a routing arrangement, wherein the routing arrangement includes corresponding conductive segments in the metallization layers. M10-M15 and includes a pad in the AP pad layer. The conductive segments in the metallization layers. M10-M15 are used for routing signals to other structures (in Fig. (2A not shown) is available. It should be noted that the routing order of the column C5 no corresponding via structures in the interconnection layers VIA9-VIA14 and has no RV contact structure in the RV layer. Accordingly, the routing arrangement in the column C5 no second electrically conductive path in the column C54 dar.

[0058] What the column C5 As far as the X-axis is concerned, neither the conductive structures in the metallization layers extend M0-M7 , the buried conductive segments in the buried metallization layers BMO-BM5 still the buried pad in the buried pad layer BAP in the column C4 ; and the conductive structures in the metallization layers M8 and M9 each extends (as noted above) into the column C4 ; and the conductive structures in the metallization layers M10-M15 extend into the column C5 .

[0059] As already mentioned, the layout diagram 208A in Fig. 2A is compatible with dual architecture and can be selectively trimmed to either the layout diagram compatible with single architecture. 208B out of Fig. 2B or the layout diagram compatible with simple architecture 208C out of Fig. to result in 2C. The layout diagram is compatible with simple architecture. 208BIt features an architecture type with a non-buried busbar (non-BPR architecture type). The layout diagram is compatible with simple architecture. 208C It features an architecture type with a buried busbar (BPR architecture type). The layout diagram 208A is set up for compatibility with the non-BPR architecture type and the BPR architecture type.

[0060] Fig. 2B is a cross-section of the layout diagram compatible with simple architecture. 208B according to some embodiments.

[0061] The layout diagram is compatible with simple architecture. 208B This represents a decoupling capacitor circuit that features an architecture type with a non-buried busbar (non-BPR architecture type). To be Fig. 2A to Fig. To achieve 2B compatibility with the non-BPR architecture type, structures (patterns) from the layout diagram are used. 208A circumcised.

[0062] In Fig. 2B are part of configuring the layout diagram. 208B with a non-BPR architecture type, all structures in the various sub-TR layers from the columns C1-C5 removed, leaving behind the TR layer and the supra-SS structures. In some embodiments, not all structures in the listed sub-TR layers are removed; that is, some, but not all, of the structures in the listed sub-TR layers are retained. In such embodiments, where some, but not all, structures in the listed sub-TR layers are retained, at least the BVD structures in the columns are preserved. C2 , C4 and C5 removed.

[0063] In Fig. 2B are also part of configuring the layout diagram. 208B with the non-BPR architecture type, sections in each of the metallization layers M8 and M9 , the ones between the columns C4and C5 in Fig. 2A are positioned and in Fig. 2A with the reference numeral 214A The sections marked have been removed. 214A from the layout diagram 208A leads to the following in Fig. 2B: a via pillar 212B in the columns C3 - C4 ; and an SS_through connection 210B in the column C5 .

[0064] The SS through-connection 210B in the column C5 is a supra-TR dummy structure and is used as an artifact of the layout diagram. 208B considered, the layout diagram based on the dual architecture compatible 208A based on the dual architecture-compatible layout diagram 208A based on this. Therefore, the SS_through connection is 210B for compatibility with the layout diagram 208Bincluded, which is otherwise compatible with the BPR architecture type. In some embodiments, the dummy SS via is used. 210B referred to as a dummy structure, since the SS via 210B is left suspended. In some embodiments, the dummy SS via is 210B referred to as a supra-TR dummy structure, since the SS through-hole 210B no part of an electrically conductive path to or from an active component in the layout diagram 208B forms. In contrast to the Supra-TR dummy SS through-hole connection. 210B The other supra-TR structures will be shown in the layout diagram. 208BThese are referred to as supra-TR non-dummy structures. Although such dummy structures are artifacts, i.e., examples of the third type of dummy structure, they can nevertheless be useful in some embodiments insofar as they serve as an indication that the layout diagram 208B on a layout diagram compatible with dual architecture 208A based.

[0065] In Fig. 2B is the base area of ​​a given structure when viewed from the Z-axis, the area defined by the given structure with respect to the X-axis and the Y-axis (where the latter is in Fig. (2A is not shown) is taken. Fig. 2B is a base surface of the Supra-TR dummy SS via. 210B essentially within a common base area of ​​the layout diagram components 208B included, which are located in the TR layer, namely the B-terminal in the columnC1 , the D-connection in the column C2 , the G-connection in the column C3 , the S-connection in the column C4 and the TSV in the column C5 With respect to the X-axis, the Supra-TR-Dummy-SS_via is 210B asymmetrical to the components of the layout diagram 208B positioned, which are located in the TR layer, namely the B-terminal in the column C1 , the D-connection in the column C2 , the G-connection in the column C3 , the S-connection in the column C4 and the TSV in the column C5 .

[0066] Fig. 2B also includes a pictogram 220B The pictogram 220B This is a simplified representation of the layout diagram. 208B , which reflects that the layout diagram 208B: represents a component with a non-BPR architecture type; and includes supra-TR non-dummy structures and supra-TR dummy structures, but does not include sub-TR non-dummy structures and sub-TR dummy structures.

[0067] Fig. 2C is a cross-section of a layout diagram. 208C according to some embodiments.

[0068] The layout diagram 208C is a decoupling capacitor circuit that features a buried busbar (BPR) architecture. To be Fig. 2A to Fig. To achieve 2C, structures (patterns) from the layout diagram are used for compatibility with the BPR architecture type. 208A cropped. Accordingly, the layout diagram preserves 208C Sub-TR structures. One of the non-dummy sub-TR structures included in the layout diagram is the sub-TR SS via. 212G .

[0069] In Fig. 2C are used as part of configuring the layout diagram. 208C The BPR architecture type removed various structures in some of the supra-TR layers. In particular, in Fig. 2C, all structures in the metallization layers M10-M15 , the corresponding interconnection layers VIA9-VIA14 , in the RV layer and in the AP layer from the columns C1-C5 In some embodiments, not all structures in the listed supra-TR layers are removed; that is, some, but not all, of the structures in the listed supra-TR layers are retained. In embodiments where some, but not all, structures in the listed supra-TR layers are retained, at least the via structures at the intersections of the interconnection layer are retained. VIA9 and each of the columns C2 , C2 and C3 removed.

[0070] What the column C3As far as this is concerned, removing all structures in the metallization layers leads to M10-M15 , the corresponding interconnection layers VIA9-VIA14 , the RV layer and the AP layer to the effect that sections in the columns C3 , C4 and C5 exhibits.

[0071] Fig. 2C also includes a pictogram 220C The pictogram 220C is a simplified representation that reflects the layout diagram 208C : represents a component with a BPR architecture type; and includes supra-TR non-dummy structures and sub-TR non-dummy structures, but does not include supra-TR dummy structures or sub-TR dummy structures.

[0072] Fig. 2D, in turn, is a top view of the layout diagram. 208D , which corresponds to the cross-section of the layout diagram 208B in Fig. 2B corresponds to the layout diagram. 208D does not include structures in layers below the layerM9 Among other structures, the layout diagram includes 208D a " M9 ( VSS )" structure, which is a conductive segment in the metallization layer M9 out of Fig. 2D representation VSS provides. In the layout diagram 208E is part of the empty space under the M9-( VSS )-structure with the reference symbol 218D In some embodiments, the term "empty space" in the context of a layout diagram, and further in the context of a given layer / level of the layout diagram, denotes an area where no structure is present, i.e., an area that has no structure. Although the layout diagram 208D no structures in layers below the layer M9 includes, is in Fig. 2D nevertheless shows an approximate underlying position of the dummy structure. 210B (if otherwise included) shown.

[0073] Fig. 2E is in turn a cross-section of the layout diagram. 208E , which corresponds to the cross-section of the layout diagram 208C in Fig. 2C corresponds to the layout diagram. 208E does not include structures below the layer M9 Compared to Fig. Among other things, one or more structures were created in 2D. 318E , which form a section of the via column 212C out of Fig. Represent 2C, added to an area that is the empty space 208D in the layout diagram 208D out of Fig. 2D corresponds. Although the layout diagram 208E no structures below the layer M9 included, are nevertheless in Fig. 2E Approximate underlying positions of Sub-TR-SS vias 210C (2) 210C (4) 210C (5) and a version 210C (3)' without VD contents of a Sub-TR-SS through-hole (if otherwise included) shown.

[0074] With reference to Fig. 2F is the circuit diagram 208F a capacitive coupling circuit comprising: a capacitor-aligned transistor P1 , which is a PMOS and is coupled between a first reference voltage and a second reference voltage. Correspondences between sections of the transistor. P1 and the columns in Fig. 2B are shown in the circuit diagram 208F designated. In some embodiments, the first reference voltage VDD , and the second reference voltage is VSS In some embodiments, the first and second reference voltages are voltages that are derived from the corresponding voltages. VDD or VSS are different.

[0075] In Fig. 2F is a gate terminal of the transistor. P1 connected to the first node, and each by a drain terminal, a source terminal and a body bias terminal of the transistor P1is with VDD tied together. Fig. 2F refers to the following: Fig. 2B: In Fig. 2B is the pad in the pad layer AP for each of the columns C1 and C2 in Fig. 2B electric with VDD coupled; the pad in the pad layer AP for the column C3 in Fig. 2B is coupled to the first node; and, as for the column C4 As far as this is concerned, the conductive segment is in the metallization layer. M7 out of Fig. 2B by a routing arrangement that is in Fig. 2B is not shown, electrically with VDD coupled.

[0076] Fig. 2G is Fig. 2F is similar, therefore the circuit diagram is 208G a capacitive coupling circuit that connects the capacitor-aligned transistor PI Fig. 2F comprises correspondences between sections of the transistor. P1 and the columns in Fig. 2C are shown in the circuit diagram. 208Gdesignated. However, since the circuit diagram 208G the layout diagram 208C out of Fig. 2C corresponds, the latter having a BPR architecture type, to the gate terminal of the transistor. P1 in the circuit diagram 208G with a first node in Fig. 2G connected; and a Sub-TR-SS through-hole. 212G is between the first nodes and VSS coupled.

[0077] Fig. 3A is a cross-section of a layout diagram compatible with dual architecture. 308A , which represents a semiconductor device, according to some embodiments. Fig. 3B and Fig. 3C are cross-sections of corresponding layout diagrams compatible with simple architecture. 308B and 308C , which represent the corresponding semiconductor components, according to some embodiments. Fig. 3D and Fig. 3E are corresponding top-down views of layout diagrams compatible with simple architecture.308D and 308E , which represent the corresponding semiconductor components, according to some embodiments. Fig. 3F and Fig. 3G corresponding circuit diagrams 308F and 308G according to some embodiments.

[0078] In particular, they correspond Fig. 3B, Fig. 3D and Fig. 3F each other. Fig. 3C, Fig. 3E and Fig. 3G correspond to each other. In some embodiments, the layout diagrams are 308A-308E the corresponding Fig. 3A-3E on a non-volatile, computer-readable medium (see Fig. 10) saved.

[0079] Fig. 3A-3E follow a similar numbering scheme as Fig. 2A-2G. Some components are different, even though they are identical. To facilitate the identification of identical but different components, the numbering convention uses 3-digit numbers for Fig. 3A-3E is used, while for Fig. 2A-2G are used as part numbers. For example, the element is... 312A in Fig. 3A a sample of a via pillar and the corresponding element 212A in Fig. 2A is an example of a via pillar, where similarities are reflected by the common ending _12A and differences by the corresponding initial digit. 3 in Fig. 3A and Fig. 2 in Fig. 2A are reflected. For the sake of brevity, the discussion will focus more on differences between Fig. 3A-3E and Fig. 2A-2G focus on similarities.

[0080] The cross-section in Fig. 3A is in turn a cross-section of the layout diagram. 308A The layout diagram 308A It is compatible with dual architecture and can be selectively trimmed to either the layout diagram compatible with single architecture or the one that is compatible with single architecture. 308B out of Fig. 3B (which represents a high-resistance (HiR) structure that has a non-BPR architecture type) or the layout diagram compatible with simple architecture 308C out of Fig. 3C (which represents a HiR structure that has a BPR architecture type).

[0081] The layout diagram is for discussion purposes. 308A into the columns C1 , C2 , C3 , C4 and C5 structured. The column C1 For example, it includes an electrically conductive path that electrically couples the pad in pad layer AP to the buried pad in layer BAP. The electrically conductive path in the column C1 includes, among other things: a Supra-TR-SS through-hole. 310A(1) , which are the metallization layers M0-M15 and the corresponding interconnection layers VIAO-VIA14 spanned; and a sub-TR-SS via that bridges the buried metallization layers. BM0-BM5 and the corresponding buried interconnection layers BVIAO-BVIA4 overstretched.

[0082] The column C2 includes, among other things, a Supra-TR-SS through-hole. 310A (2) the metallization layers M7-M9 and the corresponding interconnection layers VIA7-VIA8 overstretched.

[0083] In the layout diagram 308A do the conductive segments extend into the metallization? M8-M9 from the column C2 to the column C1 , resulting in the Supra-TR-SS through-hole connection 310A (2) of the column C2 and the Supra-TR-SS through-hole connection 310A (1) of the column C1 together form a first Supra-TR through-hole pillar 312A represent. A second supra-TR via pillar is located in the column C4and a section of the column C3 The second Supra-TR via pillar is a mirror-symmetric counterpart with respect to the Y-axis.

[0084] In Fig. 3A extends a high-resistance segment in the interconnection layer. VIA6 from the column C2 to and through the column C3 and further into the column C4 . The first end of the high-resistance segment is located in the column C2 and is electrically connected to the first Supra-TR via pillar 312A coupled. A second end of the high-impedance segment is located in the column C2 and is electrically coupled to the second Supra-TR via pillar.

[0085] Fig. 3A further includes: a routing arrangement in the metallization layers M10-M15 the columns C2-C5 ; a routing arrangement in the metallization layers M0-M16 the columns C2-C4 ; and a routing arrangement in the buried metallization layers BM0-BM5 the columns C2-C5 .

[0086] Fig. 3B is in turn a cross-section of the layout diagram. 308B , which is a HiR structure that has a non-BPR architectural type, according to some embodiments.

[0087] The layout diagram 308B is a HiR structure that features an architecture type with a non-buried busbar (non-BPR architecture type). To be Fig. 3A to Fig. To achieve 3B compatibility with the non-BPR architecture type, structures (patterns) from the layout diagram are used. 308A circumcised.

[0088] In Fig. 3B are part of configuring the layout diagram. 308B with a non-BPR architecture type, all structures in the various sub-TR layers from the columns C1-C5 removed, leaving behind the TR layer and the Supra-SS structures. In some embodiments, not all structures in the listed sub-TR layers are removed; that is, some, but not all, of the structures in the listed sub-TR layers are retained. In such embodiments, where some, but not all, of the structures in the listed sub-TR layers are retained, at least the BVD structure in the column is preserved. C1 removed.

[0089] In Fig. 3B is also part of configuring the layout diagram. 308B with the non-BPR architecture type a through-hole structure 316A at the intersection of the interconnection layer VIA6 and the column C1 It has been removed. The removal of the via structure has been removed. 316A from the layout diagram 308A leads to the following in Fig. 3B: a first supra-TR through-hole plating column 312B in the columns C1-C2 , which are the metallization layers M7-M15 and the corresponding interconnection layers VIA7-VIA14 spanned; and a first Supra-TR-SS via 310B in the column C1 , which are the metallization layers MO-M6 and the corresponding interconnection layers VIAO-VIA5 overstretched.

[0090] The first Supra-TR-SS via in column C1 is a supra-TR dummy structure and is used as an artifact of the layout diagram 308B Considering the layout diagram compatible with dual architecture 308A based on. Therefore, the first Supra-TR-SS via is in the column. C1 for compatibility with the layout diagram 308B contained, which is otherwise compatible with the BPR architecture type. In contrast to the first Supra-TR-SS via in the column C1 The other supra-TR structures will be shown in the layout diagram. 308BThese are referred to as supra-TR non-dummy structures. Although such dummy structures are artifacts, i.e., examples of the third type of dummy structure, they can nevertheless be useful in some embodiments insofar as they serve as an indication that the layout diagram 308B on a layout diagram compatible with dual architecture 308A based.

[0091] Fig. 3B also includes a pictogram 320B The pictogram 320B This is a simplified representation of the layout diagram. 308B , which reflects that the layout diagram 308B : represents a component with a non-BPR architecture type; and includes supra-TR non-dummy structures and supra-TR dummy structures, but does not include sub-TR non-dummy structures and sub-TR dummy structures.

[0092] Fig. 3C is in turn a cross-section of the layout diagram.308C , which is a HiR structure that has a BPR architecture type, according to some embodiments.

[0093] The layout diagram 308C is a HiR structure that features a buried busbar (BPR) architecture type. To be Fig. 3A to Fig. To achieve 3C compatibility with the BPR architecture type, structures (patterns) from the layout diagram are used. 308A circumcised.

[0094] In Fig. 3C are part of configuring the layout diagram. 308C With the BPR architecture type, various structures in some of the supra-TR layers have been removed. In particular, in Fig. 3C all structures in the metallization layers M10-M15 , the corresponding interconnection layers VIA9-VIA14 , in the RV layer and in the AP layer from the columns C1-C5 removed. In some embodiments, not all structures in the listed supra-TR layers are removed; that is, some, but not all, of the structures in the listed supra-TR layers are retained. In embodiments in which some, but not all, structures in the listed TR layers are retained, at least the via structure at the intersection of the interconnection layer is retained. VIA9 and the column 1 removed.

[0095] What the column C3 As far as this is concerned, removing all structures in the metallization layers leads to M10-M15 , the corresponding interconnection layers VIA9-VIA14 , the RV layer and the AP layer to create a via column 312C Sections in the columns C3 , C4 and C5 exhibits.

[0096] In Fig. 3C is a base area of ​​the sub-TR dummy SS via in the column C1essentially within a common base area of ​​the layout diagram components 308B included, which are located in the TR layer, namely the TSV in the column C1 , the G-connection in each of the columns C2-C4 and the TSV in the column C5 With respect to the X-axis, the Sub-TR-Dummy-SS_Durchfallierung is in the column C1 asymmetrical to the components of the layout diagram 208B positioned, which are located in the TR layer, namely the TSV in the column C1 , the G-connection in each of the columns C2-C4 and the TSV in the column C5 .

[0097] Fig. 3C also includes a pictogram 320C The pictogram 320C This is a simplified representation of the layout diagram. 308C , which reflects that the layout diagram 308C: represents a component with a BPR architecture type; and includes supra-TR non-dummy structures and sub-TR non-dummy structures, but does not include supra-TR dummy structures or sub-TR dummy structures.

[0098] Fig. 3D, in turn, is a top view of the layout diagram. 308D , which corresponds to the cross-section of the layout diagram 308B in Fig. 3B corresponds to the layout diagram. 308D does not include structures in layers below the layer VIA6 In the layout diagram 308E is part of the empty space in the column C1 with the reference mark 318D designated. Fig. 3D shows an approximate position of a cut pattern (CP) for the interconnection layer. VIA6 in the column C1 Although the layout diagram 308D no structures below the layer VIA6 includes, is in Fig. 2D nevertheless an approximate position of the supra-TR-SS via 310B (if otherwise included) shown.

[0099] Fig. 3E is, in turn, a top view of the layout diagram. 308E , which corresponds to the cross-section of the layout diagram 308C in Fig. 3C corresponds. The layout diagram 308E does not include structures in layers below the layer VIA6 Compared to Fig. Among other things, 3D models were created that represent a section of the via pillar 312C out of Fig. Represent 3C, added to an area that is the empty space 308D in the layout diagram 308D out of Fig. 3D corresponds. Although the layout diagram 308E no structures below the layer VIA6 includes, is in Fig. 2E nevertheless an approximate position of the sub-TR-SS via 310C (if otherwise included) shown.

[0100] With reference to Fig. 3F includes the circuit diagram 308F a high-resistance (HiR) resistor. Correspondences between sections of the circuit diagram. 308F and the columns in Fig. 3B are shown in the circuit diagram. 308F This is a path from the left terminal of the HiR resistor in the circuit diagram. 308F includes: a first node, the supra-TR sections in the column C2 exhibits; and a second node, the supra-TR sections in the column C1 exhibits a path from the right terminal of the HiR resistor in the circuit diagram. 308F includes: a third node, the supra-TR sections in the column C4 exhibits; and a fourth node, the supra-TR sections in the column C5 exhibits.

[0101] Fig. 3G is Fig. 3F similar, therefore the circuit diagram includes 308G a high-resistance (HiR) resistor. Correspondences between sections of the circuit diagram. 308G and the columns in Fig. 3C are shown in the circuit diagram. 308G designated. However, since the circuit diagram 308G the layout diagram 308C out of Fig. 3C corresponds, the latter having a BPR architecture type, and includes a path to the left terminal of the HiR resistor in the circuit diagram. 308G : a first node, the supra-TR sections in the column C2 exhibits; and a second node, the supra-TR sections in the column C1 features, and a Sub-TR-SS through-hole. 310C (which are in the column C1 (located) between the second node and a third node. A path to the right terminal of the HiR resistor in the circuit diagram. 308G includes: a fourth node, the supra-TR sections in the column C4 exhibits; and a fifth node, the supra-TR sections in the column C5 exhibits.

[0102] Fig. 4A is a cross-section of a layout diagram compatible with dual architecture. 408A , which represents a semiconductor device, according to some embodiments. Fig. 4B and Fig. 4C are cross-sections of layout diagrams compatible with simple architecture. 408B and 408C , which represent the corresponding semiconductor components, according to some embodiments. Fig. 4D and Fig. 4E are corresponding top views of layout diagrams compatible with simple architecture. 408D and 408E , which represent the corresponding semiconductor components, according to some embodiments. Fig. 4F and Fig. 4G corresponding circuit diagrams 408F and 408G according to some embodiments.

[0103] In particular, they correspond Fig. 4A, Fig. 4B and Fig. 4D each other. Fig. 4A, Fig. 4C and Fig. 4E correspond to each other. In some embodiments, the layout diagrams are 408D and 408E the Fig. 4D or Fig. 4E on a non-volatile, computer-readable medium (see Fig. 10) saved.

[0104] Fig. 4A-4E follow a similar numbering scheme as Fig. 2A-2G. Some components are different, even though they are identical. To facilitate the identification of identical but different components, the numbering convention uses 4-digit numbers for Fig. 4A-3E is used, while for Fig. 2A-2G are used as part numbers. For example, the element is... 412A in Fig. 4A one example of a via pillar and the corresponding element 212A in Fig. 2A is an example of a via pillar, where similarities are reflected by the common ending _12A and differences by the corresponding initial digit. 4 in Fig. 4A and Fig. 2 in Fig. 2A are reflected. For the sake of brevity, the discussion will focus more on differences between Fig. 4A-3E and Fig. 2A-2G focus on similarities.

[0105] The cross-section in Fig. 4A is in turn a cross-section of the layout diagram. 408A The layout diagram 408A It is compatible with dual architecture and can be selectively trimmed to either the layout diagram compatible with single architecture or the one that is compatible with single architecture. 408B out of Fig. 4B (which represents a metal-oxide-metal device (MOM device), e.g., a MOM capacitor, which has a non-BPR architecture type) or the layout diagram compatible with simple architecture 408C out of Fig. 4C (which represents a MOM component, e.g. a MOM capacitor, which has a BRP architecture type) to result.

[0106] The layout diagram is for discussion purposes. 408A into the columns C1 , C2 , C3 , C4 , C5 and C6 structured. The column C1 For example, it includes a first electrically conductive path that electrically couples the pad in pad layer AP to the buried pad in layer BAP. The first electrically conductive path in the column C1 includes, among other things: a Supra-TR-SS through-hole. 410A (1) the metallization layers M0-M15 and the corresponding interconnection layers VIAO-VIA14 spans; a Supra-TR-SS via 410A (1) the metallization layers M7-M9 and the corresponding interconnection layers VIA6-VIA8 spans; a Supra-TR-SS via 410A(2) the metallization layers M7-M9 and the corresponding interconnection layers VIA7-VIA8 overspanned; and Sub-TR-SS vias 26 (1) and 426 (2) which each contain the buried metallization layers BMO-BM5 and the buried interconnection layers BVIAO-BVIA4 span.

[0107] Furthermore, the column includes C6 a second electrically conductive path that electrically couples the pad in pad layer AP to the buried pad in layer BAP. The second electrically conductive path in the column C6 includes, among other things: a supra-TR-SS through-hole plating that connects the metallization layers M0-M15 and the corresponding interconnection layers VIAO-VIA14 spanned; and a sub-TR-SS through-hole that bridges the buried metallization layers BMO-BM5 and the corresponding buried interconnection layers BVIAO-BVIA4 overstretched.

[0108] Fig. 4B is in turn a cross-section of the layout diagram. 408B , which is a MOM capacitor that has a non-BPR architecture type, according to some embodiments.

[0109] In Fig. 4B are part of configuring the layout diagram. 408B According to a non-BPR architecture type, all structures in the various sub-TR layers from the columns C1-C5 removed. In some embodiments, not all structures in the listed sub-TR layers are removed; that is, some, but not all, of the structures in the listed sub-TR layers are retained. In such embodiments, where some, but not all, structures in the listed sub-TR layers are retained, at least the BVD structures in the columns are preserved. C1 and C6 removed.

[0110] In Fig. 4B is also part of configuring the layout diagram. 408Bwith the non-BPR architecture type, a first through-hole structure 416A at the intersection of the interconnection layer VIA6 and the column C1 It was removed. In addition, a second via structure was added at the intersection of the interconnection layer. VIA6 and the column C6 removed. Removing the first via structure 416A and the second via structure from the layout diagram 408A leads to the following in Fig. 4B: a first supra-TR first through-hole pillar 412B(1) in the columns C1-C2 , which are the metallization layers M7-M15 and the corresponding interconnection layers VIA6-VIA14 spanned; a second supra-TR first via pillar 412B(2) in the columns C5-C6 , which are the metallization layers M7-M15 and the corresponding interconnection layers VIA7-VIA14 overspanned; a first Supra-TR-SS via424(1) in the column C1 , which are the metallization layers M0-M6 and the corresponding interconnection layers VIA0 VIA5 spanned; and a second Supra-TR-SS via 424(2) in the column C6 , which are the metallization layers MO-M6 and the corresponding interconnection layers VIA0-­ VIA5 overstretched.

[0111] Each of the supra-TR first SS vias 424(1) and 424(2) in the corresponding columns C1 C6 is a supra-TR dummy structure and is used as an artifact of the layout diagram. 408B Considering the layout diagram compatible with dual architecture 408A based on this. Therefore, the supra-TR-first-SS_vias are 424 (1) in the column C1 and the Supra-TR-first-SS_via 424(2) in the column C6 for compatibility with the layout diagram 408B ​included, which is otherwise compatible with the BPR architecture type. Unlike the dummy supra-TR first SS vias. 424 (1) and 424 (2) the supra-TR first SS vias are shown in the corresponding columns C1 and C6 , the corresponding sections of the via pillars 412B (1) and 412B (2) form, referred to as supra-TR non-dummy structures. Although such dummy structures are artifacts, i.e., instances of the third type of dummy structure, such dummy structures may nevertheless be useful in some embodiments insofar as they serve as an indication that the layout diagram 408B on a layout diagram compatible with dual architecture 408A based.

[0112] Fig. 4B also includes a pictogram 420B The pictogram 420B This is a simplified representation of the layout diagram.408B , which reflects that the layout diagram 408B : represents a component with a non-BPR architecture type; and includes supra-TR non-dummy structures and supra-TR dummy structures, but does not include sub-TR non-dummy structures and sub-TR dummy structures.

[0113] Fig. 4C is in turn a cross-section of the layout diagram. 408C , which is a MOM capacitor having a BPR architecture type, according to some embodiments.

[0114] In Fig. 4C are part of configuring the layout diagram. 408C With the BPR architecture type, various structures in some of the supra-TR layers have been removed. In particular, in Fig. 4C all structures in the metallization layers M10-M15 , the corresponding interconnection layers VIA9-VIA14 , in the RV layer and in the AP layer from the columns C1-C5 removed. In some embodiments, not all structures in the listed supra-TR layers are removed; that is, some, but not all, of the structures in the listed supra-TR layers are retained. In embodiments in which some, but not all, structures in the listed supra-TR layers are retained, at least the via structures at the intersections of the interconnection layer are retained. VIA9 and each of the columns C1 and C6 removed. The layout diagram 408C includes a lower connection 422 (2) and an upper connection 422 (1) of a capacitor.

[0115] What the column C1 As far as this is concerned, removing all structures in the metallization layers leads to M10-M15 , the corresponding interconnection layers VIA9-VIA14 , the RV layer and the AP layer to create a first via column 412C(1) Sections in the columns C1 and C2 features, and that a second via column 412C (2) Sections in the columns C5 and C6 exhibits.

[0116] Fig. 4C also includes a pictogram 420C The pictogram 420C This is a simplified representation of the layout diagram. 408C , which reflects that the layout diagram 408C : represents a component with a BPR architecture type; and includes supra-TR non-dummy structures and sub-TR non-dummy structures, but does not include supra-TR dummy structures or sub-TR dummy structures.

[0117] Fig. 4D is, in turn, a top view of the layout diagram. 408D , which corresponds to the cross-section of the layout diagram 408B in Fig. 4B corresponds to the layout diagram. 408D does not include structures in layers above the layer M7 and below the layerM0 The layout diagram 408 This simplifies the process to focus on the plates of the MOM capacitor. However, in Fig. 4D approximate positions of the dummy Supra-TR-SS via 424 (1) in the column C1 and the dummy Supra-TR-SS via 424 (1) in the column C6 (if otherwise included) shown.

[0118] Fig. 4E is, in turn, a top view of the layout diagram. 408E , which corresponds to the cross-section of the layout diagram 408C in Fig. 4C corresponds. The layout diagram 408E does not include structures in layers above the layer M7 The layout diagram 408 This simplifies the process to focus on the plates of the MOM capacitor. However, in Fig. 4E Approximate positions of structures (if otherwise included) are shown as follows: one position of the dummy sub-TR-SS via. 426(1) in the column C1; and a position of the dummy sub-TR-SS via 426(2) in the column C6 .

[0119] With reference to Fig. The circuit diagram includes 4F. 408F a capacitor C. Correspondences between sections of the circuit diagram. 408F and the columns in Fig. 4B are shown in the circuit diagram. 408F denoted. A path from a lower terminal 422(2) of capacitor C in the circuit diagram 408F includes a supra-TR through-hole plating column 412B(1) , where the latter supra-TR sections are in each of the columns C2 and C1 includes a path from an upper terminal 422(1) of capacitor C in the circuit diagram 408F includes a supra-TR through-hole plating column 412B(2) , where the latter supra-TR sections are in each of the columns C5 and C6 includes.

[0120] Fig. 4G is Fig. 4F similar, therefore the circuit diagram includes408G a capacitor C. Correspondences between sections of the circuit diagram. 408G and the columns in Fig. 4C are shown in the circuit diagram. 408F denoted. A path from a lower terminal 422(2) of capacitor C in the circuit diagram 408G includes: a Supra-TR through-hole plating column 412C(1) , the latter having a supra-TR section in each of the columns C2 and C1 includes; and the Sub-TR-SS via 426(1) , the sections in the column C1 exhibits a path from an upper terminal 422(1) of capacitor C in the circuit diagram 408F includes: a Supra-TR through-hole plating column 412C(2) , where the latter supra-TR sections are in each of the columns C5 and C6 includes; and the Sub-TR-SS via 426(2) , the sections in the column C6 exhibits.

[0121] Fig. 5A is a cross-section of a layout diagram compatible with dual architecture. 508A , which represents a semiconductor device, according to some embodiments. Fig. 5B and Fig. 5C are cross-sections of corresponding layout diagrams compatible with simple architecture. 508B and 508C according to some embodiments. Fig. 5D and Fig. 5E are corresponding top-down views of layout diagrams compatible with simple architecture. 508D and 508E , which represent the corresponding semiconductor components, according to some embodiments. Fig. 5F and Fig. 5G corresponding circuit diagrams 508F and 508G according to some embodiments.

[0122] Fig. 5A-5C follow a similar numbering scheme as Fig. 2A-2G. Some components are different, even though they are identical. To facilitate the identification of identical but different components, the numbering convention uses numbers in the 5s for Fig. 5A-3E is used, while for Fig. 2A-2G are used as part numbers. For example, the element is... 512A (2) in Fig. 5A one example of a via pillar and the corresponding element 212A in Fig. 2A is an example of a via pillar, where similarities are reflected by the common ending _12A and differences by the corresponding initial digit. 5 in Fig. 5A and Fig. 2 in Fig. 2A are reflected. For the sake of brevity, the discussion will focus more on differences between Fig. 5A-5E and Fig. 2A-2G focus on similarities.

[0123] The cross-section in Fig. 5A is in turn a cross-section of the layout diagram. 508A The layout diagram 508A It is compatible with dual architecture and can be selectively trimmed to either the layout diagram compatible with single architecture or the one that is compatible with single architecture. 508B out of Fig. 5B (which represents an inductor having a non-BPR architecture type) or the layout diagram compatible with simple architecture 508C out of Fig. 5C (which represents an inductor that has a BPR architecture type).

[0124] The layout diagram is for discussion purposes. 508A into the columns C1 , C2 , C3 , C4 and C5 structured. The column C1 includes a first electrically conductive path that forms a first end of a supra-TR via column 512A(1) electrically with a first end of a sub-TR via column 512A(2)couples. The first electrically conductive path in the column C1 includes, among other things: a Supra-TR-SS through-hole. 510A , which are the metallization layers M0-M13 and the corresponding interconnection layers VIAO-VIA13 overspanned; and a Sub-TR-SS through-connection 510A(3) , which include the buried metallization layers BMO-BM3 and the corresponding buried interconnection layers BVIA0-BVTA3 spanned. The column C5 includes a second electrically conductive path that forms a second end of the supra-TR first via column 512A(1) electrically with a second end of a sub-TR second via pillar 512A(2) couples. The second electrically conductive path in the column C5 includes, among other things: a Supra-TR-SS through-hole. 510A(2) , which are the metallization layers M0-M13 and the corresponding interconnection layers VIA0-VIA13 overspanned; and a sub-TR-SS via. 510A(4) , which are the buried metallization layers BM0-BM3 and the corresponding buried interconnection layers BVIA0-BVIA3 overstretched.

[0125] Fig. 5B is in turn a cross-section of the layout diagram. 508B , which is an inductor having a non-BPR architecture type, according to some embodiments.

[0126] In Fig. 5B are part of configuring the layout diagram. 508B According to a non-BPR architecture type, all structures in the various sub-TR layers from the columns C1-C5removed. In some embodiments, not all structures in the listed sub-TR layers are removed; that is, some, but not all, of the structures in the listed sub-TR layers are retained. In such embodiments, where some, but not all, structures in the listed sub-TR layers are retained, at least the BVD structures in the columns are preserved. C1 and C5 removed. The layout diagram 508B This includes, among other things, non-dummy supra-TR structures, which include: supra-TR SS vias 510B(1) and 510B(2) ; and a non-dummy Supra-TR via pillar 512(1) .

[0127] Fig. 5B also includes a pictogram 520B The pictogram 520B This is a simplified representation of the layout diagram. 508B , which reflects that the layout diagram 508B: represents a component with a non-BPR architecture type; and includes supra-TR non-dummy structures, but does not have supra-TR dummy structures, nor does it have sub-TR non-dummy structures or sub-TR dummy structures.

[0128] Fig. 5C is in turn a cross-section of the layout diagram. 508C , which is an inductor having a BPR architecture type, according to some embodiments.

[0129] In Fig. 5C are part of configuring the layout diagram. 508C With the BPR architecture type, various structures in some of the supra-TR layers have been removed. In particular, in Fig. 5C all structures in the metallization layers M10-M15 , the corresponding interconnection layers VIA9-VIA14 , in the RV layer and in the AP layer from the columns C1-C5 removed. In some embodiments, not all structures in the listed supra-TR layers are removed; that is, some, but not all, of the structures in the listed supra-TR layers are retained. In embodiments in which some, but not all, structures in the listed supra-TR layers are retained, at least the via structures at the intersections of the interconnection layer are retained. VIA9 and each of the columns C1 and C5 removed. What the column C1 As far as this is concerned, removing all structures in the metallization layers leads to M10-M15 , the corresponding interconnection layers VIA9-VIA14 , the RV layer and the AP layer to form a via column 512C(2) .

[0130] In Fig. 5C are also part of configuring the layout diagram. 508CAccording to the BPR architecture type, the following additional structures have been removed: the VD structures in each of the columns C1 and C5 ; the MD structures in each of the columns C1 and C5 ; the via structures at the intersections of the column C1 and the interconnection layers VIA0-VIA8; and the via structures at the intersections of the column C5 and the interconnection layers VIAO-VIA8 Removing the other structures results in the following at the intersections of the column: C1 and the metallization layers M0-M9 A supra-TR routing arrangement. The layout diagram. 508C includes, among other things, dummy supra-TR structures (including supra-TR SS vias). 510C(1) and 510C(2) ) and non-dummy sub-TR structures, including: sub-TR vias 510C(3) and 510C(4) ; and a sub-TR via 512C(2) .

[0131] Fig. 5C also includes a pictogram 520C The pictogram 520C This is a simplified representation of the layout diagram. 508C , which reflects that the layout diagram 508C : represents a component with a BPR architecture type; and includes supra-TR non-dummy structures and sub-TR non-dummy structures, but does not include supra-TR dummy structures or sub-TR dummy structures.

[0132] Fig. 5D is, in turn, a top view of the layout diagram. 508D , which corresponds to the cross-section of the layout diagram 508B in Fig. 5B corresponds.

[0133] The layout diagram 508D does not include structures in layers below the layer M14 and represents one of the layers M14 , M15 and AP. Although the layout diagram 508D no structures in layers below the layer M14 included, are nevertheless in Fig. 5D approximate underlying positions of the non-dummy supra-TR-SS via 510B (1) in the column C1 and the non-dummy Supra-SS via 510B (2) in the column C5 (if otherwise included) shown.

[0134] Fig. 5E is, in turn, a top view of the layout diagram. 508E , which corresponds to the cross-section of the layout diagram 508C in Fig. 5C corresponds to the layout diagram. 508E It does not include any structures in layers above layer BM4 and represents one of the layers BM4, BM5, and BAP. Although the layout diagram 508E Although it does not include structures in layers above layer BM4, they are nevertheless in Fig. 5D approximate overlying positions of the non-dummy sub-TR-SS via 510C(3) in the column C1 and the non-dummy Supra-TR-SS via 510C(4) in the column C5 (if otherwise included) shown.

[0135] With reference to Fig. The circuit diagram includes 5F. 508F an inductor IND correspondences between sections of the circuit diagram 508F and the columns in Fig. 5B are shown in the circuit diagram. 508F This refers to a path from an upper terminal of the inductor IND in the circuit diagram. 508F includes a supra-TR through-hole plating column 510B (1) where the latter supra-TR sections are in the column C1 includes, at the top of which is a TTLV is arranged. A path from a lower terminal of the inductor IND in the circuit diagram. 508F includes a supra-TR through-hole plating column 510B(2) , where the latter supra-TR sections are in the column C6 includes, at the top of which is a TTLV is arranged.

[0136] Fig. 5G is Fig. 5F similar, therefore the circuit diagram includes 508G an inductor IND correspondences between sections of the circuit diagram508G and the columns in Fig. 5C are shown in the circuit diagram. 508G This refers to a path from an upper terminal of the inductor IND in the circuit diagram. 508G includes a sub-TR through-hole plating column 510C(3) , where the latter Sub-TR sections are in the column C1 includes, at the top of which is a TTLV is arranged. A path from a lower terminal of the inductor IND in the circuit diagram. 508G includes a sub-TR through-hole plating column 510C (2) where the latter Sub-TR sections are in the column C6 includes, at the top of which is a TTLV is arranged.

[0137] Fig. 6A is a cross-section of a layout diagram compatible with dual architecture. 608A , which represents a semiconductor device, according to some embodiments. Fig. 6B and Fig. 6C are cross-sections of corresponding layout diagrams compatible with simple architecture. 608B and 608Caccording to some embodiments. Fig. 6D and Fig. 6E are corresponding top views of layout diagrams compatible with simple architecture. 608D and 608E , which represent the corresponding semiconductor components, according to some embodiments. Fig. 6F and Fig. 6G are corresponding circuit diagrams 608F and 608G according to some embodiments.

[0138] Fig. 6A-6C follow a similar numbering scheme as Fig. 2A-2G. Some components are different, even though they are identical. To facilitate the identification of identical but different components, the numbering convention uses 6-digit numbers for Fig. 6A-3E is used, while for Fig. 2A-2G are used as part numbers. For example, the element is... 612A in Fig. 6A a sample of a via pillar and the corresponding element 212A in Fig. 2A is an example of a via pillar, where similarities are reflected by the common ending _12A and differences by the corresponding initial digit. 6 in Fig. 6A and Fig. 2 in Fig. 2A are reflected. For the sake of brevity, the discussion will focus more on differences between Fig. 6A-6E and Fig. 2A-2G focus on similarities.

[0139] The cross-section in Fig. 6A is in turn a cross-section of the layout diagram. 608A The layout diagram 608A It is compatible with dual architecture and can be selectively trimmed to either the layout diagram compatible with single architecture or the one that is compatible with single architecture. 608B out of Fig. 4B (which represents a metal-insulator-metal device (MIM device), e.g., a MIM capacitor, which has a non-BPR architecture type) or the layout diagram compatible with simple architecture 608C out of Fig. 6C (which represents a MIM capacitor having a BPR architecture type). In some embodiments, the MIM capacitor is a super-high density (SHD) type MIM capacitor (an SHDMIM capacitor).

[0140] The layout diagram is for discussion purposes. 608A into the columns C1 , C2 , C3 and C4 structured. The column C4 For example, it includes a first electrically conductive path that electrically couples the pad in pad layer AP to the buried pad in layer BAP. The first electrically conductive path in the column C4 includes, among other things: a first supra-TR first SS through-hole 612A(1) , which are the metallization layers M0-M15 and the corresponding interconnection layers VIAO-VIA14 spanned; and a first sub-TR-first-SS via spanning the buried metallization layers BM0-BM5 and the corresponding buried interconnection layers BVIAO-BVIA4 overstretched.

[0141] In Fig. 6A includes the column C3 a second electrically conductive path that electrically couples the pad in pad layer AP to the buried pad in layer BAP. The second electrically conductive path in the column C3 includes, among other things: a second supra-TR second SS through-hole. 610A(2) , which are the metallization layers M0-M15 and the corresponding interconnection layers VIAO-VIA14 spanned; and a second sub-transmission SS through-hole, which covers the buried metallization layers BM0-BM5 and the corresponding buried interconnection layers BVIAO-BVIA4 overstretched. Together they represent the first Supra-TR-SS through-hole. 610A (1) and the second supra-TR first via pillar 612A(2) a supra-TR through-hole plating column 612A dar.

[0142] The column C1 It includes a third electrically conductive path that electrically couples the pad in pad layer AP to the buried pad in layer BAP. The third electrically conductive path in the column C3 includes, among other things: a third supra-TR second SS through-hole, which connects the metallization layers MO-M15 and the corresponding interconnection layers VIAO-VIA14 spanned; and a third sub-TR-second-SS via spanning the buried metallization layers. BM0-BM5 and the corresponding buried interconnection layers BVIAO-BVIA4 overstretched.

[0143] The layout diagram 608A further includes a supra-TR-MIM structure with superhigh density (SHD) at the intersection of the slits C2 and the RV layer and a sub-TR-SHD-MIM structure at the intersection of the column C2and the BRV layer. Corresponding sections of the Supra-TR-SHD-MIM structure are electrically connected to the RV contact structures in each of the columns. C1 and C3 coupled. Corresponding sections of the Sub-TR-SHD-MIM structure are electrically coupled to the BRV contact structures in each of the columns. C1 and C3 coupled.

[0144] Fig. 6B is in turn a cross-section of the layout diagram. 608B , which is a MIM capacitor that has a non-BPR architecture type, according to some embodiments.

[0145] In Fig. 6B are part of configuring the layout diagram. 608B According to a non-BPR architecture type, all structures in the various sub-TR layers from the columns C1 - C4removed. In some embodiments, not all structures in the listed sub-TR layers are removed; that is, some, but not all, of the structures in the listed sub-TR layers are retained. In such embodiments, where some, but not all, structures in the listed sub-TR layers are retained, at least the BVD structures in the columns are preserved. C1 , C3 and C4 removed.

[0146] Fig. 6B also includes a pictogram 620B The pictogram 620B This is a simplified representation of the layout diagram. 608B , which reflects that the layout diagram 608B : represents a component with a non-BPR architecture type; and includes supra-TR non-dummy structures, but does not include supra-TR dummy structures, sub-TR non-dummy structures, or sub-TR dummy structures.

[0147] Fig. 6C is in turn a cross-section of the layout diagram. 608C , which is a MOM capacitor having a BPR architecture type, according to some embodiments.

[0148] In Fig. 6C are part of configuring the layout diagram. 608C With the BPR architecture type, various structures in some of the supra-TR layers have been removed. In particular, in Fig. 6C all structures in the metallization layers M10-M15 , the corresponding interconnection layers VIA9-VIA14 , in the RV layer and in the AP layer from the columns C1-C5 removed. In some embodiments, not all structures in the listed supra-TR layers are removed; that is, some, but not all, of the structures in the listed supra-TR layers are retained. In embodiments in which some, but not all, structures in the listed TR layers are retained, at least the via structures at the intersections of the interconnection layer are retained. VIA9 and each of the columns C1 , C3 and C5 removed.

[0149] By removing the supra-TR structures in the interconnection layer VIA9 and the following results from this: a supra-TR-SS through-hole in the column C4 (the metallization layers MO-M9 and the corresponding interconnection layers VIAO-VIA8 spanning), which is a supra-TR dummy structure; and a sub-TR SS via in the column C4(the metallization layers BM0-BM5 and the corresponding buried interconnection layers BVIA0-BVTA4 (spanning), which is a sub-TR dummy structure. It should be noted that the supra-TR dummy structure is in column C4 and the sub-TR dummy structure in the column C4 electrically, among other things, through a TSV structure in the TR layer in the column C4 are coupled. Such dummy structures are considered artifacts of the layout diagram. 608B Considering the layout diagram compatible with dual architecture 608A based. Although such dummy structures are artifacts, i.e., examples of the third type of dummy structure, they can nevertheless be useful in some embodiments insofar as they serve as an indication that the layout diagram 608C on a layout diagram compatible with dual architecture 608A based.

[0150] In Fig. 6C is a base surface of the supra-TR dummy structure and the sub-TR dummy structure in the column C4 essentially within a common base area of ​​the layout diagram components 608C included, which are located in the TR layer, namely the TSV in each of the columns C1 , C3 and C4 With respect to the x-axis, the supra-TR dummy structure and the sub-TR dummy structure are in the column. C4 asymmetrical to the components of the layout diagram 208B positioned, which are located in the TR layer, namely the TSV in each of the columns C1 , C3 and C4 .

[0151] Fig. 6C also includes a pictogram 620C The pictogram 620C This is a simplified representation of the layout diagram. 608C , which reflects that the layout diagram 608C: represents a component with a BPR architecture type; and includes Supra-TR non-dummy structures, Supra-TR dummy structures, Sub-TR non-dummy structures and Sub-TR dummy structures.

[0152] Fig. 6D is, in turn, a top view of the layout diagram. 608D , which corresponds to the cross-section of the layout diagram 608B in Fig. 6B corresponds to the layout diagram. 608D includes structures in layer RV. Although the layout diagram 608D They do not include structures in layers other than layer RV, but are nevertheless in Fig. 6D approximate positions of the underlying non-dummy Supra-TR-SS vias 610B (1) in the column C1 , 610B (2) in the column C3 and 610B (3) in the column C4 (if otherwise included) shown.

[0153] Fig. 6E is again a top view of the layout diagram. 608E , which corresponds to the cross-section of the layout diagram608C in Fig. 6C corresponds to the layout diagram. 608E includes structures in layer BRV. Although the layout diagram 608E They do not include structures in layers other than layer BRV, but are nevertheless in Fig. 6D approximate positions of the overlying non-dummy sub-TR-SS vias 610C(4) in the column C1 , 610C(5) in the column C3 and 610C(6) in the column C4 and the overlying non-dummy supra-TR-SS vias 610C(1) in the column C1 , 610C(2) in the column C3 and 610C(3) in the column C4 (if otherwise included) shown.

[0154] With reference to Fig. The circuit diagram includes 6F. 608F A MIM capacitor of type MIM0. Correspondences between sections of the circuit diagram. 608F and the columns in Fig. 6B are shown in the circuit diagram. 608FDesignated. A path from an upper terminal of the capacitor MIM in the circuit diagram. 608F includes a supra-TR through-hole plating column 610B (1) in the column C1 , at the top of which a TTLV is arranged. A path from a lower terminal of the capacitor MIM in the circuit diagram. 608F includes a supra-TR through-hole plating column 610B (2) in the column C3 and a Supra-TR through-hole plating column 610B (3) in the column C6 , at the top of which a TTLV is arranged.

[0155] Fig. 6G is Fig. 6F similar, therefore the circuit diagram includes 608G a capacitor MIM correspondences between sections of the circuit diagram 608G and the columns in Fig. 6C are shown in the circuit diagram. 608G Designated. A path from an upper terminal of the capacitor MIM in the circuit diagram. 608G includes a sub-TR through-hole plating column 610C(3) and a supra-TR through-hole pillar 610C (1) in the column C1 A path from one of the upper terminals of capacitor MIM in the circuit diagram 608G includes a sub-TR through-hole plating column 610C (2) and a Supra-TRA through-hole plating column 610C (2) in the column C6 .

[0156] Fig. 7A is a cross-section of a layout diagram compatible with dual architecture. 708A , which represents a semiconductor device, according to some embodiments. Fig. 7B and Fig. 7C are cross-sections of corresponding layout diagrams compatible with simple architecture. 708B and 708C according to some embodiments. Fig. 7D and Fig. 7E are corresponding top views of layout diagrams compatible with simple architecture. 708D and 708E according to some embodiments. Fig. 7F and Fig. 7G are corresponding circuit diagrams708F and 708G according to some embodiments. Fig. 7H and Fig. 7I are cross-sections of corresponding layout diagrams compatible with simple architecture. 708H and 7081 according to some embodiments.

[0157] In particular, they correspond Fig. 7B, Fig. 7D and Fig. 7F each other. Fig. 7C, Fig. 7E and Fig. 7G correspond to each other. In some embodiments, the layout diagrams are 708D and 708E the Fig. 7D or Fig. 7E on a non-volatile, computer-readable medium (see Fig. 10) saved.

[0158] Fig. 7A-7G follow a similar numbering scheme as Fig. 2A-2G. Some components are different, even though they are identical. To facilitate the identification of identical but different components, the numbering convention uses 7-digit numbers for Fig. 7A-3E is used, while for Fig. 2A-2G are used as part numbers. For example, the element is... 710A in Fig. 7A an example of an SS through-hole and the corresponding element 210A in Fig. 2A is an example of an SS through-hole connection, where similarities are reflected by the common ending _10A and differences by the corresponding initial digit. 7 in Fig. 7A and Fig. 2 in Fig. 2A are reflected. For the sake of brevity, the discussion will focus more on differences between Fig. 7A-7C and Fig. 2A-2G focus on similarities.

[0159] The cross-section in Fig. 7A is again a cross-section of the layout diagram. 708A The layout diagram 708A It is compatible with dual architecture and can be selectively trimmed to either the layout diagram compatible with single architecture or the one that is compatible with single architecture. 708B out of Fig. 4B (which represents a metal-oxide-semiconductor field-effect transistor (MOSFET) of a non-BPR architecture type) or the layout diagram compatible with simple architecture 708C out of Fig. 7C (which represents a MOSFET of a BPR architecture type). The layout diagram is shown for discussion purposes. 708A into the columns C1 , C2 , C3 , C4 , C5 and C6 structured.

[0160] Fig. 7B is in turn a cross-section of the layout diagram. 708B , which is a MOSFET that has a non-BPR architecture type, according to some embodiments.

[0161] In Fig. 7B are part of configuring the layout diagram. 708B According to a non-BPR architecture type, all structures in the various sub-TR layers from the columns C1-C5 The layout diagram has been removed. 708Bincludes Supra-TR-SS vias 718B(1) in the column C1 and 710B(2) in the column C6 In some embodiments, not all structures in the listed sub-TR layers are removed; that is, some, but not all, of the structures in the listed sub-TR layers are preserved. In such embodiments, where some, but not all, structures in the listed sub-TR layers are preserved, at least the BVD structures in the columns are retained. C1 and C6 removed.

[0162] Fig. 7B also includes a pictogram 720B The pictogram 720B This is a simplified representation of the layout diagram. 708B , which reflects that the layout diagram 708B: represents a component with a non-BPR architecture type; and includes supra-TR non-dummy structures, but does not include supra-TR dummy structures, sub-TR non-dummy structures, or sub-TR dummy structures.

[0163] Fig. 7C is in turn a cross-section of the layout diagram. 708C , which is an inductor having a BPR architecture type, according to some embodiments.

[0164] In Fig. 7C are part of configuring the layout diagram. 708C With the BPR architecture type, various structures in some of the supra-TR layers have been removed. In particular, in Fig. 7C all structures in the metallization layers M10-M15 , the corresponding interconnection layers VIA9-VIA14 , in the RV layer and in the AP layer from the columns C1-C5 has been removed.

[0165] Fig. 7C also includes a pictogram 720C The pictogram 720CThis is a simplified representation of the layout diagram. 708C , which reflects that the layout diagram 708C : represents a component with a BPR architecture type; and includes supra-TR non-dummy structures and sub-TR non-dummy structures, but does not include supra-TR dummy structures or sub-TR dummy structures.

[0166] Fig. 7D is, in turn, a top view of the layout diagram. 708D , which corresponds to the cross-section of the layout diagram 708B in Fig. 7B corresponds to this. For the sake of simplicity, the layout diagram includes 708D no structures in the TR layer, the layer M0 and the VD / VG layer.

[0167] Fig. 7E is again a top view of the layout diagram. 708E , which corresponds to the cross-section of the layout diagram 708C in Fig. 7C corresponds. For the sake of simplicity, the layout diagram includes 708E no structures in the TR layer, the layer M0and the VD / VG layer. Although the layout diagram 708E no other structures than the structures in the TR layer, the layer M0 and the VD / VG layer, are nevertheless in Fig. 7E Approximate underlying positions of BVD structures in layer BVD / BVG and structures in layer BM0 210B (if otherwise included) shown.

[0168] With reference to Fig. The circuit diagram includes 7F. 708F a circuit 728 e.g., an inverter circuit. Correspondences between sections of the circuit diagram. 708F and the columns in Fig. 7B are shown in the circuit diagram. 708F denoted. A path which is part of the circuit 728 a first reference voltage, e.g. VDD provides includes a Supra-TR-SS through-hole connection 710B(1) in the column C1 A path which the circuit 728 a second reference voltage, e.g. VSS provides includes a Supra-TR-SS through-hole connection 710B(2) in the column C6 .

[0169] With reference to Fig. The circuit diagram includes 7G. 708G a circuit 728 e.g., an inverter circuit. Correspondences between sections of the circuit diagram. 708G and the columns in Fig. 7C are shown in the circuit diagram. 708G denoted. A path which is part of the circuit 728 a first reference voltage, e.g. VDD provides includes a Supra-TR-SS through-hole connection 710C (1) and a Sub-TR-SS through-hole 710C(3) in the column C1 A path which the circuit 728 a second reference voltage, e.g. VSS provides includes a Supra-TR-SS through-hole connection 710C(2) and a Sub-TR-SS through-hole 710C(4) in the column C6 .

[0170] Fig. 8 is a flowchart of a process 800for manufacturing a semiconductor device according to some embodiments.

[0171] According to some embodiments, the method can 800 for example, using an EDA system 1000 ( Fig. 10, discussed below) and a manufacturing system 1100 for integrated circuits (IC manufacturing system) ( Fig. 11, discussed below) be implementable. Examples of a semiconductor device that can be implemented according to the procedure 800 which can be manufactured, include the semiconductor component 100 out of Fig. 1. Semiconductor devices corresponding to various layout diagrams disclosed herein, or the like.

[0172] In Fig. 8A includes the procedure 800 block 802 - 804 . In block 802A layout diagram is generated that includes, among other things, one or more of the layout diagrams disclosed herein or the like. According to some embodiments, Block 802 for example, using the EDA system 1000 ( Fig. 10, discussed below) will be implemented. After block 802 The process goes to block 804 above.

[0173] In block 804 Based on the layout diagram, (A) one or more photolithographic exposures will be performed, (B) one or more semiconductor masks will be fabricated, and / or (C) one or more components will be fabricated in a layer of a semiconductor device. See the discussion below regarding Fig. 11.

[0174] Fig. Figure 9 is a flowchart of a process for manufacturing a semiconductor device according to some embodiments.

[0175] In particular, the flowchart in Fig. 9 further blocks, which according to one or more embodiments in block 802 out of Fig. 8 are included. Fig. Block 9 includes 802 block 902-908 . In block 902 Structures representing the corresponding components of a transistor are created in a transistor layer of the layout diagram. Examples of transistor components in the transistor layer are the B-terminal, the D-terminal, the G-terminal, and the S-terminal in the TR layer. Fig. 2A. After block 902 The process goes to block 904 above.

[0176] In block 904Structures representing supra-TR structures are created in corresponding layers of the layout diagram above the transistor layer. These structures are compatible with both non-buried busbar (non-BPR) and buried busbar (BPR) architectures. Examples of such supra-TR structures are shown in each of the columns. C1-C5 in Fig. 2A. From block 904 The process continues to block 906 .

[0177] In block 906 Structures representing sub-TR structures are created in corresponding layers of the layout diagram below the transistor layer (sub-TR layers) that are compatible with the semiconductor device exhibiting the BPR architecture. Examples of such sub-TR structures are the sub-TR structures in each of the columns. C1-C5 in Fig. 2A. From block 906 The process continues to block 908 .

[0178] In block 908 One of the following steps is performed: if the semiconductor device is to have the non-BPR architecture, then structures representing sub-TR structures compatible with the BPR architecture type are removed; or, if the semiconductor device is to have the BPR architecture, then structures representing supra-TR structures compatible with the non-BPR architecture type are removed. An example of removing structures representing sub-TR structures to be compatible with the non-BPR architecture type is removing structures representing sub-TR structures from the layout diagram. 208A in Fig. 2A as part of generating the layout diagram 208B in Fig. 2B. An example of removing some of the structures that represent supra-TR structures in order to be consistent with the BPR architectural type is the removal of all structures located in the metallization layers. M10-M15 , the corresponding interconnection layers VIA9-VIA14 , representing supra-TR structures of the RV layer and the AP layer, from the columns C1-C5 of the layout diagram 208A in Fig. 2A as part of generating the layout diagram 208C in Fig. 2C.

[0179] According to the numerical order, the following Fig. 10 on Fig. 9. However, the discussion will not be continued with Fig. 10, but with Fig. 12A-12B continued. After discussion of Fig. 12A-12B returns to the discussion Fig. 10 and Fig. 11 back.

[0180] According to some embodiments, the method can consist of Fig. 12A-12B, for example, using the manufacturing system 1100for integrated circuits (IC manufacturing system) ( Fig. 11, discussed below) are implemented. Examples of a semiconductor device implemented according to the procedure 800 which can be manufactured, include the semiconductor component 100 out of Fig. 1. Semiconductor devices corresponding to various layout diagrams disclosed herein, or the like.

[0181] The procedure from Fig. 12A-12B includes block 1202-1206 and 1236 .

[0182] In block 1202 Components of transistors in the transistor layer of a semiconductor device are formed based on a layout diagram compatible with a simple architecture, which was generated by clipping one compatible with a dual architecture. Examples of components formed in the transistor layer include components corresponding to the G, D, S, or B terminals, or the TTLV out of Fig. 2A and Fig. 2C or similar. From block 1202 The process continues to block 1204 .

[0183] After block 1204 The process can either be done with a block 1206 or with a block 1236 to be continued, as illustrated by the fact that Block 1204 shown as a symbol for a logical exclusive-OR (XOR) branch. The discussion will begin with block 1206 continued, but later returns to Block 1236 back. Accordingly, it is assumed here that the process follows block 1. 1204 with block 1206 will be continued.

[0184] The flow path of block 1204 to block 1206 This reflects the fact that the layout diagram compatible with simple architecture features the BPR architecture type, which includes sub-TR layers and supra-TR layers. Accordingly, in block 1206Further components are manufactured according to the BPR architecture type, which includes sub-TR layers and supra-TR layers. Examples of the BPR architecture type include semiconductor devices that follow the layout diagrams from Fig. 2C, Fig. 3C, Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C or similar block 1206 includes block 1208-1220 The process continues to block 1208 above.

[0185] In block 1208 Various non-dummy sub-TR structures are formed in corresponding sub-TR layers and coupled to corresponding transistor components in the TR layer. Examples of non-dummy sub-TR structures include structures corresponding to the via pillar. 210C(4) in Fig. 2C, the via pillar 310C in Fig. 3C, the through-hole plating columns 426C(1) and 426C(2) in Fig. 4C, the SS through-holes 510C(3) and 510C(4) in Fig. 5C, the SS through-holes 610C(4) and 610C (5) in Fig. 6C, the SS through-holes 710C(3) and 710C(4) in Fig. 7C or similar. From block 1208 The process continues to block 1210 .

[0186] In block 1210 In corresponding Supra-TR layers, various dummy Supra-TR structures are formed, which are corresponding artifacts resulting from the dual-architecture design suitable for adaptation to the non-BPR architecture type. Examples of dummy Supra-TR structures include structures that correspond to the Supra-TR SS vias in the column C1 in Fig. 2C, the SS through-holes 510C(1) and 510C (2) in Fig. 5C, the SS through-hole 610(C) in Fig. 6C or similar. From block 1210 The process continues to block 1212 .

[0187] In block1212 In corresponding sub-TR layers, various dummy sub-TR structures are formed, representing artifacts resulting from the dual-architecture design suitable for adaptation to the non-BPR architecture type. Examples of dummy sub-TR structures include structures corresponding to the sub-TR SS via. 610C(6) in Fig. 6C or similar. After block 1212 The process goes to block 1214 in Fig. 12B over.

[0188] After block 1214 in Fig. 12B, the process can either be done with block 1216 , with block 1218 or with a block 1220 to be continued, as illustrated by the fact that Block 1204 shown as a symbol for a logical OR branch. The discussion begins with block 1216 continued, but later returns to each of the blocks 1218 and 1220back. Accordingly, it is assumed here that the process follows block 1. 1214 with block 1216 will be continued.

[0189] In block 1216 The various dummy supra-TR structures are positioned asymmetrically relative to the various non-dummy sub-TR structures. Examples of dummy supra-TR structures positioned asymmetrically relative to the various non-dummy sub-TR structures include structures corresponding to the dummy supra-TR SS via. 610C(3) correspond to the non-dummy sub-TR-SS vias, which are asymmetrical to the non-dummy sub-TR-SS vias. 610C(4) and 610C(5) is positioned, or the like.

[0190] Instead, it is assumed that the process of Block 1214 to block 1218 when transitioning, then in block 1218The various dummy supra-TR structures are positioned symmetrically to the various non-dummy sub-TR structures. Examples of dummy supra-TR structures positioned symmetrically to the various non-dummy sub-TR structures include structures corresponding to the supra-TR SS vias. 510C(1) and 510C(2) correspond to the Sub-TR-SS vias, which are symmetrical to the Sub-TR-SS vias. 510C(3) and 510C(4) in Fig. 5C are positioned, or the like.

[0191] Instead, it is assumed that the process of Block 1214 to block 1220 when it transitions, then it is in block 1220 a common base area of ​​the various dummy supra-TR structures and / or the various sub-TR structures is arranged such that it is contained within a base area of ​​the corresponding ones.

[0192] The discussion now returns to Block 1204back, this time assuming that the process follows block 1204 with block 1236 to be continued. Examples of the common base area of ​​the various dummy supra-TR structures being contained within the base area of ​​the corresponding components in the TR layer include the common base areas of the dummy supra-TR structures according to the layout diagrams in Fig. 2C, Fig. 3C, Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C or similar.

[0193] The flow path of block 1204 to block 1206 This reflects the fact that the layout diagram compatible with simple architecture features the non-BPR architecture type, which includes supra-TR layers. Accordingly, in block 1236Other components are manufactured according to the non-BPR architecture type, which includes supra-TR layers. Examples of the BPR architecture type include semiconductor devices that follow the layout diagrams in Fig. 2B, Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B or similar block 1236 includes block 1238 - 1240 , 1244 and block 1248 - 2250 The process continues to block 1238 above.

[0194] In block 1238 Various non-dummy sub-TR structures are formed in corresponding supra-TR layers and coupled to corresponding transistor components in the TR layer. Examples of non-dummy supra-TR structures include structures corresponding to the via pillar. 212B and the SS through-connection 210B in Fig. 2B, the via pillar 312B in Fig. 3B, the via pillars 412B(1) and412B(2) and the lower connection 422(2) and the upper connection 422(1) in Fig. 4B, the SS through-holes 519B(1) and 510B(2) in Fig. 5B, the SS through-holes 610B(1) , 610B(2) and 610B(3) in Fig. 6B, the SS vias 710B(1) and 710B(2) in Fig. 7C or similar. After block 1238 The process goes to block 1244 in Fig. 12B over.

[0195] After block 12454 in Fig. 12B, the process can either be done with block 1246 , with block 1248 or with a block 1250 to be continued, as illustrated by the fact that Block 1244 shown as a symbol for a logical OR branch. The discussion begins with block 1246 continued, but later returns to each of the blocks 1248 and 1250back. Accordingly, it is assumed here that the process follows block 1. 1244 with block 1246 will be continued.

[0196] In block 1246 The various dummy supra-TR structures are positioned asymmetrically relative to the various non-dummy supra-TR structures. Examples of dummy supra-TR structures positioned asymmetrically relative to the various non-dummy sub-TR structures include structures corresponding to the dummy supra-TR SS via. 310B ) correspond to the non-dummy sub-TR via pillars, which are asymmetrical to the non-dummy sub-TR via pillars. 310B(1) and 310B(2) is positioned, or the like.

[0197] Instead, it is assumed that the process of Block 1244 to block 1248 when transitioning, then in block 1248The various dummy supra-TR structures are positioned symmetrically to the various non-dummy supra-TR structures. Examples of dummy supra-TR structures positioned symmetrically to the non-dummy supra-TR structures include structures corresponding to the dummy supra-TR SS vias. 424B(1) and 424B(2) corresponding to the non-dummy supra-TR via pillars, which are symmetrical to the non-dummy supra-TR via pillars 414B(1) and 412B(2) in Fig. 4B are positioned, or the like.

[0198] Instead, it is assumed that the process of Block 1244 to block 1250 when it transitions, then it is in block 1250A common base area of ​​the various dummy supra-TR structures is arranged such that it is contained within a base area of ​​the corresponding components in the TR layer. Examples of the common base area of ​​the various dummy supra-TR structures being contained within the base area of ​​the corresponding components in the TR layer include the common base areas of the dummy supra-TR structures according to the layout diagrams in Fig. 2B, Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B or the like.

[0199] Fig. Figure 10 is a block diagram of an EDA system (electronic design automation system). 1000 according to some embodiments.

[0200] In some embodiments, the EDA system includes 1000An automatic placement and routing system (APR system). The methods described herein for designing layout diagrams according to one or more embodiments can, for example, be implemented using the EDA system. 1000 It may be implementable according to some embodiments.

[0201] In some embodiments, the EDA system 1000 a general-purpose computing device that uses a hardware processor 1002 and a non-volatile, computer-readable storage medium 1004 includes the storage medium. 1004 is, among other things, computer program code 1006 , i.e., a set of executable instructions encoded, i.e., the computer program code 1006 is on the storage medium 1004 saved. Execution of the instructions 1006 through the hardware processor 1002represents (at least partially) an EDA tool that implements a section or the entirety of the methods described herein according to one or more embodiments (hereinafter referred to as listed processes and / or methods).

[0202] The processor 1002 is via a bus 1008 electrically with the computer-readable storage medium 1004 coupled. The processor 1002 is also via the bus 1008 electrically with an I / O interface 1010 coupled. A network interface 1012 is also via the bus 1008 electrically connected to the processor 1002 connected. The network interface 1012 is thus connected to a network 1014 connected that the processor 1002 and the computer-readable storage medium 1004 via the network 1014 be able to connect to external elements. The processor 1002is set up to run the computer program code 1006 to execute, which is stored in the computer-readable storage medium 1004 is coded to cause the system 1000 is usable for carrying out a section or all of the listed processes and / or procedures. In one or more embodiments, the processor is 1002 a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0203] In one or more embodiments, the computer-readable storage medium 1004 An electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, computer-readable storage media includes 1004a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a magnetic hard disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium comprises 1004 a CD-ROM (Compact Disc Read-Only Memory), a CD-RW (Compact Disc ReWritable) and / or a DVD (Digital Video Disc).

[0204] In one or more embodiments, the storage medium 1004 the computer program code 1006 stored, which is set up to cause the system to 1000 (where such an implementation (at least partially) constitutes the EDA tool) can be used to carry out a section or all of the listed processes and / or procedures. In one or more embodiments, the storage medium contains 1004It also stores information that facilitates the execution of a section or all of the listed processes and / or procedures. In one or more embodiments, the storage medium contains... 1004 a library 1007 stored on standard cells, which include standard cells such as those disclosed herein. In one or more embodiments, the storage medium contains 1004 one or more layout diagrams 1009 stored, which correspond to one or more of the layout diagrams disclosed herein.

[0205] The EDA system 1000 includes the I / O interface 1010 The I / O interface 1010 is coupled to external circuits. In one or more embodiments, the I / O interface includes 1010a keyboard, keypad, mouse, trackball, touchscreen and / or cursor keys for communicating information and commands to the processor 1002 .

[0206] The EDA system 1000 It also includes the network interface 1012 , which are connected to the processor 1002 is coupled. The network interface 1012 enables the system 1000 , with the network 1014 to communicate with which one or more other computer systems are connected. The network interface 1012 This includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, a section or the entirety of the listed processes and / or procedures are implemented in two or more systems. 1000 implements.

[0207] The system 1000is set up to receive information about the I / O interface 1010 to receive. The ones via the I / O interface 1010 The received information includes instructions, data, design rules, libraries of standard cells and / or other parameters for processing by the processor. 1002 The information will be provided via the bus. 1008 to the processor 1002 transferred. The EDA system 1000 is set up to receive information relating to a UI via the I / O interface 1010 to be received. The information is or will be received on the computer-readable medium. 1004 stored as user interface (UI) 1042.

[0208] In some embodiments, a section or all of the listed processes and / or procedures are implemented as an independent software application for execution by a processor. In some embodiments, a section or all of the listed processes and / or procedures are implemented as a software application that is part of an additional software application. In some embodiments, a section or all of the listed processes and / or procedures are implemented as an add-on module for a software application. In some embodiments, at least one of the listed processes and / or procedures is implemented as a software application that is a section of an EDA tool. In some embodiments, a section or all of the listed processes and / or procedures are implemented as a software application that is executed by the EDA system. 1000In some embodiments, a layout diagram comprising standard cells is generated using a tool such as VIRTUOSO®, supplied by CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0209] In some embodiments, the processes are implemented as functions of a program stored on a non-volatile, computer-readable recording medium. Examples of a non-volatile, computer-readable recording medium include, but are not limited to, an external / removable and / or internal / built-in storage device or memory unit, e.g., an optical disc such as a DVD, a magnetic disk such as a hard drive, a semiconductor memory such as a ROM, RAM, memory card, and / or the like.

[0210] Fig. 11 is a block diagram of a manufacturing system 1100for integrated circuits (ICs) and an associated IC fabrication process according to some embodiments. In some embodiments, based on a layout diagram (A), one or more semiconductor masks and / or (B) at least one component in a layer of an integrated semiconductor circuit are fabricated using the fabrication system. 1100 manufactured.

[0211] In Fig. 11 includes the IC manufacturing system 1100 Entities such as a design house 1120 , a mask house 1130 and an IC manufacturer (a “fab”) 1150 , which are involved in the design, development and manufacturing cycles and / or services associated with the manufacture of an IC component 1160 are related, interact with each other. The entities in the system 1100are connected via a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a multitude of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities, providing services to and / or receiving services from one or more other entities. In some embodiments, two or more entities from the design house are involved. 1120 , Mask House 1130 and IC-Fab 1150 Owned by a single, larger company. In some configurations, two or more design houses coexist. 1120 , Mask House 1130 and IC-Fab 1150 in a shared facility and use shared resources.

[0212] Design house (or design team) 1120 generates an IC design layout diagram.1122 The IC design layout diagram 1122 includes various geometric structures suitable for an IC device 1160 were developed. The geometric structures correspond to structures in metal, oxide, or semiconductor layers that represent the various components of the IC component to be manufactured. 1160 form. The different layers combine to create various IC features. For example, one section of the IC design layout diagram includes 1122 Various IC features, for example an active area, a gate electrode, source and drain, metal traces or vias of an interlayer interconnect, and openings for bond pads, are to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers arranged on the semiconductor substrate. The design house 1120 implements a suitable design procedure to create the IC design layout diagram 1122to form. The design procedure includes logical design, physical design, and / or location and path. The IC design layout diagram. 1122 It is presented in one or more files that contain information about the geometric structures. For example, the IC design layout diagram might be... 1122 expressed in a GDSII file format or a DFII file format.

[0213] The Mask House 1130 includes data preparation 1132 and mask manufacturing 1144 The Mask House 1130 uses the IC design layout diagram 1122 , to use one or more masks 1145 to produce the various layers of the IC component 1160 according to the IC design layout diagram 1122 to be used. The Mask House 1130 performs the mask data processing 1132 through, where the IC design layout diagram 1122The data is translated into a representative file (“RDF” - Representative Data File). Mask data preparation. 1132 The RDF represents mask manufacturing 1144 Ready. Mask production. 1144 It includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticule). 1145 or a semiconductor wafer 1153 , to. The design layout diagram 1122 is achieved through the mask data processing 1132 so that special properties of the mask writer and / or requirements of the IC-Fab are taken into account. 1150 This will be complied with. In Fig. 11 are the mask data processing 1132 and mask manufacturing 1144 illustrated as separate elements. In some embodiments, the mask data preparation can be... 1132 and mask manufacturing 1144 collectively referred to as mask data preparation.

[0214] In some embodiments, the mask data preparation includes 1132 Optical Proximity Correction (OPC) uses lithography enhancement techniques to compensate for image defects, such as those caused by diffraction, interference, other process effects, and the like. OPC adapts the IC design layout diagram. 1122 In some embodiments, the mask data preparation includes... 1132 Further resolution enhancement techniques (RETs) are employed, such as oblique illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats the OPC as an inverse imaging problem.

[0215] In some embodiments, the mask data preparation includes 1132a mask rule checker (MRC - Mask Rule Checker) that checks the IC design layout diagram 1122 The design, which has undergone OPC processes, is reviewed with respect to a set of mask generation rules that include certain constraints regarding geometry and / or wiring to ensure sufficient edge distances to accommodate variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram. 1122 , to avoid restrictions on mask production 1144 , which can reverse some of the modifications made by the OPC, in order to comply with the mask generation rules.

[0216] In some embodiments, the mask data preparation includes 1132 a lithography process check (LPC - Lithography Process Checking) that simulates processing by the IC-Fab 1150to be implemented to use the IC component 1160 to manufacture. The LPC simulates these processes based on the IC design layout diagram. 1122 , to simulate a manufactured component, such as the IC component 1160 , to generate. Processing parameters in LPC simulation can include parameters associated with various processes in the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after generating a simulated manufactured device by LPC, OPC and / or MRC are used to further refine the IC design layout diagram. 1122repeated if the shape of the simulated component deviates too far from fulfilling the design rules.

[0217] It goes without saying that the above description of mask data processing 1132 For the sake of clarity, it has been simplified. In some embodiments, the data preparation includes 1132 Additional features such as a logical operation (LOP) to enhance the IC design layout diagram 1122 to be modified according to manufacturing rules. Additionally, the data preparation process can be modified. 1132 to the IC design layout diagram 1122 The applied processes can be executed in many different sequences.

[0218] After the mask data processing 1132 and during mask production 1144 will a mask 1145 or a group of masks 1145 based on the modified IC design layout diagram 1122manufactured. In some embodiments, mask manufacturing includes 1144 Performing one or more lithographic exposures based on the IC design layout diagram 1122 In some embodiments, an electron beam (e-beam) or a mechanism with multiple electron beams is used to, based on the modified IC design layout diagram. 1122 a structure on a mask (photomask or reticulum) 1145 to form. The mask 1145 It can be formed according to various techniques. In some embodiments, the mask 1145formed using a binary technique. In some embodiments, a mask structure has opaque and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam used to expose the layer of image-sensitive material (e.g., photoresist) with which a wafer has been coated, is blocked by the opaque region and transmitted through the transparent regions. In one example, a binary mask version of the mask comprises 1145 a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) applied as a coating to the opaque areas of the binary mask. In another example, the mask 1145 formed using a phase-shift technique. In a phase-shift mask version (PSM version) of the mask 1145Various features in the structure formed on the phase-shift mask are designed to exhibit a suitable phase difference in order to improve resolution and image quality. In different examples, the phase-shift mask can be a damped PSM or an alternating PSM. The mask fabrication process... 1144 The manufactured mask(s) are used in various processes. For example, such a mask(s) are used in an ion implantation process to create different doped regions in the semiconductor wafer. 1153 to form, used in an etching process to create different etched areas in the semiconductor wafer 1153 to form and / or used in other suitable processes.

[0219] The IC-Fab 1150 includes manufacturing tools 1152 , which are set up to perform various manufacturing processes on the semiconductor wafer 1153to be designed in such a way that the IC component 1160 according to the mask(s), e.g. mask 1145 , is manufactured. In various embodiments, the manufacturing tools include 1152 a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g. a CVD chamber or an LPCVD oven, a CMP system, a plasma etching system, a wafer cleaning system and / or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0220] The IC-Fab 1150 uses the ones from the mask house 1130 manufactured mask(s) 1145 , to the IC device 1160 to manufacture. Thus, the IC factory uses 1150 at least indirectly the IC design layout diagram 1122 , to the IC component 1160 to manufacture. In some embodiments, the semiconductor wafer 1153 from IC-Fab 1150 using the mask(s)1145 manufactured to fit the IC component 1160 to form. In some embodiments, IC fabrication involves performing one or more lithographic exposures, at least indirectly, based on the IC design layout diagram. 1122 The semiconductor wafer 1153 The semiconductor wafer comprises a silicon substrate or another suitable substrate with material layers formed on it. 1153 It also includes various doped areas, dielectric features, multi-level interconnections and / or the like (which are formed in subsequent manufacturing steps).

[0221] Details concerning a manufacturing system for integrated circuits (ICs) (e.g. the system 1100 out of Fig.11) and an associated IC manufacturing process can be found, for example, in US Patent No. 9,256,709, issued on February 9, 2016, US Preliminary Publication No. 20150278429, published on October 1, 2015, US Preliminary Publication No. 20140040838, published on February 6, 2014, and US Patent No. 7,260,442, issued on August 21, 2007, all of which are hereby incorporated in full by reference.

[0222] In one embodiment, a method for manufacturing a semiconductor device, the method comprising: forming, in a transistor layer (TR layer), one or more corresponding components of one or more transistors; forming, in a corresponding contact layer located above the transistor layer (supra-TR contact layer), one or more supra-TR contact structures corresponding to selected connection sections of the one or more components of the one or more transistors; forming, in a corresponding contact layer located below the transistor layer (sub-TR contact layer), one or more sub-TR contact structures corresponding to selected connection sections of the one or more components of the one or more transistors;Forming, in metallization layers and correspondingly alternately arranged supra-interconnection layers located above the supra-TR contact layer (supra-TR metallization layers and correspondingly alternately arranged supra-TR interconnection layers), one or more supra-TR stacks of corresponding sub-TR conductive segments and corresponding supra-TR via structures, which represent one or more supra-TR via pillars for corresponding electrical coupling with the one or more supra-TR contact structures;Forming, in metallization layers and correspondingly interposed interconnection layers located below the sub-TR contact layer (sub-TR metallization layers and correspondingly interposed sub-TR interconnection layers), one or more sub-TR stacks consisting of corresponding sub-TR conductive structures and corresponding sub-TR via structures, which represent one or more sub-TR via pillars for corresponding electrical coupling with the one or more sub-TR contact structures; forming, in a redistribution layer above a topmost of the supra-TR metallization layers (supra-TR redistribution layer), one or more corresponding supra-TR redistribution via structures (supra-TR RV structures) for corresponding electrical coupling with the one or more supra-TR stacks;Forming, in a redistribution layer below a bottommost of the sub-TR metallization layers (supra-TR redistribution layer), one or more corresponding sub-TR redistribution via structures (sub-TR RV structures) for corresponding electrical coupling with the one or more sub-TR stacks; forming, in a supra-bond pad layer above the supra-TR redistribution layer, one or more corresponding supra-TR bond pads for electrical coupling; forming, in a sub-TR bond pad layer below the sub-redistribution layer, corresponding sub-TR bond pads for corresponding electrical coupling with the one or more sub-TR RV structures;and performing one of the following steps: if the semiconductor device is intended to have a buried busbar architecture (BPR architecture type), removing at least some sections of the one or more sub-TR stacks in a region from a middle supra-TR metallization layer to the top supra-TR metallization layer and in corresponding supra-TR interconnection layers, or at least some of the one or more supra-TR RV structures, or at least some of the one or more supra-bond pads;or, if the semiconductor device is intended to have a non-buried busbar architecture (non-BPR architecture type), removal of at least some of the one or more sub-TR contact structures, or at least some of the one or more sub-RV structures, or at least some of the one or more sub-bond pads, or at least some portions of the one or more sub-TR stacks. In one embodiment, removing at least some of the one or more sub-TR contact structures, or the one or more sub-RV structures, or the one or more sub-bond pads, or portions of the one or more sub-TR stacks, removes substantially all of the one or more sub-TR contact structures, the one or more sub-RV structures, the one or more sub-bond pads, and the one or more sub-TR stacks.

[0223] In one embodiment, a semiconductor device comprises: in a transistor layer (TR layer), components of corresponding transistors (TR components); and in corresponding layers above the transistor layer (supra-TR layers): various non-dummy structures (non-dummy supra-TR structures) coupled to the transistor components and included because the semiconductor device has an architecture type with a non-buried busbar (non-BPR architecture type); and various dummy structures (dummy supra-TR structures) included as artifacts resulting from the semiconductor device based on a dual-architecture compatible design that is equally suitable for adaptation to the BPR architecture type and for adaptation to a BPR architecture type.

[0224] In one embodiment, the semiconductor device further comprises: in corresponding layers below the transistor layer (sub-TR layers): various dummy structures (dummy sub-TR structures) included as artifacts resulting from the semiconductor device based on a dual-architecture compatible design, which is substantially equally suitable for adaptation to the BPR architecture type and for adaptation to a BPR architecture type. In one embodiment, the semiconductor device is a metal-insulator-metal (MIM) capacitor; or the semiconductor device is a MIM diode. In one embodiment, the semiconductor device is a decoupling capacitor circuit; a high-impedance structure; a metal-oxide-metal capacitor; a MOM diode; a metal-insulator-metal (MIM) capacitor; or a MIM diode.In one embodiment, each of the TR layer and the supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other; the supra-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; and the various dummy supra-TR structures are positioned asymmetrically in the first direction and / or the second direction relative to the various non-dummy supra-TR structures. In one embodiment, the semiconductor device is a decoupling capacitor circuit (DECAP circuit); a high-resistance (HiR) structure; a metal-insulator-metal (MIM) capacitor; or a MIM diode.In one embodiment, each of the TR layer and the supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other; the supra-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; and the various dummy supra-TR structures are positioned symmetrically to the various non-dummy supra-TR structures in the first direction and / or the second direction. In one embodiment, the semiconductor device is a metal-oxide-metal (MOM) capacitor or a MOM diode.In one embodiment, each of the TR layer and the supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other; the sub-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; when viewed from the third direction, a base area of ​​a given structure is an area in the first and second directions occupied by the given structure; and a common base area of ​​the various dummy supra-TR structures is substantially contained within a common base area of ​​the corresponding TR components.

[0225] In one embodiment, a semiconductor device comprises: in a transistor layer (TR layer), components of corresponding transistors (transistor components); and in corresponding layers below the transistor layer (sub-TR layers): various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and included because the semiconductor device has a buried busbar architecture (BPR architecture type); and, in corresponding layers above the transistor layer (supra-TR layers): various dummy structures (dummy supra-TR structures) included to ensure compatibility so that the semiconductor device would otherwise be compatible with an unburied busbar architecture (non-BPR architecture type). In one embodiment, the semiconductor device is an inductor; a metal-insulator-metal (MIM) capacitor; or a MIM diode.In one embodiment, each of the TR layer, sub-TR layer, and supra-TR layer extends substantially in a first direction and a second direction that are perpendicular to each other; the sub-TR layer and supra-TR layer are stacked in a third direction that is substantially perpendicular to each of the first and second directions; and the various dummy supra-TR structures are positioned asymmetrically in the first direction and / or the second direction relative to the various non-dummy sub-TR structures. In one embodiment, the semiconductor device is a metal-insulator-metal (MIM) capacitor or a MIM diode. In one embodiment, the semiconductor device further comprises: in corresponding layers below the transistor layer (sub-TR layers): various dummy structures (dummy sub-TR structures) compatible with the semiconductor device, which otherwise has the non-BPR architecture type.In one embodiment, each of the TR layer, sub-TR layers, and supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other; the sub-TR layers and supra-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; and the various dummy sub-TR structures are positioned asymmetrically in the first direction and / or the second direction relative to the various non-dummy sub-TR structures. In one embodiment, the semiconductor device is a metal-insulator-metal (MIM) capacitor or a MIM diode.In one embodiment, each of the TR layer, sub-TR layer, and supra-TR layer extends substantially in a first direction and a second direction that are perpendicular to each other; the sub-TR layer and supra-TR layer are stacked in a third direction that is substantially perpendicular to each of the first and second directions; and the various dummy supra-TR structures are positioned symmetrically to the various non-dummy sub-TR structures in the first direction and / or the second direction. In one embodiment, the semiconductor device is an inductor.In one embodiment, each of the TR layer and the supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other; the sub-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; viewed from the third direction, a footprint of a given structure is an area in the first and second directions occupied by the given structure; and a common footprint of the various dummy sub-TR structures is substantially contained within a common footprint of the corresponding TR components. In one embodiment, the semiconductor device is a metal-insulator-metal (MIM) capacitor; or the semiconductor device is a MIM diode.

[0226] In one embodiment, a method for fabricating a semiconductor device based on a dual-architecture compatible design comprises: forming one or more components of one or more transistors in a transistor layer (TR layer) of the semiconductor device; and performing one of (A) fabricating further components according to a buried busbar architecture type (BPR architecture type) for the semiconductor device, wherein the BPR architecture type comprises layers below the transistor layer (sub-TR layers) and layers above the transistor layer (supra-TR layers); or (B) fabricating further components according to a non-buried busbar architecture type (non-BPR architecture type) for the semiconductor device, wherein the non-BPR architecture type comprises supra-TR layers;wherein: the dual-architecture compatible design is substantially equally suitable for adaptation to the BPR architecture type and for adaptation to the non-BPR architecture type; (A) fabricating further components according to a BPR architecture type comprises: in appropriate sub-TR layers, forming various non-dummy structures (non-dummy sub-TR structures) that are appropriately coupled to the transistor components, and, in appropriate supra-TR layers, forming various dummy structures (dummy supra-TR structures) that are appropriate artifacts resulting from the dual-architecture compatible design that is suitable for adaptation to the non-BPR architecture type;and (B) fabricating further components according to a non-BPR architecture type includes: in appropriate supra-TR layers, forming various non-dummy structures (non-dummy supra-TR structures) that are appropriately coupled to the transistor components, and forming various dummy structures (dummy supra-TR structures) that are appropriate artifacts resulting from the dual-architecture compatible design suitable for adaptation to the BPR architecture type.

[0227] In some embodiments, each of the TR layer and the supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other; the supra-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; and (B) fabricating further components according to the non-BPR architecture type further comprises positioning the various dummy supra-TR structures asymmetrically to the various non-dummy supra-TR structures in the first direction and / or the second direction, or positioning the various dummy supra-TR structures symmetrically to the various non-dummy supra-TR structures in the first direction and / or the second direction. In some embodiments, each of the TR layer and the supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other;(A) the supra-TR layers and / or (B) the sub-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; viewed from the third direction, a footprint of a given structure is an area in the first and second directions occupied by the given structure; and (A) fabricating further components according to a BPR architecture type further comprises configuring a common footprint of the various dummy sub-TR structures such that it is substantially contained within a common footprint of the corresponding TR components;or (B) fabricating further components according to a non-BPR architecture type further comprises configuring a common footprint of the various dummy supra-TR structures such that it is substantially contained within a common footprint of the corresponding TR components. In some embodiments, (A) fabricating further components according to a BPR architecture type further comprises: forming, in corresponding sub-TR layers, various dummy structures (dummy sub-TR structures) that are corresponding artifacts resulting from the dual-architecture compatible design suitable for adaptation to the non-BPR architecture type. In some embodiments, each of the TR layer, sub-TR layers, and supra-TR layers extends substantially in a first direction and a second direction that are perpendicular to each other;The sub-TR layers and the supra-TR layers are stacked in a third direction that is substantially perpendicular to each of the first and second directions; and (A) fabricating further components according to a BPR architecture type further comprises positioning the various dummy sub-TR structures asymmetrically to the various non-dummy sub-TR structures in the first and / or second direction, or positioning the various dummy supra-TR structures symmetrically to the various non-dummy sub-TR structures in the first and / or second direction. In some embodiments, (A) fabricating further components according to a BPR architecture type results in the semiconductor device being an inductor; a metal-insulator-metal (MIM) capacitor; or a MIM diode.

[0228] In some embodiments, (B) fabricating further components according to a non-BPR architecture type results in the semiconductor device being a decoupling capacitor circuit; a high-impedance structure; a metal-oxide-metal (MOM) capacitor; or a MOM diode; a metal-insulator-metal (MIM) capacitor; or a MIM diode.

[0229] The foregoing outlines features of several embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. The person skilled in the art should be aware that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. The person skilled in the art should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and modifications to them without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 031409

[0001] US 9256709

[0221] US 20150278429

[0221] US 20140040838

[0221] US 7260442

[0221]

Claims

[1] Method for manufacturing a semiconductor device based on a dual architecture compatible design, the method comprising: Forming one or more components of one or more transistors in a transistor layer (TR layer) of the semiconductor device; and Performing one of: (A) Manufacturing further components according to a buried busbar architecture type (BPR architecture type) for the semiconductor device, wherein the BPR architecture type comprises layers below the transistor layer (sub-TR layers) and layers above the transistor layer (supra-TR layers); or (B) Manufacturing further components according to an architecture type with a non-buried busbar (non-BPR architecture type) for the semiconductor device, wherein the non-BPR architecture type includes supra-TR layers; and where: The dual-architecture compatible design is essentially equally suitable for adaptation to the BPR architecture type and for adaptation to the non-BPR architecture type; (A) Manufacturing further components according to a BPR architecture type includes: in corresponding sub-TR layers, forming various non-dummy structures (non-dummy sub-TR structures) that are coupled accordingly to the transistor components; and, in corresponding supra-TR layers, forming various dummy structures (dummy supra-TR structures) that are corresponding artifacts resulting from the dual-architecture compatible design suitable for adaptation to the non-BPR architecture type; and (B) Manufacturing further components according to a non-BPR architecture type includes: in corresponding supra-TR layers: Forming various non-dummy structures (non-dummy supra-TR structures) that are coupled accordingly to the transistor components; and Forming various dummy structures (dummy supra-TR structures) that are corresponding artifacts resulting from the dual architecture compatible design suitable for adaptation to the BPR architecture type. [2] Method according to claim 1, wherein: each of the TR layer and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the supra-TR layers are stacked in a third direction that is essentially perpendicular to each of the first and second directions; and (B) Manufacturing further components according to a non-BPR architecture type further includes: Positioning the various dummy supra-TR structures asymmetrically to the various non-dummy supra-TR structures in the first direction and / or the second direction; or Positioning the different dummy supra-TR structures symmetrically to the different non-dummy supra-TR structures in the first direction and / or the second direction. [3] Method according to claim 1, wherein: each of the TR layer and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; (A) the supra-TR layers and / or (B) the sub-TR layers are stacked in a third direction which is essentially the same as both the first and second directions; When viewed from the third direction, the base area of ​​a given structure is an area in the first and second directions that is occupied by the given structure; and (A) Manufacturing further components according to a BPR architecture type further includes: Configure a common footprint of the various dummy sub-TR structures such that it is essentially contained within a common footprint of the corresponding TR components; or (B) Manufacturing further components according to a non-BPR architecture type further includes: Configure a common footprint of the various dummy supra-TR structures such that it is essentially contained within a common footprint of the corresponding TR components. [4] Method according to claim 1 or 2, wherein (A) manufacturing further components according to a BPR architecture type further comprises: in the corresponding sub-TR layers, Forming various dummy structures (dummy sub-TR structures) that are corresponding artifacts resulting from the dual architecture compatible design suitable for adaptation to the non-BPR architecture type. [5] Method according to claim 4, wherein: each of the TR layer, the sub-TR layers and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the sub-TR layers and the supra-TR layers are stacked in a third direction that is essentially perpendicular to each of the first and second directions; and (A) Manufacturing further components according to a BPR architecture type further includes: Positioning the various dummy sub-TR structures asymmetrically to the various non-dummy sub-TR structures in the first direction and / or the second direction; or Positioning the different dummy supra-TR structures symmetrically to the different non-dummy sub-TR structures in the first direction and / or the second direction. [6] Method according to any one of the preceding claims, wherein: (A) Manufacturing further components according to a BPR architecture type results in the semiconductor device an inductor; a metal-insulator-metal (MIM) capacitor; or a MIM diode. [7] Method according to any one of the preceding claims, wherein: (B) Manufacturing further components according to a non-BPR architecture type results in the semiconductor device a decoupling capacitor circuit; a high-resistance structure; a metal-oxide-metal (MOM) capacitor; a MOM diode; a metal-insulator-metal (MIM) capacitor; or a MIM diode. [8] Semiconductor device, comprising: in a transistor layer (TR layer), components of corresponding transistors (TR components); and, in corresponding layers above the transistor layer (Supra-TR layers): various non-dummy structures (non-dummy supra-TR structures) coupled to the transistor components and included because the semiconductor device has a non-buried busbar architecture type (non-BPR architecture type); and various dummy structures (dummy supra-TR structures) included as artifacts resulting from the semiconductor device based on a dual architecture compatible design, which is essentially equally suitable for adaptation to the BPR architecture type and for adaptation to a BPR architecture type. [9] Semiconductor device according to claim 8, further comprising: in corresponding layers below the transistor layer (sub-TR layers): various dummy structures (dummy sub-TR structures) included as artifacts resulting from the dual architecture compatible design suitable for adaptation to the BPR architecture type. [10] Semiconductor device according to claim 8 or 9, wherein: each of the TR layer and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the supra-TR layers are stacked in a third direction that is essentially perpendicular to each of the first and second directions; and the various dummy supra-TR structures are positioned asymmetrically to the various non-dummy supra-TR structures in the first direction and / or the second direction. [11] Semiconductor device according to claim 10, wherein: the semiconductor component a decoupling capacitor circuit; a high-resistance structure; a metal-insulator-metal (MIM) capacitor; or a MIM diode. [12] Semiconductor device according to any one of the preceding claims 8 to 11, wherein: each of the TR layer and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the supra-TR layers are stacked in a third direction that is essentially perpendicular to each of the first and second directions; and the various dummy supra-TR structures are positioned symmetrically to the various non-dummy supra-TR structures in the first direction and / or the second direction. [13] Semiconductor device according to any one of the preceding claims 8 to 11, wherein: each of the TR layer and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the supra-TR layers are stacked in a third direction, which is essentially perpendicular to each of the first and second directions; When viewed from the third direction, the base area of ​​a given structure is an area in the first and second directions that is occupied by the given structure; and a common base area of ​​the various dummy supra-TR structures is essentially contained within a common base area of ​​the corresponding TR components. [14] Semiconductor device comprising: in a transistor layer (TR layer), components of corresponding transistors (transistor components); and, in corresponding layers below the transistor layer: various non-dummy structures (non-dummy sub-TR structures) coupled to the transistor components and included because the semiconductor device has a buried busbar architecture (BPR architecture type); and, in corresponding layers above the transistor layer: various dummy structures (dummy supra-TR structures) included as artifacts resulting from the semiconductor device based on a dual architecture compatible design, which is essentially equally suitable for adaptation to the non-BPR architecture type and for adaptation to a non-BPR architecture type. [15] Semiconductor device according to claim 14, further comprising: in corresponding layers below the transistor layer: various dummy structures (dummy sub-TR structures) that are compatible with the semiconductor device, which would otherwise have the non-BPR architecture type. [16] Semiconductor device according to claim 15, wherein: each of the TR layer, the sub-TR layers and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the sub-TR layers and the supra-TR layers are stacked in a third direction that is essentially perpendicular to each of the first and second directions; and the various dummy sub-TR structures are positioned asymmetrically to the various non-dummy sub-TR structures in the first direction and / or the second direction. [17] Semiconductor device according to claim 16, wherein: the semiconductor component a metal-insulator-metal (MIM) capacitor; or a MIM diode. [18] Semiconductor device according to claim 14, wherein: each of the TR layer, the sub-TR layers and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the sub-TR layers and the supra-TR layers are stacked in a third direction that is essentially perpendicular to each of the first and second directions; and the various dummy supra-TR structures are positioned symmetrically to the various non-dummy sub-TR structures in the first direction and / or the second direction. [19] Semiconductor device according to claim 18, wherein: the semiconductor component is an inductor. [20] Semiconductor device according to claim 14, wherein: each of the TR layer and the supra-TR layers extends essentially in a first direction and a second direction that are perpendicular to each other; the sub-TR layers are stacked in a third direction, which is essentially perpendicular to each of the first and second directions; When viewed from the third direction, the base area of ​​a given structure is an area in the first and second directions that is occupied by the given structure; and a common base area of ​​the various dummy sub-TR structures is essentially contained within a common base area of ​​the corresponding TR components.