Semiconductor device and storage device, as well as manufacturing method therefor

Abstract

Semiconductor device with: a pair of transistors (110, 120) on a semiconductor substrate (102); an interconnect structure across the pair of transistors (110, 120), wherein the interconnect structure has the following: Metal leads (182, 184) and metal vias (160, 210) arranged above and connected to the pair of transistors (110, 120), and a composite spin-Hall electrode (340, 530) over the metal conductors (182, 184) and metal vias (160, 210), wherein the composite spin-Hall electrode is electrically connected to the pair of transistors (110, 120) via the metal conductors and metal vias and has a first metal layer (342, 348, 531, 535, 539), a second metal layer (342, 348, 535, 535, 539) and a first spacer layer (344, 532, 536) between the first and the second metal layer, wherein the first metal layer contains a heavy metal in a first mixture of a stable and a metastable state of the heavy metal, the second metal layer contains the heavy metal in a second mixture of the stable and the metastable state of the heavy metal, and the first spacer layer contains a first material that is the first metal layer differs; and a magnetic tunnel contact (270) over the composite spin Hall electrode (340, 530); wherein the first spacer layer (344, 532, 536) comprises a crystalline metal or a crystalline metal oxide; and wherein the first spacer layer (344, 532, 536) further comprises an amorphous ferromagnetic material.

Description

background

[0001] Semiconductor devices are used in integrated circuits for electronic devices such as radios, televisions, mobile phones, and personal computers. To meet the increasing demands for miniaturization, higher speed, and improved electrical performance (e.g., lower power consumption, higher reliability), new structures and materials are being intensively researched. For example, new memory types, such as magnetic spin-transfer torque direct access memory (STT-MRAM) and spin-orbit torque MRAM (SOT-MRAM), have recently been developed in an effort to reduce power consumption and / or access times, increase reliability, or improve other performance indicators required for the intended application.

[0002] US Patent 9,105,832 B2 describes an ST-MRAM structure with a spin Hall effect base layer contacting a free magnetic layer. This structure causes a switching of the magnetic moment within the free magnetic layer as a result of a lateral switching current within the spin Hall effect base layer. This ST-MRAM device uses an independent read current and independent read voltage through a magnetoresistive stack comprising a pinned layer, a non-magnetic spacer layer, and the free magnetic layer contacting the spin Hall effect base layer. The spin Hall effect base layer features non-magnetic conductor materials based on tungsten, exhibiting a spin diffusion length of no more than five times the thickness of the spin Hall effect base layer and a spin Hall angle of at least 0.05.

[0003] Publication US 2020 / 0312391A1 describes a storage element comprising, in this order, a magnetic reference layer, a tunnel barrier layer, a free magnetic layer, an intermediate layer, and a base layer. The intermediate layer may include an ultrathin magnesium oxide layer.

[0004] Publication US 2020 / 0 365 308 A1 describes a memory stack with a magnetic tunnel junction, wherein the magnetic tunnel junction is connected to two transistors via vias and metal structures.

[0005] Document US 2019 / 0080738A1 describes a magnetoresistive spin-orbit torque random-access memory cell (SOT MRAM) containing a magnetic tunnel junction comprising a free layer with two bistable magnetization directions, a magnetic reference layer with a fixed magnetization direction, a tunnel barrier layer between the free layer and the reference layer, and a non-magnetic spin Hall effect layer. The spin Hall effect layer may contain an alternating stack of tungsten layers in the beta phase and non-magnetic noble metal layers. Additionally, a hafnium layer may be placed between the non-magnetic spin Hall effect layer and the free layer.

[0006] Document US 2016 / 0359102A1 describes a structure for a magnetic tunnel junction (MTJ) with orthogonal magnetic anisotropy (PMA). The MTJ structure comprises a tungsten-containing seed layer, a first ferromagnetic layer layered on the seed layer containing a boron-based ferromagnetic material and PMA, a tunnel barrier layer layered on the first ferromagnetic layer, and a second ferromagnetic layer layer layered on the tunnel barrier layer and also containing PMA. The seed layer has a thickness in the range of 1 nm to 10 nm. By using a tungsten-based substance as the seed layer material, an MTJ structure can be provided in which the crystallinity of the first ferromagnetic layer is maintained even at high temperatures in the range of 350°C to 400°C.

[0007] The task is to improve appropriate storage devices.

[0008] The problem is solved by the semiconductor device according to claim 1, the storage device according to claim 11, and the method according to claim 16. Further embodiments are specified in the dependent claims. Brief description of the drawings

[0009] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a schematic representation of a semiconductor device according to some embodiments of the invention. Fig. Figure 2 is a schematic perspective representation of a memory cell of a semiconductor device according to some embodiments of the invention. Fig. Figure 3 is a circuit diagram of a memory cell of a semiconductor device according to some embodiments of the invention. Fig. Figure 4 is a schematic sectional view of a part of a memory cell of a semiconductor device according to some embodiments of the invention. The Fig. 5 and Fig. Figure 6 shows schematic sectional views of memory cells of semiconductor devices according to some embodiments of the invention. The Fig. Figures 7A to 7C are schematic perspective representations of semiconductor devices according to some embodiments of the invention. The Fig. Figures 8A to 10C are diagrams that graphically represent characterization data of some semiconductor devices according to some embodiments of the invention. The Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. Figure 20 are schematic representations of structures that arise during the manufacture of a semiconductor device according to some embodiments of the invention. The Fig. 21A and Fig. Figure 21B shows schematic sectional views of memory cells of semiconductor devices according to some embodiments of the invention. The Fig. 22A and Fig. Figures 22B are schematic perspective representations of semiconductor devices according to some embodiments of the invention. The Fig. Figures 23A to 24 are diagrams that graphically represent characterization data of some semiconductor devices according to some embodiments of the invention. The Fig. 25 and Fig. Figure 26 are schematic sectional views of memory cells of semiconductor devices according to some embodiments of the invention. The Fig. 27, Fig. 28 to Fig. Figure 29 are schematic representations of semiconductor devices according to some embodiments of the invention. Detailed description

[0010] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples. For instance, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0011] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0012] Fig. Figure 1 is a schematic representation of a semiconductor device SD10 according to some embodiments of the invention. In some embodiments, the semiconductor device SD10 comprises a semiconductor substrate 102 and an interconnect structure IN fabricated on the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 comprises one or more semiconductor materials, which may be elemental semiconductor materials, compound semiconductor materials, or semiconductor alloys. The elemental semiconductor materials may be, for example, Si or Ge. The compound semiconductor materials and the semiconductor alloys may be SiGe, SiC, or SiGeC, or a III-V semiconductor, a II-VI semiconductor, or semiconductor oxide materials. The semiconductor oxide materials may be, for example, one or more ternary or higher (e.g., quaternary, etc.) semiconductor oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium tin oxide (ITO).In some embodiments, the semiconductor substrate 102 can be a semiconductor-on-insulator substrate comprising at least one layer of a dielectric material (e.g., a buried oxide layer) arranged between a pair of semiconductor layers.

[0013] In some embodiments, functional circuits can be fabricated in and / or on the semiconductor substrate 102. For example, in Fig. 1 Transistors 110 and 120dh (two active devices) are shown, fabricated on certain regions of the semiconductor substrate 102. Each transistor 110 has a pair of source and drain regions 112S and 112D embedded in the semiconductor substrate 102, and a gate structure 114 located between the source and drain regions 112S and 112D on a portion of the semiconductor substrate 102, which functions as a channel region 116 of the transistor 110. In some embodiments, the source and drain regions 112S and 112D can be doped, for example, with n- or p-type materials. In some embodiments, the transistor 120 may also have a pair of source and drain regions 122S and 122D and a gate structure 124, which is arranged between the source and drain regions 122S and 122D on a part of the semiconductor substrate 102, which functions as a channel region 126 of the transistor 120.It should be noted that the examples do not restrict the architecture of transistors 110 and 120. Transistors 110 and 120 can, for example, be planar field-effect transistors, fin field-effect transistors, gate-all-around transistors, or transistors with a different architecture. Furthermore, different gate contact schemes, such as front-gate, back-gate, dual-gate, offset-gate, and the like, should be included. Fig. Although it has been shown that transistors 110 and 120 are fabricated on the semiconductor substrate 102, other active devices (e.g. diodes or the like) and / or passive devices (e.g. capacitors, resistors or the like) can also be fabricated as part of the functional circuit.

[0014] In some embodiments, the semiconductor device SD10 can be or include a memory device. For example, a memory matrix with a plurality of memory cells MC1 and MC2 is fabricated in at least one region of the semiconductor device SD10. Fig. Figure 1 shows two such memory cells, MC1 and MC2, for illustrative purposes, but it is understood that the invention does not limit the number of memory cells MC1 and MC2 contained in the semiconductor device SD10. In some embodiments, the memory cells MC1 and MC2 have paired transistors 110 and 120, which can function as driver transistors for the memory cells MC1 and MC2. In some embodiments, the transistors 110 and 120 of the same memory cell (e.g., MC1 or MC2) are separated from each other by a portion of the semiconductor substrate 102, which functions as a dummy channel 130. The dummy channel 130 can, for example, be arranged between the drain region 112D of transistor 110 and the drain region 122D of transistor 120. In some embodiments, a dummy gate structure 132 can be fabricated on the dummy channel 130.The dummy gate structure 132 can be electrically floating with respect to transistors 110 and 120 and can be manufactured to improve process uniformity without being connected to the operation of memory cells MC1 and MC2. In some embodiments, further dummy channels 140 and dummy gate structures 142 can be arranged between transistors 110 and 120 of adjacent memory cells MC1 and MC2. For example, the dummy channel 140 and the dummy gate structure 142 above it are arranged between the source region 122S of transistor 120 of memory cell MC1 and the adjacent source region 112S of transistor 110 of memory cell MC2.

[0015] The interconnect structure IN is fabricated over the semiconductor substrate 102 to integrate the active and passive devices fabricated on the semiconductor substrate 102 in one or more functional circuits. In some embodiments, the interconnect structure IN features alternating stacked conductive vias and conductive traces embedded in interlayer dielectrics (ILDs) that connect the active and passive devices fabricated on the semiconductor substrate 102 to each other and to other elements embedded in the interconnect structure IN. For example, memory elements ME1 and ME2 are fabricated in the interconnect structure IN and are connected to transistors 110 and 120 of the corresponding memory cells MC1 and MC2 via metallization wiring of the interconnect structure IN.For example, the memory element ME1 of the memory cell MC1 is connected to the transistors 110 and 120 of the memory cell MC1, and so on.

[0016] In some embodiments, an ILD 150 extends onto the semiconductor substrate 102, and conductive vias 160 extend through the ILD 150 to contact the source and drain regions 112S, 112D, 122S and 122D of the transistors 110 and 120. Conductive traces 182 and 184 and conductive structures 192 and 194 are fabricated above the ILD 150 to be electrically connected to the transistors 110 and 120. In some embodiments, conductive vias 162 connect the conductive lines 182 to the source regions 112S of the transistors 110, conductive vias 164 connect the conductive structures 192 to the drain regions 112D of the transistors 110, conductive vias 166 connect the conductive structures 194 to the drain regions 122D of the transistors 120, and conductive vias 168 connect the conductive lines 184 to the source regions 122S of the transistors 120.In some embodiments, the conductive vias 162, 164, 166, and 168 can be collectively referred to as conductive vias 160. Depending on the process used for their fabrication (e.g., single-Damascene process, dual-Damascene process, etc.), the conductive lines 182 and 184 and the conductive structures 192 and 194 can be buried in a separate ILD 170 or in the ILD 150. Fig. 1 further conductive vias 210, which extend through an ILD 200, connect the conductive structures 192 and 194 to the storage elements ME1 and ME2.

[0017] In some embodiments, the semiconductor device SD10 is or incorporates a spin-orbit transfer MRAM (SOT-MRAM; MRAM: magnetic random-access memory), and the memory elements ME1 and ME2 have at least one spin Hall electrode 240 and a magnetic tunnel contact (MTJ) 270 located on the spin Hall electrode 240. In some embodiments, the spin Hall electrode 240 is connected to the driver transistors 110 and 120, respectively, by conductive vias 212 and 214, and the MTJ 270 is located on the spin Hall electrode 240 on a side opposite the conductive vias 212 and 214. In some embodiments, the conductive vias 212 and 214 can be collectively referred to as conductive vias 210.In some embodiments, a conductive via 300 connects the MTJ 270 to a conductive line 320 that extends over the MTJ 270 and the spin Hall electrode 240.

[0018] Fig. Figure 2 is a schematic perspective view of a memory cell (e.g., MC1) of the semiconductor device SD10 according to some embodiments of the invention. As can be seen by comparing Fig. 1 with Fig. 2 can be seen in the schematic representations such as the one by Fig. 1. Elements belonging to different xz or yz levels are used for illustrative purposes only, while there can be no single xyz level in which the elements in Fig. The elements shown in Figure 1 are visible simultaneously. The following description assumes that the directions x, y, and z form a group of orthogonal Cartesian coordinates.

[0019] In the Fig. 1 and Fig. 2 In some embodiments, the gate structures 114 and 124 and the dummy gate structures 132 (and 142) extend along the y-direction, and the source and drain regions 112S, 112D, 122S, and 122D are arranged on opposite sides of the corresponding gate structures 114 and 124 along the x-direction. The conductive lines 182 and 184 can be lines extending along the x-direction, perpendicular to the gate structures 114 and 124. The conductive structures 192 and 194 can be plates connecting the corresponding lower-lying conductive vias 164 and 166 to corresponding higher-lying conductive vias 212 and 214. In some embodiments, the conductive vias 164, 166, 212 and 214 and the conductive structures 192 and 194 can be made between the conductive lines 182 and 184 along the y-direction.In some embodiments, the spin Hall electrode 240, the MTJ 270, and the conductive line 320 can also have an elongated shape along the x-direction. In some embodiments, the memory cells MC1 and MC2 are arranged according to columns and rows of a matrix along the x- and y-directions. In some embodiments, memory cells MC1 and MC2 distributed along the x-direction at the same level along the y-direction can share the conductive lines 182, 184, and 320, while memory cells MC1 and MC2 distributed along the y-direction at the same level along the x-direction can share the gate structures 114 and 124. Each memory cell MC1 and MC2 has an associated memory element ME1 and ME2, respectively.Individual memory cells MC1 and MC2 can be selectively addressed by applying voltages or reading potentials from combinations of the corresponding gate structures 114 and 124 and conductive lines 182, 184 and 320.

[0020] Fig. Figure 3 is a circuit diagram of a memory cell MC1 of the semiconductor device SD10 according to some embodiments of the invention. Although the following description focuses on memory cell MC1, the structure and operation of memory cell MC2 may be identical. In the Fig. 1 and Fig. In some embodiments, the memory cell MC1 comprises the driver transistors 110 and 120, which are connected to two terminals of the spin-Hall electrode 240 on one side of the spin-Hall electrode 240 at opposite ends of the spin-Hall electrode 240, while the MTJ 270 is arranged on the side of the spin-Hall electrode 240 opposite the driver transistors 110 and 120. In some embodiments, a separating layer 250 is layered between the spin-Hall electrode 240 and the MTJ 270, which can serve as a structural buffer layer to compensate for a mismatch between the structures of layers of the spin-Hall electrode 240. In some embodiments, the separating layer 250 can comprise (and in some embodiments be made of) a metallic or a dielectric material.The metallic material can be a non-ferromagnetic material, such as Ru, Pt, Mo, Ti, Mg or a combination thereof, and the dielectric material can be a metal oxide, such as magnesium oxide, cobalt oxide, aluminum oxide or a combination thereof.

[0021] The structure of the MTJ 270 is not particularly restricted, and any known structure can be used. In some embodiments, the MTJ 270 has at least one magnetic layer possessing a magnetic moment that can be switched by the action of a spin-orbit torque generated by the spin-Hall electrode 240. In some embodiments, the magnetic layer can be the layer of the MTJ 270 closest to the spin-Hall electrode 240, and it can be separated from the spin-Hall electrode 240 by the separating layer 250. In some embodiments, the MTJ 270 has additional layers, such as a barrier layer, a reference layer, a pinned layer, and / or a capping layer, or the like.

[0022] As explained above, the memory cells (such as memory cell MC1) of the semiconductor device SD10 can be operated as cells of a SOT-MRAM. In an SOT-MRAM, the magnetic moment of the magnetic layer of the MTJ 270 is switched by a spin-orbit interaction effect generated by a current Jc flowing adjacent to the magnetic layer of the MTJ 270. By manipulating the orientation of the magnetic layer, a change in the resistance of the MTJ 270 is caused, which can be used to record a data value in the memory cells MC1. The magnetic moment of the magnetic layer can be switched using only the spin-orbit torque or with an additional magnetic field. There are three general types of SOT-MRAMs, which can be classified according to the orientation relationship between the magnetization of the magnetic layer and the write current Jc flowing through the spin Hall electrode 240.An x-SOT-MRAM has a magnetic layer moment that is parallel to the current Jc through the spin Hall electrode 240 and an additional magnetic field that is perpendicular to the plane of current flow in the spin Hall electrode 240. A y-SOT-MRAM has a free magnetic layer moment that is perpendicular to the direction of the current Jc through the spin Hall electrode 240, but lies in the same plane as this direction. A z-SOT-MRAM has a free magnetic layer moment that is perpendicular to the plane of the current Jc flowing through the spin Hall electrode 240, and may require an additional magnetic field that is parallel to the current flow Jc. Although an x-SOT-RAM is discussed below, the invention is not limited to it, and other types of SOT-MRAMs are also possible.

[0023] As explained above, the spin-Hall electrode 240 is an active spin-orbit interface that exhibits strong spin-orbit interactions and can be used to switch the magnetic moment of the magnetic layer of the MTJ 270. The spin-Hall electrode 240 serves to generate a spin-orbit magnetic field H Y In particular, the current Jc is guided in a plane (perpendicular to the z-direction) through the spin Hall electrode 240, and the spin orbit magnetic field H Y is generated perpendicular to the direction of the current Jc. This spin-orbit magnetic field H Y This corresponds to a spin-orbit torque T acting on the magnetization of the MTJ 270's magnetic layer. The torque T and the magnetic field H Y They are therefore synonymous with spin-orbit torque T and spin-orbit field H. Y This reflects the fact that the spin-orbit interaction is the origin of the spin-orbit torque T and the spin-orbit field H. YThe spin-orbit torque T occurs with the current Jc, which is guided in one plane in the spin Hall electrode 240. The spin-orbit torque T can rapidly displace the magnetic moment of the magnetic layer of the MTJ 270 from its equilibrium state.

[0024] In some embodiments, the flow of current Jc through the spin Hall electrode 240 via the driver transistors 110 and 120 can be controlled, for example, by applying suitable potentials to the conductive lines 182 and 184 and the gate structures 114 and 124. In some embodiments, the conductive lines 182 and 184 can function as source lines of the memory cells MC1, the gate structures 114 and 124 can function as word lines of the memory cells MC1, and the conductive lines 320 can function as bit lines of the memory cells MC1. For example, to write data to the MTJ 270, a voltage is applied so that the gate structures 114 and 124 of transistors 110 and 120 are switched on. Then a writing voltage is applied to one of the conductive lines 182 and 184, while the other conductive line 182 or 184 is grounded.The resulting current Jc generates the spin-orbit torque T, which toggles the magnetization of the MTJ 270, allowing data to be recorded in the MTJ 270. By reversing the voltage applied to conductive lines 182 and 184, other data can be written to the MTJ 270. For example, if a write voltage is applied to conductive line 182 while conductive line 184 is grounded, the current Jc flows in one direction (e.g., from transistor 110 to transistor 120) through the spin Hall electrode 240, generating a spin-orbit torque T that sets the magnetization of the MTJ 270 to an initial state, such as "0". If the voltage between conductive lines 182 and 184 is reversed (e.g.,When a write voltage is applied to conductive line 184 while conductive line 182 is grounded, the direction of current Jc in the spin Hall electrode 240 is reversed, and therefore an opposite spin-orbit torque T is applied to MTJ 270. This sets MTJ 270 to a second state, corresponding, for example, to a "1". During write operations, conductive line 320 can be floating. To read data from MTJ 270, one of transistors 110 and 120 is switched off (for example, by leaving the corresponding gate structures 114 and 124 floating), and conductive line 182 or 184, connected to the active transistor 110 or 120, is grounded. By reading the potential on the conductive line 320, the state of the MTJ 270 can be calculated, and the data written to the MTJ 270 can be determined.

[0025] Fig. Figure 4 is a schematic sectional view of a storage element ME1 of the semiconductor device SD10 according to some embodiments of the invention. As explained above, in the Fig. 1 and Fig. 4. The storage element ME1 is connected to the transistors 110 and 120 via the conductive vias 212 and 214. Optionally, a buffer layer 230 can be deposited between the spin Hall electrode 240 and the conductive vias 212 and 214. The buffer layer 230 extends, for example, onto the ILD 200, which covers the conductive vias 212 and 214, and the spin Hall electrode 240 is located on the buffer layer 230. The buffer layer 230 can comprise (and in some embodiments can be formed by) a thin layer of an insulating material such as MgO, deposited with a thickness along the z-direction of about 0.2 nm to about 0.9 nm. In some embodiments, the thickness of the buffer layer 230 is so large that an electrical connection between the transistors 110 and 120 and the spin Hall electrode 240 is not prevented.The separation layer 250 and the MTJ 270 can be arranged on the spin-Hall electrode 240 on a side opposite the buffer layer 230 and the conductive vias 212 and 214.

[0026] In some embodiments, the spin-Hall electrode 240 has a composite structure comprising metal layers 242 and 246 and spacer layers 244, which are stacked alternately on top of each other. For example, the spin-Hall electrode 240 of Fig. 2 Two metal layers 242 and 246 are arranged, separated by the spacer layer 244. In some embodiments, along the z-direction (the stacking direction), the metal layer 242 is arranged directly on the buffer layer 230, the spacer layer 244 is stacked directly on the metal layer 242, and the metal layer 246 is stacked directly on the spacer layer 244. In some embodiments, the metal layers 242 and 246 can comprise (or be made of) a metallic material in which spin-orbit coupling is used to generate a spin-orbit field H. YThe current Jc flowing through the spin Hall electrode 240 is sufficient to switch the magnetization of the MTJ 270. The metal layers 242 and 246 can, for example, contain heavy metals and can be referred to as heavy metal layers. The heavy metals can, for example, be transition metals from period 5 or 6 of the periodic table, which have valence electrons in the 4d and 5d orbitals, such as gold, palladium, platinum, tantalum, and tungsten, and the metal layers 242 and 246 can contain these elements or alloys thereof. In some embodiments, the metallic material contained in the metal layers 242 and 246 can be in a metastable state, and it can tend to transition to a more stable state under certain conditions, such as increasing the thickness of the metal layers 242 and 246 or treatment at elevated temperatures, which may be necessary in the fabrication of semiconductor devices.The metallic material contained in the metal layers 242 and 246 can, for example, transition from the metastable state to a more stable state depending on the individual thickness of the metal layers 242 and 246 or on treatment at elevated temperatures. In some embodiments, the metastable state of the metallic material can have very good performance parameters for spin Hall applications, since the metastable state can, for example, have a larger spin Hall angle (defined as the ratio of the density of the generated spin current to the charge current density) and / or lower energy consumption than the more stable state of the metallic material. The spin Hall angle generally increases with increasing thickness of the layer of metastable metallic material, so thicker layers of the metastable metallic material would be of interest for improved performance parameters of the spin Hall electrode 240.In some embodiments, the insertion of spacer layers (such as spacer layer 244) between metastable metal layers (such as metal layers 242 and 246) stabilizes the metastable metal layers 242 and 246, thereby enabling greater thicknesses (and thus larger spin Hall angles) for the spin Hall electrode 240. In some embodiments, the material for the spacer layer 244 can be selected taking into account the properties of the metallic material for the metal layers 242 and 246.If, for example, the metastable state and the stable state (states can also be referred to as phases) of the metallic material in metal layers 242 and 246 have different 3D atomic structures (either crystalline, amorphous, or hybrid), the 3D atomic structure of the spacer layer 244 is chosen to be different from the 3D atomic structure of the stable state of the metallic material, so that it does not act as a template for the transformation of the metallic material into the metastable state. The spacer layer 244 can, for example, be an amorphous layer, or it can have atoms arranged according to a crystal lattice that differs from the crystal lattice of the metastable state of the metallic material in metal layers 242 and 246.The spacer layer 244 can, for example, interrupt the rearrangement of atoms of the metallic material from the metastable state to the stable state, thus slowing down or even inhibiting the conversion to the stable state. In some embodiments, the material for the spacer layer 244 can be selected such that a low surface roughness can be achieved after deposition. In some embodiments, the spacer layer 244 can be deposited with a surface roughness so small that subsequent deposition of the materials for the MTJ 270 is not affected. The surface roughness of the spacer layer 244 has, for example, an arithmetic mean deviation of the surface profile (Ra) of less than 0.2 nm, e.g., from about 0.1 nm to about 0.2 nm. The surface roughness of the spacer layer 244 can be measured by atomic force microscopy (AFM).In some embodiments, the material for the spacer layer 244 can be an electrical conductor or an electrical insulator. If an insulator is used, the spacer layer 244 can be made thin enough to allow an electric current to flow through it. In some embodiments, the spin Hall electrode 240 can have an elongated shape along a certain direction D1 (e.g., the x-direction of ). Fig. 2) have, where the sectional view of Fig. 4 is created in a plane defined by the stacking direction z of the metal layers 242 and 246 and the extension direction D1 of the spin Hall electrode 240. In some embodiments, the bottom metal layer 242 can consist essentially of the metallic material in the metastable state (e.g., β-tungsten), while a portion of the metallic material in the upper metal layer 246 may have transitioned to the stable state (e.g., α-tungsten). That is, in the upper metal layer 246, the metallic material can exist as a mixture of the stable and metastable states.

[0027] Examples of the metallic material for the metal layers 242 and 246 are tungsten or a tungsten-tantalum alloy. Tungsten can exist as a metastable mixture of an α- and a β-tungsten form, as β-tungsten, or as a more stable α-tungsten form. In some embodiments, the α-tungsten form has a body-centered cubic crystal structure, while the β-tungsten form can have a structure intermediate between amorphous tungsten and α-tungsten (e.g., A15 body-centered cubic). In some embodiments, the mixture of α- and β-tungsten has a larger spin Hall angle than α-tungsten, and it results in lower energy consumption than the more stable α-tungsten.In some embodiments, the mixture of α- and β-tungsten tends to transition to α-tungsten, for example, with increasing thickness of the layers made of the mixture or when these layers are exposed to elevated temperatures, as may be necessary in the manufacture of semiconductor devices. In some embodiments, the tendency of the mixture to transition to α-tungsten can increase with increasing layer thickness. For example, thicker layers of a mixture of α- and β-tungsten can transition to α-tungsten at lower temperatures than thinner layers of a mixture of α- and β-tungsten. In some embodiments, if the metal layers 242 and 246 have (or are made of) a mixture of α- and β-tungsten, the spacer layer 244 may have (or be made of) a material that has a different 3D atomic structure than α-tungsten.The material for the spacer layer 244 is not particularly restricted and may, for example, include: one or more metals or their oxides, such as magnesium, cobalt, magnesium oxide, cobalt oxide, aluminum oxide or the like; ferromagnetic materials, such as ternary mixtures of cobalt-iron-boron (CoFeB), cobalt-palladium (CoPd), cobalt-iron (CoFe), cobalt-iron-boron-tungsten (CoFeBW), nickel-iron (NiFe), magnesium-cobalt (MgCo) or combinations thereof; or other suitable materials. The spacer layer 244 can, for example, contain magnesium oxide, which, unlike the body-centered cubic structure of α-tungsten, has a face-centered cubic crystal structure, and it can therefore inhibit or prevent the conversion of the mixture of α- and β-tungsten of the metal layers 242 and 246 into α-tungsten.

[0028] In alternative embodiments, the spacer layer can have a composite structure. For example, in Fig. Figure 5 shows a sectional view of a storage element ME12 of a semiconductor device SD12 according to some embodiments of the invention. The semiconductor device SD12 can have a similar structure to that described above for the semiconductor device SD10. Fig. 1 has been described, and therefore details not explicitly addressed below may be considered identical to what has been set forth above for the semiconductor device SD10. In some embodiments, the storage element ME12 comprises a spin-Hall electrode 340 and the MTJ 270. The spin-Hall electrode 340 is connected to the conductive vias 212 and 214, with the buffer layer 230 optionally being arranged between the spin-Hall electrode 340 and the conductive vias 212 and 214. The spin-Hall electrode 340 in turn comprises metal layers 342 and 348, which may have similar compositions to those described above for the metal layers 242 and 246 of the storage element ME1. Fig. 4 have been described. In some embodiments, the metal layers 342 and 348 have a mixture of α- and β-tungsten (or are made from it). A spacer layer 344 is arranged between the metal layers 342 and 348, similar to the spacer layer 244 described above. Fig. As described in section 4, in some embodiments the spacer layer 344 is a composite layer comprising a layer 345 of a first material and a layer 346 of a second material with a different composition than the first material. The layer 345 is stacked on top of the metal layer 342, between the metal layer 342 and the layer 346. The layer 346 is stacked on top of the layer 345, between the layer 345 and the metal layer 348. In some embodiments, the material for each layer 345 or 346 can be selected individually, as described above for the material of the spacer layer 244.For example, the materials for layer 345 and layer 346 can be selected to have a 3D atomic structure that differs from that of the stable state of the material of metal layers 342 and 348, in order to prevent or inhibit the transformation of the metastable material of metal layers 342 and 348 into the more stable form. For example, if a mixture of α- and β-tungsten is used as the material for metal layers 342 and 348, the spacer layer 344 can comprise a layer 345 of magnesium (which has a hexagonal crystal structure) and a layer 346 of (amorphous) CoFeB. Of course, the invention is not limited to this, and other combinations of materials are also possible. For example, the order of layers 345 and 346 can be changed, or other combinations of materials can be used.

[0029] In Fig. Figure 6 shows a sectional view of a storage element ME14 of a semiconductor device SD14 according to some embodiments of the invention. The semiconductor device SD14 can have a similar structure to that described above for the semiconductor device SD10. Fig. 1 has been described, and therefore details not explicitly addressed below may be considered identical to what has been set forth above for the semiconductor device SD10. In some embodiments, the storage element ME14 comprises a spin-Hall electrode 360 ​​and the MTJ 270. The spin-Hall electrode 360 ​​is connected to the conductive vias 212 and 214, with the buffer layer 230 optionally arranged between the spin-Hall electrode 360 ​​and the conductive vias 212 and 214. The separating layer 250 may be arranged between the spin-Hall electrode 360 ​​and the MTJ 270. In some embodiments, the spin-Hall electrode 360 ​​may have a simple structure comprising only a metal layer, without the presence of the spin-Hall electrode 240. Fig. 4 or the spacer layers contained in the Spin Hall electrode 340 of Fig. 5. In some embodiments, the single metal layer of the spin-Hall electrode 360 ​​has a metallic material that is used as the metallic material for the metal layers 242 and 246 of Fig. 4 has been chosen. For example, the Spin Hall electrode 360 ​​has a tungsten layer that can initially be produced as β-tungsten.

[0030] To the Spin Hall electrode 240 of Fig. 4, the Spin Hall electrode 340 from Fig. 5 and the Spin Hall electrode 360 ​​from Fig. To characterize 6, a series of semiconductor devices SD16, SD18 and SD20 were fabricated, which were installed in the Fig. 7A, Fig. Figures 7B and 7C are shown. In the semiconductor devices SD16, SD18, and SD20, structures corresponding to the spin Hall electrodes 240, 340, and 360 were fabricated on a substrate 400. The substrate 400 contained silicon, and an oxide layer 410 with a thickness of approximately 200 nm was produced by thermal oxidation. Individual semiconductor devices SD16, such as those described above, were fabricated on the substrate 400. Fig. 7A, manufactured. In some embodiments, a semiconductor wafer was used as the substrate 400.

[0031] In the SD16 semiconductor devices of Fig. In 7A, spin-Hall electrodes 420 with a structure described above for spin-Hall electrode 240 were fabricated. First, a metal layer was produced on the oxide layer 410 by depositing tungsten. The tungsten for the metal layer was deposited by sputtering (e.g., DC sputtering) by applying a power of approximately 40 W to a tungsten target. The resulting metal layer had a wedge profile (e.g., with stepwise decreasing thickness) along a direction perpendicular to the direction of the applied current flow, in order to simultaneously fabricate a series of semiconductor devices SD16 with different thicknesses of metal layers 422 and 426. Subsequently, a spacer layer 424 of the semiconductor devices SD16 was deposited on the metal layers 422 by depositing a layer of magnesium oxide with a thickness T424.Subsequently, a second tungsten deposition was carried out under the aforementioned conditions to produce another wedge-shaped metal layer of a different thickness. That is, semiconductor devices SD16 were fabricated with metal layers 422 and 426 of different thicknesses T422 and T426, corresponding to the different regions of the wedge-shaped metal layers. The deposition conditions for the tungsten in metal layers 422 and 426 were chosen to favor the deposition of a mixture of α- and β-tungsten. After deposition of the top metal layer 426, an annealing process was performed (vacuum of approximately 1.3 x 10⁻⁶ mbar (10⁻⁶ Torr), planar magnetic field of 1 Tesla, 400 °C, 30 min).

[0032] This resulted in the fabrication of several SD16 semiconductor devices with metal layers 422 and 426, representing different total thicknesses (T422 + T426), on different areas of the substrate 400. These areas with varying thicknesses enabled a detailed investigation of the influence of the total thicknesses of the metal layers 422 and 426 in individual SD16 semiconductor devices according to the structure of Fig. 7A. The thicknesses T422 and T426 were varied between different semiconductor devices SD16 fabricated on the same substrate 400, while the metal layers 422 and 426 in a single semiconductor device SD16 were fabricated to have the same thicknesses T422 and T426. In all semiconductor devices SD16, the thickness T424 of the spacer layer 424 was set to 0.7 nm.

[0033] According to a process essentially similar to that described above for the SD16 semiconductor devices, several SD18 semiconductor devices were manufactured by Fig. 7B. Tungsten metal layers 442 were produced as described above for the metal layers 422. Then a magnesium layer (Mg layer) 445 of a spacer layer 444 was deposited on the metal layer 442. Subsequently, a Co 20 Fe 60 B 20Layer 446 of the spacer layer 444 and a metal layer 448 of a mixture of α- and β-tungsten were deposited on the Mg layer 445, as described above for the spacer layer 424 and the metal layer 426, respectively. Finally, the structures were annealed (vacuum of about 1.3 x 10⁻⁶ mbar (10⁻⁶ Torr), planar magnetic field of 1 Tesla, 400 °C, 30 min). Several semiconductor devices SD18 with different total thicknesses (T442 + T448) of the metal layers 442 and 448 were fabricated on the same substrate 400, as described above for the semiconductor device SD16. In the semiconductor device SD18, the spacer layer 444 had a uniform thickness T444 of about 1.35 nm, while the thickness T446 of the Co 20 Fe 60 B 20 -Layer 446 was approximately 0.8 nm thick and the thickness T445 of the magnesium oxide layer 445 was approximately 0.55 nm thick.

[0034] Several SD20 semiconductor devices were developed by Fig. 7C was produced by depositing metal layers of a mixture of α- and β-tungsten of different thicknesses T460 to produce spin Hall electrodes 460 on the oxide layer 410. The deposition conditions for the tungsten were those described above for the metal layers 422 and 426 of Fig. 7A. The same temperature conditions were used as described above (vacuum of approximately 1.3 x 10-6 mbar (10-6 Torr), planar magnetic field of 1 Tesla, 400 °C, 30 min).

[0035] The semiconductor devices SD16, SD18, and SD20, fabricated as described above, were investigated to assess the stability of the corresponding structures after the annealing process and to measure the layer resistance Rs, resistivity ρ, and spin Hall angle α. The layer resistance Rs was measured using a four-point probe method, and the resistivity ρ was then derived taking the thickness into account. The spin Hall angle α was measured using structured Hall rod devices via ferromagnetic spin-torque resonance (ST-FMR).The thickness-dependent tungsten layer structure in the metal layers 422 and 426 was identified by observing X-ray diffraction patterns (Cu-Kα X-ray beam; grazing angle of incidence: 0.5°; 2θ: 20° to 80°, 0.06° / step, 4 s / step) of the annealed semiconductor device SD16 to determine whether the mixture of the α- and β-tungsten forms of the metal layers 422 and 426 remained or transitioned to the α-tungsten form.

[0036] The results of the aforementioned investigations are shown in the diagrams of the Fig. 8A to 10C are specified. In the diagrams of the Fig. 8A to 9 and in the discussion below, the total thickness plotted on the x-axis denotes the combined thickness (T422 + T426, T442 + T448 or T460) of the corresponding metal layers 422, 426, 442, 448 or 460 of the semiconductor devices SD16, SD18 and SD20, excluding the thicknesses T424 and T444 of the spacer layers 424 and 444. For example, in the semiconductor devices SD16, the total thickness shown in the diagram of Fig. 8A, the added thicknesses T422 and T426 of the metal layers 422 and 426, and it differs from the thickness T420 of the spin Hall electrode 420 in that it does not include the thickness T424 of the spacer layer 424. Similarly, in the semiconductor devices SD18, the total thickness shown in the diagram of Fig. 8A represents the added thicknesses T442 and T448 of the metal layers 442 and 448, and it differs from the thickness T440 of the spin Hall electrode 440 in that it does not include the thickness T444 of the spacer layer 444. For the semiconductor devices SD20, the total thickness shown in the diagram of Fig. 8A is applied, the thickness T460 of the single metal layer forming the spin Hall electrode 460. Semiconductor devices SD16, SD18 and SD20 with corresponding total (metal) thicknesses T422 + T426, T442 + T448 or T460 of approximately 3.4 nm, 3.75 nm, 4.1 nm, 4.45 nm, 4.8 nm, 5.2 nm, 5.55 nm, 5.9 nm, 6.25 nm and 6.5 nm were fabricated and investigated.

[0037] In the Fig. 8A and Fig. Figure 8B shows the measured resistivity ρ and the measured film resistance Rs for the semiconductor devices SD16, SD18, and SD20. Data series 470 of Fig. 8A and the 475 data series from Fig. 8B were measured for the semiconductor devices SD16, data series 472 of Fig. 8A and the 477 data series from Fig. 8B were measured for the SD20 semiconductor devices, and the data series 474 of Fig. 8A and the 479 data series from Fig. Measurements were taken for the semiconductor devices SD18. In some embodiments, the resistivity ρ and the layer resistance Rs of the semiconductor devices SD20 drop sharply when the total thickness T460 of the single metal layer of the spin-Hall electrode 460 exceeds approximately 5 nm, indicating that during annealing of layers thicker than approximately 5 nm, the initially deposited mixture of α- and β-tungsten transforms into the more stable α-tungsten. Conversely, if a spacer layer 424 or 444 is inserted, as in the semiconductor devices SD16 and SD18, the transformation of the α- and β-tungsten mixture into α-tungsten can be delayed or even stopped.In the data series for the semiconductor devices SD16, which feature the simple spacer layer 424, the resistivity ρ and the layer resistance Rs are generally higher, and the rates of change of the resistivity ρ and the layer resistance Rs with a total thickness T422 + T426 of the metal layers 422 and 426 are lower than the corresponding values ​​observed in the semiconductor devices SD20. That is, by integrating the spacer layer 424 into the semiconductor devices SD16, the conversion of the mixture of α- and β-tungsten to α-tungsten is at least partially prevented, which enables the fabrication of spin Hall electrodes 420 with a greater total thickness T422 + T426 of the metal layers 422 and 426.When the composite spacer layer 444 is integrated into the semiconductor devices SD18, the resistivity ρ remains essentially constant in the measured area of ​​the total thickness T442 + T448, and the layer resistance Rs has a significantly lower rate of change than that observed in the semiconductor devices SD20. This indicates that the composite spacer layer 444 may be particularly effective in stabilizing the structure of the metal layers 422 and 428 in the semiconductor device SD18. In some embodiments, the conversion of the α- and β-tungsten mixture to α-tungsten in spin Hall electrodes 440, which incorporate a composite spacer layer 444, can be (completely) stopped.

[0038] The aforementioned observations were further corroborated by the data presented in Fig. Figure 9 is plotted for the measured spin Hall angle α. Fig. 9. A data series 482 was measured for the semiconductor devices SD16, a data series 484 was measured for the semiconductor devices SD18, and a data series 486 was measured for the semiconductor devices SD20. The data from Fig. Figure 9 shows that the composite spin-Hall electrodes 420 and 440 have larger spin-Hall angles α, independent of the structure of the spacer layer 424 or 444, with the spin-Hall angles α reaching up to 0.45 and generally being larger than those of the semiconductor device SD20, which has the thickest layer of the mixture of α- and β-tungsten of about 5 nm.

[0039] The increased stability of the layers made from the mixture of α- and β-tungsten in the semiconductor devices SD16 and SD18 is further confirmed by the X-ray diffraction images obtained in the Fig. 10A to 10C are shown. The data from Fig. 10A were measured for semiconductor devices SD16, which had a total thickness T422 + T426 of the metal layers 422 and 426 of approximately 3.8 nm (curve 492) and 6.3 nm (curve 494). The data from Fig. 10B were measured for semiconductor devices SD18, which had a total thickness T442 + T4448 of the metal layers 442 and 448 of approximately 3.8 nm (curve 502) and 6.3 nm (curve 504). The data from Fig. 10C were measured for semiconductor devices SD20, which had a thickness T460 of 3.8 nm (curve 512) and 6.3 nm (curve 514). From the Fig. Figures 10A to 10C show that in the curves for the smaller thicknesses (curves 492, 502, and 512), the peak structure of crystalline α-tungsten is essentially absent in all semiconductor devices SD16, SD18, and SD20, while in curve 514 for the larger thickness, the semiconductor device SD20 shows pronounced peaks due to crystalline α-tungsten. In contrast, α-tungsten peaks are barely visible in the thicker semiconductor devices SD16 with the simple spacer layer 424 (curve 494), and they are largely absent in the thicker semiconductor devices SD18 with the composite spacer layer 444.This means that X-ray diffraction analysis also confirms that the simple spacer layer 424 of the semiconductor devices SD16 at least improves the stability of the thicker layers made of the mixture of α- and β-tungsten, while the composite spacer layer 444 of the semiconductor devices SD18 can further stabilize or even completely stop the conversion of the mixture of α- and β-tungsten into α-tungsten.

[0040] Based on the above, the Spin Hall electrode 240 can be used by Fig. 4 (or the Spin Hall electrode 420 from Fig. 7A) and the Spin Hall electrode 340 from Fig. 5 (or the Spin Hall electrode 440 from Fig. 7B) with the simple spacer layers 244 (or 424) or the compound spacer layers 344 (or 444) with a total thickness of the metastable spin-Hall material (e.g. the mixture of α- and β-tungsten) of more than 5 nm, they can withstand the annealing conditions and can exhibit spin-Hall angles α of more than 0.4. In some embodiments, the individual thicknesses of the metal layers 242 and 246 or 342 and 348 can be about 1 nm to about 4 nm, and the individual thicknesses of the spacer layers 244 and 344 can be in the range corresponding to the thickness of a monolayer of spacer material (e.g., a monolayer of magnesium or magnesium oxide from 0.07 nm to 0.3 nm; or a quarter monolayer of CoFeB of about 0.05 nm; or a quarter monolayer of Co from 0.07 nm to 0.13 nm) or the thickness of several (e.g., 3 to 8) monolayers of spacer materials (e.g.,four monolayers of magnesium oxide from about 0.8 nm to 1.3 nm; four monolayers of magnesium from about 1 nm or about six monolayers of CoFeB from about 0.86 nm or four monolayers of Co from about 1 nm to 2 nm).

[0041] The Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. 20 are schematic representations showing structures that form during a manufacturing process for semiconductor devices, such as the SD10 semiconductor device from Fig. 1, according to some embodiments of the invention. In Fig. Figure 11 shows the semiconductor substrate 102 with the transistors 110 and 120 fabricated on it. The substrate 102 can be structured to form microstructures such as fins, plates, and the like, for example, according to the desired architecture for the transistors 110 and 120. Likewise, the transistors 110 and 120 can be fabricated using any suitable manufacturing process, such as a gate-first or gate-last process. The gate structures 114 and 124, as well as the dummy gate structures 132 and 142, can include one or more spacers, as well as adhesive layers, interface layers, high-k dielectric layers, output function setting layers, gate electrodes, and the like, according to the requirements of the circuits. The invention does not limit the structures of the transistors 110 and 120.

[0042] In Fig. In step 12, the ILD 150 is fabricated over the substrate 102, initially burying the transistors 110 and 120. The ILD 150 can comprise dielectric low-k materials, such as xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bis-benzocyclobutene), hydrogen silsesquioxane (HSQ), fluorinated silicon dioxide (SiOF), or a combination thereof. In some embodiments, the ILD 150 can be fabricated to a suitable thickness by flowable chemical vapor deposition (FCVD), CVD, high-density plasma chemical vapor deposition (HDP-CVD), reduced-pressure chemical vapor deposition (SACVD), spin deposition, sputtering, or other suitable methods. In some embodiments, the ILD 150 can be fabricated in several steps and can be formed from two or more layers, which may comprise the same or different dielectric materials.The ILD 150 is structured to create openings that expose the source and drain regions 112S, 112D, 122S, and 122D of transistors 110 and 120 on its underside. Additional openings can be created to expose the gate structures 114 and 124. The openings of the ILD 150 are then filled with a conductive material to create the conductive vias 160. In some embodiments, the conductive material for the conductive vias 160 is aluminum, titanium, copper, nickel, tungsten, and / or an alloy thereof, and it can be produced by a variety of deposition processes (e.g., CVD, plating, or other suitable processes) and planarization processes (e.g., chemical-mechanical polishing).

[0043] In Fig. 13. The conductive traces 182 and 184 and the conductive structures 192 and 194 are fabricated over the conductive vias 160. The ILD 170 can be fabricated using similar materials and processes as the ILD 150 and can embed the conductive traces 182 and 184 and the conductive structures 192 and 194. In some embodiments, an ILD 170 can first be fabricated having openings that expose the conductive vias 160 on its underside. These openings are then filled with a conductive material to fabricate the conductive traces 182 and 184 and the conductive structures 192 and 194.In some alternative embodiments, the conductive lines 182 and 184 and the conductive structures 192 and 194 can first be fabricated, for example, by depositing the conductive material over the ILD 150 and the conductive vias 160, structuring it, and then depositing the material for the ILD 170. In some embodiments, the ILDs 150 and 170 are fabricated together, and the conductive lines 182 and 184 and the conductive structures 192 and 194 are fabricated as a unit with the corresponding conductive vias 160. In general, the position (with respect to the height relative to the semiconductor substrate 102) of the boundaries between the ILDs (e.g., 150 and 170) can depend on the subsequent process for fabricating the interconnect structure IN.

[0044] In Fig. 14. Another ILD 200 and further conductive vias 210 are fabricated using similar processes and materials as described above for the ILD 150 and the conductive vias 160, respectively. Subsequently, precursor layers for the memory elements ME1 and ME2 (which are, for example, in Fig. (as shown in Figure 1) are deposited on the ILD 200 and the conductive vias 210, forming a layer stack that protectively covers the ILD 200. For example, the buffer layer 230 can first be fabricated over the entire ILD 200 to cover the area where several memory cells MC1 and MC2 are to be produced. In some embodiments, the buffer layer 230 can be deposited using suitable deposition methods such as CVD, PVD (physical vapor deposition), ALD (atomic layer deposition), or the like. In some embodiments, the buffer layer 230 can comprise magnesium oxide or other suitable materials and can be deposited with a thickness of approximately 0.2 nm to 0.9 nm. Then, the layers for the spin-Hall electrode 240 can be deposited successively, for example, according to the method described above for the semiconductor device SD16. Fig. 7A, or, if composite spacer layers are desired, according to the methods described above for the semiconductor device SD18 of Fig. 7B. Subsequently, the material for the separation layer 250 can be deposited on the spin-Hall electrode 240, and then the layers for the MTJ 270 can be fabricated on the separation layer 250. In the structure described in Fig. As shown in Figure 14, the layers of the spin Hall electrode 240 and the MTJ 270 (as well as the separation layer 250, if present) extend over the area in which the memory cells MC1 and MC2 are to be manufactured.

[0045] In some embodiments, an annealing process can be performed. In some embodiments, the annealing process can be carried out in situ with a perpendicular magnetic field to increase the perpendicular magnetic anisotropy of the annealed layers. In some embodiments, the annealing process can be carried out in situ with a horizontal magnetic field to increase the planar magnetic anisotropy of the annealed layers. In some embodiments, the layers for the spin-Hall electrode 240 and the MTJ 270 are deposited prior to a normal annealing process. In some embodiments, maintaining a vacuum during the deposition of the spin-Hall electrode 240 and the MTJ 270 allows for the formation of higher-quality interfaces between the deposited layers.In some embodiments, the spin Hall electrode 240 has a composite structure with a spacer layer, such as the spacer layer 244 of . Fig. 4 or the spacer layer 344 of Fig. 5. Therefore, even if metal layers (e.g., 242 and 246 of Fig. 4 or Fig. 342 and Fig. 348 of Fig. 5) the spin-Hall electrode 240 has a metastable spin-Hall material, the metastable material withstands the annealing process without, or only to a limited extent, transitioning into several stable forms.

[0046] In Fig. 15. A hard mask 280 is produced on the top layer of the MTJ 270. The hard mask 280 can be produced by any suitable method and from any suitable material. For example, the hard mask 280 can comprise dielectric materials, such as silicon oxide, silicon nitride, or silicon oxide nitride, or conductive materials, such as tantalum, tungsten, or titanium nitride, or combinations thereof. In some embodiments, the hard mask 280 can have multiple layers, with the upper layers being used to define structures of the lower layers (e.g., the layers that extend closer to the MTJ 270). In some embodiments, a lower layer of the hard mask 280 can comprise tantalum, and an upper layer of the hard mask 280 can comprise silicon nitride, but the invention is not limited thereto, and other suitable combinations of materials can optionally be used.

[0047] In the Fig. 15 and Fig. 16 The structure of the hard mask 280 is transferred, for example, to the layers of the MTJ 270 during one or more etching steps. The etching can be performed using any suitable etching method, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma etching (ICP), ion beam etching (IBE), or the like, or a combination thereof. The etching can be anisotropic. After structuring the layers of the MTJ 270, a plurality of MTJs 270 are fabricated according to the desired positions for the memory cells MC1 and MC2. In some embodiments, the MTJs 270 can have conical sidewalls, depending on the structuring conditions. In some embodiments, the hard masks 280 can remain on the MTJs 270 even after the structuring process. In some embodiments, the etching of the layers of the MTJ 270 ends at the separation layer 250.In some alternative embodiments, the etching can be carried out through the separation layer 250, and even the layers of the spin Hall electrode 240 can be partially omitted.

[0048] In Fig. 17. A protective layer 290 is deposited over the structured MTJs 270 and the hard masks 280 located above them by protective deposition. In some embodiments, the protective layer 290 extends protectively over the entire area in which the memory cells MC1 and MC2 are to be manufactured. In some embodiments, the protective layer 290 extends over the separation layer 250 (if present) that has been exposed after structuring the MTJs 270 and conformally covers the sidewalls of the MTJs 270. In some embodiments, the protective layer 290 comprises a dielectric material such as silicon carbide, silicon oxide carbide, silicon nitride, silicon oxide, silicon oxide nitride, silicon carbon oxide nitride, or other suitable dielectric materials. In some embodiments, the protective layer 290 is produced by a suitable deposition process such as PVD, CVD, ALD, or the like, or a combination thereof.In some embodiments, the protective layer 290 comprises silicon nitride produced by CVD. In some embodiments, oxides produced by less reactive processes, such as PVD, can also be used.

[0049] In Fig. 18. The protective layer 290 and the underlying layers of the spin-Hall electrode 240 (as well as the separating layer 250 and the buffer layer 230, if present) are structured, for example, by one or more etching processes to define the spin-Hall electrodes 240 for the individual memory cells MC1 and MC2. The etching can be performed using any suitable etching method, such as wet or dry etching, RIE, NBE, or the like, or a combination thereof. The etching can be anisotropic.

[0050] In Fig. 19. After structuring the spin Hall electrodes 240, an ILD 260 is fabricated to encapsulate the spin Hall electrodes 240 and the MTJs 270. The materials and methods for fabricating the ILD 260 can be selected as described above for the ILD 150. In some embodiments, the ILD 260 is fabricated with sufficient thickness to completely cover the protective layer 290 even after planarization. In some alternative embodiments, the ILD 260 can be planarized to expose the protective layer 290 on the hard mask 280 or even to remove a portion of the protective layer 290 extending onto the hard mask 280, thus exposing the hard mask 280.

[0051] In Fig. 20. The conductive vias 300 are fabricated through the ILD 260 such that they contact the MTJs 270. The materials and methods for fabricating the conductive vias 300 can be selected as described above for the conductive vias 160. In some embodiments, the conductive vias 300 extend through the protective layer 290 and the hard mask 280 to contact the MTJs 270. In some embodiments, if the hard masks 280 are fabricated from a conductive material and used as the top electrodes of the MTJs 270, the conductive vias 300 can be mounted on the hard masks 280. The semiconductor device SD10 of Fig. 1 can be derived from the structure of Fig. 20 can be obtained by fabricating an ILD 310 and the conductive lines 320, for example, using the materials and processes described above for the ILD 170 and the conductive lines 182 and 184. In some embodiments, further process steps can be used, for example, to fabricate additional interconnect layers or to provide conductive contact mounds to enable integration of the semiconductor device SD10 into larger devices.

[0052] In Fig. Figure 21A shows a sectional view of a storage element ME22 of a semiconductor device SD22 according to some embodiments of the invention. The semiconductor device SD22 can have a similar structure to that described above for the semiconductor device SD10. Fig. The storage element ME22 has been described in Section 1, and therefore details not explicitly addressed below can be considered identical to what has been set forth above for the semiconductor device SD10. In some embodiments, the storage element ME22 comprises a spin-Hall electrode 520 and the MTJ 270. The spin-Hall electrode 520 is connected to the conductive vias 212 and 214, with the buffer layer 230 optionally being arranged between the spin-Hall electrode 520 and the conductive vias 212 and 214. The separator layer 250 can be arranged between the spin-Hall electrode 520 and the MTJ 270. In some embodiments, the spin-Hall electrode 520 comprises three metal layers 521, 523, and 525, which are stacked alternately with two spacer layers 522 and 524.The metal layers 521, 523 and 525 may have similar compositions to those described above for the metal layers 242 and 246 of the storage element ME1 of . Fig. 4 have been described, and the spacer layers 522 and 524 may have similar compositions to those described above for the spacer layer 224 of Fig. 4 have been described. In some embodiments, the metal layers 521, 523, and 525 comprise (or are made of) a mixture of α- and β-tungsten, and the spacer layers 522 and 524 comprise (or are made of) magnesium oxide. The spacer layers 522 and 524 separate successive metal layers 521, 523, and 525 in a similar manner to that described above for spacer layer 224 of Fig. 4 has been explained.

[0053] In the semiconductor device SD22, the spacer layers 522 and 524 have a single-layer structure similar to the spacer layer 224 of Fig. 4, but the invention is not limited thereto. For example, in memory elements ME24, a semiconductor device SD24, which is located in Fig. Figure 21B shows a spin Hall electrode 530 comprising metal layers 531, 535 and 539 separated from each other by composite spacer layers 532 and 536, each spacer layer 532 and 536 having a similar structure to that described above for spacer layer 344 of Fig. 5 as described above. The spacer layer 532 can, for example, be arranged between the metal layers 531 and 535, and it can have a layer 533 produced on the metal layer 531 and a layer 534 produced on the layer 533, wherein the metal layer 535 is produced on the layer 534. The layer 533 can have a different material than the layer 534. The materials for the layers 533 and 534 can be selected as described above for layers 345 and 346 of Fig. As described in section 5. For example, layer 534 can be an (amorphous) CoFeB layer, and layer 533 can be a (hexagonal) magnesium layer. The spacer layer 536 can have the same structure as the spacer layer 532, wherein, for example, layer 538 is an (amorphous) CoFeB layer and layer 537 is a (hexagonal) magnesium layer. The invention is, of course, not limited thereto, and other combinations of materials are also possible.

[0054] To use the Spin Hall electrode 520 from Fig. 21A and the Spin Hall electrode 530 from Fig. To characterize 21B, semiconductor devices SD26, which are in Fig. 22A are shown, and semiconductor devices SD28, which are in Fig. Figure 22B shows the fabrication of structures corresponding to the spin Hall electrodes 520 and 530 in semiconductor devices SD26 and SD28. These structures were fabricated over substrate 400 using processes similar to those described above. In a single semiconductor device SD26, metal layers 541, 543, and 545 of equal thicknesses T541, T543, and T545 were fabricated, and spacer layers 542 and 544 of equal thicknesses T542 and T544 were fabricated. The same applies to metal layers 551, 555, and 559 and spacer layers 552 and 556 of semiconductor devices SD28. A series of semiconductor devices SD26 and SD28 with different total thicknesses T541 + T543 + T545 and T551 + T555 + T559 of the metal layers 541, 543, 545, 551, 555 and 559 were fabricated. In the SD26 semiconductor devices of this series, the spacer layers 542 and 544 were magnesium oxide layers with individual thicknesses T542 and T544 of approximately 0.7 nm.In the SD28 semiconductor devices of this series, the spacer layers 552 and 556 Co. 20 Fe 60 B 20 -Layers 554 and 558 with individual thicknesses T554 and T558 of about 0.8 nm and magnesium layers 553 and 557 with individual thicknesses T553 and T557 of about 0.55 nm.

[0055] Semiconductor devices SD26 and SD28 with corresponding total (metal) thicknesses T541 + T543 + T545 or T551 + T555 + T559 of approximately 3.4 nm, 3.75 nm, 4.1 nm, 4.45 nm, 4.8 nm, 5.2 nm, 5.55 nm, 5.9 nm, 6.25 nm and 6.5 nm were fabricated and investigated in the same manner as described above for the semiconductor devices SD16, SD18 and SD20. Fig. 7A to 7C has been explained. In the diagrams of the Fig. 23A and Fig. 23B denotes the total thickness plotted on the abscissa axes as the combined thickness T541 + T543 + T545 or T551 + T555 + T559 of the metal layers 541, 543 and 545 or 551, 555 and 559 of a mixture of α- and β-tungsten, without taking into account the thicknesses T542, T544, T552 and T556 of the spacer layers 542, 544, 552 and 556. In the Fig. 23A and Fig. In 23B, data series 562 and 566 were obtained from semiconductor devices SD26, and data series 564 and 568 were obtained from semiconductor devices SD28. For easy comparison, in the Fig. 23A and Fig. 23B also plotted the data series 470 and 475 obtained from the semiconductor devices SD16, as well as the data series 474 and 479 obtained from the semiconductor devices SD18.

[0056] As through the in the Fig. 23A and Fig. As shown in the data plotted on Figure 23B, spin-Hall electrodes that have several simple spacer layers, such as the spin-Hall electrode 520 from Fig. 21A or the Spin Hall electrode 540 from Fig. 22A, a higher resistivity ρ and a higher layer resistance Rs than spin-Hall electrodes that only have a simple spacer layer, such as the spin-Hall electrodes 240 from Fig. 4 or the Spin Hall electrodes 420 from Fig. 7A. Without limiting oneself to a single theory, the observed increase in resistivity ρ and layer resistance Rs may be caused by increased scattering at the interfaces between the magnesium oxide spacer layers (e.g., 542 and 544) and the metal layers (e.g., 541, 543, and 545). The increased stability of the metastable mixture of α- and β-tungsten is also observed in the SD26 semiconductor devices.

[0057] In contrast, spin-Hall electrodes that have several composite spacer layers, such as the Spin-Hall electrode 530 from Fig. 21B or the Spin Hall electrode 550 from Fig. 22B, a lower resistivity ρ than spin-Hall electrodes that only have a composite spacer layer, such as the spin-Hall electrode 340 from Fig. 5 or the Spin Hall electrode 430 from Fig. 7B. Without limiting oneself to a single theory, the observed decrease in resistivity ρ could be attributed to the parallel resistance effect. A comparison of data series 474 with data series 564 and a comparison of data series 479 with data series 568 show that the stability of the metal layers made from the mixture of α- and β-tungsten (e.g., metal layers 551, 555, and 559) is comparable to the stability observed for the spin Hall electrode 340 or 430, which have only a composite spacer layer. That is, the conversion of the mixture of α- and β-tungsten to α-tungsten is strongly inhibited, if not completely stopped. The comparable stability of the layers made from the metastable mixture of α- and β-tungsten is further confirmed by the analysis of the X-ray diffraction pattern for the semiconductor devices SD28, which was presented in Fig. 24 is plotted. A comparison of the diffraction patterns measured for the semiconductor devices SD28 with a total thickness T551 + T555 + T559 of the metal layers 551, 555 and 559 of about 3.8 nm (curve 582) and 6.3 nm (curve 584) shows, if anything, only slight changes, without a significant increase in peaks originating from α-tungsten.

[0058] In Fig. Figure 25 shows a sectional view of a storage element ME30 of a semiconductor device SD30 according to some embodiments of the invention. The semiconductor device SD30 can have a similar structure to that described above for the semiconductor device SD10. Fig. As described in Section 1, details not explicitly addressed below can be considered identical to what has been set forth above for the semiconductor device SD10. In some embodiments, the storage element ME30 comprises a spin Hall electrode 590 and the MTJ 270. The spin Hall electrode 590 is connected to the conductive vias 212 and 214, with the buffer layer 230 optionally arranged between the spin Hall electrode 590 and the conductive vias 212 and 214. The separator layer 250 can be arranged between the spin Hall electrode 590 and the MTJ 270. In some embodiments, the spin Hall electrode 590 has several metal layers 591, 593, 595, 597 and 599, which are stacked alternately with spacer layers 592, 594, 596 and 598. Fig. Figure 25 shows only some metal layers 591, 593, 595, 597, and 599 and only some spacer layers 592, 594, 596, and 598, with further layers schematically represented by dots. In the invention, the number of metal layers 591, 593, 595, 597, and 599 or of spacer layers 592, 594, 596, and 598 is not limited, and the numbers can be determined according to the application requirements. The metal layers 591, 593, 595, 597, and 599 can have similar compositions to those described above for the metal layers 242 and 246 of the storage element ME1. Fig. 4 have been described, and the spacer layers 592, 594, 596 and 598 may have similar compositions to those described above for the spacer layer 224 of Fig. 4 have been described. In some embodiments, the metal layers 591, 593, 595, 597, and 599 comprise (or are made of) a mixture of α- and β-tungsten, and the spacer layers 592, 594, 596, and 598 comprise (or are made of) magnesium oxide. For example, each metal layer 591, 593, 595, 597, and 599 can be a layer of a mixture of α- and β-tungsten with a thickness of about 1 nm to 3 nm, e.g., about 2.5 nm, and each spacer layer 592, 594, 596, and 598 can be a magnesium oxide layer with a thickness of about 0.21 nm to about 0.84 nm, corresponding to about 1 to 4 monolayers of magnesium oxide. Such a spin-Hall electrode 590 has a thermal stability up to 400 °C and a spin-Hall angle α of about 0.45.The spacer layers 592, 594, 596 and 598 separate successive metal layers 591, 593, 595, 597 and 599 in a similar manner to that described above for the spacer layer 224 of . Fig. 4 has been explained.

[0059] In the semiconductor device SD30, the spacer layers 592, 594, 596 and 598 have a single-layer structure like the spacer layer 224 of Fig. 4, but the invention is not limited thereto. For example, in memory elements ME32, a semiconductor device SD32, which is located in Fig. Figure 26 shows a spin-Hall electrode 600 comprising metal layers 601, 605, 609, 613 and 617 separated from each other by composite spacer layers 602, 606, 610 and 614, each spacer layer 602, 606, 610 and 614 having a similar structure to that described above for spacer layer 344 of Fig. 5 as described above. The spacer layer 602 can, for example, be arranged between the metal layers 601 and 605, and it can have a layer 603 produced on the metal layer 601 and a layer 604 produced on the layer 603, wherein the metal layer 605 is produced on the layer 604. The layer 603 can have a different material than the layer 604. The materials for the layers 603 and 604 can be selected as described above for layers 345 and 346 of Fig. As outlined in Section 5. For example, layer 604 can be an (amorphous) CoFeB layer, and layer 603 can be a (hexagonal) magnesium layer. The other spacer layers 606, 610, and 614 can have the same structure as spacer layer 602, with layers 608, 612, and 616 being, for example, (amorphous) CoFeB layers, and layers 607, 611, and 615 being, for example, (hexagonal) magnesium layers. For example, each metal layer 601, 605, 609, 613, and 617 can be a layer of a mixture of α- and β-tungsten with a thickness of about 1 nm to 4 nm, e.g., 3.3 nm. Each layer 604, 608, 612, and 616 can be a CoFeB layer with a thickness of approximately 0.14 nm to approximately 0.86 nm, corresponding to approximately 1 to 6 monolayers of CoFeB with a thickness of, for example, approximately 0.8 nm. Each layer 603, 607, 611, and 615 can be a magnesium layer with a thickness of approximately 0.07 nm to approximately 1.04 nm, corresponding to approximately 1 to 4 monolayers of magnesium.Such a spin-Hall electrode 600 has thermal stability up to 400 °C and a spin-Hall angle α of approximately 0.39. Of course, the invention is not limited to this, and other combinations of materials are also possible.

[0060] In Fig. Figure 27 shows a schematic representation of a semiconductor device SD34 according to some embodiments of the invention. The semiconductor device SD34 can have a similar structure to that described above for the semiconductor device SD10. Fig. 1 has been described, and therefore details not explicitly addressed below may be considered identical to what has been set forth above for the semiconductor device SD10. The semiconductor device SD34 has memory cells MC33 and MC34, which have a similar structure to the memory cells MC1 and MC2 of Fig. 1. A difference between memory elements ME33 and ME34 of the semiconductor device SD34 on the one hand and the memory elements ME1 and ME2 of the semiconductor device SD10 on the other hand lies in the relative elongation of the separation layer 250 with respect to the underlying spin-Hall electrode 240. For example, in the process which is described in the Fig. 15, Fig. 16 to Fig. As shown in Figure 17, the separating layers 250 are structured together with the layers of the spin Hall electrodes 240 such that the separating layers 250 project laterally with respect to the MTJs 270 above them and have essentially the same footprint as the spin Hall electrodes 240 below them. However, in the semiconductor device SD34, the separating layers 250 are structured together with the MTJs 270 above them such that the spin Hall electrodes 240 project laterally with respect to the separating layers 250 above them. Consequently, the protective layers 290 are in contact with portions of the spin Hall electrodes 240 that are no longer covered by the separating layers 250. In some embodiments, the 3D atomic structure of the protective layers 290 differs from the 3D atomic structure of the top metal layer of the spin Hall electrode 240.Although the spin Hall electrodes 240 are included in the semiconductor device SD34, the invention is of course not limited to this device. In some alternative embodiments, another spin Hall electrode discussed above can be used instead of the spin Hall electrode 240, including the spin Hall electrode 340 from [reference missing]. Fig. 5, the Spin Hall electrode 520 from Fig. 21A or the Spin Hall electrode 530 from Fig. 21B. In other words, the structuring process for the separation layer 250, as carried out in the semiconductor device SD34, can be used for any other storage element of the invention.

[0061] In Fig. Figure 28 shows a schematic representation of a semiconductor device SD36 according to some embodiments of the invention. The semiconductor device SD36 can have a similar structure to that described above for the semiconductor device SD10. Fig. 1 has been described, and therefore details not explicitly addressed below may be considered identical to what has been set forth above for the semiconductor device SD10. The semiconductor device SD36 has memory cells MC35 and MC36, which have a similar structure to the memory cells MC1 and MC2 of Fig. One difference between memory cells MC35 and MC36 of semiconductor device SD36 on the one hand, and memory cells MC1 and MC2 of semiconductor device SD10 on the other, is that transistor 120 of memory cell MC35 shares the source region 122S with transistor 110 of the adjacent memory cell MC36. That is, a common conductive line 185 can be connected to the source region 122S via a common conductive via 169. Since each memory cell MC35 and MC36 is controlled by a pair of driver transistors 110 and 120, even if one of the conductive lines 185, which acts as a source line, is shared by the two memory cells MC35 and MC36, the memory cells MC35 and MC36 can still be selectively addressed with respect to each other because of the non-shared conductive lines 182 and 184.In some embodiments, the device density of the semiconductor device SD36 can be increased by having adjacent memory cells MC35 and MC36 share a single conductive line 185. Although the spin Hall electrodes 240 are included in the semiconductor device SD36, the invention is not limited to this. In some alternative embodiments, another spin Hall electrode described above can be used instead of the spin Hall electrode 240, including the spin Hall electrode 340. Fig. 5, the Spin Hall electrode 520 from Fig. 21A or the Spin Hall electrode 530 from Fig. 21B.

[0062] In Fig. Figure 29 shows a schematic representation of a semiconductor device SD38 according to some embodiments of the invention. The semiconductor device SD38 can have a similar structure to that described above for the semiconductor device SD10. Fig. The semiconductor device SD38 has been described in Section 1, and therefore details not explicitly addressed below may be considered identical to what has been set forth above for the semiconductor device SD10. The semiconductor device SD38 also includes a semiconductor substrate 620 on which active and passive devices, such as transistors 630, are fabricated. The transistors 630 may have a structure similar to transistors 110 and 120, and they feature source and drain regions 632 and gate structures 634 arranged on channel regions 636 between the source and drain regions 632. The transistors 630 may have any transistor geometry and may be, among others, planar transistors, fin field-effect transistors, gate-all-around transistors, or the like. Dummy channels 640 and dummy gate structures 642 may be fabricated between adjacent transistors 630 for greater process uniformity.One or more ILDs 650 and 652 can be fabricated on the semiconductor substrate 620, the ILDs having conductive vias 660 and conductive traces 670 extending through them to contact the active and passive devices fabricated on the semiconductor substrate 620. Further interconnect layers can be fabricated on the bottommost ILDs 650 and 652, each further layer having its own interlayer dielectric 680 and its own conductive traces 682 (which are shown in ). Fig. 29 are represented schematically by points) and has 684.

[0063] In some embodiments, transistors 700 and 710 are embedded in an upper ILD 690 within an interconnect structure IN2 of the semiconductor device SD38. The transistors 700 and 710 can be BEOL transistors (BEOL: Back End of Line), each comprising a corresponding semiconductor channel layer 701 or 711, a high-k dielectric layer 703 or 713, source and drain contacts 705S and 705D or 715S and 715D, and a gate contact 707 or 717. Portions of the interlayer dielectric 690 can separate the transistors 700 and 710 from each other and from the underlying conductive lines 684. The transistors 700 and 710 are in Fig. Although the transistors in Figure 29 have been represented with a specific geometry, the invention is not limited to this, and any transistor architecture can be used for the 700 and 710 transistors according to the requirements of the application.

[0064] In some embodiments, transistors 700 and 710 are used as driver transistors for the MC38 memory cells of the SD38 semiconductor device. That is, in the SD38 semiconductor device, the transistors 630, fabricated on the semiconductor substrate 620, can be used to perform other logic functions, while the BEOL transistors 700 and 710 are integrated into the MC38 memory cells. The source and drain contacts 705S, 705D, 715S, and 715D and the gate contacts 707 and 717 of the driver transistors 700 and 710 are contacted by dedicated through-holes 720 to be connected to corresponding conductive lines 731, 732, 735, and 736 or conductive structures 733 and 734.For example, conductive lines 731 and 736 can be used as source lines for the MC38 memory cells, and conductive lines 732 and 735 can be used to apply a potential to the gate contacts 707 and 717 and as word lines for the MC38 memory cells. Conductive structures 733 and 734 connect the conductive vias 720, which are located on the drain contacts 705D and 715D, in a bridge with conductive vias 750, which extend through an ILD 740, to connect the transistors 700 and 710 to the memory elements ME38 of the MC38 memory cells. The memory elements ME38 can have the structure of another memory element of the invention. For example, the ME38 storage elements can have a spin-Hall electrode 770 and an MTJ 790, wherein the spin-Hall electrode 770 can have the structure of a spin-Hall electrode described above, including the spin-Hall electrode 240 of . Fig. 4, the Spin Hall electrode 340 from Fig. 5, the Spin Hall electrode 520 from Fig. 21A or the Spin Hall electrode 530 from Fig. 21B. Optionally, a buffer layer 760 and a spacer layer 780 may be used, the spacer layer 780 being able to coincide with the spin-Hall electrode 770 or the MTJ 790. The memory elements ME38 may also have hard masks 800 and a protective layer 810, which may be configured according to any of the embodiments described above and may optionally be embedded in an ILD 820. Conductive vias 830 connect the MTJs 790 to conductive lines 850 embedded in an ILD 840, the conductive lines 850 being used as bit lines of the memory cells MC38. Fig. 29. Although the driver transistors 700 and 710 are arranged between the spin Hall electrodes 770 and the semiconductor substrate 620, the invention is not limited thereto. In some alternative embodiments, the MTJs 790 can be arranged between the spin Hall electrodes 770 and the semiconductor substrate 620, and the spin Hall electrodes 770 can be arranged between the driver transistors 700 and 710 and the semiconductor substrate 620.

[0065] The embodiments of the spin-Hall electrodes described above (e.g., 240, 340, 360, 420, 440, 460, 520, 530, 540, 550, 590, 600, and 770) have generally been described and illustrated as spin-Hall electrodes in which a metal layer is first produced before a spacer layer, but the aforementioned spin-Hall electrodes can also have a spacer layer that is produced before a metal layer. For example, in Fig. 4. After the fabrication of the spacer layer 244, the metal layer 242 is fabricated on the spacer layer 244. In this example, another spacer layer can be fabricated on the metal layer 242, and subsequently, optionally, another metal layer 246 can be fabricated, as specified for the spin Hall electrode design.

[0066] In some embodiments, layer stacks in the spin Hall electrodes can be repeated up to 10 times. For example, in the spin Hall electrode 240 of Fig. 4 of the layer stacks 242 / 244 / 246 can be repeated up to 10 times.

[0067] One embodiment relates to a semiconductor device. The semiconductor device comprises: a pair of transistors on a semiconductor substrate; and an interconnect structure over the pair of transistors, wherein the interconnect structure comprises: metal conductors and vias arranged over and connected to the pair of transistors, a composite spin-Hall electrode over the metal conductors and vias, the composite spin-Hall electrode being electrically connected to the pair of transistors through the metal conductors and vias, and comprising a first metal layer and a first spacer layer, wherein the first metal layer contains a first heavy metal in a mixture of α and β states, and the first spacer layer contains a first material different from that of the first metal layer.The device also features a magnetic tunnel contact over the composite spin Hall electrode.

[0068] Embodiments may have one or more of the following features. The first metal is a mixture of α- and β-tungsten. The first spacer layer contains a metal oxide. The metal oxide is magnesium oxide with a face-centered cubic crystal structure. The first spacer layer is arranged above the first metal layer. The semiconductor device further comprises a second metal layer above the first spacer layer, wherein the second metal layer contains a first heavy metal in a mixture of α- and β-states. The first metal layer is arranged above the first spacer layer. The semiconductor device further comprises a second spacer layer above the first metal layer, wherein the second spacer layer contains the first material, which is different from the first metal layer. The first spacer layer is made of an insulating material.The first spacer layer is made of a crystalline metal and an amorphous ferromagnetic material.

[0069] One embodiment relates to a storage device. The storage device has a first storage cell above a substrate, the first storage cell comprising: a first transistor and a second transistor on the substrate; first conductive lines and first conductive vias above and in electrical connection with the first and second transistors; a composite spin-Hall electrode above and in electrical connection with the first conductive lines and the first conductive vias, the composite spin-Hall electrode comprising a first tungsten-based layer and a second tungsten-based layer separated by a first spacer, the first tungsten-based layer containing a first mixture of α- and β-tungsten and the second tungsten-based layer containing a second mixture of α- and β-tungsten;a magnetic tunnel contact over the second tungsten-based layer; and second conductive conductors and second conductive vias over and in electrical connection with the magnetic tunnel contact.

[0070] Embodiments may have one or more of the following features. In the storage device, the first spacer is configured to interrupt the conversion of tungsten from the β-phase to the α-phase in the first and second tungsten-based layers. The composite spin Hall electrode further comprises a third tungsten-based layer above the second tungsten-based layer and is separated from the second tungsten-based layer by a second spacer, wherein the third tungsten-based layer contains a third mixture of α- and β-tungsten. The second spacer comprises a plurality of layers, wherein at least one of the plurality of layers is a crystalline material and at least one of the plurality of layers is an amorphous material, the crystalline material comprising magnesium and the amorphous material comprising cobalt.The storage device also features a buffer layer between the first conductive lines and the first conductive vias on the one hand and the composite spin-Hall electrode on the other.

[0071] One embodiment relates to a method. The method comprises the following steps: fabricating transistors on a substrate; fabricating a composite spin Hall electrode over and in electrical connection with the transistors; and fabricating a magnetic tunnel junction over the composite spin Hall electrode. Fabricating the composite spin Hall electrode comprises the following: depositing a first layer of a first material, wherein the first material is a Hall metal in a metastable state and capable of transitioning to a stable state; depositing a second layer of a second material onto the first layer of the first material, wherein the second layer has a different composition than the first material; and depositing a third layer of the first material in the metastable state onto the second layer of the second material.The process further includes annealing the first, second and third layers, wherein after annealing the first material in the first layer and in the third layer is in a mixture of the metastable state and the stable state.

[0072] Embodiments may have one or more of the following features. The fabrication of the composite spin-Hall electrode further comprises depositing a fourth layer of a third material onto the second layer prior to the deposition of the third layer, wherein the third material has a different composition than the second material. The third material and / or the second material remain amorphous after annealing. The first layer and the third layer contain a mixture of α- and β-tungsten.

Claims

[1] Semiconductor device with: a pair of transistors (110, 120) on a semiconductor substrate (102); an interconnect structure across the pair of transistors (110, 120), wherein the interconnect structure has the following: Metal leads (182, 184) and metal vias (160, 210) arranged above and connected to the pair of transistors (110, 120), and a composite spin-Hall electrode (340, 530) over the metal conductors (182, 184) and metal vias (160, 210), wherein the composite spin-Hall electrode is electrically connected to the pair of transistors (110, 120) via the metal conductors and metal vias and has a first metal layer (342, 348, 531, 535, 539), a second metal layer (342, 348, 535, 535, 539) and a first spacer layer (344, 532, 536) between the first and the second metal layer, wherein the first metal layer contains a heavy metal in a first mixture of a stable and a metastable state of the heavy metal, the second metal layer contains the heavy metal in a second mixture of the stable and the metastable state of the heavy metal, and the first spacer layer contains a first material that is the first metal layer differs; and a magnetic tunnel contact (270) over the composite spin Hall electrode (340, 530); wherein the first spacer layer (344, 532, 536) comprises a crystalline metal or a crystalline metal oxide; and wherein the first spacer layer (344, 532, 536) further comprises an amorphous ferromagnetic material. [2] Semiconductor device according to claim 1, wherein the heavy metal is tungsten. [3] Semiconductor device according to claim 1 or 2, wherein the first spacer layer (344, 532, 536) comprises the crystalline metal oxide. [4] Semiconductor device according to claim 3, wherein the crystalline metal oxide is magnesium oxide having a face-centered cubic crystal structure. [5] Semiconductor device according to claim 4, wherein the amorphous ferromagnetic material is arranged above the crystalline metal oxide. [6] Semiconductor device according to one of the preceding claims, wherein the first spacer layer (344, 532) is arranged over the first metal layer (342, 531). [7] Semiconductor device according to any one of claims 1 to 4, wherein the first metal layer (348, 535) is arranged over the first spacer layer (344, 532). [8] Semiconductor device according to claim 7, further comprising a second spacer layer (536) over the first metal layer (535), wherein the second spacer layer contains the first material different from the first metal layer. [9] Semiconductor device according to one of the preceding claims, wherein the thicknesses of the first metal layer (342, 348) and the second metal layer (342, 348) are each between 1 nm and 4 nm. [10] Semiconductor device according to one of the preceding claims, wherein the amorphous ferromagnetic material is a cobalt-iron-boron mixture. [11] Storage device with a first storage cell above a substrate (102), wherein the first storage cell has the following features: a first transistor (110) and a second transistor (120) on the substrate (102); first conductive lines (182, 184) and first conductive vias (160, 210) over and in electrical connection with the first and second transistors; a composite spin-Hall electrode (340, 530) above and in electrical connection with the first conductive lines (182, 184) and the first conductive vias (160, 210), wherein the composite spin-Hall electrode has a first tungsten-based layer (342, 531) and a second tungsten-based layer (348, 535) separated by a first spacer (344, 532), wherein the first tungsten-based layer contains a first mixture of α- and β-tungsten and the second tungsten-based layer contains a second mixture of α- and β-tungsten; a magnetic tunnel contact (270) above the second tungsten-based (348, 535) layer; and second conductive lines (320) and second conductive vias (300) over and in electrical connection with the magnetic tunnel contact (270); wherein the first spacer (344, 532) comprises a crystalline metal or a crystalline metal oxide; and wherein the first spacer (344, 532, 536) further comprises an amorphous ferromagnetic material. [12] Storage device according to claim 11, wherein the amorphous ferromagnetic material is a cobalt-iron-boron mixture. [13] Storage device according to claim 11 or 12, wherein the composite spin Hall electrode (530) further comprises a third tungsten-based layer (539) arranged above the second tungsten-based layer (535) and separated from the second tungsten-based layer (535) by a second spacer (536), wherein the third tungsten-based layer (539) contains a third mixture of α- and β-tungsten. [14] Storage device according to claim 13, wherein the second spacer (536) has a plurality of layers (537, 538), wherein at least one of the plurality of layers is a crystalline material and at least one of the plurality of layers is an amorphous material, wherein the crystalline material comprises magnesium and the amorphous material comprises cobalt. [15] Storage device according to one of claims 11 to 14, which further comprises a buffer layer (230) between the first conductive lines (182, 184) and the first conductive vias (160, 210) on the one hand and the composite spin Hall electrode (340, 530) on the other. [16] Procedure with the following steps: Fabrication of transistors (110, 120) on a substrate (102); Fabrication of a composite spin Hall electrode (340, 530) via and in electrical connection with the transistors (110, 120); and Establishing a magnetic tunnel contact (270) over the composite spin Hall electrode (340, 530), the fabrication of the composite spin Hall electrode (340, 530) comprises the following: Deposition of a first layer (342, 531) from a first material, wherein the first material is a Hall metal in a metastable state and can transition to a stable state, Deposition of a second layer (344, 532) of a second material on the first layer (342, 531) of the first material, wherein the second layer has a different composition than the first material, wherein the second layer comprises a crystalline metal or a crystalline metal oxide, and wherein the second layer further comprises an amorphous ferromagnetic material, and Deposition of a third layer (348, 535) from the first material in the metastable state on the second layer (345, 533) from the second material; and Annealing of the first, second and third layer, wherein after annealing the first material in the first layer (342, 531) and in the third layer (348, 535) is in a mixture of the metastable state and the stable state. [17] Method according to claim 16, wherein the second layer (344, 532) comprises a first sublayer (345, 533) with the crystalline metal oxide and a second sublayer (346, 534) with the amorphous ferromagnetic material, and the second sublayer (346, 534) is arranged above the first sublayer. [18] Method according to claim 16 or 17, wherein the amorphous ferromagnetic material remains amorphous after annealing. [19] Method according to any one of claims 16 to 18, wherein the first layer (342, 531) and the third layer (348, 535) contain a mixture of α- and β-tungsten after tempering.

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