Lighting device with only one CAN data bus connection and multiple CAN bus nodes without an internal CAN data bus

Abstract

Lighting module with a bus transceiver (TRX), in particular a CAN or CAN FD transceiver, and with a logical operator (&), in particular an AND gate, and with n bus nodes (IC1, IC2, IC3), where n is a positive integer greater than 1 and wherein the bus transceiver (TRX) has a first data bus connection (CAN_H) and wherein the bus transceiver (TRX) has a second data bus connection (CAN_L) and wherein the bus transceiver (TRX) has a receive data output (RXX) and wherein the bus transceiver (TRX) has a transmit data input (TXX) and wherein the bus transceiver (TRX) outputs the logical level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXX) and wherein the first data bus terminal (CAN_H) and the second data bus terminal (CAN_L) represent the terminal (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN), in particular a CAN or CAN-FD data bus, which may have a first logical level and a second logical level, and where the bus transceiver (TRX) can transmit data via this connection (CAN_H, CAN_L) onto the differential bidirectional two-wire data bus (CAN) and where the bus transceiver (TRX) brings or holds the differential bidirectional two-wire data bus (CAN) in a first logical state via this connection (CAN_H, CAN_L), - if its transmit data input (TXX) has a first logical state and where the bus transceiver (TRX) does not change the logical state of the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L), - if its transmit data input (TXX) has a second logical state and where the bus transceiver (TRX) can receive data via this connection (CAN_H, CAN_L) from the differential bidirectional two-wire data bus (CAN) and wherein each of the n bus nodes has a transmit port (TX) which can have a first logical level and a second logical level, and where each of the n bus nodes has a receive port (RX) and where m bus nodes of the n bus nodes (IC1, IC2, IC3) are designed and suitable to supply light sources with electrical energy, and where m is a positive integer less than or equal to n and wherein the m bus nodes include means for supplying light sources with electrical energy and where the m bus node can exchange lighting data with a higher-level control system via its receive port (RX) and its transmit port (TX) and where the m bus nodes receive the lighting data via the bidirectional differential two-wire data bus (CAN), where the m bus nodes can influence the light output of the light sources depending on these lighting data and wherein each of the n bus nodes has a Communication Controller (CCC), which is preferably a CAN Communication Controller or a CAN FD Communication Controller, and wherein each of the Communication Controllers (CCC) of the n bus nodes has a transmit port (TXC) and where each of the Communication Controllers (CCC) of the n bus nodes has a receive port (RXC) and wherein the receive port (RXC) of the Communication Controller (CCC) of the respective bus node of the n bus nodes is connected to the receive port (RX) of this respective bus node of the n bus nodes and wherein the transmit port (TXC) of the Communication Controller (CCC) of the respective bus node of the n bus nodes is connected to the transmit port (TX) of this respective bus node of the n bus nodes and wherein the respective Communication Controllers (CCC) of the respective bus nodes compare the logical level at their respective receive port (RXC) with the logical level at their respective transmit port (TXC) and wherein the respective Communication Controllers (CCC) of the respective bus nodes interrupt the data transmission via their transmit port (TXC) for a predetermined, programmed, or otherwise determined time and output a second logical level at their transmit port (TXC) if the logical level at their respective receive port (RXC) does not match the logical level at their respective transmit port (TXC), and where the lighting module includes a logical logic (&), where the logical logic (&) can include a wired-OR logical operation, and where the logic (&) n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) includes and wherein the linking logic (&) includes a transmit signal output (TX&) and wherein the respective transmit terminals (TX) of the respective bus nodes (IC1, IC2, IC3) are connected to exactly one respective transmit signal input (TX1, TX2, TX3, ..... TX) n) of the linking logic (&) are pairwise connected and wherein the transmit signal output (TX&) of the logic gate (&) is connected to the transmit data input (TXX) of the bus transceiver (TRX) and wherein the receive data output (RXX) of the bus transceiver (TRX) is connected to the receive port (RX) of each of the n bus nodes (IC1, IC2, IC3) and where the logical combination of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX) n ) the linking logic (&) in the linking logic (&) is done in such a way, that the transmit signal output (TX&) of the logic gate (&) assumes a first logical level when one of the n transmit signal inputs (TX1, TX2, TX3, ..... TX) n ) the linking logic (&) has a first logical value, and that the transmit signal output (TX&) of the logic gate (&) assumes a second logical level if none of the n transmit signal inputs (TX1, TX2, TX3, ..... TX)n ) the linking logic (&) has a first logical value.

Description

Field of invention

[0001] The invention is directed to lighting devices with only one CAN data bus connection. General introduction

[0002] The CAN data bus is one of the most important automotive data buses. It is characterized by high data speed and high reliability.

[0003] Recently, there has been a growing desire to connect a large number of CAN bus nodes to a CAN data bus without having to increase the number of CAN interfaces actually connected to such a CAN data bus. This is because only a limited number of physical CAN nodes (bus transceivers) are permitted on the CAN bus. This paper addresses this inherently contradictory and thus seemingly unsolvable problem.

[0004] As speeds increase, fewer and fewer bus nodes are permitted on a CAN bus for physical reasons. At the same time, for example, when using LED taillights with multiple channels, it is necessary to operate multiple bus nodes on a single bus to manage thermal power loss or to circumvent limitations on the number of connections on the housing.

[0005] DE 10 2018 111 976 B3 discloses an LED driver comprising a differential first interface and a second single-ended interface. According to the technical teaching of DE 10 2018 111 976 B3, the LED driver of DE 10 2018 111 976 B3 communicates via the first interface according to a bidirectional differential bus communication protocol as a slave and via the second interface according to a single-ended bus protocol. According to the technical teaching of DE 10 2018 111 976 B3, the LED driver of DE 10 2018 111 976 B3 converts signals between the first interface and the second interface. At the same time, according to the technical teaching of DE 10 2018 111 976 B3, the LED driver of DE 10 2018 111 976 B3 supplies one or more LEDs with electrical power depending on signals that the LED driver has received via the first interface.

[0006] US 2020 / 0 215 962 A1 discloses an arrangement of multiple headlights for a vehicle. The arrangement of US 2020 / 0 215 962 A1 includes a primary serial Controller Area Network (CAN) data bus for transmitting first serial communications between spaced-apart CAN nodes communicatively connected to this data bus. According to the technical teaching of US 2020 / 0 215 962 A1, the first serial communications initiate a flash sequence from the arrangement via second serial communications provided to the multiple headlights. The headlights of US 2020 / 0 215 962 A1 are communicatively connected to a nested serial CAN data bus. An array controller of US 2020 / 0 215 962 A1 separates the nested serial CAN data bus from the primary serial CAN data bus and at the same time provides a communication bridge between the nodes of the two buses.Accordingly, the headlights of US 2020 / 0 215 962 A1 provide self-identification and diagnostic information on the nested bus to other nodes, such as a computer configuration program with a graphical user interface.

[0007] A warning light system in a motorcycle is known from US 2020 / 0 029 642 A1. The warning light system of US 2020 / 0 029 642 A1 includes a brake light comprising a plurality of light-emitting diodes (LEDs). According to the technical teaching of US 2020 / 0 029 642 A1, each LED is configured to illuminate in a first color when a motorcycle brake is applied. According to the technical teaching of US 2020 / 0 029 642 A1, only a subgroup of LEDs is configured to illuminate when the motorcycle is not decelerating in response to the brake being applied. The system of US 2020 / 0 029 642 A1 further includes a Controller Area Network (CAN) bus for transmitting messages. The system of US 2020 / 0 029 642 A1 further includes a controller configured to monitor events of a motorcycle. The controller is further configured to transmit a message on the CAN bus when a monitored event occurs in the motorcycle.According to the technical teaching of US 2020 / 0 029 642 A1, this message includes data indicating that the vehicle is decelerating. The system of US 2020 / 0 029 642 A1 includes a CAN bus interface configured to receive the message from the CAN bus and determine whether the brake is being applied or whether the motorcycle is not decelerating in response to the brake being applied. According to the technical teaching of US 2020 / 0 029 642 A1, the CAN bus interface is firstly configured to send a message to illuminate all LEDs on the brake light when the brake is applied and secondly configured to send a message to illuminate only the subset of LEDs on the brake light when the motorcycle is decelerating for a reason other than the brake being applied.Furthermore, the system of US 2020 / 0 029 642 A1 includes a processor configured to receive the message from the CAN bus interface. According to the technical teaching of US 2020 / 0 029 642 A1, the processor is further configured to illuminate the brake light or a subset of LEDs on the brake light based on the received message to indicate to a rider following the motorcycle that the motorcycle is slowing down. Task

[0008] The proposal is therefore based on the task of creating a solution to enable the connection of several CAN bus nodes to a CAN data bus via a single CAN data bus interface without using a new CAN data bus.

[0009] This object is achieved by a device according to the independent claims. Further embodiments are the subject of the dependent claims. Solution to the task

[0010] A key step toward solving the problem was the realization that CAN bus nodes typically include a transceiver that converts an RX / TX data signal from a serial UART interface into a CAN data stream. The idea is to combine the TX transmit data stream from the normally internal serial UART transmit data streams of multiple bus nodes using a combination logic (&).

[0011] By logically ANDing the TX signals, several participants can easily share a CAN transceiver.

[0012] Instead of the obvious solution of decoupling the participants from the CAN bus by means of a private bus behind a gateway connected to the CAN bus, the proposed solution allows several participants to share a CAN transceiver by interconnecting them with an AND gate.

[0013] The solution to the problem presented above is based on the realization that the data rate required by a small subset of bus nodes is significantly lower than the data rate required on the differential bidirectional two-wire data bus (CAN). FIRST FORM OF THE PROPOSAL

[0014] The document presented here proposes a lighting module comprising a bus transceiver (TRX) with which the lighting module is connected to a higher-level data network. This allows the lighting module to receive lighting data from this data network, for example, as setpoints, and return status information to other computer systems in the vehicle. The bus transceiver is particularly preferably a bus transceiver for a bidirectional, differential two-wire data bus. Most preferably, the differential bidirectional two-wire data bus is a CAN or CAN-FD data bus. In this case, the bus transceiver (TXR) is typically a CAN or CAN-FD transceiver. To solve the problem at hand, the lighting module additionally comprises logic (&). The logic (&) can be implemented, for example, using an AND gate.Implementation via a wired OR operation is also possible. For this purpose, the person skilled in the art selects a suitable physical representation of the logical levels of the components' inputs and outputs. The person skilled in the art knows that an OR operation can be converted into an AND operation of the likewise inverted inputs by inversion.

[0015] The proposed lighting module preferably comprises n bus nodes (IC1, IC2, IC3 to ICn). Where n is typically a positive integer greater than 1. The bus transceiver (TRX) of the lighting module typically has a first data bus connection (CAN_H) and a second data bus connection (CAN_L). Furthermore, the bus transceiver (TRX) preferably has a receive data output (RXX) and a transmit data input (TXX).

[0016] The bus transceiver (TRX) determines the current logic level on the differential bidirectional two-wire data bus (CAN). The bus transceiver (TRX) of the proposed lighting module outputs the determined current logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXX) and forwards it to the subsequent bus nodes (IC1 to ICn).

[0017] The first data bus connection (CAN_H) and the second data bus connection (CAN_L) represent the connection (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN). This means that in the case of a CAN or CAN-FD data bus as a differential bidirectional two-wire data bus, the first data bus connection (CAN_H) and the second data bus connection (CAN_L) represent the connection (CAN_H, CAN_L) of a CAN or CAN-FD data bus. This differential bidirectional two-wire data bus (CAN) can typically have a first logical level and a second logical level. In the case of using a CAN or CAN-FD data bus as a bidirectional differential two-wire data bus (CAN), the first logical level is typically the dominant bus state and the second logical level is typically the so-called recessive bus state.

[0018] The bus transceiver (TRX) can then send data to the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L).

[0019] The bus transceiver (TRX) brings the differential bidirectional two-wire data bus (CAN) into a first logical state via this connection (CAN_H, CAN_L) or keeps it in this state if its transmit data input (TXX) has a first logical state.

[0020] However, the bus transceiver (TRX) does not change the logical state of the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) if its transmit data input (TXX) has a second logical state. The bus transceiver (TRX) can therefore typically only overwrite a second logical level of the differential bidirectional two-wire data bus (CAN), but not the first logical level of the differential bidirectional two-wire data bus (CAN). The bus transceiver (TRX) can typically continuously receive receive data from the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) that other bus participants of the differential bidirectional two-wire data bus (CAN) transmit to the differential bidirectional two-wire data bus (CAN).

[0021] Typically, each of the n bus nodes (IC1 to ICn) of the lighting device has a transmit terminal (TX), which can have a first logic level and a second logic level. The physical representations of the logic levels of the transmit terminals (TX) of the bus nodes (IC1, IC2, IC3) can differ from the physical representations of the logic levels on the bidirectional differential two-wire data bus (CAN).

[0022] Typically, each of the n bus nodes (IC1 to ICn) also has a receive port (RX). Each of the n bus nodes (IC1 to ICn) receives serial data via its receive port (RX). Typically, the receive port (RX) is a UART receive port, while the transmit port (TX) of the respective bus node of the n bus nodes (IC1 to ICn) is typically a UART transmit port.

[0023] Typically, m of the n bus nodes (IC1, IC2, IC3) are designed and suitable for supplying lighting devices with electrical energy. These lighting devices (LEDs) are typically light-emitting diodes, also referred to below with the abbreviation LED. The LEDs are preferably connected in series to form LED chains. Each LED chain preferably comprises one or more LEDs. Typically, the bus nodes that supply lighting devices with electrical energy have power sources (see Fig. 1) with which these bus nodes feed an electrical current into the LED chain connected to the respective power source. Preferably, each bus node that supplies a light source with electrical energy supplies at least one LED chain with an electrical current from a power source of this bus node. The amount of electrical current supplied by the power sources of the respective bus node typically depends on the said lighting data that the respective bus node receives via the bidirectional, differential two-wire data bus (CAN) and the receive port (RX) of this respective bus node. Here, m is a positive integer less than or equal to n. Preferably, m is equal to n.

[0024] The m bus nodes of the n bus nodes (IC1 to ICn) thus preferably comprise means for supplying electrical energy to light sources (LEDs). In the case of LEDs as light sources, these means are typically the aforementioned power sources that supply the operating currents to the LED chains connected to them.

[0025] In order to be able to control these according to the requirements of the vehicle state, the state of the vehicle environment, and the commands of the occupants, it is therefore provided that the m bus nodes of the n bus nodes (IC1 to ICn) can exchange lighting data with a higher-level control system via the differential bidirectional two-wire data bus (CAN) and via their receive ports (RX) and their transmit ports (TX). The m bus nodes receive the lighting data for controlling the LED chains preferably via the bidirectional differential two-wire data bus (CAN). The m bus nodes of the n bus nodes (IC1 to ICn) can then influence the light output of the lamps (LEDs) depending on this lighting data. This light output of the lamps (LEDs) can, for example, be the light output of the LEDs.

[0026] Furthermore, each of the n bus nodes (IC1 to ICn) preferably has a communication controller (CCC). The communication controller (CCC) is preferably a CAN communication controller or a CAN FD communication controller. The communication controller (CCC) serves to generate the protocol-compliant serial bit data stream when sending data on the bidirectional two-wire data bus (CAN) according to the bus protocol of the bidirectional two-wire data bus (CAN). The communication controller (CCC) typically also serves to decode the bit data streams received from the bidirectional two-wire data bus (CAN) according to the bus protocol.

[0027] Each of the communication controllers (CCC) of the n bus nodes (IC1 to ICn) has a transmit port (TXC), which is typically a UART transmit data output. The communication controller (CCC) uses this transmit port (TXC) to send the bit data stream it generates to the bus transceiver (TRX).

[0028] Preferably, each of the communication controllers (CCC) of a bus node of the n bus nodes (IC1 to ICn) has a receive connection (RXC).

[0029] This respective receive port (RXC) of the communication controller (CCC) of the respective bus node of the n bus nodes (IC1 to ICn) is directly or indirectly connected to the receive port (RX) of this respective bus node of the n bus nodes (IC1 to ICn). Accordingly, the transmit port (TXC) of the communication controller (CCC) of the respective bus node of the n bus nodes (IC1 to ICn) is typically directly or indirectly connected to the transmit port (TX) of this respective bus node of the n bus nodes (IC1 to ICn).

[0030] The respective communication controllers (CCC) of the respective bus nodes of the n bus nodes (IC1 to ICn) typically each compare the logical level at the respective receive port (RXC) of the respective communication controller (CCC) with the logical level at the respective transmit port (TXC) of the respective communication controller (CCC).

[0031] The respective communication controllers (CCC) of the respective bus nodes of the n bus nodes (IC1 to ICn) each interrupt the data transmission via the transmit connection (TXC) of the communication controller (CCC) concerned by the n bus nodes (IC1 to ICn) for a predetermined or programmed or otherwise determined time. In this case, these respective communication controllers (CCC) of the respective bus nodes of the n bus nodes (IC1 to ICn) output a second logic level at their transmit connection (TXC) if the logic level at the respective receive connection (RXC) of the respective communication controller (CCC) of the respective bus node did not match the logic level at the transmit connection (TXC) of the respective communication controller (CCC) of the respective bus node when the comparison was carried out.

[0032] The lighting module proposed in this document is characterized, among other things, by the fact that the lighting module comprises a logic circuit (&). This logic circuit (&) enables the operation of multiple bus nodes on a single connection (CAN_H, CAN_L) of the bidirectional differential two-wire data bus (CAN). This makes it possible to comply with the specifications of automobile manufacturers, who wish to limit the number of bus nodes for reasons of data transmission quality on the bidirectional differential two-wire data bus. For example, the logic circuit (&) can comprise a wired-OR operation as a particularly efficient implementation of the necessary operation. The logic circuit (&) preferably comprises n transmit signal inputs (TX1, TX2, TX3, ..... TX n ). In other implementations of the other figures in this document, the logic (&) can also have n-1 transmit signal inputs (TX1, TX2, TX3, ..... TX n) and a further internal transmission signal input (TX0). This is then explicitly included in the corresponding claim. The logic (&) can also be implemented as a process that, for example, is executed by a computer unit of the lighting device. As a rule, the bus nodes include such computer units. In this respect, they can, for example, perform the relevant connections. In this case, the n transmission signal inputs (TX1, TX2, TX3, ..... TX n ) then prefers digital inputs of the computer unit of such a bus node.

[0033] The result of the logical combination of the logical states of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n) outputs the logic (&) via a transmit signal output (TX&) of the logic (&). If the logic operation of the logic (&) is carried out by a computer unit, the transmit signal output (TX&) of the logic (&) can be a memory location in the memory of the computer unit. The computer unit then transfers the value of this memory location to the bus transceiver (TRX) or makes this value available for query by the bus transceiver (TRX) in this memory location of the computer unit. The logic (&) thus comprises, as proposed, a transmit signal output (TX&). The respective transmit connection (TX) of the respective bus node (IC1, IC2, IC3) is thus, as proposed, connected to exactly one respective transmit signal input (TX1, TX2, TX3, ..... TX n) of the logic circuit (&) are connected in pairs. Such a connection is particularly preferably a connection via an electrical line for signaling the logic result of the logic circuit (&) to the bus transceiver (TRX). However, such a connection can also be the signaling of the logic result of the logic circuit (&) to the bus transceiver (TRX) via a memory location of a computer system or the data content of a data packet on a data bus. In this way, the transmit signal output (TX&) of the logic circuit (&) is typically connected to the transmit data input (TXX) of the bus transceiver (TRX).

[0034] The receive data output (RXX) of the bus transceiver (TRX) is proposed to be connected to the receive port (RX) of each of the n bus nodes (IC1, IC2, IC3) of the lighting module. This enables each of these bus nodes, using its communication controller (CCC), to check whether the current data on the bidirectional differential two-wire data bus (CAN) matches the data transmitted by the respective bus node via its transmit port (TX). In the event of a bus collision, the bus node thus recognizes via this receive port (RX) of this bus node of the n bus nodes (IC1, IC2, IC3) that, firstly, this bus node has a lower priority and, secondly, that it must transmit the data again at a later time after a calculated, programmed, specified, or otherwise determined time has elapsed.In order to enable such detection without data loss in the data of the higher-priority bus participant of the differential bidirectional two-wire data bus (CAN), the logical linking of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX. n ) of the linking logic (&) in the linking logic (&) in the following way: a. The transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the connection logic (&) has a first logical value. b. The transmit signal output (TX&) of the logic (&) assumes a second logic level if none of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the connection logic (&) has a first logical value.

[0035] As already described, the device presented here solves the problem of limiting the number of bus participants of the differential bidirectional two-wire data bus (CAN) and still enabling correct bus arbitration. FIRST VARIANT OF THE FIRST FORM OF THE PROPOSAL

[0036] A first variant of the above proposal concerns a lighting module according to the above proposal (see also Fig. 2), in which the bus transceiver (TRX) and the logic circuit (&) are manufactured in one piece on or in a semiconductor crystal. This forms a modified bus transceiver (ICO) that includes a bus transceiver (TRX) and logic circuit (&). Consequently, the lighting module comprises this modified bus transceiver (ICO) instead of the individual bus transceiver (TRX) and logic circuit (&).

[0037] This variant offers a number of advantages. Firstly, it enables the use of various bus nodes equipped with a UART interface. In the context of the document presented here, the bus nodes are generally light source controllers that supply light sources (LEDs) with electrical energy in a controlled manner depending on lighting parameters. These bus nodes typically receive these lighting parameters via the differential two-wire data bus (CAN) and their serial UART interface connection via their receive port (RX) and their transmit port (TX). The modified bus transceiver (ICO) can also control other bus nodes in this variant without controlling and / or supplying power to light sources. It is therefore conceivable that a lighting device according to the proposal could, in special cases,even temporarily, does not have any bus nodes that supply light sources (LEDs) with electrical energy and / or control their light output. Therefore, for the purposes of this document, such devices are also considered lighting devices. The immediately preceding statement expressly refers to the entire document. SECOND VERSION OF THE PROPOSAL (Figure 2)

[0038] The second variant of the proposal can also be a first sub-variant of the first variant of the first proposal.

[0039] The second variant of the proposal concerns a modified bus transceiver (IC0). As already explained above, it may be useful to monolithically integrate the logic (&) into the bus transceiver (TRX) on a semiconductor substrate. The use of such a monolithically integrated modified bus transceiver (ICO) in a lighting module according to the first variant of the first proposal of this document is particularly preferred.

[0040] A lighting device according to the second embodiment of the proposal described here preferably again comprises a bus transceiver (TRX) as part of the modified bus transceiver (IC0). As before, the modified bus transceiver (ICO) has a first data bus connection (CAN_H) and a second data bus connection (CAN_L). The integrated bus transceiver (TRX), which is now part of the modified bus transceiver (ICO), has a first internal data bus connection (CAN_H0) and a second internal data bus connection (CAN_L0). The first internal data bus connection (CAN_H0) is typically connected to the first data bus connection (CAN_H). The second internal data bus connection (CAN_L0) is typically connected to the second data bus connection (CAN_L).

[0041] The modified bus transceiver (ICO) has a receive data output (RXX). The internal bus transceiver (TRX) has an internal receive data output (RXT). The receive data output (RXX) of the modified bus transceiver (ICO) is connected to the internal receive data output (RXT) of the internal bus transceiver (TRX).

[0042] The internal bus transceiver (TRX) has an internal transmit data input (TXT).

[0043] The internal bus transceiver (TRX) outputs the logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXT). Thus, the modified bus transceiver (ICO) outputs the logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXX), since the internal bus transceiver (TRX) is part of the modified bus transceiver (ICO).

[0044] The first data bus connection (CAN_H) and the second data bus connection (CAN_L) represent the connection (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN), in particular a CAN or CAN-FD data bus. The differential bidirectional two-wire data bus (CAN) can typically assume a first logic level and a second logic level. This document expressly does not exclude the possibility that the differential bidirectional two-wire data bus (CAN) may exhibit additional logic levels during operation.

[0045] The modified bus transceiver (ICO) and thus the internal bus transceiver (TRX) can transmit data to the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L). The internal bus transceiver (TRX) and thus the modified bus transceiver (ICO) can bring the differential bidirectional two-wire data bus (CAN) into a first logical state or maintain it in this first logical state via this connection (CAN_H, CAN_L) if the internal transmit data input (TXT) of the internal bus transceiver (TRX) has a first logical state. This first logical state can, for example, be the dominant state of the CAN data bus in the case of a CAN or CAN-FD data bus as a differential bidirectional two-wire data bus (CAN).

[0046] However, the internal bus transceiver (TRX) and thus the modified bus transceiver (ICO) does not change the logical state of the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) if the internal transmit data input (TXT) has a second logical state. In the case of a CAN or CAN-FD data bus as a differential bidirectional two-wire data bus (CAN), this second logical state can, for example, be the recessive state of the CAN data bus.

[0047] The modified bus transceiver (ICO) and thus the internal bus transceiver (TRX) can now receive data from the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L).

[0048] The second version of the proposal presented here is again characterized by the fact that the modified bus transceiver (ICO) includes a logic circuit (&). This logic circuit (&) typically has n transmit signal inputs (TX1, TX2, TX3, ..... TX n ). The modified bus transceiver then also has n transmit signal inputs (TX1, TX2, TX3, ..... TX n), where n here again represents the aforementioned positive integer greater than 1. The logic circuit (&) comprises a transmit signal output (TX&) now arranged internally within the modified bus transceiver (IC0). As before, the logic circuit (&) can comprise a wired-OR operation. In this context, the document presented here refers to the above explanations regarding the implementation forms of the logic circuit (&). These embodiments can expressly apply here as well. The transmit signal output (TX&) of the logic circuit (&) is typically connected to the transmit data input (TXT) of the internal bus transceiver (TRX) of the modified bus transceiver (ICO) within the modified bus transceiver (ICO).

[0049] The logical combination of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n) of the logic operation (&) is now preferably carried out in the logic operation (&) in such a way that the transmission signal output (TX&) of the logic operation (&) assumes a first logic level when one of the n transmission signal inputs (TX0, TX1, TX2, ..... TX n ) of the modified bus transceiver (ICO) and thus one of the n transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the connection logic (&) has a first logical value.

[0050] The logical combination of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic operation (&) is now preferably carried out in the logic operation (&) in such a way that the transmit signal output (TX&) of the logic operation (&) assumes a second logic level if none of the n transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the modified bus transceiver (ICO) and thus none of the n transmit signal inputs (TX0, TX1, TX2, ..... TX n) of the connection logic (&) has a first logical value.

[0051] Such a modified bus transceiver (ICO) has the advantage that it solves the problem of limiting the number of data bus interfaces connected to the bidirectional differential two-wire data bus (CAN) and yet increases the number of possible bus participants without requiring a second bidirectional differential two-wire data bus (CAN) with corresponding hardware and software effort. SECOND VARIANT OF THE FIRST VERSION OF THE PROPOSAL (Figure 3)

[0052] The second variant of the first variant of the proposal concerns a lighting module based on the first variant of the proposal.

[0053] In this second variant of the first embodiment of the proposal, the communication controller (CCC) of a bus node of the n bus nodes (IC1, IC2, IC3) and the logic circuit (&) are manufactured in one piece on or in a semiconductor crystal. This minimizes the effects of electromagnetic compatibility. Furthermore, a lighting module can comprise several such bus nodes. Preferably, all bus nodes of a lighting module are such bus nodes. This considerably simplifies the logistics of manufacturing such lighting modules because the manufacturing process requires only one type of bus node controller. The communication controller (CCC) and the logic circuit (&) then form a modified bus node (IC1'). The modified bus node (IC1') then comprises a communication controller (CCC) and logic circuit (&). THIRD VERSION OF THE PROPOSAL

[0054] A third embodiment of the proposal relates to a modified bus node of the modified bus nodes (IC1' to ICn'). Such a modified bus node can, for example, be provided in particular for a lighting module according to the second variant of the first embodiment of the proposal. Such a modified bus node typically has a receive port (RX) and a transmit port (TX). A communication controller (CCC) is preferably arranged within the modified bus node. The modified bus node preferably comprises, as already described above, means for supplying lighting devices with electrical energy. At this point, the document presented here refers to the explanations regarding the supply voltage line (Vbat), the reference potential line (GND), the voltage regulator (Vreg), the current sources, and the lighting devices (LED) in the preceding variants and embodiments of the proposal, which also apply here.The modified bus node can exchange lighting data with a higher-level control system via its receive port (RX) and its transmit port (TX). In this third variant, this exchange takes place via a bus transceiver (TRX) and from there via the aforementioned bidirectional differential two-wire data bus (CAN). The modified bus node can influence the light output of the lamps depending on this lighting data. The relevant explanations in the description of the previous subvariants, variants, and variants also apply here.

[0055] As before, the communication controller (CCC) can preferably be a CAN communication controller or a CAN FD communication controller.

[0056] The communication controller (CCC) has a transmit port (TXC) and a receive port (RXC). The communication controller (CCC) of the modified bus node compares the logic level at its receive port (RXC) with the logic level at its transmit port (TXC). The communication controller (CCC) interrupts data transmission via its transmit port (TXC) for a predetermined, programmed, or otherwise determined time if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC). In addition, the communication controller (CCC) outputs a second logic level at its transmit port (TXC) if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC).

[0057] The receive port (RX) of the modified bus node is typically connected to the receive port (RXC) of the communication controller (CCC).

[0058] The modified bus node of the third variant of the proposal is particularly distinguished by the fact that it incorporates a logic logic (&). This enables the solution to the problem. Recall: The problem is that the bidirectional differential two-wire data bus should only be loaded with a few data bus interfaces. At the same time, however, the number of bus nodes should not be limited. Furthermore, the solution presented here eliminates the complexity of the hardware and software required for a complete second differential bidirectional two-wire data bus.

[0059] Since the logic (&) n transmit signal inputs (TX1, TX2, TX3, ..... TX n), the modified bus node comprises n transmit signal inputs (TX1, TX2, TX3, ..... TX n ), where n again represents a positive integer greater than 1. The logic (&) also includes a transmit signal output (TX&).

[0060] In order to be able to feed the data stream of the internal transmit signal output (TXC) of the internal communication controller (CCC) of the bus node into the data stream of the transmit signal output (TX&) of the link logic (&), the link logic (&) of the modified bus node comprises an additional transmit signal input (TX0).

[0061] As before, the logic operation (&) can include a wired-OR operation. The document presented here refers to the above explanations for implementing the operation of the logic states at the n transmit signal inputs (TX1, TX2, TX3, ..... TX n) to the logical state at the transmit signal output (TX&) of the logic gate (&). These also apply here.

[0062] The transmit terminal (TX) of the modified bus node is typically connected to the transmit signal output (TX&) of the logic (&).

[0063] The transmit port (TX) of the modified bus node is typically provided with a transmit line (TXL) or a functionally equivalent device connecting the transmit port (TX) of the modified bus node to a transmit data input (TXX) of a bus transceiver (TRX).

[0064] As before, the logic (&) performs the logical combination of the logical levels at the transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the logic circuit (&) in the logic circuit (&) and at the additional transmission signal input (TX0) of the logic circuit (&) in the following manner, a. The transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the logic operation (&) or the additional transmission signal input (TX0) of the logic operation (&) has a first logical value. b. The transmit signal output (TX&) of the logic (&) assumes a second logic level if none of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the logic operation (&) has a first logical value and the additional transmission signal input (TX0) of the logic operation (&) also does not have a first logical value.

[0065] Such a modified bus node has the advantage that it solves the problem of limiting the number of data bus interfaces connected to the bidirectional differential two-wire data bus (CAN) and yet increases the number of possible bus participants without requiring a second bidirectional differential two-wire data bus (CAN) with corresponding hardware and software effort. FIRST VARIANT of the THIRD FORM

[0066] The first variant of the third embodiment of the proposal relates to a lighting module according to the second variant of the first embodiment of the proposal, wherein the lighting module comprises a plurality of modified bus nodes according to the third variant. FOURTH VERSION OF THE PROPOSAL

[0067] The fourth embodiment of the proposal relates to a lighting module corresponding to the first embodiment of the proposal, wherein the bus transceiver (TRX) and the communication controller (CCC) of a bus node of the n bus nodes (IC1, IC2, IC3), and the logic circuit (&) are manufactured in one piece on or in a semiconductor crystal. This document refers to this bus node hereinafter as a modified, fully integrated bus transceiver (IC0*). The bus transceiver (TRX) and the communication controller (CCC) of a bus node of the n bus nodes (IC1, IC2, IC3), and the logic circuit (&) form this modified, fully integrated bus transceiver (IC0*). The modified, fully integrated bus transceiver (IC0*) comprises a bus transceiver (TRX), a communication controller (CCC), and a logic circuit (&).

[0068] As a result, the lighting module includes this modified, fully integrated bus transceiver (IC0*) instead of the individual bus transceiver (TRX) and the linking logic (&) and a bus node.

[0069] The advantages already mentioned above for the partial solutions apply here accordingly. FIFTH VERSION OF THE PROPOSAL

[0070] The fifth variant of the proposal concerns a modified, fully integrated bus node (IC1* to ICn*). A lighting module according to the fourth variant of the proposal can use the modified, fully integrated bus node presented here as a modified, fully integrated bus transceiver (IC0*).

[0071] A modified, fully integrated bus node (IC1* to ICn*) typically comprises a bus transceiver (TRX). The bus transceiver (TRX) typically has a first data bus connection (CAN_H) and a second data bus connection (CAN_L). The modified, fully integrated bus node preferably has a first data bus connection (CAN_H) and a second data bus connection (CAN_L) for connecting said bidirectional, differential two-wire data bus (CAN). The internal bus transceiver (TRX) has a first internal data bus connection (CAN_H0) and a second internal data bus connection (CAN_L0). The first data bus connection (CAN_H) is typically connected to the first internal data bus connection (CAN_H0). The second data bus connection (CAN_L) is typically connected to the second internal data bus connection (CAN_L0).

[0072] The bus transceiver (TRX) preferably has an internal receive data output (RXT). The modified, fully integrated bus node preferably has a receive data output (RXX). The receive data output (RXX) is typically connected to the receive data output (RXT).

[0073] The bus transceiver (TRX) typically has an internal transmit data input (TXT). The bus transceiver (TRX) outputs the logic level to the differential bidirectional two-wire data bus (CAN) via its receive data output (RXT).

[0074] Thus, the modified fully integrated bus node then outputs the logic level to the differential bidirectional two-wire data bus (CAN) via its receive data output (RXX).

[0075] The first data bus connection (CAN_H) and the second data bus connection (CAN_L) form the connection (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN). The differential bidirectional two-wire data bus (CAN) can, in particular, be a CAN or CAN-FD data bus. The differential bidirectional two-wire data bus (CAN) preferably has a first logic level and a second logic level.

[0076] The bus transceiver (TRX) can transmit data to the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L).

[0077] The bus transceiver (TRX) brings the differential bidirectional two-wire data bus (CAN) into a first logical state via this connection (CAN_H, CAN_L) or maintains the differential bidirectional two-wire data bus (CAN) in a first logical state when its internal transmit data input (TXT) has a first logical state.

[0078] However, the bus transceiver (TRX) does not change the logical state of the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) if its internal transmit data input (TXT) has a second logical state.

[0079] The bus transceiver (TRX) can receive data from the differential bidirectional two-wire data bus (CAN) via this connector (CAN_H, CAN_L).

[0080] The fourth version of the proposal is characterized by the fact that the modified fully integrated bus node a) a Communication Controller (CCC), b) a linking logic (&), c) n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) and d) a transmit connection (TX out ) includes.

[0081] Here, n again represents a positive integer greater than 1.

[0082] The modified, fully integrated bus node again includes means for supplying lighting with electrical power. The information described in the previous sections also applies here.

[0083] The modified fully integrated bus node can exchange lighting data with a higher-level control system via its receive port (RX) and its transmit port (TX).

[0084] The modified, fully integrated bus node can influence the light output of the lamps depending on these lighting data.

[0085] The logic (&) includes a transmit signal output (TX&) and an additional transmit signal input (TX0). As before, the logic (&) can include a wired-OR operation.

[0086] The communication controller (CCC) can be, for example, a CAN communication controller or a CAN FD communication controller.

[0087] The Communication Controller (CCC) typically has a transmit port (TXC) and a receive port (RXC).

[0088] The communication controller (CCC) of the modified, fully integrated bus node compares the logic level at its receive port (RXC) with the logic level at its transmit port (TXC). The communication controller (CCC) interrupts data transmission via its transmit port (TXC) for a predetermined, programmed, or otherwise determined time if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC). At the same time, the communication controller (CCC) outputs a second logic level at its transmit port (TXC) if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC).

[0089] The receive port (RXT) of the bus transceiver (TRX) is connected to the receive port (RXC) of the communication controller (CCC) and the receive port (RX) of the modified fully integrated bus node.

[0090] The internal transmit connection (TXT) of the bus transceiver (TRX) is preferably connected to the internal transmit signal output (TX&) of the logic circuit (&).

[0091] The additional transmit signal input (TX0) of the logic (&) is preferably connected in this variant to the transmit connection (TX out ) of the modified fully integrated bus node and the transmit connection (TXC) of the Communication Controller (CCC).

[0092] In this variant, the transmit signal output (TX&) of the logic circuit (&) is preferably connected to the transmit data input (TXX) of the bus transceiver (TRX).

[0093] The logic (&) performs the logical operation of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic circuit (&) and at the additional transmit signal input (TX0) in the logic circuit (&) preferably as follows: a. The transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic operation (&) has a first logical value or the additional transmission signal input (TX0) has a first logical value. b. The transmit signal output (TX&) of the logic circuit (&) assumes a second logic level if none of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic operation (&) has a first logical value and the additional transmit signal input (TX0) also has no first logical value.

[0094] The transmit connection (TX out) of the modified fully integrated bus node is preferably provided so that a transmission connection line (TX IC1 , TX IC2 ) the transmit connection (TX out ) of the modified bus node with a transmit signal input (TX0, TX1, TX2, ..... TX n ) of another modified bus node.

[0095] The logical combination of the logical levels at the transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the linking logic (&) is carried out in the linking logic (&) so that that the transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the logic operation (&) has a first logical value, and that the transmit signal output (TX&) of the logic (&) assumes a second logic level if none of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n) of the connection logic (&) has a first logical value. FIRST VARIANT OF THE FIFTH VERSION OF THE PROPOSAL

[0096] The first variant of the fifth embodiment of the proposal concerns a lighting module corresponding to the preceding fourth embodiment of the proposal. According to this first variant of the fifth proposal, the lighting module comprises a plurality of modified, fully integrated bus nodes corresponding to the preceding fifth embodiment of the proposal. Advantage

[0097] Bus nodes can be used in all products that use CAN or CAN-FD as a communication interface, at least in some implementations. However, the advantages are not limited to this.

[0098] In particular, the fully integrated version (see following Fig. 3) has the advantage that no additional signal-delaying components occur in the TX path and thus the requirements of the OEM CAN specifications are still met. List of characters Fig. 1 shows, as a first option, a proposed device with an external CAN transceiver and a separate logic circuit (&) comprising a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn). Fig. 2 shows, as a second option, a proposed device with a multi-TX CAN FD transceiver which is designed in one piece and comprises a CAN transceiver and the linking logic (&) with a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn). Fig. 3 shows, as a third option, a proposed device with a plurality of bus nodes, each of which is designed in one piece and preferably monolithically, wherein each bus node comprises a communication controller and linking logic (&) with a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn). Fig. 4 shows, as a fourth option, a proposed device with a plurality of bus nodes, each of which is designed as a single piece and preferably monolithically fully integrated, wherein each bus node comprises a communication controller and logic circuit (&) with a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn) and a bus transceiver (TRX). Description of the characters

[0099] The figures show various embodiments of the proposal. Combinations of features that appear at various points in this document are expressly included in the disclosure, provided that they do not result in nonsensical, nonfunctional, or contradictory combinations of features. The claims are decisive for the assertion of claims.

[0100] Fig. 1 Fig. 1 shows, as a first option, a proposed device with an external CAN transceiver and a separate logic circuit (&) comprising a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn).

[0101] The bus transceiver (TRX) is connected to the bidirectional differential data bus (CAN) with its first data bus connection (CAN_H) and to its second data connection (CAN_L). This allows the bus transceiver (TRX) to place data on the bidirectional differential two-wire data bus (CAN), provided this data is dominant over the current logical state of the bidirectional differential two-wire data bus (CAN). Conversely, the bus transceiver (TRX) can read data from the differential two-wire data bus (CAN). The bus transceiver (TRX) outputs the read data via its receive data output (RXX) on the bus transceiver (TRX). The bus transceiver receives the data to be transmitted via its transmit data input (TXX) on the bus transceiver (TRX).

[0102] The lighting module of the Fig. 1 comprises, for example, three bus nodes. These three bus nodes are the first bus node (IC1), the second bus node (IC2), and the third bus node (IC3). Each of the bus nodes (IC1, IC2, IC3) has, in the example of Fig. 1 an exemplary plurality of power sources, each of which supplies one of a plurality of LED strings with electrical energy. During operation, the bus nodes receive lighting data via the bidirectional differential data bus, which serves, among other things, to control the light emission of the lamps. In the present case, the Fig. 1, the currents with which the power sources supply the LED strings depend on these lighting data.

[0103] In the example of Fig. 1, each of the bus nodes includes, by way of example, a voltage regulator (Vreg) that generates the necessary voltages for the operation of the bus node and / or the lighting devices from the supply voltage between the potential of the supply voltage line (Vbat) and the reference potential of the reference voltage line (GND). These voltages are not included in the following drawings for the sake of clarity. This document requests the person skilled in the art to refer to the voltage regulators (Vreg), the supply voltage line (Vbat), the reference voltage line (GND), the current sources, and the lighting devices (LEDs) in the following figures.

[0104] A first transmit line (TXL1) connects the first transmit signal input (TX1) of the logic logic (&) to the transmit terminal (TX) of the first bus node (IC1). The transmit terminal (TX) of the first bus node (IC1) is connected to the internal transmit terminal (TXC) of the communication controller (CCC) of the first bus node (IC1).

[0105] A second transmit line (TXL2) connects the second transmit signal input (TX2) of the logic logic (&) to the transmit terminal (TX) of the second bus node (IC1). The transmit terminal (TX) of the second bus node (IC2) is connected to the internal transmit terminal (TXC) of the communication controller (CCC) of the second bus node (IC2).

[0106] A third transmit line (TXL3) connects the third transmit signal input (TX3) of the logic logic (&) to the transmit terminal (TX) of the third bus node (IC3). The transmit terminal (TX) of the third bus node (IC3) is connected to the internal transmit terminal (TXC) of the communication controller (CCC) of the third bus node (IC3).

[0107] A receive line of the lighting module connects the receive terminals (RX) of the bus nodes (IC1, IC2, IC3) with the receive data output (RXX) of the bus transceiver (TRX).

[0108] A logic operation (&) performs the logical operation of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the linking logic (&) in the linking logic (&) preferably looks like this: a. The transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the connection logic (&) has a first logical value. b. The transmit signal output (TX&) of the logic circuit (&) assumes a second logic level if none of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the connection logic (&) has a first logical value.

[0109] A transmit line (TXL) connects the transmit signal output (TX&) of the logic circuit (&) with the transmit data input (TXX) of the bus transceiver (TRX).

[0110] The communication controllers (CCC) of the bus nodes (IC1 to IC3) compare the logic levels at their respective receive ports (RXC) with the logic levels at their respective transmit ports (TXC). The communication controllers (CCC) interrupt data transmission via their transmit ports (TXC) for a predetermined, programmed, or otherwise determined time if the logic level at their respective receive port (RXC) does not match the logic level at their respective transmit port (TXC). At the same time, the respective communication controller (CCC) outputs a second logic level at its transmit port (TXC) if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC).

[0111] Fig. 2 Fig. 2 shows, as a second option, a proposed device with a multi-TX CAN FD transceiver which is designed in one piece and comprises a CAN transceiver and the linking logic (&) with a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn).

[0112] The bus transceiver (TRX) is part of a modified bus transceiver (IC0).

[0113] The logic (&) is also part of this modified bus transceiver (IC0).

[0114] The modified bus transceiver (ICO) is connected to the bidirectional differential data bus (CAN) with its first data bus port (CAN_H) and its second data port (CAN_L). The first data port (CAN_H) is connected to the first internal data port (CAN_H0) of the bus transceiver (TRX). The second data port (CAN_L) is connected to the first internal data port (CAN_L0) of the bus transceiver (TRX).

[0115] This allows the bus transceiver (TRX) to place data on the bidirectional differential two-wire data bus (CAN), provided this data is dominant over the current logical state of the bidirectional differential two-wire data bus (CAN). Conversely, the bus transceiver (TRX) can read data from the differential two-wire data bus (CAN). The bus transceiver (TRX) outputs the read data via its internal receive data output (RXT) of the bus transceiver (TRX). The bus transceiver receives the data to be transmitted via its internal transmit data input (TXT) of the bus transceiver (TRX).

[0116] An internal receive line (RXL0) connects the internal receive data output (RXT) of the bus transceiver (TRX) to the receive data output (RXX) of the modified bus transceiver (IC0).

[0117] The lighting module of the Fig. 2 again includes three bus nodes as an example. These three bus nodes are the first bus node (IC1), the second bus node (IC2), and the third bus node (IC3). Each of the bus nodes (IC1, IC2, IC3) has, in the example of Fig. 1 again shows an exemplary, but not shown, plurality of power sources, each of which supplies electrical energy to a likewise not shown LED string of a plurality of LED strings. The document presented here refers to Fig. 1 as an example. During operation, the bus nodes receive lighting data via the bidirectional differential data bus, which is used, among other things, to control the light emission of the lamps. In the case of the Fig. 2, the currents with which the power sources supply the LED strings depend on these lighting data.

[0118] In the example of Fig. 2, each of the bus nodes comprises, for example, a voltage regulator (Vreg) that generates the necessary voltages from the supply voltage between the potential of the supply voltage line (Vbat) and the reference potential of the reference voltage line (GND) for the operation of the bus node and / or the lighting devices. Fig. 2, these are not shown for clarity. This document asks the specialist to identify the voltage regulators (Vreg), the supply voltage line (Vbat), the reference voltage line (GND), the power sources and the light sources (LED) in the Fig. 2 to read along.

[0119] A first transmit line (TXL1) connects the first transmit signal input (TX1) of the modified bus transceiver (ICO) and thus the first transmit signal input (TX1) of the logic circuit (&) to the transmit connection (TX) of the first bus node (IC1). The transmit connection (TX) of the first bus node (IC1) is connected to the internal transmit connection (TXC) of the communication controller (CCC) of the first bus node (IC1).

[0120] A second transmit line (TXL2) connects the second transmit signal input (TX2) of the modified bus transceiver (ICO) and thus the second transmit signal input (TX2) of the logic circuit (&) to the transmit connection (TX) of the second bus node (IC1). The transmit connection (TX) of the second bus node (IC2) is connected to the internal transmit connection (TXC) of the communication controller (CCC) of the second bus node (IC2).

[0121] A third transmit line (TXL3) connects the third transmit signal input (TX3) of the modified bus transceiver (ICO) and thus the third transmit signal input (TX3) of the logic circuit (&) to the transmit connection (TX) of the third bus node (IC3). The transmit connection (TX) of the third bus node (IC3) is connected to the internal transmit connection (TXC) of the communication controller (CCC) of the third bus node (IC3).

[0122] A receive line of the lighting module connects the receive terminals (RX) of the bus nodes (IC1, IC2, IC3) with the receive data output (RXX) of the modified bus transceiver (IC0).

[0123] A logic operation (&) performs the logical operation of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the linking logic (&) in the linking logic (&) preferably looks like this: a. The transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the connection logic (&) has a first logical value. b. The transmit signal output (TX&) of the logic circuit (&) assumes a second logic level if none of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the connection logic (&) has a first logical value.

[0124] A transmit line (TXL0) connects the transmit signal output (TX&) of the logic circuit (&) with the internal transmit data input (TXT) of the bus transceiver (TRX).

[0125] The communication controllers (CCC) of the bus nodes (IC1 to IC3) compare the logic levels at their respective receive ports (RXC) with the logic levels at their respective transmit ports (TXC). The communication controllers (CCC) interrupt data transmission via their transmit ports (TXC) for a predetermined, programmed, or otherwise determined time if the logic level at their respective receive port (RXC) does not match the logic level at their respective transmit port (TXC). At the same time, the respective communication controller (CCC) outputs a second logic level at its transmit port (TXC) if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC).

[0126] Fig. 3 shows, as a third option, a proposed device with a plurality of bus nodes, each of which is designed in one piece and preferably monolithically, wherein each bus node comprises a communication controller and linking logic (&) with a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn).

[0127] A linking logic (&) is part of each of the three modified bus nodes (IC1', IC2', IC3').

[0128] The bus transceiver (TRX) is connected to the bidirectional differential data bus (CAN) with its first data bus connection (CAN_H) and to its second data connection (CAN_L). This allows the bus transceiver (TRX) to place data on the bidirectional differential two-wire data bus (CAN), provided this data is dominant over the current logical state of the bidirectional differential two-wire data bus (CAN). Conversely, the bus transceiver (TRX) can read data from the differential two-wire data bus (CAN). The bus transceiver (TRX) outputs the read data via its receive data output (RXX) on the bus transceiver (TRX). The bus transceiver receives the data to be transmitted via its transmit data input (TXX) on the bus transceiver (TRX).

[0129] The lighting module of the Fig. 3 comprises, by way of example, three modified bus nodes. These three modified bus nodes are the first modified bus node (IC1'), the second modified bus node (IC2'), and the third modified bus node (IC3'). Each of the modified bus nodes (IC1', IC2', IC3') has, in the example of Fig. 3 shows an exemplary plurality of power sources (not shown), each of which supplies electrical energy to a likewise not shown LED string of a plurality of LED strings. During operation, the modified bus nodes receive lighting data via the bidirectional differential data bus, which serves, among other things, to control the light emission of the lamps. In the present case, the Fig. 3 The currents with which the power sources supply the LED strings depend on these lighting data.

[0130] In the example of Fig. 3, each of the modified bus nodes comprises, for example, a voltage regulator (Vreg) (also not shown), which generates the necessary voltages from the supply voltage between the potential of the supply voltage line (Vbat) and the reference potential of the reference voltage line (GND) for the operation of the modified bus node and / or the lighting devices. Fig. 3, these are not shown for clarity. This document asks the specialist to identify the voltage regulators (Vreg), the supply voltage line (Vbat), the reference voltage line (GND), the power sources and the light sources (LED) in the Fig. 3. This document refers to Fig. 1.

[0131] A first transmission line (TXL1) connects the first transmission signal input (TX1) of the third modified bus node (IC3') to the transmission connection (TX) of the first modified bus node (IC1'). The first transmission line (TXL1) thereby connects the first transmission signal input (TX1) of the logic logic (&) to the transmission connection (TX) of the first modified bus node (IC1'). The transmission connection (TX) of the first modified bus node (IC1') is connected to the internal transmission connection (TXC) of the communication controller (CCC) of the first modified bus node (IC1').

[0132] A second transmission line (TXL2) connects the second transmission signal input (TX2) of the third modified bus node (IC3') to the transmission connection (TX) of the second modified bus node (IC2'). The second transmission line (TXL2) thereby connects the second transmission signal input (TX2) of the logic logic (&) to the transmission connection (TX) of the second modified bus node (IC2'). The transmission connection (TX) of the second modified bus node (IC2') is connected to the internal transmission connection (TXC) of the communication controller (CCC) of the second modified bus node (IC2').

[0133] An unmarked third transmit line (TXL3) connects the transmit signal output (TX&) of the logic circuit (&) to the transmit terminal (TX) of the third modified bus node (IC3'). A transmit line (TXL) connects the transmit terminal (TX) of the third modified bus node (IC3') to the transmit data input (TXX) of the bus transceiver (TRX).

[0134] The internal transmit terminal (TXC) of the communication controller (CCC) of the third modified bus node (IC3') is connected to the additional transmit signal input (TX0).

[0135] A receive line (RXL) of the lighting module connects the receive terminals (RX) of the modified bus nodes (IC1', IC2', IC3') with the receive data output (RXX) of the bus transceiver (TRX).

[0136] A logic operation (&) performs the logical operation of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic circuit (&) and the additional transmit signal input (TX0) of the logic circuit (&) in the logic circuit (&) preferably as follows: a. The transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the transmit signal inputs (TX0, TX1, TX2, ..... TX n) of the logic operation (&) has a first logical value or the additional transmission signal input (TX0) of the logic operation (&) has a first logical value. b. The transmit signal output (TX&) of the logic circuit (&) assumes a second logic level if none of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic operation (&) has a first logical value and the additional transmission signal input (TX0) of the logic operation (&) has no first logical value.

[0137] A transmission line (TXL) connects the transmission connection (TX) of the third modified bus node (IC3') and thus the transmission signal output (TX&) of the logic circuit (&) with the transmission data input (TXX) of the bus transceiver (TRX).

[0138] The communication controllers (CCC) of the bus nodes (IC1 to IC3) compare the logic levels at their respective receive ports (RXC) with the logic levels at their respective transmit ports (TXC). The communication controllers (CCC) interrupt data transmission via their transmit ports (TXC) for a predetermined, programmed, or otherwise determined time if the logic level at their respective receive port (RXC) does not match the logic level at their respective transmit port (TXC). At the same time, the respective communication controller (CCC) outputs a second logic level at its transmit port (TXC) if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC).

[0139] Fig. 4 Fig. Figure 4 shows, as a fourth option, a proposed device with a plurality of bus nodes, each of which is designed as a single piece and preferably as a monolithic, fully integrated device. Each bus node comprises a communication controller and logic circuit (&) with a plurality of transmission signal inputs (TX1, TX2, TX3, ..... TXn) and a bus transceiver (TRX). The monolithic, fully integrated bus node acts as a modified, fully integrated bus transceiver (IC0*).

[0140] The bus transceiver (TRX) is part of a modified fully integrated bus transceiver (IC0*).

[0141] The logic (&) is also part of this modified fully integrated bus transceiver (IC0*).

[0142] The modified fully integrated bus transceiver (IC0*) is also a modified fully integrated bus node (IC0*)

[0143] The modified fully integrated bus node (IC0*) is connected to the bidirectional differential data bus (CAN) with its first data bus connection (CAN_H) and its second data connection (CAN_L). The first data connection (CAN_H) is connected to the first internal data connection (CAN_H0) of the internal bus transceiver (TRX) (not shown). The second data connection (CAN_L) is connected to the first internal data connection (CAN_L0) of the internal bus transceiver (TRX) (not shown).

[0144] This allows the internal bus transceiver (TRX) to place data on the bidirectional differential two-wire data bus (CAN), provided this data is dominant over the current logical state of the bidirectional differential two-wire data bus (CAN). Conversely, the internal bus transceiver (TRX) can read data from the differential two-wire data bus (CAN). The internal bus transceiver (TRX) outputs the read data via its internal receive data output (RXT) of the internal bus transceiver (TRX). The internal bus transceiver (TRX) receives the data to be transmitted via its internal transmit data input (TXT) of the internal bus transceiver (TRX).

[0145] An internal receive line (RXL0) connects the internal receive data output (RXT) of the internal bus transceiver (TRX) to the receive port (RX) of the modified fully integrated bus node (IC0*). This output is designed so that when the internal bus transceiver (TRX) is not in use, another bus node can overwrite the logical value of the receive port (RX) of the modified fully integrated bus node (IC0*) using its receive port (RX).

[0146] The lighting module of the Fig. 4 again includes three bus nodes as an example. These three bus nodes are the first modified fully integrated bus node (IC1*), the second modified fully integrated bus node (IC2), and the modified fully integrated bus transceiver (IC0*). Each of the three modified fully integrated bus nodes (IC0*IC1*, IC2*) has, in the example of Fig. 4 again shows an exemplary, but not shown, plurality of power sources, each of which supplies electrical energy to a likewise not shown LED string of a plurality of LED strings. The document presented here refers to Fig. 1 as an example. During operation, the bus nodes receive lighting data via the bidirectional differential data bus, which is used, among other things, to control the light emission of the lamps. In the case of the Fig. 4 The currents with which the power sources supply the LED strings depend on these lighting data.

[0147] In the example of Fig. 4, each of the bus nodes comprises, for example, a voltage regulator (Vreg) which generates the necessary voltages from the supply voltage between the potential of the supply voltage line (Vbat) and the reference potential of the reference voltage line (GND) for the operation of the bus node and / or the lighting devices. Fig. 4, these are not shown for clarity. This document asks the specialist to identify the voltage regulators (Vreg), the supply voltage line (Vbat), the reference voltage line (GND), the power sources and the light sources (LED) in the Fig. 4 to read along.

[0148] A first transmission line (TXL1) connects the first transmission signal input (TX1) of the modified fully integrated bus transceiver (IC0*) and thus the first transmission signal input (TX1) of the logic circuit (&) of the modified fully integrated bus transceiver (IC0*) with the transmission connection (TX out ) of the first modified fully integrated bus node (IC1*).

[0149] A second transmission line (TXL2) connects the second transmission signal input (TX2) of the modified fully integrated bus transceiver (IC0*) and thus the second transmission signal input (TX2) of the logic circuit (&) of the modified fully integrated bus transceiver (IC0*) with the transmission connection (TXout ) of the second modified fully integrated bus node (IC2*).

[0150] The additional transmit signal input (TX0) of the logic (&) of the modified fully integrated bus transceiver (IC0*) is in the Fig. 4 with the transmit connection (TX out ) of the modified fully integrated bus transceiver (IC0*) and the transmit connection (TXC) of the communication controller (CCC) of the modified fully integrated bus transceiver (IC0*).

[0151] The additional transmit signal input (TX0) of the logic (&) of the first modified fully integrated bus node (IC1*) is in the Fig. 4 with the transmit connection (TX out ) of the first modified fully integrated bus node (IC1*) and the transmit connection (TXC) of the communication controller (CCC) of the first modified fully integrated bus node (IC1*).

[0152] The additional transmit signal input (TX0) of the logic (&) of the second modified fully integrated bus node (IC2*) is in the Fig. 4 with the transmit connection (TX out ) of the second modified fully integrated bus node (IC2*) and the transmit connection (TXC) of the communication controller (CCC) of the second modified fully integrated bus node (IC2*).

[0153] A receive line (RXL) of the lighting module connects the receive ports (RX) of the modified, fully integrated bus nodes (IC0*, IC1*, IC2*). The receive port (RX) of the modified, fully integrated bus transceiver (IC0*) overwrites the states at the receive ports (RX) of the other receive ports (RX) of the modified, fully integrated bus nodes (IC1*, IC2*), since these other modified, fully integrated bus nodes (IC1*, IC2*) do not use their internal bus transceivers (TRX).

[0154] In the modified fully integrated bus transceiver (IC0*), the logic (&) performs the logical linking of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the modified fully integrated bus transceiver (IC0*) and thus at the n transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic circuit (&) in the logic circuit (&) preferably as follows, taking into account the logic level at the additional transmit signal input (TX0) of the logic circuit (&): a. The transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic operation (&) has a first logical value or the additional transmission signal input (TX0) has a first logical value. b. The transmit signal output (TX&) of the logic circuit (&) assumes a second logic level if none of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic operation (&) has a first logical value or the additional transmission signal input (TX0) does not have a first logical value.

[0155] A not shown transmit line (TXL0) connects the not shown transmit signal output (TX&) of the logic circuit (&) with the not shown internal transmit data input (TXT) of the internal bus transceiver (TRX) within the modified fully integrated bus transceiver (IC0*).

[0156] The communication controllers (CCC) of the modified, fully integrated bus nodes (IC0*, IC1*, IC3*) compare the logic levels at their respective receive ports (RXC) with the logic levels at their respective transmit ports (TXC). The communication controllers (CCC) interrupt data transmission via their transmit ports (TXC) for a predetermined, programmed, or otherwise determined time if the logic level at their respective receive port (RXC) does not match the logic level at their respective transmit port (TXC). At the same time, the respective communication controller (CCC) outputs a second logic level at its transmit port (TXC) if the logic level at its respective receive port (RXC) does not match the logic level at its respective transmit port (TXC). GlossaryCANZit from Wikipedia:

[0157] “The CAN bus (Controller Area Network) is a serial bus system and belongs to the field buses.

[0158] It was developed by Bosch in 1983 and introduced in collaboration with Intel in 1986. Its purpose was to reduce the number of wiring harnesses, thereby saving costs and weight. At that time, the total length of all cables in motor vehicles, for example, without CAN, could be up to 2 km.

[0159] CAN is internationally standardized in ISO 11898-1 and defines Layer 2 (data link layer) in the ISO / OSI reference model. The two most common implementations of the physical layers are defined in ISO 11898-2 (high-speed physical layer) and ISO 11898-3 (fault-tolerant physical layer). They differ in numerous properties and are not compatible with each other. Link: https: / / de.wikipedia.org / wiki / Controller_Area_Network List of reference symbols and abbreviations

[0160] Preliminary note: Some symbol combinations listed here are abbreviations or serve to improve the clarity of the description, even if they are not shown in the figures. & linking logic; CAN: bidirectional differential two-wire data bus. The bidirectional differential two-wire data bus is preferably a CAN or ACN-FD data bus; CAN_H first data bus connection of the bidirectional differential two-wire data bus (CAN) to the bus transceiver (TRX); CAN_H0 first internal data bus connection of the bidirectional differential two-wire data bus (CAN) to the internal bus transceiver (TRX) within the modified bus transceiver (IC0); CAN_L second data bus connection of the bidirectional differential two-wire data bus (CAN) to the bus transceiver (TRX); CAN_L0 second internal data bus connection of the bidirectional differential two-wire data bus (CAN) to the internal bus transceiver (TRX) within the modified bus transceiver (IC0); CAN_H, CAN_L the connection (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN) to the bus transceiver (TRX); CCC Communication Controller. The communication controller is preferably a CAN Communication Controller or a CAN FD Communication Controller. The communication controller generates a serial transmit data stream, which it outputs to its transmit port (TXC). GND: Reference potential line to reference potential. Typically, the reference potential line is the ground line of the lighting module. In vehicles, the ground is often the vehicle body; IC0 modified bus transceiver, which includes a bus transceiver (TRX) and a link logic (&); IC0* modified fully integrated bus transceiver. The modified fully integrated bus transceiver (IC0*) preferably comprises a bus transceiver (TRX), a communication controller (CCC), and logic (&). The modified fully integrated bus transceiver is a modified fully integrated bus node like the other modified fully integrated bus nodes (IC1*, IC2*); IC1 first bus node; IC1' first modified bus node. The first modified bus node comprises a communication controller (CCC) and a logic circuit (&). Preferably, the first modified bus node is implemented as a single piece on a common semiconductor crystal; IC1* first modified fully integrated bus node. The first modified fully integrated bus node (IC1*) preferably comprises a bus transceiver (TRX), a communication controller (CCC), and a logic circuit (&); IC2 second bus node; IC2' second modified bus node. The second modified bus node comprises a communication controller (CCC) and a logic circuit (&). Preferably, the second modified bus node is integrally formed on a common semiconductor crystal; IC2* second modified fully integrated bus node. The second modified fully integrated bus node (IC2*) preferably comprises a bus transceiver (TRX), a communication controller (CCC), and a logic circuit (&); IC3 third bus node; IC3' third modified bus node. The third modified bus node comprises a communication controller (CCC) and a logic circuit (&). Preferably, the third modified bus node is integrally formed on a common semiconductor crystal; ICn nth bus node (This reference symbol is not shown in the drawings for clarity. The drawings generally refer to n=3 as an example); ICn' nth modified bus node. The nth modified bus node comprises a communication controller (CCC) and a logic circuit (&). Preferably, the nth modified bus node is implemented integrally on a common semiconductor crystal; LED bulbs. In the Fig. 1, the lamps are designed as serial connections of light-emitting diodes. The lamps are only available in the Fig. 1 are shown at the respective bus node. In the other figures of this document, the reader can see these as being present there. This serves to improve the clarity of the other figures. Therefore, this document explicitly discloses these lamps and their control by current sources of the bus nodes (IC1 to ICn) in the other figures of this document as well. RX receive terminal of a bus node of the bus nodes (IC1, IC2, IC3); RXC receive port of the Communication Controller (CCC); RXL receive line of the lighting module; RXL0 internal receive line; RXX Receive data output of the bus transceiver (TRX) or the modified bus transceiver (IC0); TRX bus transceiver. In the example presented here, the bus transceiver is preferably a CAN transceiver or a CAN FD transceiver that communicates with a bidirectional and differential two-wire data bus (CAN) via a first data bus port (CAN_H) and a second data bus port (CAN_L). TX transmit connection of a bus node of the n bus nodes (IC1, to ICn); TX& Transmit signal output of the logic (&); TX0 additional transmit signal input; TX1 first transmit signal input; TX2 second transmit signal input; TX3 third transmit signal input; TX n nth transmit signal input; TXC transmission port of the communication controller (CCC); TXL transmission line; TXL1 first transmit connection line between the first modified fully integrated bus node (IC1*) and the first transmit signal input (TX1) of the modified fully integrated bus transceiver (IC0*) which is in the Fig. 4 is also an example of a first modified fully integrated bus node, which can therefore also include means for operating lighting devices; TXL2 second transmission connection line between the second modified fully integrated bus node (IC2*) and the second transmission signal input (TX2) of the modified fully integrated bus transceiver (IC0*) which is located in the Fig. 4 is also an example of a first modified fully integrated bus node, which can therefore also include means for operating lighting devices; TX out Transmitting port (TX out) of the modified fully integrated bus node. The additional transmit signal input (TX0) of the logic (&) is in the Fig. 4 with the transmit connection (TX out ) of the modified fully integrated bus node and the transmit connection (TXC) of the Communication Controller (CCC); TXT internal transmit data input of the bus transceiver (TRX); TXX transmit data input of the bus transceiver (TRX); Vbat supply voltage line. The supply voltage line is typically at a supply voltage potential. The difference between the supply voltage potential and the reference potential of the reference potential line (GND) is the supply voltage for the purposes of this document. Vreg Voltage regulator of a bus node of the n bus nodes (IC1 to ICn). The voltage regulator preferably provides one or more internal operating voltages for operating its bus node. It can be a buck converter, a boost converter, a buck / boost converter, or another voltage regulator. The voltage regulator shown in the figures can actually comprise multiple voltage regulators. The voltage regulator can also supply other bus nodes and / or other components of the lighting module with electrical energy, which means they typically no longer require a voltage regulator. The voltage regulator is only in the Fig.1 is shown at the respective bus node. In the other figures in this document, the reader can see this as being present there. This serves to improve the clarity of the other figures. The voltage regulator draws electrical energy from the supply voltage line (Vbat) and the reference voltage line (GND). The voltage regulator also makes this energy available, if necessary, to the power sources of its bus node for controlling the lighting devices (LEDs).

Claims

[1] Lighting module with a bus transceiver (TRX), in particular a CAN or CAN-FD transceiver, and with a logic operation (&), in particular an AND gate, and with n bus nodes (IC1, IC2, IC3), where n is a positive integer greater than 1 and wherein the bus transceiver (TRX) has a first data bus connection (CAN_H) and wherein the bus transceiver (TRX) has a second data bus connection (CAN_L) and wherein the bus transceiver (TRX) has a receive data output (RXX) and wherein the bus transceiver (TRX) has a transmit data input (TXX) and where the bus transceiver (TRX) outputs the logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXX) and wherein the first data bus connection (CAN_H) and the second data bus connection (CAN_L) represent the connection (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN), in particular a CAN or CAN-FD data bus, which can have a first logic level and a second logic level, and The bus transceiver (TRX) can send data to the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) and wherein the bus transceiver (TRX) brings or maintains the differential bidirectional two-wire data bus (CAN) in a first logical state via this connection (CAN_H, CAN_L), - if its transmit data input (TXX) has a first logical state and where the bus transceiver (TRX) does not change the logical state of the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L), - if its transmit data input (TXX) has a second logical state and where the bus transceiver (TRX) can receive data from the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) and wherein each of the n bus nodes has a transmit terminal (TX) which can have a first logic level and a second logic level, and wherein each of the n bus nodes has a receive port (RX) and where m bus nodes of the n bus nodes (IC1, IC2, IC3) are intended and suitable for supplying lighting devices with electrical energy, and where m is a positive integer less than or equal to n and wherein the m bus nodes comprise means for supplying lighting devices with electrical energy and where the m bus node can exchange lighting data with a higher-level control system via its receive port (RX) and its one transmit port (TX) and where the m bus nodes receive the lighting data via the bidirectional differential two-wire data bus (CAN), where the m bus nodes can influence the light output of the lamps depending on these lighting data and wherein each of the n bus nodes has a communication controller (CCC), which is preferably a CAN communication controller or a CAN FD communication controller, and where each of the Communication Controllers (CCC) of the n bus nodes has a transmit connection (TXC) and where each of the Communication Controllers (CCC) of the n bus nodes has a receive port (RXC) and wherein the receiving terminal (RXC) of the communication controller (CCC) of the respective bus node of the n bus nodes is connected to the receiving terminal (RX) of this respective bus node of the n bus nodes and wherein the transmit terminal (TXC) of the communication controller (CCC) of the respective bus node of the n bus nodes is connected to the transmit terminal (TX) of this respective bus node of the n bus nodes and whereby the respective communication controllers (CCC) of the respective bus nodes compare the logic level at their respective receive port (RXC) with the logic level at their respective transmit port (TXC) and wherein the respective communication controllers (CCC) of the respective bus nodes interrupt the data transmission via their transmit connection (TXC) for a predetermined or a programmed or otherwise determined time and output a second logic level at their transmit connection (TXC) if the logic level at their respective receive connection (RXC) does not match the logic level at their respective transmit connection (TXC), and wherein the lighting module comprises a linking logic (&), wherein the linking logic (&) may comprise a wired-OR link, and where the logic (&) n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) and wherein the logic circuit (&) comprises a transmission signal output (TX&) and wherein the respective transmission terminals (TX) of the respective bus nodes (IC1, IC2, IC3) are connected to exactly one respective transmission signal input (TX1, TX2, TX3, ..... TX n) of the linking logic (&) are connected in pairs and where the transmit signal output (TX&) of the logic circuit (&) is connected to the transmit data input (TXX) of the bus transceiver (TRX) and wherein the receive data output (RXX) of the bus transceiver (TRX) is connected to the receive terminal (RX) of each of the n bus nodes (IC1, IC2, IC3) and where the logical combination of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the linking logic (&) in the linking logic (&) is done so, that the transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the logic operation (&) has a first logical value, and that the transmit signal output (TX&) of the logic (&) assumes a second logic level if none of the n transmit signal inputs (TX1, TX2, TX3, ..... TXn ) of the connection logic (&) has a first logical value. [2] Lighting module according to claim 1 wherein the bus transceiver (TRX) and the logic circuit (&) are manufactured in one piece on or in a semiconductor crystal, so that they form a modified bus transceiver (ICO) which includes a bus transceiver (TRX) and a linking logic (&), and so that the lighting module thus includes this modified bus transceiver (ICO) instead of the single bus transceiver (TRX) and the linking logic (&). [3] Modified Bus Transceivers (ICO) with a bus transceiver (TRX) and wherein the modified bus transceiver (IC0) has a first data bus connection (CAN_H) and wherein the modified bus transceiver (IC0) has a second data bus connection (CAN_L) and wherein the internal bus transceiver (TRX) has a first internal data bus connection (CAN_H0) and wherein the internal bus transceiver (TRX) has a second internal data bus connection (CAN_L0) and wherein the first data bus connection (CAN_H) is connected to the first internal data bus connection (CAN_H0) and wherein the second data bus connection (CAN_L) is connected to the second internal data bus connection (CAN_L0) and wherein the modified bus transceiver (IC0) has a receive data output (RXX) and wherein the internal bus transceiver (TRX) has an internal receive data output (RXT) and wherein the receive data output (RXX) of the modified bus transceiver (ICO) is connected to the internal receive data output (RXT) of the internal bus transceiver (TRX) and where the internal bus transceiver (TRX) has an internal transmit data input (TXT) and where the internal bus transceiver (TRX) outputs the logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXT) and whereby the modified bus transceiver (ICO) outputs the logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXX) and wherein the first data bus connection (CAN_H) and the second data bus connection (CAN_L) represent the connection (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN), in particular a CAN or CAN-FD data bus, which can have a first logic level and a second logic level, and where the modified bus transceiver (ICO) and thus the internal bus transceiver (TRX) can send data to the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) and whereby the internal bus transceiver (TRX) and thus the modified bus transceiver (ICO) brings or maintains the differential bidirectional two-wire data bus (CAN) in a first logical state via this connection (CAN_H, CAN_L), - if the internal transmit data input (TXT) of the internal bus transceiver (TRX) has a first logical state and whereby the internal bus transceiver (TRX) and thus the modified bus transceiver (ICO) does not change the logical state of the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L), - if the internal transmit data input (TXT) has a second logical state and where the modified bus transceiver (ICO) and thus the internal bus transceiver (TRX) can receive data from the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) and wherein the modified bus transceiver (IC0) comprises a logic circuit (&) and wherein the modified bus transceiver (ICO) has n transmit signal inputs (TX1, TX2, TX3, ..... TX n ), where n represents a positive integer greater than 1, and wherein the logic circuit (&) comprises a transmit signal output (TX&) and where the linking logic (&) may include a wired-OR operation and where the transmit signal output (TX&) of the logic circuit (&) is connected to the transmit data input (TXT) of the internal bus transceiver (TRX) of the modified bus transceiver (ICO) and where the logical combination of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the linking logic (&) in the linking logic (&) is done so, that the transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the n transmit signal inputs (TX0, TX1, TX2, ..... TXn ) of the logic operation (&) has a first logical value, and that the transmit signal output (TX&) of the logic (&) assumes a second logic level if none of the n transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the connection logic (&) has a first logical value. [4] Lighting module according to claim 1 wherein the communication controller (CCC) of a bus node of the n bus nodes (IC1, IC2, IC3) and the logic circuit (&) are manufactured in one piece on or in a semiconductor crystal, so that they form a modified bus node (IC1) which includes a communication controller (CCC) and a linking logic (&). [5] Modified bus node with a receive port (RX) and with a transmit connection (TX) and with a Communication Controller (CCC) and wherein the modified bus node comprises means for supplying lighting devices with electrical energy and wherein the modified bus node can exchange lighting data with a higher-level control system via its receive port (RX) and its transmit port (TX), and whereby the modified bus node can influence the light output of the lamps depending on these lighting data and Where the Communication Controller (CCC) can preferably be a CAN Communication Controller or a CAN FD Communication Controller and wherein the Communication Controller (CCC) has a transmit connection (TXC) and wherein the Communication Controller (CCC) has a receive port (RXC) and where the Communication Controller (CCC) of the modified bus node compares the logic level at its receive port (RXC) with the logic level at its transmit port (TXC) and wherein the Communication Controller (CCC) interrupts the data transmission via its transmitting port (TXC) for a predetermined or a programmed or otherwise determined time and outputs a second logic level at its transmitting port (TXC) if the logic level at its respective receiving port (RXC) does not match the logic level at its respective transmitting port (TXC), and wherein the receive terminal (RX) of the modified bus node is connected to the receive terminal (RXC) of the communication controller (CCC) and wherein the modified bus node comprises a link logic (&) and where the modified bus node has n transmit signal inputs (TX1, TX2, TX3, ..... TX n ), where n represents a positive integer greater than 1, and wherein the logic circuit (&) comprises an additional transmit signal input (TX0) and wherein the logic circuit (&) comprises a transmit signal output (TX&) and where the linking logic (&) may include a wired-OR operation and wherein the transmit terminal (TX) of the modified bus node is connected to the transmit signal output (TX&) of the logic circuit (&) and wherein the transmit terminal (TX) of the modified bus node is intended to be connected to a transmit data input (TXX) of a bus transceiver (TRX), and where the logical combination of the logical levels at the transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the logic circuit (&) and additional transmit signal input (TX0) of the logic circuit (&) in the logic circuit (&) is carried out in such a way that that the transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n) of the logic circuit (&) or the additional transmission signal input (TX0) of the logic circuit (&) has a first logical value, and that the transmit signal output (TX&) of the logic (&) assumes a second logic level if none of the n transmit signal inputs (TX1, TX2, TX3, ..... TX n ) of the logic operation (&) has a first logical value and the additional transmission signal input (TX0) of the logic operation (&) also does not have a first logical value. [6] Lighting module according to claim 4 wherein the lighting module comprises a plurality of modified bus nodes according to claim 5. [7] Lighting module according to claim 1 wherein the bus transceiver (TRX) and the communication controller (CCC) of a bus node of the n bus nodes (IC1, IC2, IC3) and the logic circuit (&) are manufactured in one piece on or in a semiconductor crystal, and This bus node is referred to below as a modified, fully integrated bus transceiver (IC1*) and wherein the bus transceiver (TRX) and the communication controller (CCC) of one of the n bus nodes (IC1, IC2, IC3) and the linking logic (&) form this modified fully integrated bus transceiver (IC1*), which comprises a bus transceiver (TRX) and a communication controller (CCC) and a linking logic (&), so that the lighting module thus comprises this modified, fully integrated bus transceiver (IC1*) instead of the single bus transceiver (TRX) and the linking logic (&) and a bus node. [8] Modified fully integrated bus node with a bus transceiver (TRX) and wherein the bus transceiver (TRX) has a first data bus connection (CAN_H) and wherein the bus transceiver (TRX) has a second data bus connection (CAN_L) and wherein the modified fully integrated bus node has a first data bus connection (CAN_H) and wherein the modified fully integrated bus node has a second data bus connection (CAN_L) and wherein the internal bus transceiver (TRX) has a first internal data bus connection (CAN_H0) and wherein the internal bus transceiver (TRX) has a second internal data bus connection (CAN_L0) and wherein the first data bus connection (CAN_H) is connected to the first internal data bus connection (CAN_H0) and wherein the second data bus connection (CAN_L) is connected to the second internal data bus connection (CAN_L0) and wherein the bus transceiver (TRX) has an internal receive data output (RXT) and wherein the modified fully integrated bus node has a receive data output (RXX) and wherein the receive data output (RXX) is connected to the receive data output (RXT) and where the bus transceiver (TRX) has an internal transmit data input (TXT) and where the bus transceiver (TRX) outputs the logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXT) and whereby the modified fully integrated bus node outputs the logic level on the differential bidirectional two-wire data bus (CAN) via its receive data output (RXX) and wherein the first data bus connection (CAN_H) and the second data bus connection (CAN_L) represent the connection (CAN_H, CAN_L) of a differential bidirectional two-wire data bus (CAN), in particular a CAN or CAN-FD data bus, which can have a first logic level and a second logic level, and The bus transceiver (TRX) can send data to the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) and wherein the bus transceiver (TRX) brings or maintains the differential bidirectional two-wire data bus (CAN) in a first logical state via this connection (CAN_H, CAN_L), - if its internal transmit data input (TXT) has a first logical state and where the bus transceiver (TRX) does not change the logical state of the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L), - if its internal transmit data input (TXT) has a second logical state, and where the bus transceiver (TRX) can receive data from the differential bidirectional two-wire data bus (CAN) via this connection (CAN_H, CAN_L) and wherein the modified fully integrated bus node comprises a Communication Controller (CCC) and wherein the modified fully integrated bus transceiver comprises a link logic (&) and where the modified fully integrated bus transceiver has n transmit signal inputs (TX1, TX2, TX3, ..... TX n ), where n represents a positive integer greater than 1, and The modified fully integrated bus transceiver has a transmit connection (TX out ) and wherein the modified fully integrated bus node comprises means for supplying lighting devices with electrical energy and wherein the modified fully integrated bus node can exchange lighting data with a higher-level control system via its receive port (RX) and its transmit port (TX), and whereby the modified fully integrated bus node can influence the light output of the lamps depending on these lighting data and wherein the logic circuit (&) comprises a transmit signal output (TX&) and wherein the logic circuit (&) comprises an additional transmit signal input (TX0) and where the linking logic (&) may include a wired-OR operation and Where the Communication Controller (CCC) can preferably be a CAN Communication Controller or a CAN FD Communication Controller and wherein the Communication Controller (CCC) has a transmit connection (TXC) and wherein the Communication Controller (CCC) has a receive port (RXC) and Wherein the Communication Controller (CCC) of the modified fully integrated bus node compares the logic level at its receive port (RXC) with the logic level at its transmit port (TXC) and wherein the Communication Controller (CCC) interrupts the data transmission via its transmitting port (TXC) for a predetermined or a programmed or otherwise determined time and outputs a second logic level at its transmitting port (TXC) if the logic level at its respective receiving port (RXC) does not match the logic level at its respective transmitting port (TXC), and wherein the receive port (RXT) of the bus transceiver (TRX) is connected to the receive port (RXC) of the communication controller (CCC) and the receive port (RX) of the modified fully integrated bus node and where the transmit terminal (TXT) of the bus transceiver (TRX) is connected to the transmit signal output (TX&) of the logic circuit (&) and where the additional transmit signal input (TX0) of the logic (&) is connected to the transmit connection (TX out) of the modified fully integrated bus node and the transmit connection (TXC) of the Communication Controller (CCC) and where the transmit signal output (TX&) of the logic circuit (&) is connected to the transmit data input (TXX) of the bus transceiver (TRX) where the logical combination of the logical levels at the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic circuit (&) and the logic level of the additional transmission signal input (TX0) of the logic circuit (&) in the logic circuit (&) is carried out in such a way that that the transmit signal output (TX&) of the logic circuit (&) assumes a first logic level when one of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic circuit (&) has a first logical value or the additional transmission signal input (TX0) has a first logical value, and that the transmit signal output (TX&) of the logic (&) assumes a second logic level if none of the transmit signal inputs (TX0, TX1, TX2, ..... TX n ) of the logic circuit (&) has a first logical value and the additional transmit signal input (TX0) also has no first logical value, and where the transmitting port (TX out ) of the modified fully integrated bus node is provided with a transmit signal input (TX0, TX1, TX2, ..... TX n ) of another modified bus node. [9] Lighting module according to claim 7, wherein the lighting module comprises a plurality of modified bus nodes according to claim 8.

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