Semiconductor device with vertical DMOS and manufacturing process thereof

Abstract

Semiconductor device comprising: a substrate (100); a buried doped layer (102) formed on the substrate (100); a trench-gate (200) formed on the buried doped layer (102); a source area (410) formed next to the trench gate (200); a dielectric intermediate layer (400) formed on the trench gate (200) and the source area (410); a source contact terminal (710) formed to extend to and connect with the source area (410); and a drain contact (600) formed deeper than the source contact terminal (710), which extends to and is connected with the buried doped layer (102), a drift area (103) formed on the buried doped layer (102); a body area (220) formed in the drift area (103); a source metal wiring connected to the source contact terminal (710); and a drain metal wiring (820) connected to the drain contact terminal (600), wherein the drain contact connection (600) is formed such that it extends through the body region (220) and the drift region (103) and extends to the buried doped layer (102).

Description

BACKGROUND 1. Area

[0001] The following description concerns a semiconductor device with a vertical DMOS structure. 2. Description of the state of the art

[0002] The process of simultaneously fabricating multiple semiconductor devices on a single semiconductor substrate can be quite costly. This can result from the use of dozens of masks for each device and the potential involvement of dozens of lithography and etching processes. A key to producing less expensive semiconductor devices or chips may be to reduce the number of these processes. This is exemplified by bipolar CMOS-DMOS (BCD) technology among methods for fabricating multiple semiconductor devices on a single semiconductor substrate at the same time.

[0003] In recent years, the development of BCD technology has made it possible to integrate a DDMOS (Double-Diffused Metal-Oxide-Semiconductor) transistor and a CMOS (Complementary Metal-Oxide-Semiconductor) transistor, both high-voltage power MOSFET devices, onto a single IC chip. Combining a DMOS transistor and a CMOS transistor on a single IC chip can provide design versatility, improved performance and reliability, and may also reduce the overall system manufacturing costs.

[0004] Typically, DMOS devices can still be fabricated using a lateral structure in semiconductor devices using BCD technology. However, when the DMOS device is fabricated in a lateral type, a problem can arise: the integration level may be adversely affected due to lateral diffusion of the semiconductor device. There may also be a limitation in increasing the channel density, as current can flow in the horizontal direction.

[0005] Furthermore, semiconductor devices are known from JP 2009 - 043 795 A, DE 102 14 160 A1 and US 5 582 048 A, each comprising a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed next to the trench gate, a dielectric intermediate layer formed on the trench gate (200) and the source region; a source contact terminal formed to extend to and connect with the source region, and a drain contact terminal formed deeper than the source contact terminal, extending to and connected with the buried doped layer. OVERVIEW

[0006] This overview is provided to introduce, in simplified form, a selection of concepts that are described in detail below. This overview is not intended to determine key features or essential characteristics of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In a general embodiment, a semiconductor device comprises a substrate, a buried doped layer formed on the substrate, a trench-gate formed on the buried doped layer, a source region formed next to the trench-gate, a dielectric intermediate layer formed on the trench-gate and the source region, a source contact terminal formed to extend to and connect with the source region, and a drain contact terminal formed deeper than the source contact terminal, extending to and connected with the buried doped layer.Furthermore, the semiconductor boron direction has a drift region formed on the buried doped layer, a body region formed in the drift region, a source metal wiring connected to the source contact terminal, and a drain metal wiring connected to the drain contact terminal (600), wherein the drain contact terminal is formed such that it extends through the body region and the drift region and extends to the buried doped layer.

[0008] The drain contact connection can be deeper than the bottom surface of the trench gate.

[0009] The drain contact terminal directly contacts both the drain metal wiring and the buried doped layer.

[0010] The width of the drain contact connection can be greater than the width of the trench gate.

[0011] The width of the drain contact terminal can be greater than the width of the source contact terminal.

[0012] The device may also include a body contact area formed in the body region.

[0013] The drain contact connection can be formed in a drain contact hole.

[0014] The device may further include a central trench filled with a dielectric gap-filling material or dielectric gap-filling material to surround the drain contact terminal and directly contact the buried doped layer.

[0015] The device may further comprise a shallow trench with a depth shallower than the depth of the middle trench, and a deep trench with a depth deeper than the depth of the middle trench. The shallow trench may be filled with a dielectric gap-filling material, and the deep trench may be filled with the dielectric interlayer.

[0016] The deep trench may be formed deeper than the buried doped layer, and an air gap may be formed in the deep trench.

[0017] The buried doped layer can be used as a drain region. The semiconductor device can be a vertical DMOS device, and the electron flow path can be formed in a vertical direction to the substrate surface.

[0018] The trench gate can surround the drain contact port.

[0019] The source contact terminal can comprise a multitude of source contact terminals, and in a top view, the multitude of source contact terminals can surround the drain contact terminal, and the drain contact terminal can be located in the middle of the multitude of source contact terminals.

[0020] The device may further include a CMOS (Complementary Metal-Oxide-Semiconductor) device, an EDMOS (Extended Drain MOS) device and a BJT (Bipolar Junction Transistor) on the substrate.

[0021] In another general embodiment, a method for manufacturing a semiconductor device comprises forming a trench-gate in a substrate, forming a source region adjacent to the trench-gate, forming a dielectric intermediate layer on the trench-gate and the source region, forming a drain contact terminal by etching the dielectric intermediate layer and the substrate, and forming a source contact terminal connected to the source region by etching the dielectric intermediate layer, wherein the drain contact terminal is formed deeper than the source contact terminal.

[0022] The method can further include forming a central trench in the substrate and forming a dielectric void filler material in the central trench. The drain contact terminal can be formed within the dielectric void filler material.

[0023] Forming the drain contact connection can include forming a drain contact mask pattern on the dielectric interlayer, etching the dielectric interlayer using the drain contact mask pattern, forming a drain contact hole by etching a dielectric gap filler material in the central trench, and filling the drain contact hole with a metallic material.

[0024] The process can further include the formation of a buried doped layer on the substrate. The drain contact terminal can be configured to extend from the dielectric intermediate to the buried doped layer.

[0025] The method may further include forming a drift region on the buried doped layer, forming a body region in the drift region, forming a body contact region in the body region, and forming a source metal wiring connected to the source contact terminal and a drain metal wiring connected to the drain contact terminal.

[0026] The method may further include forming a shallow trench in the substrate and forming a deep trench in the substrate. The depth of a bottom surface of the drain contact connection may be positioned between the bottom surface of the shallow trench and the bottom surface of the deep trench.

[0027] The deep trench can be filled with the dielectric intermediate layer, and an air gap can be formed in the deep trench.

[0028] The method may further include forming a CMOS (Complementary Metal-Oxide Semiconductor) device, an EDMOS (extended drain MOS) device and a BJT (bipolar junction Transistor) device on the substrate.

[0029] The drain contact connection can extend through the body area and the drift area, reaching down to the buried doped layer.

[0030] In another general embodiment, a semiconductor device comprises a buried doped layer formed on a substrate, a drift region and a trench gate formed on the buried doped layer, a body region formed in the drift region and a drain contact terminal formed in such a way as to extend through the body region and the drift region and to the buried doped layer.

[0031] The device may further comprise a source region and a body contact region formed within the body region, a dielectric intermediate layer formed on the trench gate, and a source contact terminal connected to the source region. The drain contact terminal may be configured to be longer than the source contact terminal.

[0032] The device may further comprise a metal wiring formed on the dielectric intermediate layer and connected to the source contact terminal, and a drain metal wiring formed on the dielectric intermediate layer and connected to the drain contact terminal.

[0033] The drain contact connection can be formed starting from the dielectric intermediate layer and extended to the buried doped layer.

[0034] In another general embodiment, a semiconductor device comprises a buried doped layer formed between a substrate and a dielectric intermediate layer, source contact terminals each formed to extend to and connect with a source region, a drain contact terminal formed deeper than the source contact terminals between each adjacent to the source contact terminals to extend to and connect with the buried doped layer, and trench gates each formed opposite the drain contact terminal. One of the trench gates is formed between the drain contact terminal and one of the source contact terminals, and another of the trench gates is formed between the drain contact terminal and another of the source contact terminals.

[0035] The device can further comprise a dielectric intermediate layer formed on the trench gates and the source region. The source region can be formed adjacent to one of the trench gates.

[0036] The device can further comprise a drift region formed on the buried doped layer, a body region formed within the drift region, and a body contact region formed within the body region. The drain contact connection can be configured to extend through the body region and the drift region to the buried doped layer.

[0037] Further features and designs will become apparent from the following detailed description, the drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A shows a sectional view of a vertical DMOS semiconductor device according to one or more examples. Fig. Figure 1B shows an enlarged view of a drain contact terminal and its periphery of a vertical DMOS semiconductor device according to one or more examples. Fig. Figure 2 shows a top view illustrating a plurality of unit cells of a DMOS semiconductor device according to one or more examples. Fig. 3A and Fig. Figure 3B shows top views illustrating a source contact terminal and a drain contact terminal according to one or more examples. Fig. Figure 4 shows a diagram representing a cross-section of semiconductor devices including a vertical DMOS semiconductor according to one or more examples. Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12 to Fig. Figure 13 shows process diagrams illustrating a method for manufacturing a semiconductor device with a vertical DMOS device according to one or more examples. Fig. 14A, Fig. 14B, Fig. 14C and Fig. Figure 14D represents a formation of a DMOS drain contact terminal according to one or more examples. Fig. Figure 15 shows a process diagram illustrating a method for manufacturing a semiconductor device with a vertical DMOS device according to one or more examples. Fig. Figure 16 shows an ID-VG graph of a semiconductor device according to one or more examples. Fig. Figure 17 shows a graph of a breakdown voltage according to the operation of a semiconductor device according to one or more examples. Fig. Figure 18 shows an ID-VD graph of a semiconductor device according to one or more examples.

[0038] In all drawings and in the detailed description, the same reference symbols refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and representation of the elements in the drawings may be exaggerated for the sake of clarity, illustration, and convenience. DETAILED DESCRIPTION

[0039] The following detailed description is intended to assist the reader in gaining a more comprehensive understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be apparent upon understanding the disclosure of this application. For example, the sequences of operations or processes described herein are merely examples and are not limited to those presented here, but may be modified, as will be evident upon understanding the disclosure of this application, with the exception of operations or processes that necessarily occur in a specific order. Furthermore, descriptions of features known in the prior art may be omitted to improve clarity and conciseness.

[0040] Extensive reference is now made to embodiments, examples of which are shown in the accompanying drawings, where identical reference numerals consistently refer to the same elements. In this respect, the present embodiments may have different forms and should not be interpreted as being limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by reference to the figures to illustrate configurations or aspects. As used herein, the term "and / or" encompasses all combinations of one or more of the associated listed elements. Expressions such as "at least one of" modify the entire list of elements before a list of elements, and not the individual elements of the list.

[0041] If, throughout the description, an element such as a layer, area, or substrate is described as "on / at," "connected to," or "coupled to" another element, it can be directly "on / at," "connected to," or "coupled to" that other element, or one or more other elements can be in between. Conversely, if an element is described as "directly on / at," "directly connected to another element," or "directly coupled to another element," no other elements can be in between.

[0042] Although terms such as "first," "second," and "third" may be used herein to describe different elements, components, areas, layers, or sections, these elements, components, areas, layers, or sections are not meant to be limited by these terms. Rather, these terms are used only to distinguish one element, component, area, layer, or section from another. Thus, a first element, component, area, layer, or section referenced in the examples described herein may also be referred to as a second element, component, area, layer, or section without deviating from the lessons of the examples.

[0043] Spatially relative terms such as "above / above," "above," "below / below," and "below" can be used herein for the sake of simplicity to describe the relationship of one element to another, as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. For example, if the device in the figures is inverted, an element described as "above / above" or "above" relative to another element is then "below / below" or "below" relative to that other element. Thus, the term "above / above" encompasses both the above and below orientations, depending on the spatial orientation of the device.The device may also be oriented in other ways (for example, rotated by 90 degrees or in other orientations), and the spatially relative terms used here are to be interpreted accordingly.

[0044] The terminology used here serves only to describe various examples and is not intended to limit the disclosure. The articles "a" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. The terms "has," "comprising," and "has" indicate the presence of specified features, numbers, operations, parts, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, parts, elements, and / or combinations thereof.

[0045] Due to manufacturing techniques and / or tolerances, variations in the shapes shown in the drawings may occur. Therefore, the examples described here are not limited to the specific shapes shown in the drawings, but include shape changes that occur during manufacturing.

[0046] The features of the examples described here can be combined in various ways, as will become apparent upon understanding the disclosure of this application. Although the examples described here exhibit a multitude of arrangements or configurations, other arrangements or configurations are possible, as will become apparent upon understanding the disclosure of this application.

[0047] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as they would normally be understood by a person skilled in the art in the field to which this disclosure relates and based on an understanding of the disclosure of the present application. Terms as defined in commonly used dictionaries are to be interpreted in a manner consistent with their meaning in the context of the relevant prior art and the disclosure of the present application, and are not to be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0048] Terms such as “comprehensive / including” or “having” used in the embodiments should not be interpreted as necessarily encompassing all the different components or different processes or operations described in the description, and should be interpreted as meaning that some of the components or some of the processes / operations may not be included, or may also include additional components or processes / operations.

[0049] The use of the term “may” herein in relation to an example or embodiment (e.g., what an example or embodiment may include or realize or implement) means that at least one example or embodiment exists which includes or realizes or implements such a feature, while all examples are not limited to such.

[0050] Objects and effects, as well as technical arrangements or configurations for achieving the objectives of this disclosure, are evident from the examples described in detail below and the accompanying drawings. If, in describing this disclosure, it is determined that a detailed description of a known function, arrangement, or configuration might unnecessarily obscure the subject matter of this disclosure, the detailed description will be omitted.

[0051] The following terms are defined taking into account the functions in the present disclosure, which may vary depending on the user, the intention or the operator's habit.

[0052] The present disclosure is not limited to the examples disclosed below, but can be realized or implemented in various forms. The examples provided here are merely intended to supplement the disclosure and to fully inform the person skilled in the art of the scope of the present disclosure, which is defined by the scope of the claims. Therefore, the definition of the content should be provided throughout the entire description.

[0053] The present disclosure describes a semiconductor device in which a vertical DMOS structure and a DMOS drain contact termination structure are formed. The present disclosure also describes a manufacturing method for such a semiconductor device.

[0054] One purpose of the present disclosure is to provide a semiconductor device with a DMOS device whose occupancy area in the semiconductor device is reduced compared to a semiconductor device of an alternative prior art.

[0055] Another purpose of the present disclosure is to provide a semiconductor device capable of maximizing channel density. And although the manufacturing process of the semiconductor device is modified for these purposes, the other processes, with the exception of some processes of the present disclosure, can be applied to the known BCD process as it is, so that the purposes described above are achieved with minimal process improvement.

[0056] The present disclosure will be described in more detail below, based on the examples shown in the drawings.

[0057] Fig. Figure 1A shows a sectional view of a vertical DMOS semiconductor device according to one or more examples of the present disclosure.

[0058] The vertical DMOS device 10 comprises a substrate 100, an n-conducting buried doped layer 102 formed on the substrate 100, a drift region 103 formed on the buried doped layer 102, and a body region 220 formed in the drift region 103. The vertical DMOS device 10 further comprises a plurality of vertical trench gates 200 extending from an upper surface of the substrate into the drift region through the body region 220, with a trench gate electrode being formed in each of the trench gates. The vertical DMOS device 10 further comprises a source region 410 and a body contact region 420 formed in the body region 220, the source region 410 and the body contact region 420 being arranged between the trench gates.

[0059] The vertical DMOS device 10 further comprises a shallow trench 120 formed on the substrate surface, a medium trench 110 extending from the substrate surface to the buried doped layer 102 and overlapping with the shallow trench 120. The medium trench 110 and the shallow trench 120 are filled with a dielectric gap-filling material 115. The vertical DMOS device 10 also comprises a deep trench 500 with a depth greater than that of the shallow trench 120 and the medium trench 110. The deep trench 500 extends through the buried doped layer 102 and also overlaps with the shallow trench 120. The deep trench 500 has a depth greater than that of the buried doped layer 102.

[0060] The vertical DMOS device 10 further comprises a dielectric intermediate layer 400 formed on the substrate 100. The dielectric intermediate layer 400 may be filled into the deep trench 500. An air gap 520 may be formed in the deep trench 500. A drain contact hole 540 is formed in the dielectric intermediate layer 400 and extends further into a section of the substrate such that a bottom surface of the drain contact hole 540 contacts the buried doped layer 102. The drain contact hole 540 is formed within the middle trench 110, and its depth is greater than the depth of the middle trench 110. A drain contact terminal 600 formed in the drain contact hole 540 contacts the buried doped layer 102 to form a current path. The drain contact terminal 600A also contacts the dielectric gap-filling material 115 arranged in the middle trench 110.The use of the term "may" herein in relation to an example or embodiment, e.g., what an example or embodiment may include, implement, realize, or achieve, means that at least one example or embodiment with such a feature, realization, implementation, achievement, or performance exists, noting that all examples and embodiments are not limited thereto and that alternative examples or embodiments may also exist.

[0061] A source contact terminal 710 is formed spaced apart from the drain contact terminal 600 and simultaneously connected to the source area 410 and the body contact area 420. The vertical DMOS device 10 further comprises a source metal wiring 810 connected to the source contact terminal 710 and a drain metal wiring 820 connected to the drain contact terminal 600. Both the source metal wiring 810 and the drain metal wiring 820 are formed on the dielectric intermediate layer 400.

[0062] In this example, the buried doped layer 102 is used as a drain region, and a path of electrons 230 is formed in a direction perpendicular to the substrate surface. The N-type drift region 103 is used for the path of electrons. That is, the buried doped layer 102 is used as a drain region and serves as a passage for a drain current. Electrons generated in the N-type source region 410 pass through the P-type body region 220 and through the N-type drift region 103. They then reach the buried N-type doped layer 102. Since the n-type buried doped layer 102 is a region doped with a highly concentrated N-type dopant, its resistance is very low. Consequently, the electrons can flow into the drain contact terminal 600.That is, electrons flow through the source metal wiring 810, the source contact terminal 710, the body contact area 420, the n-type source area 410, the p-type body area 220, the n-type drift area 103, the buried doped layer 102, and finally the drain contact terminal 600.

[0063] By using the vertical-type DMOS device 10 of the semiconductor device of the present disclosure, the chip area can be drastically reduced compared to the lateral-type DMOS device. It is possible to ensure a wide variety of chip device designs. It is also possible to improve channel density.

[0064] In this example, the middle trench 110 is formed to surround the drain contact port 600. Therefore, the width of the middle trench 110 is greater than the width of the drain contact port 600. Furthermore, the depth of the middle trench 110 is deeper than the bottom of the trench gates 200. The middle trench 110 may also be in direct contact with the buried doped layer 102. The middle trench 110 is deeper than the shallow trench 120 and has a depth that is shallower than that of the deep trench 500. That is, the middle trench 110 has a depth between that of the shallow trench 120 and the deep trench 500.

[0065] The shallow trench 120 can be filled with the dielectric gap-filling material 115, and the deep trench 500 can be filled with the dielectric intermediate layer 400. The deep trench 500 can be formed deeper than the buried doped layer 102, and the air gap 520 can be formed in the deep trench 500.

[0066] The drain contact port 600 can be deeper than the base area of ​​the trench gate 200. Furthermore, the width of the drain contact port 600 can be greater than the width of the source contact port 710. Additionally, the width of the drain contact port 600 can be greater than the width of the trench gate 200.

[0067] Fig. Figure 1B shows an enlarged view of a drain contact terminal of a vertical DMOS semiconductor device and its periphery according to one or more examples of the present disclosure.

[0068] In the vertical DMOS semiconductor device 10, an n-type buried doped layer 102, used as a drain region, is formed on a substrate 100. Then, an n-type drift region 103 is formed on the buried n-type doped layer 102. Furthermore, a central trench 110 is formed in the semiconductor substrate 100, and the central trench 110 is filled internally with a dielectric gap-filling material 115. A drain contact hole 540 is then formed in the central trench 110. Additionally, metal wiring is formed within the drain contact hole 540 to create a drain contact terminal 600. The middle trench 110, the dielectric gap-filling material 115, the drain contact hole 540 and the drain contact terminal 600 are in direct contact with the n-conducting buried doped layer 102.In this example, the drain contact hole 540 and the drain contact terminal 600 can be formed deeper than the trench 110 in the buried N-type doped layer 102. The depth of the drain contact hole 540 and the drain contact terminal 600 can be greater than the depth of the central trench 110 or the dielectric gap-filling material 115. The difference in depth is due to an etching process for forming the drain contact hole 540 and the drain contact terminal 600 (see Figure 1). Fig. 14B). The drain contact terminal 600 can be formed by filling the drain contact hole 540 with a conductive material such as tungsten or copper. Metallic materials such as tungsten (W), aluminum, and copper can be used as the conductive material. Alternatively, a doped polysilicon material can be used. In one or more examples of the present disclosure, the drain contact terminal 600 is formed by filling it with tungsten (W).

[0069] Furthermore, the drain contact 600 is formed to extend through the body area 220 and the drift area 103, and to extend into the buried doped layer 102. The outer surface of the drain contact hole 540 or the drain contact 600 is surrounded by the dielectric gap filler material 115 and the dielectric intermediate layer 400. That is, it is surrounded by the dielectric gap filler material 115 within the substrate and by the dielectric intermediate layer 400 above the substrate 100. Its width can be tapered downwards to form a cone. In addition, the DMOS drain contact 600 has a vertical length that is the sum of the depth of the central trench 110 and the thickness of the dielectric intermediate layer 400.In a non-restrictive example, the mean trench 110 is formed in a range of 1 to 10 µm in the substrate 100, where a value obtained by adding the thickness of the dielectric intermediate layer 400 to the 1 to 10 µm can be a total vertical length of the DMOS drain contact terminal 600 of 2 to 15 µm.

[0070] A trench gate 200 is formed around the drain contact terminal 600. In this example, the trench gate can also refer to the trench gate electrode formed within the trench. Before the trench gate electrode 200 is formed, a dielectric gate layer (not shown) can be formed on / at the side wall of the trench. Furthermore, an N-type source region 410 and a P-type body contact region 420 are formed within the P-type body region 220. Additionally, a DMOS source contact terminal 710 is formed, which is electrically connected to the N-type source region 410 and the P-type body contact region 420. A source metal wiring 810 connected to the DMOS source contact terminal 710 is formed. A metal wiring 820 connected to the drain contact terminal 600 is formed.

[0071] Fig. Figure 2 shows a top view representing a plurality of unit cells of a DMOS semiconductor device according to one or more examples of the present disclosure. As in Fig. As shown in Figure 2, the basic unit of the DMOS device 10 can be defined as a unit cell. Unit cells 50 come together to form a DMOS device. A unit cell 50 comprises one DMOS drain contact terminal 600 and a plurality of DMOS source contacts (or DMOS source contact terminals) 710. In this example, only one DMOS drain contact terminal 600 is shown at the center of the unit cell 50, whereas in another example, at least two or more DMOS disconnect contact terminals 600 may be arranged in the unit cell 50. For example, the unit cell 50 comprises one drain contact terminal 600 and twelve source contacts 710. The DMOS device 10 consists of several such unit cells 50. The number of unit cells can vary depending on the size and power of the DMOS device 10. A DMOS drain contact terminal 600 is located in / at the center of the unit cell 50.A multitude of DMOS source contacts 710 surround a DMOS drain contact terminal 600. Furthermore, the DMOS drain contact terminal 600 occupies an area larger than the DMOS source contact 710. This is because the diameter of the DMOS drain contact terminal 601 is many times larger than the diameter of the DMOS source contact 710. One of the trench gates 200 is formed between the DMOS drain contact terminal 600 and one of the DMOS source contact terminals 710. Additionally, another trench gate 200 is formed between the DMOS drain contact terminal 600 and another of the source contact terminals 710. Furthermore, a trench gate 200 is formed between the DMOS source contact 710 and another DMOS source contact 710. The trench gate 200 surrounds the drain contact connection 600.The source contact terminal 710 comprises a plurality of source contact terminals, and in a top view the plurality of source contact terminals 710 surrounds the drain contact terminal 600, and the drain contact terminal 600 may be located at / in the middle of the plurality of source contact terminals 710.

[0072] Fig. 3A and Fig. Figure 3B shows top views illustrating a source contact terminal and a drain contact terminal according to one or more examples of the present disclosure.

[0073] Fig. 3A represents a source contact terminal 710 with a first high-concentration N+-doped region 410 and a second high-concentration P+-doped region 420. The first high-concentration N+-doped region 410 and the second high-concentration P+-doped region 420 are formed in the trench-gate 200 with a width of W2. In this example, W2 can also represent a distance between the N+-doped regions 410. The trench-gate 200 has a structure that is interconnected like a net or grid using a trench. In this example, the first high-concentration N+-doped region 410 is a source region, and the second high-concentration P+-doped region 420 is a body contact region 420. In this example, the first high-concentration N+-doped region 410 surrounds the second high-concentration P+-doped region 420.A DMOS source contact terminal 710 is formed, which simultaneously contacts the first high-concentration N+-doped region 410 and the second high-concentration P+-doped region 410. In . Fig. 3A, the area indicated by the diagonal dots, is a region or area of ​​the DMOS source contact terminal 710. The DMOS source contact terminal 710 is designed to completely cover the P+-doped region 420 and to partially overlap the N+-doped region 410. The DMOS source contact terminal 710 is in contact with the boundary between the first high-concentration N+-doped region 410 and the second high-concentration P+-doped region 420. In this example, the source contact terminal 710 has a width W1. Therefore, the DMOS source contact terminal 710 has a width that is smaller than the width of the N+ source region and larger than the width of the P+ body contact region 420.

[0074] Fig. Figure 3B represents a drain contact terminal 600 with a central groove 110 and a drain contact hole 540. The drain contact terminal 600 is located at / in the center of the central groove 110, and the central groove 110 surrounds the drain contact terminal 600. The central groove 110 is filled with a dielectric gap filler material 115. Therefore, the drain contact terminal 600 is formed within the drain contact hole 540 and is surrounded by the dielectric gap filler material 115. Thus, the drain contact terminal 600 can be electrically insulated from the substrate 100 or the body contact area 220. The central groove 110 has a width of W4, and the drain contact terminal 600 has a width of W3. The width W3 of the drain contact terminal 600 is at least equal to or greater than the width W1 of the source contact terminal 710.Furthermore, the widths of the DMOS drain contact terminal 600 and the DMOS source contact 710 are larger than the width W2 of a trench gate 200.

[0075] Fig. Figure 4 shows a diagram representing a cross-section of a semiconductor device according to one or more examples of the present disclosure. The present disclosure relates to a semiconductor device comprising BCD devices and a plurality of semiconductor devices encompassed in a semiconductor substrate. As shown in the figure, a CMOS (complementary metal-oxide semiconductor) device 20, an EDMOS (extended drain MOS) device 30, and a BJT (bipolar junction transistor) device 40 are encompassed in a semiconductor device. The devices 10, 20, 30, and 40 can be arranged side by side in the horizontal direction.

[0076] With reference to Fig. 4. The DMOS device 10 is formed in the semiconductor substrate 100. A description of this is omitted, as the DMOS device 10 has been described in detail previously.

[0077] With reference to Fig. In the semiconductor device, a CMOS device 20, an EDMOS device 30, and a BJT device 40 are formed side-by-side on a DMOS device 10. Each device 10, 20, 30, 40 is isolated from each other by a deep trench 500. That is, an active region, which is the region in which the DMOS device 10, the CMOS device 20, the EDMOS device 30, and the BJT device 40 are formed, is divided. The deep trench 500 can be formed to a depth of 10 to 30 µm. The device isolation layers 500 have the same depth.

[0078] With reference to Fig. 4. The CMOS device 20, the EDMOS device 30, and the BJT device 40 are formed on a semiconductor substrate 100. In this example, the semiconductor substrate 100 can be a P-type or N-type silicon substrate. In another example, a substrate in which an epilayer is formed can be used for a P-type or N-type silicon substrate. In yet another example, an SOI substrate comprising a buried oxide layer (BOX) can be used.

[0079] The CMOS device 20 can be formed on the buried N-type doped layer 102, which is a highly doped region in the semiconductor substrate 100. A P-type epilayer 101 is formed on the buried N-type doped layer 102, and a P-type well region (PW) 130 and an N-type well region (NW) 132 are formed on the p-type epilayer 101. The areas occupied by the P-type well region 130 and the N-type well region 132 can be the same or different. For example, the area of ​​the P-type well region 130 and the N-type well region 132 can be larger or smaller than the other in the semiconductor substrate 100. The CMOS device 20 comprises a first gate electrode and a second gate electrode, designated by reference numeral 300. The first gate electrode and the second gate electrode 300 are located on the P-type well area 130, respectively.The first and second gate electrodes are spaced from the P-type and N-type well regions 130 and 132, respectively, by a dielectric gate layer provided in the lower part or section. Spacers are formed on the left and right side walls of the first and second gate electrodes 300. A shallow trench 120 is formed between the first and second gate electrodes 300 for insulation. Furthermore, a high-concentration source / drain region is formed on each side of the gate electrode. CMOS source / drain contacts are formed in each of the high-concentration regions and connected to them with metal wires. The CMOS source / drain contact and the DMOS source contact 710 are formed simultaneously in the same operation.

[0080] As in Fig. As shown in Figure 4, the EDMOS device 30 comprises a semiconductor substrate 100 and a buried N-type doped layer (NBL) 102, which is a high-concentration doped region within the semiconductor substrate 100. Two well regions are formed on the buried N-type doped layer 102. The two well regions are an N-type drift region 103 and a P-type low-concentration well (DPW) region 104. The area occupied by one of the regions 103 and 104 within the semiconductor substrate 100 can be larger or smaller than the other. An N+ source region and a P+ contact region are formed within the DPW region 104 with a flat device insulation layer between them. An N-type well (NW) region 132 is formed within the N-type drift region 103. The concentration in the N-type drift area 103 is lower than in the NW area 132. In the NW area 132, a high-concentration N+ drain area is formed.The high-concentration N+ drain region is spaced at a predetermined distance from the gate electrode 350 spacer to increase the breakdown voltage. Since the concentration of the high-concentration N+ drain region is highest, and the concentration of the NW region 132 is higher than that of the N-type drift region 103, the electric field is relaxed in both the horizontal and vertical directions. An apparatus insulation layer is arranged between the NW region 132 and the gate electrode 350. This insulation layer extends from below the gate electrode 53 to the NW region 132 and into contact with the high-concentration N+ drain region.Spacers are formed on the left and right side walls of the gate electrode 300, with the spacer arranged in the DPW area 104 being in contact with the N+ source area and the N-type spacer arranged in the drift area 103 overlapping the device insulation layer.

[0081] In Fig. 4. The BJT device comprises a semiconductor substrate 100 and a buried N-type doped layer (NBL) 102, which is a high-concentration doped region within the semiconductor substrate 100. Three well regions are formed on the buried N-type doped layer 102. These three well regions are a P-type low-concentration well (DPW) region 104 and an N-type low-concentration well 103, which is located on the left / right side of the DPW region 104. Each of the regions 103 and 104 can occupy a different or the same area within the semiconductor substrate 100. A P-type well (PW) region 130 is formed within the DPW region 104. The concentration of the PW area 130 is higher than that of the DPW area 104. Furthermore, a trough (NW) area 132 of N type is formed within the low-concentration trough area 103 of N type. A device insulation layer is formed between the PW area 130 and the NW area 132.The low-concentration trough area 103 of the N-type BJT device 40 and the drift area 103 of the N-type EDMOS device 30 are formed at the same concentration in the same process.

[0082] Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. Figure 15 shows process diagrams illustrating a method for manufacturing a BCD semiconductor device including a trench-gate DMOS device according to one or more examples of the present disclosure.

[0083] With reference to Fig. In step 5, a buried doped layer 102 and a P-type epilayer 101 are formed in the semiconductor substrate 100. The substrate 100 and the epilayer 101 are of the same conductivity type, and the buried doped layer 102 is of a different conductivity type. The substrate 100 can be an epilayer 101 or a silicon substrate. For example, the substrate 100 can be a P-type silicon substrate, and the buried doped layer 102 can be a layer doped with an N-type impurity. The buried doped layer 102 is formed horizontally in the center of the substrate 100 and is not formed continuously, but rather spaced at constant intervals relative to the unit devices 10, 20, 30, 40 to be formed in the semiconductor device.That is, the first through fourth unit devices 10, 20, 30, 40 are a DMOS device, a CMOS device, an EDMOS device, and a BJT device, respectively, and devices 10, 20, 30, and 40 are spaced apart by a device insulation film for electrical insulation, and the buried doped layer 102 is also formed spaced apart like devices 10, 20, 30, and 40. When forming the buried doped layer 102, the buried doped layer is formed only in a predetermined area using a mask pattern (not shown) for forming the buried doped layer.

[0084] With reference to Fig. 6 A low-concentration trough area is formed in a portion of a P-type epilayer 101. The low-concentration trough area can be formed from different concentrations according to the properties of the unit devices 10, 30, and 40. As shown in Fig. As shown in Figure 6, an N-type drift region 103 is formed in the area where the DMOS device 10 is to be formed. The N-type drift region 103 is formed while in contact with the buried doped layer 102. In the EDMOS device 30, two well regions are formed. The two well regions are the N-type drift region 103 and the P-type low-concentration well (DPW) region 104, and the area occupied by each well region 103 and 104 in the semiconductor substrate 100 can be configured such that one side is larger or smaller than the other. In the BJT device 40, a P-type low-concentration well (DPW) region 104 is formed in the center, and an N-type drift region 103 is formed on its left / right side.The low-concentration basin 103 of type N can be formed, and the low-concentration basin (DPW) 104 of type P can be formed. Or they can be formed in reverse order.

[0085] Fig. 7A to 7E represent a process for forming insulation. A multitude of insulation zones are formed on the substrate on which the trough zones are formed, as in Fig. Figure 6 illustrates this. The isolation zone can be formed to provide the desired depth for isolation devices, and deep trench isolation (DTI) can be combined with STI or medium trench isolation (MIT). STI is an isolation zone formed thinly on the surface of the substrate to isolate the device and trough areas. MIT refers to a trench (i.e., a medium trench) formed relatively deeper to create a drain contact zone. A process for forming multiple isolation zones on a substrate is described.

[0086] As in Fig. As shown in Figure 7A, a shallow trench 120 is formed using the first mask pattern 105. Since the isolation area formed on the substrate 100 can have a different size (width), a mask pattern with a corresponding shape must be provided.

[0087] As in Fig. As shown in Figure 7B, a second mask pattern 106 is formed with respect to the entire surface of the substrate 100. This second mask pattern 106 can fill the area of ​​the shallow trench 120. Furthermore, a second mask pattern 106 is removed from the area 107 where the central DMOS trench 110 is to be formed. The removed section exposes the upper surface of the substrate 100 to the outside.

[0088] As in Fig. As shown in Figure 7C, a mean trench 110 is formed in an area where a DMOS drain contact is to be established. The mean trench 110 is formed from the surface of the substrate 100 and extends through the N-type drift area 103 to be in contact with the buried doped layer 102 or to extend slightly below it. The mean trench 110 can be removed from the substrate by various methods, such as wet etching or dry etching. Since the degree of etching decreases with increasing depth, the mean trench 110 is formed to have a narrower width as the depth increases. Furthermore, compared to Fig. 7B A section of size 'd' is removed from the upper section of the second mask 106, leaving only one section 106'. The thickness of the mask pattern is reduced by the etching process. After the central trench 110 is formed, the mask is removed.

[0089] Fig. 7D represents a state in which a dielectric gap-filling material 115 is deposited on the entire substrate, including the central trench. The shallow trench 120 and the central trench 110 are filled by the dielectric gap-filling material 115. The dielectric gap-filling material 115 can be deposited by various methods, such as chemical vapor deposition (CVD), high-density plasma (HDP) CVD, etc. The dielectric gap-filling material 115 can be a silicon oxide layer deposited by an HDP CVD process. A material used to form the dielectric intermediate layer 400 can also be a silicon oxide layer using a TEOS material.Therefore, the dielectric gap-filling material 115 and the dielectric intermediate layer 400 may not be distinguishable from each other. This is because they all consist of an oxide layer.

[0090] With reference to Fig. In step 7E, the upper surface of the dielectric gap-filling material 115 is planarized by a CMP (Chemical Mechanical Planarization) process. As a result, the insulation of the middle trench 110 and the insulation of the shallow trench 120, which represent the insulation regions, are formed in the semiconductor substrate.

[0091] Fig. Figure 8 shows a method for forming a low-voltage (LV) trough region, which is a second trough region, in some areas of substrate 100. With reference to Fig. 8. A PW region 130 and an NW-132 are formed in the epilayer 200 of the P-type CMOS device 20. Furthermore, the NW region 132 is formed in the drift region 103 of the N-type EDMOS device 30, and the BJT device 40 forms PW 130 in the DPW region 104, and NW 132 is formed in the low-concentration N-type well region 103. The second well regions 130 and 132 are doped with a higher concentration than the first well regions 103 and 104 and are formed such that they are relatively thin on the surface of the substrate 100.

[0092] Fig. Figure 9 presents a method for forming a trench to form a trench-gate electrode as described in the present disclosure. As in Fig. As shown in Figure 9, a plurality of trenches 205 are formed in the N-type drift region 103 of the DMOS device 10 to form a trench-gate electrode. The trenches 205 are all formed at a predetermined depth on the surface of the substrate 100 and are arranged so that they are uniformly spaced. The trench 205 is formed deeper than the shallow trench 120 and is thinner than the central trench 110 for the DMOS drain contact. The trenches 205 are arranged in the n-type conducting drift region 103.

[0093] Fig. 10 presents a method for forming a P-type body region, a trench gate and a trench gate electrode of the present disclosure.

[0094] With reference to Fig. In this process, a dielectric gate layer and a conductive film (not shown) are deposited over the entire surface of the substrate 100, including the trench 205, to form a trench-gate electrode. In this example, a metallic material such as polysilicon, aluminum, copper, or tungsten can be used as the conductive layer 210. Furthermore, a mask pattern for the body region (not shown) is formed on the surface of the previously deposited conductive layer 210. Ion implantation is then performed to penetrate the conductive film to the substrate to form a P-type body region 220. Thus, the P-type body region 220 can be formed on the substrate to a predetermined depth. The P-type body region 220 becomes a channel region. The depth of the P-type body region 220 is deeper than the shallow trench 120 and thinner than the trench-gate (or trench-gate electrode) 200.The dielectric gate layer (not shown) and the trench gate electrode 200 are formed in trench 205 by etching the deposited conductive layer. A planarization process such as CMP is performed to form the trench gate electrode within trench 205 instead of etching the deposited conductive layer. The conductive film deposited on the other region 20 and 30 is structured to form CMOS gate electrodes 300 and one EDMOS gate electrode 350. Therefore, the trench gate electrode 200 is formed in the vertical DMOS device 10. The CMOS gate electrodes 300 and one EDMOS gate electrode 350 are formed in the CMOS device and EDMOS device regions 20 and 30, respectively. In the CMOS device 20, the CMOS gate electrodes 300 are formed on the PW region 130 and on the NW region 132, respectively. The CMOS gate electrodes 300 are insulated from the PW region 130 and from the NW region 132 by the dielectric gate layer.Furthermore, the EDMOS gate electrode 350 in the EDMOS device 30 is formed on the DPW area 104 and the drift area 103 of the N type.

[0095] With reference to Fig. In step 11, an LDD region (not shown) is formed on a substrate, and spacers 310 are formed on both side walls of the gate electrode 300. Additionally, an N+-doped region 410 and a P+-doped region 420 are formed in the DMOS 10, CMOS 20, or EDMOS 30. A trough region or the like may also be formed. The N+-doped regions 410 are formed in the DMOS 10, CMOS 20, or EDMOS 30 by simultaneously performing the same ion implantation conditions in the same process. Similarly, the P+-doped region 420 is formed by performing the same ion implantation conditions in the same process.

[0096] Fig. Figure 12 describes a method for forming a deep trench 500. As shown, a deep trench 500 is formed in the substrate to insulate between the DMOS device 10, the CMOS device 20, the EDMOS device 30, and the BJT device 40 formed on the substrate 100. Furthermore, the deep trench 500 structure can be formed to overlap the shallow trench (STI) structure 120. That is, the deep trench 500 structure can be formed by etching the area where the shallow trench 120 is formed and by additionally etching the substrate 100. The formation of the deep trench (DTI) is carried out after the formation of the gate electrode and the source / drain regions. The depth of deep trench 500 is greater than that of trench gate 200 and middle trench 110. The depth of deep trench 500 is approximately 5 to 30 µm.Accordingly, the deep trench 500 is formed from the upper surface to the lower region of the substrate 100, in order to divide completely between the device 10, 20, 30, and 40. Furthermore, the deep trench 500 is formed deeper than the bottom surface of the buried doped layer 102. Thus, the deep trench 500 can electrically insulate the buried doped layer 102 and the adjacent buried doped layer 102.

[0097] Fig. Figure 13 describes a method for depositing a dielectric intermediate layer in the deep trench 500. As shown, the dielectric intermediate layer 400 fills the deep trench 500. Furthermore, the deep dielectric intermediate layer 400 is also formed on the gate electrodes 300 and 350 and likewise within the deep trench 500. An air gap or void 520 can be formed within the deep trench 500. When the dielectric intermediate layer is deposited, not all of them are filled, so the void 520 can be formed. To improve the void-filling properties before the dielectric intermediate layer 400 is deposited, a sidewall oxide layer (not shown), for example, an LPCVD oxide layer or a TEOS layer, can be pre-formed.For example, BPSG, PSG, or TEOS are used for the dielectric intermediate layer (ILD) 400 material using an LPCVD or PECVD process. BPSG, PSG, and TEOS are all oxide-based materials. As in... Fig. As shown in Figure 13, the dielectric intermediate layer (ILD) 400 and the electrical gap-filling material 115 can be formed in contact with each other within the central trench 100.

[0098] Fig. 14A, Fig. 14B, Fig. 14C and Fig. Figure 14D describes processes for forming a DMOS drain contact connection in the middle trench 110 filled with an insulator.

[0099] First, with reference to Fig. In Figure 14B, a DMOS drain contact etching process is performed using the DMOS drain contact mask pattern 530. In this example, a portion of the dielectric intermediate layer 400 is etched by the DMOS drain contact etching process. The etching process then continues to etch the dielectric gap filler material 115 located within the central trench 110. The etching is stopped when the buried doped layer 102 formed on the substrate 100 is exposed upon removal of the dielectric gap filler material 115. Since the dielectric gap filler material 115 and the buried doped layer 102 have different etch selectivities, the etch stop point can be easily determined. Thus, a DMOS drain contact hole 540 is formed over the dielectric intermediate layer 400 and the substrate 100.

[0100] Fig. 14C represents the DMOS drain contact mask pattern 530, which is being removed.

[0101] With reference to Fig. 14D is formed after filling the DMOS drain contact hole 540 with a metal material such as tungsten, the DMOS drain contact terminal 600 is formed using a tungsten CMP process.

[0102] Fig. Figure 15 describes a process for forming a metal wiring connection. When the drain contact terminal 600 is formed, a DMOS source contact terminal 710 is formed. To form the DMOS source contact terminal 700, a contact mask pattern (not shown) is formed on the dielectric intermediate layer 400. Then, a contact etching process is performed to form a contact hole (not shown) in the dielectric intermediate layer 400. A tungsten DMOS source contact terminal 710 is formed by filling the formed contact hole with a metallic material such as tungsten. During the formation of the DMOS source contact terminal 710, the CMOS / EDMOS / BJT contact terminals 720 are formed simultaneously in the EDOS-20, CMOS-30, and BJT-40 devices. Therefore, the DMOS drain contact terminal 600 and the DMOS source contact terminal 710 can be formed at different depths.To form the DMOS drain contact terminal 600 and the source contact terminal 710 with different depths as described above, at least two contact mask patterns are required. In this example, the DMOS source contact 710 and the DMOS drain contact 600 can be manufactured using various methods. For instance, the DMOS drain contact 600 and the source contact 710 can be formed simultaneously by performing CMP after filling the hole with a metallic material, such as tungsten, following the formation of a DMOS drain contact hole 540 and a DMOS source contact hole. To this end, a DMOS source contact hole 540 can be formed first, then a DMOS drain contact mask pattern can be formed, and then a DMOS drain contact hole 540 can be formed. Alternatively, conversely, a DMOS drain contact hole 540 can be formed first, then a DMOS source contact mask pattern can be formed, and then a DMOS source contact hole can be formed.The present disclosure describes the example as being constructed in the sequence of forming a DMOS drain contact hole 540, a DMOS drain contact terminal 600, a DMOS source contact hole, and then a DMOS source contact terminal 710. The sequence and the manufacturing process can be varied depending on manufacturing costs and feasibility. Furthermore, a source metal wiring (first metal wiring) 810 and a drain metal wiring (second metal wiring) 820 are formed, which are connected to the DMOS source contact terminal 710 and the DMOS drain contact terminal 600, respectively. A third metal wiring 830 is also formed in the EDOS-20, CMOS-30, and BJT-40 devices. Al-Cu, Cu or the like can be used as materials for the first metal wiring 810, the second metal wiring 820 and the third metal wiring 830.

[0103] As described above, the present disclosure provides for the simultaneous fabrication of a plurality of devices on a semiconductor substrate using ICD technology, and desirablely, a drain metal wiring (second metal wiring) 820 is formed on a front surface of the substrate rather than on a back surface of the substrate. In this way, the channel density of the DMOS device can be maximized.

[0104] Fig. Figure 16 shows an ID-VG graph of the semiconductor device of the present disclosure. In the semiconductor device according to one or more examples of the present disclosure, even if the gate voltage VG increases, the drain current ID does not increase until the gate voltage exceeds the threshold voltage (VT = 1.0 V in the example). When the gate voltage VG exceeds the threshold voltage VT, the drain current ID also increases.

[0105] Fig. Figure 17 shows an ID-VD graph according to the operation of the semiconductor device of the present disclosure. In the semiconductor device according to the example of the present disclosure, the VD voltage exhibits a stable drain current (ID) value up to about 35V, and breakdown occurs at about 40V. Consequently, it can be confirmed that the stable breakdown voltage, which is the objective, is obtained.

[0106] Fig. Figure 18 shows an ID-VD graph of the semiconductor device of the present disclosure by changing the gate voltage. As shown, when the gate voltage is changed from 1V to 5V, the voltage and current characteristics of the drain region are typically measured.

[0107] According to the semiconductor device with a vertical DMOS and a manufacturing method thereof as described above, a DMOS device is formed as a trench-gate in a semiconductor device using ICD technology, and the drain-contact termination structure is formed starting from the dielectric intermediate layer and extends to the substrate. Consequently, there is an effect to improve the channel density while minimizing the chip area.

Claims

Semiconductor device comprising: a substrate (100); a buried doped layer (102) formed on the substrate (100); a trench gate (200) formed on the buried doped layer (102); a source region (410) formed adjacent to the trench gate (200); a dielectric intermediate layer (400) formed on the trench gate (200) and the source region (410); a source contact terminal (710) formed to extend to and connect with the source region (410); and a drain contact terminal (600) formed deeper than the source contact terminal (710), extending to and connected with the buried doped layer (102), a drift region (103) formed on the buried doped layer (102), a body region (220) formed in the drift region (103), and a source metal wiring connected to the source contact terminal (710).and a drain metal wiring (820) connected to the drain contact terminal (600), wherein the drain contact terminal (600) is formed such that it extends through the body region (220) and the drift region (103) and extends to the buried doped layer (102). Device according to claim 1, wherein the drain contact connection (600) is deeper than a bottom surface of the trench gate (200). Device according to claim 1, wherein the drain contact terminal (600) directly contacts both the drain metal wiring and the buried doped layer (102). Device according to claim 1, wherein a width of the drain contact connection (600) is greater than a width of the trench gate (200). Device according to claim 1, wherein the width of the drain contact terminal (600) is greater than the width of the source contact terminal (710). Device according to claim 1, further comprising: a body contact area (420) formed in the body area (220). Device according to claim 1, wherein the drain contact connection (600) is formed in a drain contact hole (540). Device according to claim 1, further comprising a central trench (110) which is filled with a dielectric gap-filling material (115) to surround the drain contact terminal (600) and to directly contact the buried doped layer (102). Device according to claim 8, further comprising: a shallow trench (120) with a depth that is shallower than the depth of the middle trench (110); and a deep trench (500) with a depth that is deeper than the depth of the middle trench (110), wherein the shallow trench (120) is filled with the dielectric gap-filling material (115), and the deep trench (500) is filled with the dielectric intermediate layer (400). Device according to claim 9, wherein the deep trench (500) is formed deeper than the buried doped layer (102), and an air gap (520) is formed in the deep trench (500). Device according to claim 1, wherein the buried doped layer (102) is a drain region, wherein the semiconductor device is a vertical DMOS (double-diffused metal-oxide semiconductor) device (10), and a path of electrons is formed in a vertical direction to the surface of the substrate (100). Device according to claim 1, wherein the trench gate (200) surrounds the drain contact port (600). Device according to claim 1, wherein the source contact terminal (710) comprises a plurality of source contact terminals (710), and in a top view the plurality of source contact terminals (710) surrounds the drain contact terminal (600), and the drain contact terminal (600) is arranged in the middle of the plurality of source contact terminals (710). Device according to claim 1, further comprising a CMOS (Complementary Metal-Oxide-Semiconductor) device (20), an EDMOS (Extended Drain MOS) device (30) and a BJT (Bipolar Junction Transistor) device (40) on the substrate (100).

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