Display device

Abstract

Display device (DSP) comprising: a base material (10), a first insulating layer (11) arranged on the base material (10), a first pixel electrode (PE1) arranged on the first insulating layer (11) at a pixel (PX) positioned in a display area (DA), a second pixel electrode (PE2) arranged on the first insulating layer (11) at a dummy pixel (DP) positioned in a circumferential area (SA) outside the display area (DA), a second insulating layer (12) arranged on the first insulating layer (11) and having an opening (OP) that overlaps the first pixel electrode (PE1), a first organic layer (OR1) arranged at the pixel (PX) and in contact with the first pixel electrode (PE1) through the opening (OP), a second organic layer (OR2) arranged at the dummy pixel (DP), a first supply line (FL1) and a second supply line (FL2),which are arranged on the second insulating layer (12), a first partition (PT1) arranged on the first supply line (FL1), a second partition (PT2) arranged on the second supply line (FL2), and a common electrode (CE) comprising a first section (P1) covering the first organic layer (OR1) and a second section (P2) covering the second organic layer (OR2), wherein the first organic layer (OR1) is positioned between and spaced apart from the first partition (PT1) and the second partition (PT2), the second supply line (FL2) and the second partition (PT2) are positioned between the first organic layer (OR1) and the second organic layer (OR2), the first partition (PT1) and the second partition (PT2) have a shape in which the width (W1) of an upper part is greater than the width (W2) of a lower part,and the first section (P1) is in contact with the first supply line (FL1) between the first partition (PT1) and the first organic layer (OR1).

Description

Field of InterestEmbodiments of the present invention relate to a display device.BackgroundIn recent years, display devices to which an organic light emitting diode (OLED) is applied as a display element have been put to practical use. This display apparatus is provided with pixel electrodes, common electrodes and an organic layer disposed between the pixel electrode and the common electrode.In patterning elements such as electrodes and wiring which are repeatedly arranged in the display area, the shape of the outermost circumferential elements among these elements may not conform to the design. For example, when the pixel electrodes of each pixel are patterned by etching, the outermost circumferential pixel electrodes may be excessively eroded. By occurrence of such a shape error, the display quality of the display device is reduced. Furthermore, US 2015 / 0 060 823 A1 discloses an OLED display with an inspection region around the active display region. In this inspection region, dummy pixels are present which have the same layer structure as the active pixels. These dummy pixels allow early detection of moisture leakage from defects in the sealing layer before the active display region is damaged. Furthermore, US 2015 / 0 372 067 A1 discloses a further OLED display having dummy pixels in the edge region of the active display region. The dummy pixels contain fine grid patterns that serve as calibration grids for ink jet coating of the organic layers. By observing the ink droplets on these grid patterns, the accuracy of droplet placement and propagation can be optimized before the actual coating of the active pixels.Brief Explanation of the DrawingsFIG. 1 is a configuration for a display device according to a first embodiment. FIG. 2 is a view for an example of the layout of subpixels and dummy subpixels. FIG. 3 is a schematic sectional view of the display device taken along line III-III of FIG. 2. FIG. 4 is a sectional view for an example of film formation that can be applied to an organic film. FIG. 5 is a schematic plan view of a pixel electrode and an organic layer shown in FIG. 3. FIG. 6 is a schematic plan view of a power line, a partition wall, a common electrode, and a conductive layer shown in FIG. 3. FIG. 7 is a schematic sectional view of a display device according to a second embodiment.DETAILED DESCRIPTIONIn general, a display device according to an embodiment is provided with: a base material, a first insulating layer, a first pixel electrode, a second pixel electrode, a second insulating layer, a first organic layer, a second organic layer, a first supply line, a second supply line, a first partition wall, a second partition wall, and a common electrode. The first insulating layer is disposed on the base material. The first pixel electrode is disposed on the first insulating layer at a pixel positioned in the display region. The second pixel electrode is disposed on the first insulating layer at a dummy pixel positioned in a peripheral region outside the display region. The second insulating layer is disposed on the first insulating layer and has an opening overlying the first pixel electrode. The first organic layer is disposed at the pixel and is in contact with the first pixel electrode through the opening. The second organic layer is disposed at the dummy pixel. The first supply line and the second supply line are disposed on the second insulating layer. The first partition wall is disposed on the first supply line. The second partition wall is disposed on the second supply line. The common electrode includes a first portion covering the first organic layer and a second portion covering the second organic layer. The first organic layer is positioned between the first partition and the second partition and is spaced apart from the first partition and the second partition. The second supply line and the second partition wall are positioned between the first organic layer and the second organic layer. The first partition wall and the second partition wall have a shape in which the width of an upper part is larger than the width of a lower part. The first portion is in contact with the first power line between the first partition wall and the first organic layer.According to the above configuration, a display device can be provided that displays the display device. This is also possible to improve display quality.Hereinafter, embodiments of the present invention will be explained with reference to the drawings.The disclosure is merely an example, and the subject matter that is readily apparent to those skilled in the art while retaining the essential content of the invention is, of course, included within the scope of the present invention. Further, in order to make the explanation more clear, the drawings may schematically show the width, thickness, shape, etc. of the individual portions as compared with the actual shape, but this is merely an example and does not limit the interpretation of the present invention. In the present specification and the respective drawings, constituent elements that exhibit the same or similar functions as those with reference to the already mentioned drawings are denoted by the same reference numerals, and overlapping detailed explanations may be omitted as appropriate.In order to facilitate understanding, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are indicated as appropriate in the drawings. The direction along the X axis is referred to as an X direction or a first direction, the direction along the Y axis is referred to as a Y direction or a second direction, and the direction along the Z axis is referred to as a Z direction or a third direction. The plane defined by the X axis and the Y axis is referred to as an X-Y plane, and the plane defined by the X axis and the Z axis is referred to as an X-Z plane. The observation of the X-Y plane is called a plan view.The display device DSP according to the present embodiment is an organic electroluminescence display device provided with an organic light emitting diode (OLED) as a display element, and is installed in a television, a PC, an on-board device, a mobile terminal, a mobile phone, etc.[First Embodiment]FIG. 1 is a configuration for a display device DSP according to a first embodiment. The display device DSP includes, on an insulating base material 10, a display area DA that displays an image, and a peripheral area SA outside the display area DA. The base material 10 may be a glass or a resin film having flexibility.The display area DA is provided with a plurality of pixels PX arrayed in a matrix shape in a first direction X and a second direction Y. The pixel PX is provided with a plurality of subpixels SP. In an example, the pixel PX is provided with a red subpixel SP 1, a green subpixel SP 2, and a blue subpixel SP 3. It is also possible that the pixel PX is provided with four or more subpixels in which, in addition to the subpixels of the above three colors, subpixels of other colors such as white are also added.The subpixel SP is provided with a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 is provided with a pixel switch 2, a driving transistor 3 and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements made of, for example, thin film transistors.In the pixel switch 2, the gate electrode is connected to a scan line GL, the source electrode is connected to a signal line SL, and the drain electrode is connected to an electrode forming the capacitor 4 and the gate electrode of the driving transistor 3. In the drive transistor 3, the source electrode is connected to the other electrode forming the capacitor 4 and the power line PL, and the drain electrode is connected to the anode of the display element 20. The cathode of the display element 20 is connected to a power line FL (auxiliary wiring) supplied with a common voltage. The configuration of the pixel circuit 1 is not limited to the example shown in the drawings.The display element 20 is an organic light emitting diode (OLED) as a light emitting element. For example, the subpixel SP 1 is provided with a display element that emits light corresponding to a red wavelength, the subpixel SP 2 is provided with a display element that emits light corresponding to a green wavelength, and the subpixel SP 3 is provided with a display element that emits light corresponding to a blue wavelength. The configuration of the display elements 20 will be explained later.The peripheral region SA is provided with a plurality of dummy pixels DP that do not display an image. For example, the plurality of dummy pixels DP surround the display region DA. That is, the dummy pixels DP are positioned between the pixel PX at the outermost periphery and each side of the base material 10.The dummy pixel DP is provided with a plurality of dummy subpixels DS. In an example, the dummy pixel DP is provided with a dummy subpixel DS 1 having a structure similar to the subpixel SP 1, a dummy subpixel DS 2 having a structure similar to the subpixel SP 2, and a dummy subpixel DS 3 having a structure similar to the subpixel SP 3.FIG. 2 is a view for an example of the layout of subpixels SP 1, SP 2, SP 3 and dummy subpixels DS 1, DS 2, DS 3. Here, the four pixels PX surrounded by the frame of the dash-dotted line in FIG. 1 and the five dummy pixels DP around the pixels PX are considered.In each pixel PX, the subpixels SP 1 and the subpixels SP 2 are arrayed in the second direction Y, the subpixels SP 1 and the subpixels SP 3 are arrayed in the first direction X, and the subpixels SP 2 and the subpixels SP 3 are arrayed in the first direction X. The subpixel SP 1 is formed in a substantially rectangular shape extending in the first direction X, and the subpixel SP 2 and the subpixel SP 3 are formed in a substantially rectangular shape extending in the second direction Y. The area of the subpixel SP 2 is larger than the area of the subpixel SP 1, and the area of the subpixel SP 3 is larger than the area of the subpixel SP 2. The area of the subpixel SP 1 may also be the same as the area of the subpixel SP 2.With respect to a plurality of pixels PX arranged in the display area DA, the subpixels SP 1 and the subpixels SP 3 are alternately arrayed in the first direction X. The subpixels SP 2 and the subpixels SP 3 are also alternately arrayed in the first direction X. The subpixels SP 1 and the subpixels SP 2 are further alternately arrayed in the second direction Y. The sub-pixels SP 3 are arrayed in the second direction Y without intermediation of the sub-pixels SP 1, SP 2.Dummy subpixel DS 1 has the same shape as subpixel SP 1, dummy subpixel DS 2 has the same shape as subpixel SP 2, and dummy subpixel DS 3 has the same shape as subpixel SP 3. The arrangement shape of the dummy subpixels DS 1, DS 2, DS 3 in the dummy pixel DP is the same as the arrangement shape of the subpixels SP 1, SP 2, SP 3 in the pixel PX.Although the outer shapes of the subpixels SP 1, SP 2, SP 3 and dummy subpixels DS 1, DS 2, DS 3 shown in FIG. 2 correspond to the outer shapes of the pixel electrodes of the display element or the light emitting surface of the display element, the outer shapes are illustrated in a simplified manner and do not necessarily reflect the actual shapes. In addition, the shape of each of the dummy subpixels DS 1, DS 2, DS 3 may be similar to the shape of each of the subpixels SP 1, SP 2, SP 3, and is not necessarily limited to the same shape.FIG. 3 is a schematic sectional view of the display device DSP taken along line III-III of FIG. 2 ; the display device DSP is provided with an insulating layer 11 (first insulating layer) disposed on the base material 10 and an insulating layer 12 (second insulating layer) disposed on the insulating layer 11. The pixel circuit 1, the scan line GL, the signal line SL, and the power line PL shown in FIG. 1 are disposed on the base material 10 and covered with the insulating layer 11, but illustration thereof is omitted here. The insulating layers 11, 12 are, for example, organic insulating layers. The insulating layer 11 may be referred to as a base layer of the display element 20. The insulating layer 12 is formed to divide the display element 20 or the subpixel SP. This can be referred to as a rib or partition wall.Like the subpixel SP 3 illustrated in FIG. 3, the display element 20 of each subpixel SP is provided with a pixel electrode PE 1 (first pixel electrode), an organic layer OR 1 (first organic layer), and a common electrode CE. The pixel electrode PE 1 is an electrode disposed for each subpixel SP or each display element 20, and may be referred to as a lower electrode or an anode. The common electrode CE is an electrode that is arranged commonly for the plurality of subpixels SP or the plurality of display elements 20, and may be referred to as a counter electrode, an upper electrode, or a cathode.The pixel electrode PE1 is disposed on the insulating layer 11 and its edge portion is covered by the insulating layer 12. The pixel electrode PE1 is electrically connected to the driving transistor 3 shown in Fig. 1. The pixel electrode PE1 is a transparent electrode made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode PE1 may also be a metal electrode made of a metallic material such as silver or aluminum. The pixel electrode PE 1 may also be a stack of the transparent electrode and the metal electrode. The pixel electrode PE 1 may be formed as a stack in which a transparent electrode, a metal electrode, and a transparent electrode are stacked in this order, for example, or may also be formed as a stack of three or more layers.The insulating layer 12 has an opening OP that overlays the pixel electrode PE 1 in each subpixel SP. The organic layer OR 1 is disposed on the insulating layer 12 and is in contact with the pixel electrode PE 1 through the openings OP.FIG. 4 is a sectional view for an example of film formation that can be applied to the organic layer OR 1. The organic layer OR 1 includes, for example, a functional layer F 1, a light emitting layer EL, and a functional layer F 2 sequentially stacked from the pixel electrode PE 1 toward the common electrode CE. The function layers F 1, F 2 are, for example, a hole injection layer, a hole transport layer, a hole blocking layer, an electron injection layer, an electron transport layer, and an electron blocking layer, but may be other function layers. Each of the function layers F 1, F 2 is not limited to a single layer, and may be a stack in which a plurality of function layers are stacked. In addition, at least one of the function layers F 1, F 2 may be omitted.As illustrated in FIGS. 3 and 4, the common electrode CE covers the organic layer OR 1.The common electrode CE is a transparent electrode made of a transparent conductive material such as ITO or IZO. The common electrode CE may be covered with a transparent protective film (including at least one inorganic or organic insulating film).When the potential of the pixel electrode PE 1 is relatively higher than that of the common electrode CE, the pixel electrode PE 1 corresponds to an anode and the common electrode CE corresponds to a cathode. Also, when the potential of the common electrode CE is relatively higher than the potential of the pixel electrode PE 1, the common electrode CE corresponds to the anode and the pixel electrode PE 1 corresponds to the cathode.When the pixel electrode PE 1 corresponds to the anode as an example, the functional layer F 1 includes at least one hole injection layer or a hole transport layer, and the functional layer F 2 includes at least one electron transport layer or an electron injection layer.Like the dummy subpixels DS 1, DS 3 shown in FIG. 3, the dummy subpixels DS include a pixel electrode PE 2 (second pixel electrode) and an organic layer OR 2 (second organic layer). The pixel electrode PE2 is disposed on the insulating layer 11 like the pixel electrode PE1, and is covered by the insulating layer 12. The pixel electrode PE 2 is formed by the same process as the pixel electrode PE 1 and by the same material as the pixel electrode PE 1. The organic layer OR2 is disposed on the insulating layer 12 like the organic layer OR1, and is covered by the common electrode CE. The organic layer OR 2 has the same structure as the organic layer OR 1, and includes the light emitting layer EL and the functional layers F 1, F 2 in an example.In the example of FIG. 3, the insulating layer 12 does not have an opening in the dummy subpixel DS. As a result, the pixel electrode PE 2 and the organic layer OR 2 of each dummy subpixel DS are opposed via the insulating layer 12. In the dummy subpixel DS of such a configuration, the organic layer OR 2 does not emit light even when a potential difference is formed between the pixel electrode PE 2 and the common electrode CE.The dummy subpixel DS may be provided with the pixel circuit 1 as well as the subpixel SP. This pixel circuit 1 may be connected to the pixel electrode PE2 or may not be connected to the pixel electrode PE2. When the dummy subpixel DS is provided with the pixel circuit 1, this pixel circuit 1 can protect the pixel circuit 1 of the subpixel SP from electrostatic discharge generated in the manufacturing process of the display device DSP, etc.Between the organic layers OR 1 disposed in each of the adjacent two sub-pixels SP, between the organic layer OR 1 disposed in the sub-pixel SP and the organic layer OR 2 disposed in the dummy sub-pixel DS adjacent to this sub-pixel SP, and between the organic layers OR 2 disposed in each of the adjacent two dummy sub-pixels DS, the supply line FL and the partition wall PT are disposed. In the example of FIG. 3, the partition wall PT is also arranged on the right side of the dummy subpixel DS 3. The supply line FL is made of a metallic material. The partition wall PT is, for example, an organic insulating layer.In the following description, the three supply lines FL shown in FIG. 3 may be referred to as supply line FL 1 (first supply line), supply line FL 2 (second supply line), and supply line FL 3 (third supply line) in the order from the left. The four partition walls PT shown in FIG. 3 may also be referred to as partition wall PT 1 (first partition wall), partition wall PT 2 (second partition wall), partition wall PT 3 (third partition wall), and partition wall PT 4 (fourth partition wall) in the order from the left.The partition wall PT 1 is disposed on the lead line FL 1. The partition wall PT 2 is disposed on the supply line FL 2. The partition wall PT 3 is disposed on the supply line FL 3. The partition wall PT 4 is disposed on the conductive layer CL 1 (first conductive layer). The conductive layer CL 1 is disposed on the insulating layer 12 and is formed by the same process and from the same metal material as each supply line FL.Each partition wall PT has an inverted tapered shape. Here, the reverse tapered shape means a shape in which the width W 1 of the upper part is larger than the width W 2 of the lower part as shown for the partition wall PT 1 in FIG. 3. The side surface of the partition wall PT may be both a plane inclined to the third Z direction and a curved surface. The partition wall PT may be formed of a plurality of portions whose width gradually decreases from the upper part toward the lower part.The organic layer OR 1 of the subpixel SP 3 is positioned between the partition wall PT 1 and the partition wall PT 2 and spaced apart from the partition wall PT 1 and the partition wall PT 2. The organic layer OR 2 of the dummy subpixel DS 1 is positioned between the partition wall PT 2 and the partition wall PT 3 and spaced apart from the partition wall PT 2 and the partition wall PT 3. The organic layer OR 2 of the dummy subpixel DS 3 is positioned between the partition wall PT 3 and the partition wall PT 4 and spaced apart from the partition wall PT 3 and the partition wall PT 4.The width of the supply line FL is larger than the width W 2 of the lower part of the partition wall PT. In addition, in the example of FIG. 3, the width of the supply line FL is larger than the width W 1 of the upper part of the partition wall PT. The two ends of the supply line FL protrude from the partition wall PT arranged on this supply line FL. That is, for example, when the second power line FL 2 is considered, this second power line FL 2 has a first end portion E 11 on the organic layer OR 1 side of the subpixel SP 3 and a second end portion E 12 on the organic layer OR 2 side of the dummy subpixel DS 1. The first end portion E 11 protrudes to the organic layer OR 1 more than the partition wall PT 2, and is not covered by the partition wall PT 2. The second end portion E 12 protrudes to the organic layer OR 2 more than the partition wall PT 2 and is not covered by the partition wall PT 2. The first end portion E 11 is covered by the organic layer OR 1. The second end portion E 12 is covered by the organic layer OR 2. A gap is formed between the first end portion E 11 and the organic layer OR 1. A gap is formed between the second end portion E 12 and the organic layer OR 2. Depending on the conditions of the width W 1 and the height of the upper part of the partition wall PT and the width of the supply line FL, the organic layer OR may not cover the end portion of the supply line FL.The conductive layer CL 1 has a first end portion E 21 on the side of the organic layer OR 2 disposed in the dummy subpixel DS 3 and a second end portion E 22 on the opposite side. These end portions E 21, E 22 are not covered by the partition wall PT 4.The common electrode CE is formed for the region including the subpixel SP and the dummy subpixel DS as a whole, for example, by evaporation. Here, the upper parts of the organic layers OR 1, OR 2 and the partition wall PT are covered by the common electrode CE. In the example of FIG. 3, the conductive layer CL 1 is also covered by the common electrode CE. On the other hand, since the partition wall PT takes the above-mentioned reverse tapered shape, the common electrode CE is hardly formed on the side surface of the partition wall PT. Therefore, the common electrode CE is divided at the position of the partition wall PT.Here, of the common electrode CE, the portion covering the organic layer OR 1 is referred to as a first portion P 1, the portion covering the organic layer OR 2 is referred to as a second portion P 2, the portion covering the upper part of the partition wall PT is referred to as a third portion P 3, and the portion covering the conductive layer CL 1 is referred to as a fourth portion P 4. The third portion P 3 is spaced apart from the first portion P 1, second portion P 2, and fourth portion P 4.As shown in FIG. 3, the first portion P 1 covering the organic layer OR 1 of the subpixel SP 3 is in contact with the power line FL 1 through a gap between the partition wall PT 1 and the organic layer OR 1. In addition, this first portion P 1 is in contact with the power line FL 2 through a gap between the partition wall PT 2 and the organic layer OR 1. The other subpixels SP also have the same structure as the subpixel SP 3 shown in FIG. 3.The second portion P 2 covering the organic layer OR 2 of the dummy subpixel DS 1 is in contact with the power line FL 2 through a gap between the partition wall PT 2 and the organic layer OR 2. In addition, this second portion P 2 is in contact with the power line FL 3 through a gap between the partition wall PT 3 and the organic layer OR 2. The second portion P 2 covering the organic layer OR 2 of the dummy subpixel DS 3 is in contact with the power line FL 3 through a gap between the partition wall PT 3 and the organic layer OR 2. In addition, this second portion P 2 is in contact with the conductive layer CL 1 through a gap between the partition wall PT 4 and the organic layer OR 2. Also, the other dummy subpixels DS have the same structure as the dummy subpixel DS 1 or dummy subpixel DS 3 shown in FIG. 3.The display device DSP is further provided with a conductive layer CL 2 (second conductive layer) disposed between the insulating layers 11, 12 and a conductive layer CL 3 (third conductive layer) disposed between the base material 10 and the insulating layer 11. In the peripheral region SA, the insulating layer 12 has a contact hole CH 1 (first contact hole), and the insulating layer 11 has a contact hole CH 2 (second contact hole). The conductive layer CL 2 is formed by, for example, the same process as the pixel electrodes PE 1, PE 2 and with the same material as the pixel electrodes PE 1, PE 2.The conductive layer CL 1 is in contact with the conductive layer CL 2 through the contact hole CH 1. The conductive layer CL 2 is in contact with the conductive layer CL 3 through the contact hole CH 2. The conductive layer CL3 is supplied with a common voltage; this common voltage is supplied to the first portion P1, the second portion P2 and the fourth portion P4 of the common electrode CE via the conductive layer CL2, the conductive layer CL1 and the supply line FL.In the example of FIG. 3, an organic layer OR 3 is disposed on the conductive layer CL 1. The organic layer OR 3 is covered by the fourth portion P 4. For example, the above-explained light emitting layer EL is formed separately among the organic layers OR 1, OR 2 for each color of the subpixel SP and the dummy subpixel DS. On the other hand, at least a portion of the layers included in the above-explained function layers F 1, F 2 is simultaneously formed as a whole for the region including the subpixel SP and the dummy subpixel DS. For example, the organic layer OR 3 is a portion where the layers (common layers) simultaneously formed for each subpixel SP and each dummy subpixel DS in this manner are divided by the partition wall PT 4. In this case, the organic layer OR 3 may not include the light emitting layer EL.At least a part of the layers forming the organic layers OR 1, OR 2 may be disposed above the partition wall PT. For example, when the light emitting layer EL and the function layers F 1, F 2 are deposited in the region where the partition wall PT intersects, a part of the light emitting layer EL and the function layers F 1, F 2 is disposed between the upper part of the partition wall PT and the third portion P 3. The part concerned is spaced apart from the organic layers OR1, OR2 because the partition wall PT assumes an inverted tapered shape.FIG. 5 is a schematic plan view of the pixel electrodes PE1, PE2 and the organic layers OR1, OR2, OR3. The pixel electrodes PE1 are spaced apart from each other for each of the subpixels SP1, SP2, SP3. These pixel electrodes PE1 overlap with the above-mentioned opening OP. The pixel electrodes PE 2 are spaced apart from each other for each of the dummy subpixels DS 1, DS 2, DS 3.The organic layer OR 1 overlaps with the pixel electrode PE 1 in each of the subpixels SP 1, SP 2, SP 3. In the example of FIG. 5, a continuous organic layer OR 1 is disposed for a plurality of sub-pixels SP 3 arrayed in the second direction Y.The organic layer OR 2 overlaps with the pixel electrode PE 2 in each of the dummy subpixels DS 1, DS 2, DS 3. In the example of FIG. 5, a continuous organic layer OR 2 is disposed for a plurality of dummy subpixels DS 3 arrayed in the second direction Y. The organic layer OR 2 of the dummy subpixel DS 3 adjacent to the subpixel SP 3 in the second direction Y is connected to the organic layer OR 1 of the subpixel SP 3.The organic layer OR 3 has a portion extending in the first direction X and a portion extending in the second direction Y. The organic layer OR 3 is formed annularly, for example, in the peripheral region SA. The dummy subpixels DS 1, DS 2, DS 3 are positioned between the display region DA and the organic layer OR 3.FIG. 6 is a schematic plan view of the power line FL, the partition wall PT, the common electrode CE, and the conductive layers CL 1, CL 2, CL 3. The supply line FL includes a supply line FLx extending in a first direction X and a supply line FLy extending in a second direction Y.The supply lines FLx, FLy are arranged between adjacent two subpixels SP, between adjacent two dummy subpixels DS and between adjacent subpixels SP and dummy subpixels DS and are formed overall in the form of a grid. The supply lines FL 1, FL 2, FL 3 shown in FIG. 3 are all supply lines FLy.The partition wall PT corresponds to the area marked with a dot in the drawing. The partition wall PT includes a partition wall PTx extending in a first direction X and a partition wall PTy extending in a second direction Y. The partition walls PT 1, PT 2, PT 3, PT 4 shown in FIG. 3 are all partition walls PTy.The partition wall PTy is disposed on the supply line FLy The partition wall PTy farthest in the first direction X intersects with the conductive layer CL 1. The partition wall PTx is disposed on the supply line FLx and connected to the adjacent partition wall PTy between the sub-pixels SP 1, SP 2 arrayed in the second direction Y and between the dummy sub-pixels DS 1 and DS 2 arrayed in the second direction Y. The partition wall PTx is not disposed between the sub-pixels SP 3 arrayed in the second direction Y and the dummy sub-pixels DS 3 arrayed in the second direction Y. The partition wall PTx farthest in the second direction Y overlaps with the conductive layer CL 1, extends longer than the other partition wall PTx, and is connected to all the partition walls PTy.The conductive layers CL 1, CL 2, CL 3 are formed annularly in the peripheral region SA, for example. The dummy subpixels DS 1, DS 2, DS 3 are positioned between the display region DA and the conductive layers CL 1, CL 2, CL 3. The supply lines FLx, FLy are connected to the conductive layer CL 1.In the example of FIG. 6, a plurality of contact holes CH 1, CH 2 are formed around the dummy subpixels DS 1, DS 2, DS 3. The contact hole CH 1 is positioned closer to the display region DA than the contact holes CH 2. As another example, the contact hole CH 1 may have an elongated shape in which a plurality of contact holes CH 1 arrayed in the first direction X or the second direction Y in FIG. 6 are connected to one. Also, the contact hole CH 2 may have an elongated shape in which a plurality of contact holes CH 2 arrayed in the first direction X and a plurality of contact holes CH 2 arrayed in the second direction Y in FIG. 6 are connected to each other.As illustrated by broken lines in FIG. 6, the common electrode CE is disposed in a region including the subpixels SP 1, SP 2, SP 3 and the dummy subpixels DS 1, DS 2, DS 3. The edge of the common electrode CE is positioned between the contact holes CH1, CH2.In FIG. 3, the sectional structure along the first direction X of the subpixels SP 3 and the dummy subpixels DS 1, DS 3 is shown, but the sectional structure along the first direction X of the subpixels SP 1, SP 2 is also the same as that of the subpixels SP 3, and the sectional structure along the first direction X of the dummy subpixel DS 2 is also the same as that of the dummy subpixel DS 1. The sectional structure along the second direction Y of the subpixels SP 1, SP 2 is the same as that of the subpixel SP 3 in FIG. 3, and the sectional structure along the second direction Y of the dummy subpixels DS 1 and DS 2 is the same as that of the dummy subpixel DS 1 in FIG. 3.Among the elements arranged in each subpixel SP in the display area DA, for example, the pixel electrode PE 1 is patterned by etching. When a plurality of elements are formed simultaneously by etching in this manner, the outermost portion of these elements may be excessively eroded. Thus, when no conductive layer similar to the pixel electrode PE 1 is present outside the outermost pixel electrode PE 1 in the display area DA, the intended formation cannot be achieved in the pixel PX including the outermost pixel electrode PE 1, and the display quality may be reduced.On the other hand, in the present embodiment, dummy pixels DP including a pixel electrode PE 2 having the same shape as the pixel electrode PE 1 are arranged outside the outermost pixel PX in the display region DA. Therefore, excessive erosion of the pixel electrode PE 1 of the outermost pixel PX is less likely to occur, and as a result, the display quality of the display device DSP can be improved.Further, when a reverse tapered partition wall PT is disposed between the sub-pixel SP and the dummy sub-pixel DS as shown in FIG. 3, the common electrode CE is divided by the partition wall PT, so that it is necessary to find a structure for supplying power to the common electrode CE disposed in the sub-pixel SP. With respect to this point, as explained with reference to FIGS. 3 and 6, when a power line FL is disposed under the partition wall PT and this power line FL is connected to the common electrode CE, voltage can be appropriately applied to the common electrode CE of each subpixel SP.Moreover, with the present invention. Various suitable effects can be obtained.[Second Embodiment]The second embodiment will now be explained. A configuration not specifically mentioned is the same as the configuration of the first embodiment.FIG. 7 is a schematic sectional view of the display device DSP according to the present embodiment. In the example of this drawing, one end of the supply line FL is covered by a partition wall PT. That is, for example, when the second supply line FL 2 is considered, the first end portion E 11 thereof is covered by the partition wall PT 2, and the second end portion E 12 is not covered by the partition wall PT 2. The same applies to the relationship between the supply line FL 1 and the partition wall PT 1 as well as to the relationship between the supply line FL 3 and the partition wall PT 3. Also in the example of FIG. 7, the first end portion E 21 of the conductive layer CL 1 is covered by the partition wall PT 4, and the second end portion E 22 is not covered by the partition wall PT 4.Of the common electrode CE, the first portion P 1 covering the organic layer OR 1 of the subpixel SP 3 is in contact with the power line FL 1 through a gap between the partition wall PT 1 and the organic layer OR 1. This first portion P 1 is not in contact with the supply line FL 2 because the first end E 11 of the supply line FL 2 is covered by the partition wall PT 2. The other subpixels SP have the same structure as the subpixel SP 3 shown in FIG. 7.Among the common electrodes CE, the second portion P 2 covering the organic layer OR 2 of the dummy subpixel DS 1 is in contact with the power line FL 2 but not the power line FL 3 through a gap between the partition wall PT 2 and the organic layer OR 2. In addition, the second portion P 2 covering the organic layer OR 2 of the dummy subpixel DS 3 is in contact with the power line FL 3 but not with the conductive layer CL 1 through the gap between the partition wall PT 3 and the organic layer OR 2. The other dummy subpixels DS also have the same structure as the dummy subpixel DS 1 or dummy subpixel DS 3 shown in FIG. 7.As described herein, in the present embodiment, the two first portions P 1 each disposed in the adjacent subpixels SP are not connected via the intermediate power line FL. Also, the first and second portions P 1, P 2 each disposed in the adjacent subpixel SP and the dummy subpixel DS and the two second portions P 2 each disposed in the adjacent dummy subpixel DS are not connected by the intermediate lead FL either. In FIG. 7, a cross section along the first direction X is explained, but the same applies to a cross section along the second direction Y.When the first portion P 1 disposed in each of the adjacent subpixels SP is connected via the supply line FL, there is a possibility that, as in the above-described example of FIG. 3, the current flowing in the display element 20 of one subpixel SP may leak to the display element 20 of the other subpixel SP. When such leakage occurs between the subpixels SP, it may cause a display error or an increase in driving power of the DSP of the display device. On the other hand, the structure of the present embodiment can suppress the leakage between the display elements 20 of adjacent subpixels SP.In each of the above embodiments, the layout and the formation of the pixel PX and the dummy pixel DP are not limited to those shown in FIGS. 1 and 2. For example, in each pixel PX, subpixels SP (SP 1, SP 2, SP 3) of the same shape may be arrayed in the first direction X. Also, dummy subpixels DS (DS 1, DS 2, DS 3) of the same shape may be arrayed in the first direction X at a dummy pixel DP. In. FIGS. 1 and 2 show dummy pixels DP arranged only once around display area DA, but they may be arranged two or more times.FIG. 7 illustrates a configuration in which the first end portion E 11 of the supply line FL 2 is covered by the partition wall PT 2 and the second end portion E 12 is not covered by the partition wall PT 2. As another example, the first end portion E 11 may not be covered by the partition wall PT 2, and the second end portion E 12 may be covered by the partition wall PT 2. The relationship between the other supply line FL and the partition wall PT may also be changed.FIGS. 3 and 7 show a configuration in which the second section P 2 arranged in the dummy subpixel DS is connected to one of the supply lines FL. As another example, the second portion P 2 may not be connected to any of the supply lines FL. In this case, the second portion P 2 becomes floating.Based on the display apparatus explained above as an embodiment of the present invention, all the display apparatuses that can be appropriately designed and modified by a person skilled in the art are also included in the scope of the present invention as long as they include the gist of the present invention.Within the scope of the idea of the present invention, the skilled person can appreciate various variations, and it is understood that such variations also belong to the scope of the present invention. For example, a person skilled in the art can supplement the above-explained embodiment by adding, brushing or changing the design of a constituent element or by adding, omitting or changing the conditions of a process accordingly.Moreover, other effects brought about by the modes explained in the above-explained embodiments, which are apparent from the present description or which can be appropriately devised by a person skilled in the art, are naturally understood to be brought about by the present invention.

Claims

A display device (DSP) comprising: a base material (10); a first insulating layer (11) disposed on the base material (10); a first pixel electrode (PE1) disposed on the first insulating layer (11) at a pixel (PX) positioned in a display area (DA); a second pixel electrode (PE2) disposed on the first insulating layer (11) at a dummy pixel (DP) positioned in a peripheral area (SA) outside the display area (DA); a second insulating layer (12) disposed on the first insulating layer (11) and having an opening (OP) overlying the first pixel electrode (PE1); a first organic layer (OR1), which is arranged at the pixel (PX) and is in contact with the first pixel electrode (PE1) through the opening (OP), a second organic layer (OR2) arranged at the dummy pixel (DP), a first supply line (FL1) and a second supply line (FL2) arranged on the second insulating layer (12), a first partition wall (PT1) arranged on the first supply line (FL1), a second partition wall (PT2) arranged on the second supply line (FL2), and a common electrode (CE) including a first portion (P1) covering the first organic layer (OR1) and a second portion (P2), which covers the second organic layer (OR2), wherein the first organic layer (OR1) is positioned between the first partition wall (PT1) and the second partition wall (PT2) and is spaced apart from the first partition wall (PT1) and the second partition wall (PT2), the second supply line (FL2) and the second partition wall (PT2) are positioned between the first organic layer (OR1) and the second organic layer (OR2), the first partition wall (PT1) and the second partition wall (PT2) have a shape in which the width (W1) of an upper part is larger than the width (W2) of a lower part, and the first portion (P 1) is in contact with the first power line (FL 1) between the first partition wall (PT 1) and the first organic layer (OR 1).The display device (DSP) according to claim 1, wherein the second organic layer (OR2) is spaced apart from the second partition wall (PT2), and the second portion (P2) is in contact with the second supply line (FL2) between the second partition wall (PT2) and the second organic layer (OR2).The display device (DSP) according to claim 2, wherein the first portion (P1) is in contact with the second supply line (FL2) between the second partition wall (PT2) and the first organic layer (OR1).The display device (DSP) according to claim 1, wherein the first portion (P1) is not in contact with the second power line (FL2).The display device (DSP) according to claim 4, wherein the second supply line (FL2) has a first end portion (E11) on the first organic layer (OR1) side and a second end portion (E12) on the second organic layer (OR2) side, the first end portion (E11) is covered by the second partition wall (PT2), and the second end portion (E12) is not covered by the second partition wall (PT2).The display device (DSP) according to claim 1, wherein the common electrode (CE) further includes third portions (P3) disposed above the first partition wall (PT1) and the second partition wall (PT2), respectively, and the third portions (P3) are spaced apart from the first portion (P1) and the second portion (P2).The display device (DSP) according to claim 1, further comprising: a first conductive layer (CL1) disposed on the second insulating layer (12) in the peripheral region (SA) and to which the first supply line (FL1) and the second supply line (FL2) are connected; and a second conductive layer (CL2) disposed between the first insulating layer (11) and the second insulating layer (12) in the peripheral region (SA), wherein the second insulating layer (12) has a first contact hole (CH1) in the peripheral region (SA), and the first conductive layer (CL1) is in contact with the second conductive layer (CL2) through the first contact hole (CH1).The display device (DSP) according to claim 7, further comprising: a third conductive layer (CL3) disposed between the base material (10) and the first insulating layer (11) in the peripheral region (SA), wherein the first insulating layer (11) has a second contact hole in the peripheral region (SA), and the second conductive layer (CL2) is in contact with the third conductive layer (CL3) through the second contact hole (CH2).The display device (DSP) according to claim 7, wherein the common electrode (CE) further comprises a fourth portion (P4) disposed in the peripheral region (SA), and the fourth portion (P4) covers the first conductive layer (CL1).The display device (DSP) according to claim 9, further comprising a third organic layer (OR3) disposed on the first conductive layer (CL1), wherein the fourth portion (P4) covers the third organic layer (OR3).A display device (DSP) comprising: a base material (10); a first insulating layer (11) disposed on the base material (10); a first pixel electrode (PE1) disposed on the first insulating layer (11) at a pixel (PX) positioned in the display area (DA); a second pixel electrode (PE2) disposed on the first insulating layer (11) at a dummy pixel (DP) positioned in a peripheral area (SA) outside the display area (DA); a second insulating layer (12) disposed on the first insulating layer (11) and having an opening (OP) overlying the first pixel electrode (PE1); a first organic layer (OR1), which is arranged at the pixel (PX) and is in contact with the first pixel electrode (PE1) through the opening (OP), a second organic layer (OR2) arranged at the dummy pixel (DP), a first supply line (FL1) and a second supply line (FL2) arranged on the second insulating layer (12), a first partition wall (PT1) arranged on the first supply line (FL1), a second partition wall (PT2) arranged on the second supply line (FL2), and a common electrode (CE) including a first portion (P1) covering the first organic layer (OR1) and a second portion (P2), which covers the second organic layer (OR2), wherein the first organic layer (OR1) is positioned between the first and second partition walls (PT2) and is spaced apart from the first and second partition walls (PT2), and the second supply line (FL2) and the second partition wall (PT2) are positioned between the first organic layer (OR1) and the second organic layer (OR2), the first partition wall (PT1) and the second partition wall (PT2) have a shape in which the width (W1) of an upper part is larger than the width (W2) of a lower part, the first portion (P1) is in contact with the first supply line (FL1) between the first partition wall (PT1) and the first organic layer (OR1), and the first portion (P1) is in contact with the second supply line (FL2) between the second partition wall (PT2) and the first organic layer (OR1).The display device (DSP) according to claim 11, wherein the common electrode (CE) further includes third portions (P3) disposed above the first partition wall (PT1) and the second partition wall (PT2), respectively, and the third portions (P3) are spaced apart from the first portion (P1) and the second portion (P2).The display device (DSP) according to claim 12, further comprising: a first conductive layer (CL1) disposed on the second insulating layer (12) in the peripheral region (SA) and to which the first supply line (FL1) and the second supply line (FL2) are connected; and a second conductive layer (CL2) disposed between the first insulating layer (11) and the second insulating layer (12) in the peripheral region (SA), wherein the second insulating layer (12) has a first contact hole (CH1) in the peripheral region (SA), and the first conductive layer (CL1) is in contact with the second conductive layer (CL2) through the first contact hole (CH1).The display device (DSP) according to claim 13, further comprising: a third conductive layer (CL3) disposed between the base material (10) and the first insulating layer (11) in the peripheral region (SA), wherein the first insulating layer (11) has a second contact hole in the peripheral region (SA), and the second conductive layer (CL2) is in contact with the third conductive layer (CL3) through the second contact hole (CH2).A display device (DSP) comprising: a base material (10); a first insulating layer (11) disposed on the base material (10); a first pixel electrode (PE1) disposed on the first insulating layer (11) at a pixel (PX) positioned in a display area (DA); a second pixel electrode (PE2) disposed on the first insulating layer (11) at a dummy pixel (DP) positioned in a peripheral area (SA) outside the display area (DA); a second insulating layer (12) disposed on the first insulating layer (11) and having an opening (OP) overlying the first pixel electrode (PE1); a first organic layer (OR1), which is arranged at the pixel (PX) and is in contact with the first pixel electrode (PE1) through the opening (OP), a second organic layer (OR2) arranged at the dummy pixel (DP), a first supply line (FL1) and a second supply line (FL2) arranged on the second insulating layer (12), a first partition wall (PT1) arranged on the first supply line (FL1), a second partition wall (PT2) arranged on the second supply line (FL2), and a common electrode (CE) including a first portion (P1) covering the first organic layer (OR1) and a second portion (P2), which covers the second organic layer (OR2), wherein the first organic layer (OR1) is positioned between the first partition wall (PT1) and the second partition wall (PT2) and is spaced apart from the first partition wall (PT1) and the second partition wall (PT2), the second supply line (FL2) and the second partition wall (PT2) are positioned between the first organic layer (OR1) and the second organic layer (OR2), the first partition wall (PT1) and the second partition wall (PT2) have a shape in which the width (W1) of an upper part is larger than the width (W2) of a lower part, and the second supply line (FL 2) has a first end portion (E 11) on the first organic layer (OR 1) side and a second end portion (E 12) on the second organic layer (OR 2) side, the first end portion (E 11) is covered by the second partition wall (PT 2), and the second end portion (E 12) is not covered by the second partition wall (PT 2).The display device (DSP) according to claim 15, wherein the common electrode (CE) further includes third portions (P3) disposed above the first partition wall (PT1) and the second partition wall (PT2), respectively, and the third portions (P3) are spaced apart from the first portion (P1) and the second portion (P2).The display device (DSP) according to claim 16, further comprising: a first conductive layer (CL1) disposed on the second insulating layer (12) in the peripheral region (SA) and to which the first supply line (FL1) and the second supply line (FL2) are connected; and a second conductive layer (CL2) disposed between the first insulating layer (11) and the second insulating layer (12) in the peripheral region (SA), wherein the second insulating layer (12) has a first contact hole (CH1) in the peripheral region (SA), and the first conductive layer (CL1) is in contact with the second conductive layer (CL2) through the first contact hole (CH1).The display device (DSP) according to claim 17, further comprising: a third conductive layer (CL3) disposed between the base material (10) and the first insulating layer (11) in the peripheral region (SA), wherein the first insulating layer (11) has a second contact hole in the peripheral region (SA), and the second conductive layer (CL2) is in contact with the third conductive layer (CL3) through the second contact hole (CH2).

Images