Circuit arrangement for monitoring a battery cell

Abstract

Circuit arrangement (10) for monitoring a battery cell of a battery, in which - the circuit arrangement (10) comprises a main monitoring channel (20) with a first analog-to-digital converter, ADC, (24) a redundant monitoring channel (30) with a second ADC (34) and a comparator unit (40), - the first ADC (24) is configured to perform an analog-to-digital conversion of a broadened signal (Ucell) that is representative of a cell voltage of the accumulator cell in order to obtain a first digital cell voltage signal (U_MAIN), - the second ADC (34) is configured to perform an analog-to-digital conversion of a differential signal (Udiff) that is representative of a difference between a reference voltage (VREF) or a supply voltage (VDD) of the second ADC (34) and the provided signal (Ucell) in order to obtain a second digital level-shifted cell voltage signal (U_AUX), - the first ADC (24) and the second ADC (34) are configured to perform the analog-to-digital conversion of the signal (Ucell) or the differential signal (Udiff) depending on the reference voltage (VREF) and the reference voltage (VREF) of the first ADC (24) is equal to the reference voltage (VREF) of the second ADC (34) and - the comparison unit (40) is configured to determine a comparison value (U_delta) according to a predefined comparison function depending on the digital first cell voltage signal (U_MAIN) and the digital level-shifted second cell voltage signal (U_AUX) and to provide the comparison value (U_delta) at an output of the comparison unit (40) and / or to compare the comparison value (U_delta) with a predefined threshold value (TH) and, if the comparison value (U_delta) exceeds the predefined threshold value (TH), to provide an error signal at an output of the comparison unit (40).

Description

[0001] The invention relates to a circuit arrangement for monitoring a battery cell. The battery cell is arranged in a battery, in particular in a traction battery of an electric vehicle. Furthermore, the invention relates to a battery system and a motor vehicle.

[0002] As the powertrain becomes increasingly electrified, battery monitoring is becoming increasingly demanding in order to improve the range and operational reliability of electric vehicles, such as hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and fully electric vehicles (BEVs). A key factor in this regard is the measurement accuracy of cell voltage monitoring. A high Automotive Safety Integrity Level (ASIL) of Class C or D requires that the cell voltage be available as a measured value with high accuracy, even in the event of undetected faults. With higher cell voltage measurement accuracy, the traction battery can be operated closer to the cell voltage limits without risk, thereby increasing the achievable range with the same battery capacity.In recent years, the performance of the semiconductor components used for battery monitoring has improved significantly. However, due to the high safety requirements, the measuring circuits, such as the analog-to-digital converters for converting the detected voltage sensor signals, must be partially redundant, which leads to high costs.

[0003] US 2012 / 0 035 874 A1 discloses a battery pack. The battery pack includes a battery cell; a protection circuit for protecting the battery cell; a first analog-to-digital (A / D) converter for converting a voltage of the battery cell into a digital value and outputting the digital value as a first voltage value; a second A / D converter for converting the voltage of the battery cell into another digital value and outputting the other digital value as a second voltage value; and a comparator for comparing the first voltage value with the second voltage value and determining whether the A / D conversion of the battery pack is normal or defective based on the comparison.

[0004] US 2011 / 0 196 632 A1 discloses a device for monitoring a battery pack. The battery pack comprises battery blocks connected in series and each contains battery cells connected in series. The monitoring device for the battery pack includes a cell monitoring circuit provided for each of the battery blocks and a control circuit. Each of the cell monitoring circuits includes a cell voltage detection circuit for detecting cell voltages of the battery cells contained in a corresponding one of the battery blocks and a block voltage detection circuit for detecting a block voltage of the corresponding one of the battery blocks. The control circuit is configured to detect the state of the battery cells based on the cell voltages and block voltages transmitted from the respective cell monitoring circuits.

[0005] The object underlying the invention is to provide a circuit arrangement for monitoring a battery cell, which enables an accurate and cost-effective determination of a cell voltage of the battery cell.

[0006] The problem is solved by the features of the independent patent claims. Advantageous developments of the invention are characterized in the subclaims.

[0007] According to a first aspect, the above-mentioned object is achieved by a circuit arrangement for monitoring a rechargeable battery cell. The circuit arrangement has a main monitoring channel with a first analog-to-digital converter (ADC), a redundant monitoring channel with a second ADC, and a comparison unit. The first ADC is designed to perform an analog-to-digital conversion of a provided signal that is representative of a cell voltage of the rechargeable battery cell, in order to obtain a first digital cell voltage signal. The second ADC is designed to perform an analog-to-digital conversion of a difference signal that is representative of a difference between a reference voltage used by the two ADCs for the analog-to-digital conversion and the signal, in order to obtain a second digital level-shifted cell voltage signal.Alternatively, the second ADC is configured to perform an analog-to-digital conversion of a difference signal representative of a difference between a supply voltage of the second ADC and the signal, so as to obtain the second digital level-shifted cell voltage signal.

[0008] The first ADC and the second ADC are designed to perform the analog-to-digital conversion of the signal or the difference signal depending on the reference voltage, wherein the reference voltage of the first ADC is equal to the reference voltage of the second ADC.

[0009] The comparison unit is configured to determine a comparison value according to a predetermined function depending on the digital first cell voltage signal and the digital level-shifted second cell voltage signal. The comparison unit is further configured to provide the comparison value at an output of the comparison unit and / or to compare the comparison value with a predetermined threshold value, and if the comparison value exceeds a predetermined threshold value, to provide an error signal at an output of the comparison unit.

[0010] The error signal and / or the comparison signal are provided, for example, for an evaluation unit or a higher-level processing unit.

[0011] The comparison value of the digital first cell voltage signal and the digital level-shifted second cell voltage signal is preferably determined again at predetermined time intervals.

[0012] The use of a common reference voltage by the first and second ADCs enables space and cost savings in the implementation of the two ADCs. However, because the first and second ADCs share a common-mode reference voltage, a common-mode error in the reference voltage affects both the first ADC and the second ADC equally. The circuit arrangement allows this common-mode error to be detected through the special comparison, eliminating the need for additional safety mechanisms. Measurement accuracy can thus be significantly improved.

[0013] In at least one advantageous embodiment according to the first aspect, the circuit arrangement is embodied as an integrated circuit. This enables a compact and cost-effective implementation. Since the comparison of the output signals of the first ADC and the second ADC takes place in the same integrated circuit, propagation time differences between the two measurement results are easily avoided, enabling a significantly more accurate comparison and thus a significantly more reliable verification of the first ADC.

[0014] In at least one advantageous embodiment according to the first aspect, the circuit arrangement comprises a reference voltage source that provides the reference voltage for the first ADC and the second ADC. The use of a common reference voltage source enables more cost-effective and space-saving manufacture of the circuit arrangement.

[0015] In at least one advantageous embodiment according to the first aspect, the first ADC and the second ADC each have a first input terminal for receiving a first measurement signal representative of a potential at a positive terminal of the battery cell. Furthermore, the first ADC and the second ADC each have a second input terminal for receiving a second measurement signal representative of a potential at a negative terminal of the battery cell.

[0016] The first ADC has a first level converter on the input side, which is designed to form a first cell potential difference between the first measurement signal and the second measurement signal, wherein the first measurement signal represents the minuend and the second measurement signal represents the subtrahend. The first cell potential difference thus corresponds to the cell voltage of the battery cell or is equal to the cell voltage of the battery cell.

[0017] The second ADC has a second level converter on the input side, which is designed to form a second cell potential difference between the second measurement signal and the first measurement signal, wherein the second measurement signal represents the minuend and the first measurement signal represents the subtrahend. The second level converter is further designed to provide the difference signal for the second ADC by adding the second cell potential difference and the reference voltage when the difference signal is representative of a difference between the reference voltage and the signal, and to provide the difference signal for the second ADC by adding the second cell potential difference and the reference voltage when the difference signal is representative of a difference between the supply voltage of the second ADC and the signal.

[0018] Preferably, the first ADC and the second ADC have the same supply voltage.

[0019] In at least one embodiment according to the first aspect, the comparison function represents the sum of the digital first cell voltage signal and the digital level-shifted second cell voltage signal minus the reference voltage if the difference signal is determined as a function of the reference voltage. If the difference signal is determined as a function of the supply voltage of the second ADC, the comparison function represents the sum of the digital first cell voltage signal and the digital level-shifted second cell voltage signal minus a target value of the supply voltage of the second ADC.

[0020] In at least one embodiment according to the first aspect, the circuit arrangement comprises a first analog filter connected upstream of the first ADC and / or a second analog filter connected upstream of the second ADC. Preferably, the first and second filters are part of the integrated circuit and / or the first and second filters have different frequency responses.

[0021] The different frequency responses have the advantage that differences in the frequency responses that can arise from preprocessing can be at least partially compensated.

[0022] In at least one embodiment according to the first aspect, the first ADC and the second ADC differ in their resolution and / or their settling time.

[0023] According to a second aspect, the above-mentioned object is achieved by a battery system comprising a battery with at least one battery cell. Furthermore, the battery system comprises a circuit arrangement according to the first aspect for all or at least some of the battery cells.

[0024] According to a third aspect, the above-mentioned object is achieved by a motor vehicle having an accumulator system according to the second aspect.

[0025] Optional embodiments of the first aspect may also be present in the other aspects and have corresponding effects.

[0026] Embodiments of the invention are explained in more detail below with reference to the schematic drawings. In the figures, the same reference numerals are used for elements with essentially the same function; however, these elements need not be identical in all details.

[0027] The description of the objects specified here is not limited to the individual specific embodiments.

[0028] Features of different embodiments may be combined with one another—where technically feasible—to form further embodiments. For example, variations or modifications described with respect to one of the embodiments may also be applicable to other embodiments, unless otherwise stated.

[0029] They show: Fig. 1 an exemplary block diagram of a circuit arrangement for monitoring a battery cell, Fig. 2 an exemplary equivalent circuit diagram of a first level converter and Fig. 3 an example equivalent circuit diagram of a second level converter.

[0030] It should be noted that when an element is described as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "coupled" to another element, no intervening elements are present. Other terms used to describe the relationship between elements should be interpreted similarly (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0031] The functions of the circuit arrangement for monitoring a battery cell are described below in connection with Fig. 1, which is a simplified representation of the circuit according to the invention, in which many of the basic components have been omitted for the sake of clarity.

[0032] Fig. 1 shows an exemplary block diagram of an embodiment of a circuit arrangement 10 for monitoring a battery cell of a battery (battery cell and battery are not shown in Fig. 1). The accumulator preferably has a plurality of accumulator cells connected in parallel and / or in series. The accumulator is designed, for example, as a traction accumulator for a vehicle.

[0033] The accumulator cell is connected to the circuit arrangement 10 and the circuit arrangement receives on the input side from the accumulator cell directly or indirectly via a preprocessing unit a first cell potential signal Ucell_p and a second cell potential signal Ucell_c.

[0034] The circuit arrangement 10 has a main monitoring channel 20 with a first analog-to-digital converter (ADC) 24 and a redundant monitoring channel 30 with a second ADC 34. Furthermore, the circuit arrangement 10 has a comparison unit 40.

[0035] The circuit arrangement 10 is preferably embodied as an integrated circuit in a semiconductor chip. In particular, the semiconductor chip can comprise several such circuit arrangements 10, so that several battery cells can be monitored with the semiconductor chip.

[0036] The main monitoring channel 20 has, for example, an analog first filter 22 on its input side. The first ADC 24 is connected downstream of the first filter 22. For example, the analog first filter 22 of the main monitoring channel 20 is connected directly or indirectly to the battery cell. The analog first filter 22 is used to condition the cell potential signals Ucell_p, Ucell_n received from the battery cell.

[0037] For example, a digital low-pass filter 26 is connected downstream of the first ADC 24. For example, a filtered digital cell voltage signal UC, which represents the cell voltage of the connected battery cell, is provided at the output of the digital low-pass filter 26 for an evaluation unit 50. The evaluation unit 50 can be a control unit assigned to the circuit arrangement or a higher-level processing unit.

[0038] The redundant monitoring channel 30 of the circuit arrangement 10 has, for example, an analog second filter 32 on its input side. The second ADC 34 is connected downstream of the second filter 32. The analog second filter 32 of the redundant monitoring channel 30 is connected, for example, directly or indirectly to the battery cell. The analog second filter 32 serves to condition the cell potential signals Ucell_p, Ucell_n received from the battery cell.

[0039] In an optional embodiment, a first discrete hardware filter 28 and a second discrete hardware filter 38 are connected upstream of the circuit arrangement, wherein the first discrete hardware filter 28 is connected upstream of the first filter of the main monitoring path 20 and the second discrete hardware filter 38 is connected upstream of the second filter 32 of the redundant monitoring path.

[0040] The input of the first ADC 24 has a first input terminal for receiving a first measurement signal Uin_p, which is representative of a potential at a positive pole of the battery cell, and a second input terminal for receiving a second measurement signal Uin_n, which is representative of a potential at a negative pole of the battery cell.

[0041] The first ADC 24 includes a first level converter 241. Fig. 2 shows an exemplary equivalent circuit diagram of the first level converter 241 of the first ADC 24.

[0042] The first level shifter 241 is configured to form a first cell potential difference between the first measurement signal Uin_p and the second measurement signal Uin_n. The first cell potential difference can also be referred to as cell voltage Ucell.

[0043] The first ADC 24 (see Fig. 1) further comprises a converter unit which is designed to carry out the actual analog-to-digital conversion of the cell voltage Ucell and to provide a digital first cell voltage signal U_MAIN at the output of the converter unit.

[0044] The input of the second ADC 34 has a first input terminal for receiving the first measurement signal Uin_p, which is representative of the potential at the positive pole of the battery cell, and a second input terminal for receiving the second measurement signal Uin_n, which is representative of the potential at the negative pole of the battery cell.

[0045] The second ADC 34 includes a second level converter 341. Fig. 3 shows a simplified exemplary equivalent circuit diagram of the second level converter 341 of the second ADC 34.

[0046] The second level converter 341 is configured to form a second cell potential difference between the second measurement signal Uin_n and the first measurement signal Uin_n, wherein the second measurement signal forms the minuend and the first measurement signal forms the subtrahend. The second level converter 341 is further configured to generate a difference signal U by adding the supply voltage VCC of the second ADC and the second cell potential difference. diff to provide for the second ADC 34.

[0047] Alternatively, the second level converter 341 is designed to generate the difference signal U by adding a reference voltage VREF, which the two ADCs use for the analog-to-digital conversion, and the second cell potential difference. diff to provide for the second ADC 34.

[0048] The second ADC 34 (see Fig. 1) comprises a converter unit which is designed to carry out the actual analog-digital conversion of the difference signal U diffand to provide a digital second cell voltage signal U_AUX at the output of the converter unit.

[0049] The converter units of the first ADC 24 and the second ADC 34 can be configured identically or differently. In particular, the second ADC 34 can have a lower resolution and / or a longer settling time, since it is sufficient for the comparison to be performed only at specific time intervals. This enables a cost-effective implementation, while still ensuring the required reliability.

[0050] The first ADC 24 and the second ADC 34 are designed to perform the analog-to-digital conversion of the cell voltage U cell or the difference signal U diff depending on a reference voltage VREF that is the same for both ADCs 24, 34. In particular, the first ADC 24 and the second ADC 34 use the same reference voltage source.

[0051] The comparison unit 40 of the circuit arrangement (see Fig. 1) is designed to determine a comparison value according to a predetermined comparison function depending on the digital first cell voltage signal U_MAIN and the digital level-shifted second cell voltage signal U_AUX and, if the comparison value exceeds a predetermined threshold value TH, to provide an error signal SERR at an output of the comparison unit.

[0052] If the supply voltage VCC is used for the level shift for the second ADC 34, the comparison function comprises in particular the sum of the digital first cell voltage signal U_MAIN and the digital level-shifted second cell voltage signal U_AUX minus a setpoint value VCC_setpoint of the supply voltage of the second ADC 34.

[0053] The digital comparison mechanism thus provides the comparison values U_delta=U_MAIN+U_AUX−VCC

[0054] If the reference voltage VREF is used for the level shift for the second ADC 34, the comparison function comprises in particular the sum of the digital first cell voltage signal U_MAIN and the digital level-shifted second cell voltage signal U_AUX minus the reference voltage VREF.

[0055] In this case, the digital comparison mechanism provides the comparison values U_delta=U_MAIN+U_AUX−VREF

[0056] Furthermore, the comparison unit is designed to provide an error signal at an output of the comparison unit when the comparison value exceeds a predetermined threshold value.

[0057] The first ADC 24 and the second ADC 34 use the same reference voltage VREF. In the event that the reference voltage VREF deviates upwards by 10% due to an error, the first ADC 24 determines a cell voltage of U_MAIN=1,1*Ucell and the second ADC 34 determines a level-shifted cell voltage of U_AUX=1.1*VCC_ist−1.1*Ucell, where U cell is the measured cell voltage of the accumulator cell and VCC_ist is the actual value of the supply voltage.

[0058] When using the reference voltage VREF for level shifting, the second ADC 34 determines the level-shifted cell voltage U_AUX=1.1*VREF−1.1*Ucell.

[0059] In case of using the supply voltage VCC for level shifting at the second ADC 34 and assuming that the setpoint VCC_soll and the actual value VCC_ist of the supply voltage are equal to VCC_target=VCC_actual=VCC, the comparison unit 40 provides a comparison value of U_delta=U_MAIN+U_AUX−VCC=0.1*VCC For a supply voltage of, for example, VCC = 5V, this corresponds to 0.5 V.

[0060] When using the reference voltage VREF to shift the level of the second ADC 34, the comparison value is: U_delta=U_MAIN+U_AUX−VREF=0.1*VREF

[0061] If the comparison value U_delta, in particular an amount of the comparison value U_delta, exceeds a specified threshold value TH, it can be assumed that the reference voltage VREF has an error.

[0062] The threshold TH can be 0V, for example. However, for a fault decision, a threshold can be selected that takes a certain tolerance range into account. In particular, the threshold TH can also be specified depending on a temperature, for example, the temperature of the battery cells. The threshold TH is specified, for example, by the microcontroller or the higher-level processing unit connected to the comparison unit.

[0063] Alternatively, it is possible that the comparison with the threshold value is carried out in the microcontroller or the higher-level processing unit. List of reference symbols 10 Circuit arrangement 20 Main monitoring channel 22 analog first filter 24 first ADC 241 first level converter 26 digital filters 30 redundant monitoring channels 32 analog second filter 34 second ADC 341 second level converter 40 comparison unit 50 evaluation unit ERR error signal UC cell voltage U_MAIN first cell voltage signal U_AUX second level-shifted cell voltage signal TH threshold VCC supply voltage VREF reference voltage

Claims

[1] Circuit arrangement (10) for monitoring a battery cell of a battery, in which - the circuit arrangement (10) has a main monitoring channel (20) with a first analog-to-digital converter, ADC, (24) a redundant monitoring channel (30) with a second ADC (34) and a comparison unit (40), - the first ADC (24) is designed to perform an analog-to-digital conversion of a wide-range signal (Ucell) representative of a cell voltage of the accumulator cell in order to obtain a first digital cell voltage signal (U_MAIN), - the second ADC (34) is designed to perform an analog-to-digital conversion of a difference signal (Udiff) representative of a difference between a reference voltage (VREF) or a supply voltage (VDD) of the second ADC (34) and the provided signal (Ucell) in order to obtain a second digital level-shifted cell voltage signal (U_AUX), - the first ADC (24) and the second ADC (34) are designed to carry out the analog-digital conversion of the signal (Ucell) or the difference signal (Udiff) depending on the reference voltage (VREF) and the reference voltage (VREF) of the first ADC (24) is equal to the reference voltage (VREF) of the second ADC (34) and - the comparison unit (40) is designed to determine a comparison value (U_delta) according to a predetermined comparison function as a function of the digital first cell voltage signal (U_MAIN) and the digital level-shifted second cell voltage signal (U_AUX) and to provide the comparison value (U_delta) at an output of the comparison unit (40) and / or to compare the comparison value (U_delta) with a predetermined threshold value (TH) and, if the comparison value (U_delta) exceeds the predetermined threshold value (TH), to provide an error signal at an output of the comparison unit (40). [2] Circuit arrangement (10) according to claim 1, wherein the circuit arrangement (10) is designed as an integrated circuit. [3] Circuit arrangement (10) according to claim 1 or 2, wherein the circuit arrangement (10) comprises a reference voltage source which provides the reference voltage (VREF) for the first ADC (24) and the second ADC (34). [4] Circuit arrangement (10) according to one of the preceding claims, wherein - the first ADC (24) has a first level converter (241) and - the input of the first ADC (24) has a first input terminal for receiving a first measurement signal (U in_p ), which is representative of a potential at a positive pole of the accumulator cell, and a second input terminal for receiving a second measurement signal (U in_n ), which is representative of a potential at a negative terminal of the battery cell, and - the first level converter (241) is designed to generate a first cell potential difference between the first measurement signal (U in_p ) and the second measuring signal (U in_n ) and thus provide the signal (Ucell) for the first ADCs (24). [5] Circuit arrangement (10) according to one of the preceding claims, wherein - the second ADC (34) has a second level converter 341 and - the input of the second ADC (34) has a first input terminal for receiving a first measurement signal (U in_p ), which is representative of a potential at a positive pole of the accumulator cell, and a second input terminal for receiving a second measurement signal (U in_n ), which is representative of a potential at a negative terminal of the battery cell, and - the second level converter (341) is designed to form a second cell potential difference between the second measurement signal and the first measurement signal, wherein the second measurement signal forms the minuend and the second measurement signal forms the subtrahend, - the second level converter (341) is designed to generate the difference signal (U diff ) for the second ADC (34). [6] Circuit arrangement (10) according to one of the preceding claims, wherein the comparison function (40) represents the sum of the digital first cell voltage signal (U_MAIN) and the digital level-shifted second cell voltage signal (U_AUX) minus the reference voltage (VREF) or minus a setpoint value of the supply voltage (VCC_soll) of the second ADC (34). [7] Circuit arrangement (10) according to one of the preceding claims, which has a first analog filter (22) connected upstream of the first ADC (24) and / or a second analog filter (32) connected upstream of the second ADC (34). [8] Circuit arrangement (10) according to claim 7, wherein the first filter (22) and the second filter (32) have different frequency responses. [9] Circuit arrangement (10) according to one of the preceding claims, wherein the first ADC (24) and the second ADC (34) differ in their resolution and / or settling time. [10] Accumulator system comprising an accumulator with at least one accumulator cell and for all or at least some of the accumulator cells a circuit arrangement (10) according to one of the preceding claims 1 to 9. [11] Motor vehicle comprising an accumulator system according to claim 10.

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