Oxide semiconductor structure thin-layer transistor matrix substrate and indicator device having the same

Abstract

A thin-film transistor matrix substrate comprising: a substrate (410) having an active region (AA) and a non-active region (NA) arranged around the active region (AA); and a first thin-film transistor (DT) arranged on the substrate (410), the first thin-film transistor (DT) exhibits: an upper buffer layer (445) arranged on the substrate (410) and comprising at least one inorganic insulating layer; a first oxide semiconductor structure (474) arranged on the upper buffer layer (445); a first gate electrode (478) arranged above the first oxide semiconductor structure (474) and overlapping the first oxide semiconductor structure (474), and a first source electrode (479S) and a first drain electrode (479D) electrically connected to the first oxide semiconductor structure (474); a first light shielding structure (BSM-1) arranged below the first oxide semiconductor structure (474) and overlapping the first oxide semiconductor structure (474), wherein the first light shielding structure (BSM-1) has a semiconductor material layer; a first insulating layer (446) arranged between the first oxide semiconductor structure (474) and the first gate electrode (478); and a second insulating layer (445b, 445c) that is positioned between the first oxide semiconductor structure (474) and the first light shielding structure (BSM-1) and is part of the upper buffer layer (445), where a first parasitic capacity (C buf ), which is generated between the first light shielding structure (BSM-1) and the first oxide semiconductor structure (474), is larger than a second parasitic capacitance (C gi ), which is generated between the first gate electrode (478) and the first oxide semiconductor structure (474), and where a permittivity of the second insulating layer (445, 445a, 445b) is greater than a permittivity of the first insulating layer (446).

Description

BACKGROUND OF THE REVELATION AREA OF REVELATION

[0001] The present disclosure relates to a matrix substrate of a thin-film transistor having an oxide semiconductor structure, and in particular to a thin-film transistor matrix substrate that enables a thin-film transistor mounted on a substrate to achieve a low-grayscale display, blocking of leakage current, and an increase in threshold voltage, and to a display device having the same features. In particular, the present disclosure relates to a display device in which an s-factor value of a drive thin-film transistor is increased, enabling it to implement a fast turn-on / turn-off process while achieving a grayscale display over a wide range. DISCUSSION OF THE RELATED TECHNOLOGY

[0002] Recently, in line with advances in multimedia technology, the importance of flat panel displays has increased. To meet this demand, flat panel displays, such as liquid crystal displays, plasma displays, and organic light-emitting displays, have been introduced to the market. Currently, organic light-emitting displays are the most widely used flat panel displays due to their fast response time, high brightness, and wide viewing angle.

[0003] In such an organic light-emitting device, a plurality of pixels are arranged in a matrix, and each of the pixels comprises a light-emitting device part, represented by an organic light-emitting layer, and a pixel circuit part, represented by a thin-film transistor (hereinafter referred to as a "TFT"). The pixel circuit part comprises a drive TFT configured to operate an organic light-emitting element by supplying a drive current, and a switching TFT configured to supply a gate signal to the drive TFT.

[0004] Furthermore, a gate drive circuit part configured to supply a gate signal to each pixel may be located in a non-display area of ​​the organic light-emitting display device.

[0005] US 2015 / 0 187 959 A1 describes a matrix substrate comprising a thin-film transistor with a layer of an oxide semiconductor, comprising: gate and data lines formed on the matrix substrate and defining a pixel area, wherein the thin-film transistor is located in a device area of ​​the pixel area; a light-shielding structure located on the matrix substrate in the device area; an auxiliary line connected to the light-shielding structure and supplying a constant voltage to the light-shielding structure, wherein the auxiliary line runs parallel to and spaced apart from one of the gate and data lines; a buffer layer of an inorganic material located on the light-shielding structure and on a surface of the matrix substrate, wherein the oxide semiconductor layer is located on the buffer layer and the light-shielding structure;an intermediate insulating layer on the buffer layer, wherein the oxide semiconductor layer has an active section that is entirely located on the light-shielding structure and has a channel formed thereon, and conductive sections that are located on the side of the active section.

[0006] The following publications are also mentioned in relation to the relevant field of technology: KR 10 2015 0 002 279 A1, KR 10 2014 0 102 043 A1, KR 10 2015 0 034 077 A1, KR 10 2018 0 003 367 A1, KR 10 2015 0 074 825 A1, US 2022 / 0 190 170 A1 and US 2017 / 0 162 606 A1.

[0007] In this context, the present disclosure relates to a matrix substrate comprising a thin-film transistor arranged on a circuit part of a subpixel and configured to block a leakage current in an off state, as well as a thin-film transistor configured to achieve free grayscale representation at low grayscale levels, and a display device comprising the same. OVERVIEW

[0008] Accordingly, the present disclosure relates to a thin-film transistor matrix substrate having an oxide semiconductor structure, and to a device having the same, which substantially eliminates one or more problems due to limitations and disadvantages of the related technology.

[0009] One objective of the present disclosure is to provide a matrix substrate comprising a thin-film transistor capable of exhibiting a high effect in an off state while blocking leakage current, ensuring a threshold voltage equal to or higher than a target value, achieving free grayscale representation at low grayscale levels, and ensuring an increased s-factor value, while using an oxide semiconductor structure as an active layer thereof, and a display device comprising the same.

[0010] Additional advantages, objectives, and features of the disclosure are partly set forth in the following description and partly will become apparent to those with ordinary technical knowledge of the prior art upon examination of the following or can be learned from the application of the disclosure. The objectives and other advantages of the disclosure can be realized and achieved through the structure particularly emphasized in the written description and the claims thereto, as well as in the accompanying drawings.

[0011] To achieve these objectives and other advantages, and in accordance with the purpose of the disclosure as set forth herein and generally described, a thin-film transistor matrix substrate according to claim 1, a thin-film transistor matrix substrate according to claim 21, and a display device comprising a thin-film transistor matrix substrate according to claim 22 are provided. Further embodiments are described in the dependent claims.

[0012] According to the invention, a thin-film transistor matrix substrate is provided, comprising a substrate having an active region and a non-active region arranged around the active region, and a first thin-film transistor comprising an upper buffer layer arranged on the substrate and containing at least one inorganic insulating layer, a first oxide semiconductor structure arranged on the upper buffer layer, a first gate electrode arranged above the first oxide semiconductor structure and overlapping the first oxide semiconductor structure, a first source electrode and a first drain electrode electrically connected to the first oxide semiconductor structure, and a first light-shielding structure arranged below the first oxide semiconductor structure and overlapping the first oxide semiconductor structure, wherein the first light-shielding structure comprises a semiconductor material layer.The thin-film transistor matrix substrate further comprises a first insulating layer located between the first oxide semiconductor structure and the first gate electrode, and a second insulating layer located between the first oxide semiconductor structure and the first light-shielding structure. The first parasitic capacitance generated between the first light-shielding structure and the first oxide semiconductor structure is greater than the second parasitic capacitance generated between the first gate electrode and the first oxide semiconductor structure. The permittivity of the second insulating layer is greater than the permittivity of the first insulating layer.

[0013] The thin-film transistor matrix substrate can further comprise a second thin-film transistor comprising a second oxide semiconductor structure arranged on the upper buffer layer, a second gate electrode arranged above and overlapping the second oxide semiconductor structure, a second source electrode and a second drain electrode electrically connected to the second oxide semiconductor structure, and a second light shielding structure arranged below and overlapping the second oxide semiconductor structure, which comprises a semiconductor material layer.

[0014] The thin-film transistor matrix substrate can further include a third thin-film transistor comprising a third oxide semiconductor structure arranged on the upper buffer layer, a third gate electrode arranged above and overlapping the third oxide semiconductor structure, a third source electrode and a third drain electrode electrically connected to the third oxide semiconductor structure, and a third light shielding structure arranged below and overlapping the third oxide semiconductor structure.

[0015] The thin-film transistor matrix substrate can further comprise a fourth thin-film transistor comprising a lower buffer layer arranged on the substrate and having at least one insulating layer, a polycrystalline semiconductor structure arranged on the lower buffer layer, a fourth gate electrode arranged above the polycrystalline semiconductor structure and overlapping the polycrystalline semiconductor structure, and a fourth source electrode and a fourth drain electrode electrically connected to the polycrystalline semiconductor structure.

[0016] The thickness of the first insulating layer can be greater than the thickness of the second insulating layer.

[0017] Each of the first oxide semiconductor structure, the second oxide semiconductor structure, and the third oxide semiconductor structure can be made from an N-type semiconductor material. The semiconductor material layer can be formed from a P-type semiconductor material.

[0018] At least one of the first, second, or third light-shielding structure may further comprise a metal structure. The semiconductor material layer may be stacked on the metal structure.

[0019] At least one of the first light-shielding structure, the second light-shielding structure, or the third light-shielding structure may furthermore have a metal structure, and the semiconductor material layer may be stacked on the metal structure.

[0020] The second light-shielding structure can have a structure in which the metal structure and the semiconductor material layer are stacked. The third light-shielding structure can consist solely of the metal structure.

[0021] The thin-film transistor matrix substrate can further comprise at least one intermediate insulating layer arranged between the first and second light-shielding structures. The second and third light-shielding structures can be arranged on the same layer.

[0022] The first light-shielding structure and the second light-shielding structure can be arranged on the same layer.

[0023] The first thin-film transistor can be a driver transistor, configured to control a pixel. Each of the second and third thin-film transistors can be a switching transistor.

[0024] The first light-shielding structure may have a structure embedded in the upper buffer layer.

[0025] The upper buffer layer can have a plurality of upper sub-buffer layers, and the upper sub-buffer layers can be arranged at an upper end or at a lower end of the first light-shielding structure.

[0026] The second thin-film transistor can be electrically connected to the first gate electrode of the first thin-film transistor.

[0027] The fourth thin-film transistor can be located in at least one of the non-active area or the active area, and the first thin-film transistor can be located at a pixel in the active area.

[0028] The first light shielding structure can be electrically connected to one of the first source electrodes and the first drain electrode.

[0029] The reflectivity of the semiconductor material layer can be lower than the reflectivity of the metal structure.

[0030] The polycrystalline semiconductor structure and the semiconductor material layer can be doped with p-type impurity ions.

[0031] According to the invention, a thin-film transistor matrix substrate is further provided, comprising a substrate having an active region and a non-active region arranged around the active region, and a switching thin-film transistor arranged on the substrate, wherein the switching thin-film transistor has a buffer layer arranged on the substrate, an oxide semiconductor structure arranged on the buffer layer, a gate electrode arranged above the oxide semiconductor structure and overlapping the oxide semiconductor structure, a source electrode and a drain electrode electrically connected to the oxide semiconductor structure, and a light shielding structure arranged below the oxide semiconductor structure and comprising a semiconductor material layer.The thin-film transistor matrix substrate further comprises a first insulating layer located between the first oxide semiconductor structure and the first gate electrode, and a second insulating layer located between the first oxide semiconductor structure and the first light-shielding structure. The first parasitic capacitance generated between the first light-shielding structure and the first oxide semiconductor structure is greater than the second parasitic capacitance generated between the first gate electrode and the first oxide semiconductor structure. The permittivity of the second insulating layer is greater than the permittivity of the first insulating layer.

[0032] In another aspect of the present disclosure, a display device is provided comprising the thin-film transistor matrix substrate and a light-emitting device part. The light-emitting device part has an anode arranged on the substrate, a cathode facing the anode, and a light-emitting layer arranged between the anode and the cathode.

[0033] The objectives of this disclosure are not limited to those described above, and further, as yet undescribed, objectives of this disclosure will be more clearly understood by those skilled in the art based on the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are provided to further clarify the disclosure and are embedded in and form part of this application, represent embodiment(s) of the disclosure and, together with the description, serve to explain the principle of the disclosure. The drawings include: Fig. Figure 1 is a schematic block diagram of a display device according to an exemplary embodiment of the present disclosure; Fig. Figure 2 is a schematic block diagram of a subpixel of the display device according to the exemplary embodiment of the present disclosure; Fig. Figure 3 is a circuit diagram of a subpixel of the display device according to the exemplary embodiment of the present disclosure; Fig. 4A is a cross-sectional view showing a thin-film transistor arranged in a non-active region on a gate control circuit part, a control thin-film transistor, a switching thin-film transistor and a storage capacitor arranged in an active region, according to a first embodiment of the present disclosure; Fig. 4B is an enlarged cross-sectional view, showing only the area shown in Fig. The control thin-film transistor shown in 4A is enlarged; Fig. 4C is a circuit diagram that shows a relationship between parasitic capacitances that occur in the design of the Fig. 4B are generated; Fig. Figure 5 is a cross-sectional view showing only a pixel portion according to a second embodiment of the present disclosure; and Fig. Figure 6 is a cross-sectional view representing a third embodiment of the present disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0035] The advantages and features of the present disclosure and methods for achieving them will become clear from embodiments which are described in detail below with reference to the accompanying drawings. However, the present disclosure can be formulated in many different forms and should not be understood as being limited to the embodiments set forth herein. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and fully conveys its scope to the person skilled in the art.

[0036] In the drawings illustrating the exemplary embodiments of the present disclosure, the depicted shape, size, ratio, angle, and number are given as examples and are therefore not limited to the disclosure of the present disclosure. Throughout the present application, the same reference numerals denote the same components. Furthermore, in the following description of the present disclosure, a detailed description of known functions and embodiments will be omitted if it might further obscure the subject matter of the present disclosure. The terms "has," "contains," and / or "has" used in this application do not preclude the presence or addition of further elements unless they are used together with the term "only." The singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0037] In interpreting the components contained in the various embodiments of the present disclosure, it is assumed that the components have a defect area, even if this is not expressly described.

[0038] In the description of the various embodiments of the present disclosure, when describing spatial relationships, for example, when the spatial relationship between two parts is described using “on”, “above”, “under”, “next to” or the like, one or more further parts may be positioned between the two parts, unless the term “directly” or “close to” is used.

[0039] If temporal relationships are described in the description of the various embodiments of the present disclosure, for example, if the temporal relationship between two processes is described using "after", "subsequently", "next", "before" or the like, the processes cannot occur sequentially unless the term "immediately" or "just" is used.

[0040] It should be understood that, although the terms "first," "second," etc., may be used here to describe different elements, these elements are not intended to be restricted by these terms. These terms are used merely to distinguish one element from another. Therefore, in the present description, an element designated as "first" may be the same as an element designated as "second" without exceeding the technical scope of this disclosure, unless otherwise stated.

[0041] The respective features of the various embodiments of the present disclosure can be partially or completely coupled and combined, and various technical interconnections and operating modes are possible. These different embodiments can be implemented independently of one another or in association with one another. - First embodiment -

[0042] A first embodiment of the present disclosure will below be described in detail with reference to the accompanying drawings.

[0043] Fig. Figure 1 is a schematic block diagram of a display device 100 according to an exemplary embodiment of the present disclosure.

[0044] Fig. 2 is a schematic block diagram of a Fig. 1 displayed subpixel SP.

[0045] As in Fig. As shown in Figure 1, the display device 100 comprises an image processor 110, a degradation compensator 150, a memory 160, a timing controller 120, a data driver 140, a power supply 180, a gate driver 130, and a display panel PAN formed with the gate driver 130. In particular, a non-active area NA of the display panel PAN has a bending area BA. The display panel PAN can be folded in the bending area BA, and thus an aperture of it can be reduced.

[0046] The image processor 110 outputs control signals for controlling various devices, along with image data supplied from the outside.

[0047] The degradation compensator 150 modulates input image data IData of each subpixel SP of a current frame based on a detection data voltage Vsen supplied by the data driver 140 and then feeds the modulated image data, i.e. data MData, to the timing control 120.

[0048] The timing control 120 generates and outputs a gate timing control signal GDC for controlling the operating timing of the gate driver 130 and a data timing control signal DDC for controlling the operating timing of the data driver 140, based on a control signal that is input into it by the image processor 110.

[0049] The gate driver 130 outputs a sampling signal to the display panel PAN in response to the gate timing control signal GDC supplied by the timing controller 120. The gate driver 130 outputs the sampling signal via a plurality of gate lines GL1 to GLm. In particular, the gate driver 130 can be configured to have a gate-in-panel (GIP) structure in which a thin-film transistor is stacked on a substrate in the display device 100, which may be an organic electroluminescent display device. The GIP can include a plurality of circuits, such as a shift register, a level shifter, etc.

[0050] In response to the data timing control signal DDC input from the timing controller 120, the data driver 140 outputs a data voltage to the display panel PAN. The data driver 140 outputs the data voltage via a plurality of data lines DL1 to DLn.

[0051] The 180 power supply outputs a high-level drive voltage EVDD, a low-level drive voltage EVSS, etc., and delivers these output voltages to the PAN display panel. The high-level drive voltage EVDD and the low-level drive voltage EVSS are supplied to the PAN display panel via power lines.

[0052] The PAN display panel shows an image corresponding to the data voltage and sampling signal supplied in an associated manner by the data driver 140 and the gate driver 130, which may be located in the non-active area NA and which are powered by the power supply 180.

[0053] An active area AA of the display panel PAN is defined by a plurality of subpixels SP and thus displays a current image. The subpixels SP have a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel, or they have a white (W) subpixel, a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. In this case, the W, R, G, and B subpixels SP can be configured to have the same area, or they can be configured to have different areas.

[0054] Memory 160 not only stores a lookup table for degradation compensation gains, but also stores a degradation compensation time point for an organic light-emitting element of each subpixel SP. In this case, the degradation compensation time point of the organic light-emitting element can be the number of times an organic light-emitting display panel is driven, or the duration for which the organic light-emitting display panel is driven.

[0055] This can be done, as in Fig. As shown in Figure 2, each subpixel SP is connected to a gate line, for example, the gate line GL1, a data line, for example, the data line DL1, a detection voltage readout line, for example, a detection data voltage readout line SRL1, and a power line, for example, a power line PL1. The number of transistors and capacitors of the subpixel SP and the control method of the subpixel SP are determined according to a circuit configuration of the subpixel SP.

[0056] Fig. Figure 3 is a circuit diagram of a subpixel SP of the display device 100 according to the exemplary embodiment of the present disclosure.

[0057] As in Fig. As shown in Figure 3, the display device 100 according to the exemplary embodiment of the present disclosure has a gate line GL, a data line DL, a power supply line PL and a scanning line SL that intersect each other, defining a subpixel SP, and has a control thin-film transistor DT, a light-emitting element D, a storage capacitor Cst, a first switching thin-film transistor ST-1 and a second switching thin-film transistor ST-2 at the subpixel SP.

[0058] The light-emitting element D can have an anode connected to a second node N2, a cathode connected to an input terminal for a low-level drive voltage EVSS, and an organic light-emitting layer positioned between the anode and the cathode.

[0059] The control thin-film transistor DT controls a current Id flowing through the light-emitting element D in accordance with a gate-source voltage Vgs. The control thin-film transistor DT has a gate electrode connected to a first node N1, a drain electrode connected to the current line PL for receiving a high-level control voltage EVDD, and a source electrode connected to the second node N2.

[0060] The storage capacitor Cst is connected between the first node N1 and the second node N2.

[0061] When the display panel PAN is activated, the first switching thin-film transistor ST-1, in response to a scanning signal SCAN, applies a data voltage VData, charged into the data line DL, to the first node N1, thereby switching on the drive thin-film transistor DT. In this case, the first switching thin-film transistor ST-1 has a gate electrode connected to the gate line GL for receiving the scanning signal SCAN, a drain electrode connected to the data line DL for receiving the data voltage VData, and a source electrode connected to the first node N1. The first switching thin-film transistor ST-1 is known to operate more sensitively than other switching thin-film transistors in the pixel. Therefore, it is necessary to increase the threshold voltage of the first switching thin-film transistor ST-1 to facilitate its control.

[0062] The second switching thin-film transistor ST-2 stores a source voltage of the second node N2 in a detection capacitor Cx of a detection voltage readout line SRL by switching current between the second node N2 and the detection voltage readout line SRL in response to a detection signal SEN. In response to the detection signal SEN, the second switching thin-film transistor ST-2 resets a source voltage of the drive thin-film transistor DT to an initialization voltage Vpre by switching current between the second node N2 and the detection voltage readout line SRL when the display panel PAN is driven. In this case, one gate electrode of the second switching thin-film transistor ST-2 is connected to the detection line SL, one drain electrode is connected to the second node N2, and one source electrode is connected to the detection voltage readout line SRL.

[0063] Although a display device with a 3T1C structure comprising three thin-film transistors and a storage capacitor has been presented and described, the display device of the present disclosure can be applied to various pixel structures, such as 4T1C, 5T1C, 6T1C, 7T1C and 8T1C, without being limited to the structure described above.

[0064] This is Fig. 4A a cross-sectional view showing a thin-film transistor GT for a gate drive circuit, which is a representative thin-film transistor arranged in a non-active region NA, in particular a GIP region, and comprising a polycrystalline semiconductor structure, a drive thin-film transistor DT arranged in a subpixel in an active region AA and comprising an oxide semiconductor structure configured to drive a light-emitting element, a first switching thin-film transistor ST-1 having an oxide semiconductor structure, and a storage capacitor Cst, in accordance with the first embodiment of the present disclosure.

[0065] As in Fig. As shown in Figure 4A, the drive thin-film transistor DT and the first switching thin-film transistor ST-1 are arranged in a subpixel on a substrate 410. Although the drive thin-film transistor DT and only one switching thin-film transistor ST-1 are shown in Fig. 4A is shown, this representation is only for the purpose of simplifying the description, and a plurality of switching thin-film transistors may actually be arranged on substrate 410.

[0066] Furthermore, a plurality of thin-film transistors GT for a gate-driven circuit, forming a gate driver, can be arranged in the inactive region NA on substrate 410, particularly in the GIP region. The thin-film transistor GT for the gate-driven circuit, referred to as a "gate-driven thin-film transistor GT," can utilize a polycrystalline semiconductor structure as one of its active layers.

[0067] Although the case in which the gate-driven thin-film transistor GT, which has the polycrystalline semiconductor structure, is located in the non-active region NA is described in the first embodiment, a switching thin-film transistor, which has the same structure as that of the gate-driven thin-film transistor GT, can be located in the subpixel.

[0068] Of course, the gate-driven thin-film transistor GT, located in the non-active region NA, and the switching thin-film transistor, located in the active region AA, can have different configurations, such as an N-type thin-film transistor and a P-type thin-film transistor, because the types of impurities implanted in them are different.

[0069] In this case, the majority of thin-film transistors arranged in the gate driver can establish a CMOS configuration in which a thin-film transistor for a gate driver circuit, which has a polycrystalline semiconductor structure, and a switching thin-film transistor, which has an oxide semiconductor structure, are paired.

[0070] The following description is given in conjunction with an example in which a thin-film transistor for a gate control circuit, which uses a polycrystalline semiconductor structure as its active layer, is located in the non-active region NA.

[0071] The gate-driven thin-film transistor GT has a polycrystalline semiconductor structure 414 arranged on a lower buffer layer 411 formed on the substrate 410, a first insulating gate-insulating layer 442 configured to insulate the polycrystalline semiconductor structure 414, a first gate electrode 416 arranged on the first gate-insulating layer 442 overlapping the polycrystalline semiconductor structure 414, a plurality of insulating layers arranged on the first gate electrode 416, and a first source electrode 417S and a first drain electrode 417D arranged on the plurality of insulating layers.

[0072] Substrate 410 can be formed by a multilayer structure in which an organic layer and an inorganic layer are stacked alternately. For example, substrate 410 can have a multilayer structure in which an organic layer, such as polyimide, and an inorganic layer, such as silicon dioxide (SiO2), are stacked alternately.

[0073] The lower buffer layer 411 is formed on the substrate 410. The lower buffer layer 411 serves to prevent the ingress of moisture, etc., from the outside. The lower buffer layer 411 can be formed by depositing an inorganic insulating layer, for example, silicon dioxide (SiO2), in a quantity of at least one layer.

[0074] The polycrystalline semiconductor structure 414 is formed on the lower buffer layer 411. The polycrystalline semiconductor structure 414 is used as the active layer of the thin-film transistor. The polycrystalline semiconductor structure 414 has a first channel region 414a, as well as a first source region 414b and a first drain region 414c, which are opposite each other with the first channel region 414a inserted between them.

[0075] The polycrystalline semiconductor structure 414 is insulated by the first gate insulating layer 442. The first gate insulating layer 442 is formed by depositing an inorganic insulating layer, for example, silicon dioxide (SiO2), in at least one layer over the entire surface of the substrate 410, which is formed with the polycrystalline semiconductor structure 414. The first gate insulating layer 442 protects and insulates the polycrystalline semiconductor structure 414 from the outside.

[0076] The first gate electrode 416, which overlaps the first channel region 414a of the polycrystalline semiconductor structure 414, is formed on the first gate insulating layer 442.

[0077] The first gate electrode 416 can be made of a metallic material. For example, the first gate electrode 416 can take the form of a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, without being limited thereto.

[0078] A plurality of insulating layers can be formed between the first gate electrode 416 and the first source electrode 417S and drain electrode 417D.

[0079] Referring to Fig. 4A can be the plurality of insulating layers a first intermediate insulating layer 443 contacting an upper surface of the first gate electrode 416, and a second intermediate insulating layer 444, an upper buffer layer 445, a second gate insulating layer 446 and a third intermediate insulating layer 447 stacked successively on the first intermediate insulating layer 443 in that order.

[0080] The first source electrode 417S and the first drain electrode 417D are arranged on the third intermediate insulating layer 447. The first source electrode 417S and the first drain electrode 417D are connected to the polycrystalline semiconductor structure 414 in an associated manner via a first contact hole CH1 and a second contact hole CH2. The first contact hole CH1 and the second contact hole CH2 extend through the first gate insulating layer 442, the first intermediate insulating layer 443, the second intermediate insulating layer 444, the upper buffer layer 445, the second gate insulating layer 446, and the third intermediate insulating layer 447, thereby exposing the first source region 414b and the first drain region 414c, respectively, of the polycrystalline semiconductor structure 414.

[0081] Here, the control thin-film transistor DT, the first switching thin-film transistor ST-1 and the storage capacitor Cst are arranged at the subpixel in the active area AA.

[0082] In the first embodiment, both the control thin-film transistor DT and the first switching thin-film transistor ST-1 use an oxide semiconductor material as one of its active layers.

[0083] The control thin-film transistor DT has a first oxide semiconductor structure 474, a second gate electrode 478 that overlaps the first oxide semiconductor structure 474, as well as a second source electrode 479S and a second drain electrode 479D that are electrically connected to the first oxide semiconductor structure 474.

[0084] The oxide semiconductor can be made from an oxide of a metal, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or similar, or from a combination of a metal, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), or similar, and an oxide thereof. In particular, the oxide semiconductor can comprise zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc-tin oxide (IZTO), or similar.

[0085] Generally, a polycrystalline semiconductor structure is used as the active layer of a driver thin-film transistor, which is advantageous for high-speed operation. However, in the case of a driver thin-film transistor with a polycrystalline semiconductor structure, a power consumption problem can arise because leakage current is generated when the driver thin-film transistor is off. In particular, the problem of leakage current generation in an off-state of the driver thin-film transistor can be significant when the display device is driven at a low speed to display a still image, such as a document screen.For this purpose, in the first embodiment of the present disclosure, a control thin-film transistor is proposed which uses an oxide semiconductor structure as its active layer, which is advantageous in preventing the generation of leakage current.

[0086] However, if the thin-film transistor uses an oxide semiconductor structure as an active layer, the current fluctuation value relative to a voltage fluctuation value can be large due to the properties of an oxide semiconductor material, and thus failure can occur in a low-grayscale region where precise current control is required. Therefore, in accordance with the first embodiment of the present disclosure, a drive thin-film transistor is proposed in which a current fluctuation is relatively insensitive to a fluctuation of a voltage applied to a gate electrode.

[0087] A structure of the control thin-film transistor is described with reference to Fig. 4A to Fig. 4C described. Fig. 4B is an enlarged cross-sectional view, showing only the area shown in Fig. The control thin-film transistor DT shown in 4A is enlarged. Fig. 4C is a circuit diagram that represents a relationship between the parasitic capacitances generated in the drive thin-film transistor DT.

[0088] The driver thin-film transistor DT comprises the first oxide semiconductor structure 474, which is arranged on the upper buffer layer 445; the second gate insulating layer 446, which covers the first oxide semiconductor structure 474; the second gate electrode 478, which is formed on the second gate insulating layer 446 and overlaps the first oxide semiconductor structure 474; and the second source electrode 479S and the second drain electrode 479D, which are formed on the third intermediate insulating layer 447, which covers the second gate electrode 478. The second gate electrode 478, the second source electrode 479S, and the second drain electrode 479D can be arranged on the same layer.

[0089] The first oxide semiconductor structure 474, which is an active layer, has a second channel region 474a through which charges move, as well as a second source region 474b and a second drain region 474c, which are arranged adjacent to the second channel region 474a, provided that the second channel region 474a is inserted between them.

[0090] Here, a first light-shielding structure BSM-1 is formed beneath the first oxide semiconductor structure 474. The first light-shielding structure BSM-1 prevents externally incident light from irradiating the first oxide semiconductor structure 474, thus preventing the first oxide semiconductor structure 474, which is sensitive to external light, from malfunctioning.

[0091] In the first embodiment of the present disclosure, the first light shielding structure BSM-1 can be provided by having a semiconductor material layer.

[0092] Referring to Fig. 4A and Fig. 4B The first light shielding structure BSM-1 can have a structure in which a first layer BSM-1a, which is made up of a conductive material layer, such as a metal structure, and a second layer BSM-1b, which is made up of a semiconductor material layer, are arranged on top of each other.

[0093] The semiconductor material layer can be of various types, such as amorphous semiconductor material, polycrystalline semiconductor material, oxide semiconductor material, etc.

[0094] The semiconductor material layer can be a P-type semiconductor material layer doped with P-type impurity ions, such as boron ions.

[0095] The thin-film transistor, which uses an oxide semiconductor structure as its active layer, is an N-type thin-film transistor. Accordingly, when P-type impurity ions are implanted into the semiconductor material layer, the Fermi level of the semiconductor material layer is lowered. Furthermore, the Fermi level of the first oxide semiconductor structure 474, corresponding to the semiconductor material layer, is also lowered to achieve an equilibrium of Fermi levels in a thermal equilibrium state. Consequently, the threshold voltage Vth, required to turn on the driver thin-film transistor DT, can be increased.

[0096] The driver thin-film transistor DT, which has the first oxide semiconductor structure 474, requires a very high threshold voltage compared to other switching thin-film transistors in the pixel. Typically, switching thin-film transistors require a threshold voltage of approximately 0 V, whereas the driver thin-film transistor DT requires a threshold voltage of 1 V or more. Accordingly, the driver thin-film transistor DT, according to the embodiment of the present disclosure, has the advantage that an increase in the threshold voltage can be achieved because a semiconductor material layer doped with p-type impurity ions is arranged beneath the first oxide semiconductor structure 474.

[0097] Furthermore, the first layer BSM-1a of the first light-shielding structure BSM-1 can be a metal layer comprising titanium (Ti) capable of collecting hydrogen particles. For example, the metal layer can be a single titanium layer, a double layer of molybdenum (Mo) and titanium (Ti), or an alloy layer of molybdenum (Mo) and titanium (Ti). However, the embodiment of the present disclosure is not limited to the condition described above, and other metal layers comprising titanium (Ti) can also be used.

[0098] Titanium (Ti) can collect hydrogen particles that diffuse into the upper buffer layer 445, thereby preventing the hydrogen particles from reaching the first oxide semiconductor structure 474.

[0099] If the first light-shielding structure BSM-1 is composed of a plurality of layers, it is preferred that the first light-shielding structure BSM-1 has a stacked structure in which the semiconductor material layer is arranged on one top side. This is because the semiconductor layer must be exposed at the top during the execution of a process to allow p-type impurity ions to be introduced into the semiconductor material layer.

[0100] Preferably, the first light-shielding structure BSM-1 is formed vertically below the first oxide semiconductor structure 474, such that it overlaps the first oxide semiconductor structure 474. Furthermore, the first light-shielding structure BSM-1 can be formed such that it has a larger extent than the first oxide semiconductor structure 474, such that it completely overlaps the first oxide semiconductor structure 474.

[0101] The semiconductor material layer contained in the first light-shielding structure BSM-1 has a lower reflectivity than the metal layer contained in the first light-shielding structure BSM-1. Accordingly, it may be possible to reduce a phenomenon in which external light enters the first oxide semiconductor structure 474 after being reflected by the first light-shielding structure BSM-1.

[0102] Here, the second source electrode 479S of the driver thin-film transistor DT is electrically connected to the first light-shielding structure BSM-1. When the first light-shielding structure BSM-1 is electrically connected to the second source electrode 479S, the following additional effect can be achieved.

[0103] Since the second source region 474b and the second drain region 474c of the first oxide semiconductor structure 474 become conductive, a parasitic capacitance C will be present in the first oxide semiconductor structure 474 during on / off operation. act Furthermore, a parasitic capacitance C is generated between the second gate electrode 478 and the first oxide semiconductor structure 474. gi Furthermore, a parasitic capacitance C is generated between the first light shielding structure BSM-1, which is electrically connected to the second source electrode 479S, and the first oxide semiconductor structure 474. buf generated.

[0104] Since the first oxide semiconductor structure 474 and the first light shielding structure BSM-1 are electrically connected to each other by the second source electrode 479S, the parasitic capacitance C act and the parasitic capacity C buf connected in parallel, and the parasitic capacitance C actand the parasitic capacity C gi are connected in series. Furthermore, it is fulfilled if a gate voltage of V is applied. gat An effective voltage V is applied to the second gate electrode 478. eff , which is actually applied to the first oxide semiconductor structure 474, the following expression 1. ΔVeff=CgiCgi+Cbuf+Cact*ΔVgat

[0105] Thus, the effective voltage V applied to the second channel area 474a is eff inversely proportional to the parasitic capacity C buf , and in this way it may be possible to determine the effective voltage V applied to the first oxide semiconductor structure 474 eff by adjusting the parasitic capacitance C buf to adapt.

[0106] This means that if the first light-shielding structure BSM-1 is used to increase the parasitic capacitance C bufBy positioning the device close to the first oxide semiconductor structure 474, it may be possible to reduce the actual value of the current flowing through the first oxide semiconductor structure 474.

[0107] A reduction in the effective value of the current flowing through the first oxide semiconductor structure 474 means that an s-factor may be increased, and means that an actual control range of the driving thin-film transistor DT, which is controllable by the voltage Vgat applied to the second gate electrode 478, may be extended.

[0108] This means that if the second source electrode 479S of the control thin-film transistor DT is electrically connected to the first light-shielding structure BSM-1 and the first light-shielding structure BSM-1 is located close to the first oxide semiconductor structure 474, it may be possible to accurately control the organic light-emitting element even at low gray levels and thus solve a problem of a Mura defect that frequently occurs at low gray levels.

[0109] Accordingly, in the first embodiment of the present disclosure, the parasitic capacity C can buf , which is generated between the first oxide semiconductor structure 474 and the first light shielding structure BSM-1, shall be greater than the parasitic capacitance C gi , which is generated between the second gate electrode 478 and the first oxide semiconductor structure 474.

[0110] Here, "s-factor" means the inverse value of a current change to a gate voltage change during the on / off transition period of a thin-film transistor. This means that the s-factor can be the inverse value of the gradient of a curve in a property diagram of a drain current with respect to a gate voltage (VI curve diagram).

[0111] A small s-factor signifies a steep slope in the property graph of a drain current with respect to a gate voltage. Accordingly, if a thin-film transistor has a small s-factor, it can even be switched on with a low voltage, thus improving its switching characteristics. However, achieving sufficient grayscale representation is difficult because the thin-film transistor reaches a threshold voltage within a short time.

[0112] A large s-factor indicates a shallow slope in the drain current characteristic curve with respect to the gate voltage. Consequently, if a thin-film transistor has a large s-factor, its on / off response time may be degraded, and thus its switching characteristics may be impaired. However, adequate grayscale representation may still be possible because the thin-film transistor reaches a threshold voltage after a relatively long time.

[0113] In particular, the first light-shielding structure BMS-1 ​​can be arranged close to the first oxide semiconductor structure 474 and embedded in the upper buffer layer 445. Naturally, the first embodiment illustrates the use of multiple upper partial buffer layers.

[0114] This means that the upper buffer layer 445 can have a structure in which a first upper partial buffer layer 445a, a second upper partial buffer layer 445b, and a third upper partial buffer layer 445c are stacked sequentially. The first light-shielding structure BSM-1 can be formed above the first upper partial buffer layer 445a. Furthermore, the second upper partial buffer layer 445b completely covers the first light-shielding structure BSM-1. Additionally, the third upper partial buffer layer 445c is formed above the second upper partial buffer layer 445b. This configuration is an example of a configuration in which the first light-shielding structure BSM-1 is embedded in the upper buffer layer 445.

[0115] The first upper partial buffer layer 445a and the third upper partial buffer layer 445c can be made of silicon dioxide (SiO2).

[0116] If the first upper partial buffer layer 445a and the third upper partial buffer layer 445c are made of silicon dioxide (SiO2) that does not contain hydrogen particles, it is possible to prevent hydrogen particles from penetrating the oxide semiconductor structure during heat treatment. If hydrogen particles do penetrate the oxide semiconductor structure, the reliability of the thin-film transistor is compromised.

[0117] On the other hand, the second upper partial buffer layer 445b can be made of silicon nitride (SiN₂). x ) be set up, which has an excellent ability to trap hydrogen particles. The second upper partial buffer layer 445b can only be formed in an area where the first light-shielding structure BSM-1 is formed, such that the first light-shielding structure BSM-1 is completely encapsulated. This means that a silicon nitride layer (SiN) x) can be partially formed on the first upper partial buffer layer 445a to completely cover a top surface and a side surface of the first light-shielding structure BSM-1. In addition, the second upper partial buffer layer 445b can be formed on the entire surface of the first upper partial buffer layer 445a formed with the first light-shielding structure BSM-1.

[0118] Silicon nitride (SiN) xOxide has a superior ability to trap hydrogen particles compared to silicon dioxide (SiO2). When hydrogen particles penetrate an active layer made of an oxide semiconductor material, the resulting thin-film transistors can exhibit different threshold voltages or conductivities in their channels. This compromises the reliability of the thin-film transistors. Ensuring reliability is particularly important in the case of a driver thin-film transistor, as it directly contributes to the operation of the associated light-emitting element.

[0119] In the first embodiment of the present disclosure, it may therefore be possible to prevent an impairment of the reliability of the control thin-film transistor DT caused by hydrogen particles by forming the second upper partial buffer layer 445b partially or completely over the first upper partial buffer layer 445a, which covers the first light-shielding structure BSM-1.

[0120] If the second upper partial buffer layer 445b is partially deposited on the first upper partial buffer layer 445a, the following advantage results.

[0121] This means that, since the second upper partial buffer layer 445b is formed from a material different from that of the first upper partial buffer layer 445a, bubbles can form between the heterogeneous material layers if the second upper partial buffer layer 445b is deposited over the entire surface of the active area. To solve this problem, the second upper partial buffer layer 445b can be selectively formed only in the area where the first light-shielding structure BSM-1 is formed, in order to increase adhesion.

[0122] Preferably, the first light-shielding structure BSM-1 is formed vertically below the first oxide semiconductor structure 474 such that it overlaps the first oxide semiconductor structure 474. Furthermore, the first light-shielding structure BSM-1 can be formed to have a size larger than that of the first oxide semiconductor structure 474 in order to completely overlap it.

[0123] In the first embodiment of the present disclosure, the first light-shielding structure BSM-1 can have a semiconductor material layer doped with P-type ions, thereby increasing the threshold voltage of the driver thin-film transistor DT. Furthermore, the first light-shielding structure BSM-1 can be located close to the first oxide semiconductor structure 474, thereby increasing the parasitic capacitance generated between the first oxide semiconductor structure 474 and the first light-shielding structure BSM-1. In this case, the s-factor of the driver thin-film transistor DT is increased, and thus grayscale representation can be achieved even at low grayscale levels.

[0124] Here, the second gate electrode 478 of the control thin-film transistor DT is insulated by the third intermediate insulating layer 447. The second source electrode 479S and the second drain electrode 479D are formed on the third intermediate insulating layer 447.

[0125] Although the second source electrode 479S and the second drain electrode 479D in the first embodiment of the present disclosure with reference to Fig. If the second gate electrode 4A is shown to be arranged on the same layer and the second gate electrode 478 is shown to be formed on a layer different from that of the second source electrode 479S and the second drain electrode 479D, all of the second gate electrode 478, the second source electrode 479S and the second drain electrode 479D can be arranged on the same layer.

[0126] The second source electrode 479S and the second drain electrode 479D are connected to the second source region 474b and the second drain region 474c, respectively, via a third contact hole CH3 and a fourth contact hole CH4. Furthermore, the first light-shielding structure BSM-1 is connected to the second source electrode 479S via a fifth contact hole CH5.

[0127] The first switching thin-film transistor ST-1 has a second oxide semiconductor structure 432, a third gate electrode 433, a third source electrode 434S and a third drain electrode 434D.

[0128] The second oxide semiconductor structure 432 has a third channel region 432a as well as a third source region 432b and a third drain region 432c, which are arranged adjacent to the third channel region 432a, provided that the third channel region 432a is inserted between them.

[0129] The third gate electrode 433 is arranged above the second oxide semiconductor structure 432, provided that the second gate insulating layer 446 is inserted between them.

[0130] The third source electrode 434S and the third drain electrode 434D can be arranged on the same layer as the second source electrode 479S and the second drain electrode 479D. This means that the second source / drain electrodes 479S and 479D and the third source / drain electrodes 434S and 434D can be arranged on the third intermediate insulation layer 447.

[0131] Of course, the third source / drain electrodes 434S and 434D can be arranged on the same layer as the third gate electrode 433. This means that the third source / drain electrodes 434S and 434D can be formed on the second gate insulating layer 446 using the same material as the third gate electrode 433, simultaneously with the third gate electrode 433.

[0132] Furthermore, a second light shielding structure BSM-2 can be arranged under the second oxide semiconductor structure 432.

[0133] The second light-shielding structure, BSM-2, can have the same configuration as the first light-shielding structure, BSM-1. This means that the second light-shielding structure, BSM-2, can have a structure in which a first layer, BSM-2a, made of a metallic material, and a second layer, BSM-2b, made of a semiconductor material, are stacked. Alternatively, the second light-shielding structure, BSM-2, can have a single-layer structure made of a semiconductor material layer doped with foreign atoms.

[0134] P-type impurity ions are introduced into the second layer BSM-2b of the second light shielding structure BSM-2.

[0135] The second light shielding structure BSM-2 is arranged below the second oxide semiconductor structure 432 and overlaps the second oxide semiconductor structure 432 to protect the second oxide semiconductor structure 432 from externally incident light.

[0136] The second light shielding structure BSM-2 can be formed together with the first gate electrode 416 above the first gate insulating layer 442.

[0137] The third gate electrode 433 and the second light shielding structure BSM-2 can be electrically connected to each other, thereby establishing a double gate.

[0138] Since the second light-shielding structure BSM-2 has a semiconductor material layer doped with p-type impurity ions, it can raise the threshold voltage of the first switching thin-film transistor ST-1, which has the oxide semiconductor structure. In other words, because the third gate electrode 433 becomes conductive due to the introduction of p-type impurity ions, its Fermi level is lowered. Furthermore, the Fermi level of the second oxide semiconductor structure 432, corresponding to the third gate electrode 433, is also lowered. Consequently, the threshold voltage of the first switching thin-film transistor ST-1 is increased. Specifically, with regard to Fig. 3. If the first switching thin-film transistor ST-1 is a sampling transistor connected to a gate node of the drive thin-film transistor DT, a significant effect will be shown. The sampling transistor serves to provide a data voltage at one electrode of the storage capacitor during a sampling period.

[0139] The sampling transistor is known as a very sensitive transistor in which one channel is open even at a low voltage. In the first embodiment of the present disclosure, since the second light-shielding structure BSM-2, which has the semiconductor material layer doped with P-type impurity ions, is arranged under the second oxide semiconductor structure 432, it is possible to increase the threshold voltage of the first switching thin-film transistor ST-1, and thus there is an advantage in that the freedom of an internal compensation circuit configuration can be improved.

[0140] It is preferred that each of the first light-shielding structure BSM-1 and the second light-shielding structure BSM-2 is composed of a plurality of layers, each having a metal material layer and a semiconductor material layer, such that the semiconductor material layer is arranged above the metal material layer. This is because, to prevent the introduction of impurities into the semiconductor material layer, the semiconductor material layer should be deposited above the metal material layer in such a way that the semiconductor material layer is exposed at the top.

[0141] In this context, referring to Fig. 4A, the subpixel has a storage capacitor Cst.

[0142] The storage capacitor Cst stores a data voltage applied via a data line for a predetermined period and then supplies the stored data voltage to the organic light-emitting element.

[0143] The storage capacitor Cst has two corresponding electrodes and a dielectric arranged between the two electrodes. The storage capacitor Cst has a first electrode 450A, which is arranged on the same layer as the first gate electrode 416 and is made of the same material as the first gate electrode 416, and a second electrode 450B, which is opposite the first electrode 450A and overlaps the first electrode 450A.

[0144] The first intermediate insulation layer 443 can be inserted between the first electrode 450A and the second electrode 450B of the storage capacitor Cst.

[0145] The second electrode 450B of the storage capacitor Cst can be electrically connected to the second source electrode 479S via an eighth contact hole CH8.

[0146] Furthermore, there may be an advantage in that the number of mask processes is reduced because the first electrode 450A of the storage capacitor Cst is formed on the same layer as the first gate electrode 416 and the second light shielding structure BSM-2.

[0147] In this context, with reference to Fig. 4A, a first planarization layer PLN1 is formed over the substrate 410, on which the driver thin-film transistor DT and the first switching thin-film transistor ST-1 are arranged. Although the first planarization layer PLN1 can be formed from an organic material, such as photoacrylic, it can also be formed from a plurality of layers consisting of an inorganic layer and an organic layer. A connecting electrode 455 electrically connects an anode 456, which is part of a light-emitting device part 460, and the driver thin-film transistor DT via a ninth contact hole CH9 formed in the first planarization layer PLN1.

[0148] Furthermore, a conductive layer used to form the connecting electrode 455 can establish some of the various connecting leads that are arranged in the bending area BA.

[0149] A second planarization layer PLN2 can be formed above the connecting electrode 455. Although the second planarization layer PLN2 can be formed from an organic material, such as photoacrylic, it can also be formed from a plurality of layers consisting of an inorganic layer and an organic layer.

[0150] The anode 456 is formed on the second planarization layer PLN2. The anode 456 is electrically connected to the connecting electrode 455 via a tenth contact hole CH10, which is formed in the second planarization layer PLN2.

[0151] The anode 456 can take the form of a single layer or multiple layers made of a metal, such as Ca, Ba, Mg, Al, Ag, etc., or an alloy thereof. The anode 456 is connected to the second drain electrode 479D of the control thin-film transistor DT, and an external video signal is applied to it in this way.

[0152] In addition to the anode 456, an anode connection electrode 457, which electrically connects a common voltage line VSS and a cathode 463, can also be provided in the non-active area NA.

[0153] A dam layer 461 is formed above the second planarization layer PLN2. The dam layer 461 acts as a barrier and can subdivide subpixels, thus preventing light of certain colors emitted by adjacent subpixels from being emitted in a mixed state.

[0154] An organic light-emitting layer 462 is formed on a surface of the anode 456 and a section of an inclined surface of the dam layer 461. The organic light-emitting layer 462 can be an R-organic light-emitting layer configured to emit red light, a G-organic light-emitting layer configured to emit green light, or a B-organic light-emitting layer configured to emit blue light, formed at each subpixel. Furthermore, the organic light-emitting layer 462 can be a W-organic light-emitting layer configured to emit white light.

[0155] The organic light-emitting layer 462 can include not only a light-emitting layer, but also an electron injection layer and a hole injection layer, which are arranged in an appropriate manner to inject electrons and holes into the light-emitting layer, an electron transport layer and a hole transport layer, which are arranged in an appropriate manner to transport injected electrons and holes to an organic layer, etc.

[0156] The cathode 463 is formed above the organic light-emitting layer 462. The cathode 463 can be made of a translucent, conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a thin metal that allows transmission of visible light, but is not limited to this.

[0157] An encapsulation layer part 470 is formed over the cathode 463. The encapsulation layer part 470 can be formed from a single layer consisting of an inorganic layer, a double layer consisting of an inorganic layer / organic layer, or a triple layer consisting of an inorganic layer / organic layer / inorganic layer. The inorganic layer can be made of an inorganic material such as SiN x The organic layer may be composed of, but is not limited to, an organic material such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, etc. Furthermore, the organic layer may be composed of, but is not limited to, an organic material such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, etc.

[0158] In Fig. 4A is an embodiment of the encapsulation layer part 470 such that it is arranged from a triple layer of inorganic layer 471 / organic layer 472 / inorganic layer 473.

[0159] A cover glass (not shown) can be arranged over the encapsulation layer part 470 and can be bonded to the encapsulation layer part 470 by an adhesive layer (not shown). Although any material can be used as the adhesive layer, provided that the material has excellent adhesive strength and is also excellent with respect to heat and water resistance, a heat-curing resin, such as an epoxy-based compound, an acrylate-based compound, or an acrylic-based rubber, can be used in the present disclosure. Alternatively, a photocurable resin can also be used as the adhesive. In this case, the adhesive layer is cured by irradiation of the adhesive layer with light, such as ultraviolet light.

[0160] The adhesive layer can not only serve to join the substrate 410 and the cover glass (not shown), but also to act as an encapsulation to prevent moisture from entering the interior of the display device, which may be an organic electroluminescent display device.

[0161] The cover glass (not shown) can be an encapsulation attachment for the organic electroluminescent display device and can use a protective layer, such as a polystyrene (PS) layer, a polyethylene (PE) layer, a polyethylene naphthalate (PEN) layer, a polyimide (PI) layer or similar, and can use glass. - Second embodiment -

[0162] The following refers to Fig. 5 A second embodiment of the present disclosure is described. In the second embodiment, configurations of thin-film transistors arranged in an active region AA are described.

[0163] Referring to Fig. In the second embodiment, a control thin-film transistor DT and two switching thin-film transistors ST-1 and ST-2 are disclosed.

[0164] The control thin-film transistor DT and the first switching thin-film transistor ST-1 can have the same configurations as those of the first embodiment, which is based on Fig. 4A refers to.

[0165] In the second embodiment, the first switching thin-film transistor ST-1 and the second switching thin-film transistor ST-2 have a second light-shielding structure BSM-2 and a third light-shielding structure BSM-3, respectively. The second light-shielding structure BSM-2 and the third light-shielding structure BSM-3 can be arranged on the same insulating layer. Furthermore, similar to the first switching thin-film transistor ST-1 in the first embodiment, the second light-shielding structure BSM-2 can have a structure in which a first layer BSM-2a, composed of a metallic material, and a second layer BSM-2b, composed of a semiconductor material doped with positive p-type impurity ions, are stacked. Alternatively, the third light-shielding structure BSM-3 can consist solely of a layer of metallic material.

[0166] The first switching thin-film transistor ST-1 can be a sampling transistor that sets up an internal circuit, and the second switching thin-film transistor ST-2 can be a switching thin-film transistor that is different from the sampling transistor. For example, the second switching thin-film transistor ST-2 can be an initialization transistor.

[0167] The control thin-film transistor DT and the first switching thin-film transistor ST-1 in the second embodiment can have the same configurations as those of the first embodiment, and therefore no detailed description of them is given.

[0168] The second switching thin-film transistor ST-2 can also have the same configuration as the first switching thin-film transistor ST-1, except for the third light-shielding structure BSM-3.

[0169] This means that the second switching thin-film transistor ST-2 has a third oxide semiconductor structure 482 arranged on an upper buffer layer 445, a fourth gate electrode 488 arranged to overlap the third oxide semiconductor structure 482, and a fourth source electrode 484S and a fourth drain electrode 484D electrically connected to the third oxide semiconductor structure 482. Furthermore, the second switching thin-film transistor ST-2 has a third light-shielding structure BSM-3 arranged beneath the third oxide semiconductor structure 482.

[0170] The third oxide semiconductor structure 482 has a fourth channel region 482a and conductive regions, that is, a fourth source region 482b and a fourth drain region 482c.

[0171] The fourth source electrode 484S and the fourth drain electrode 484D are connected to the fourth source area 482b and the fourth drain area 482c via an eleventh contact hole CH11 and a twelfth contact hole CH12, respectively.

[0172] All of the second source / drain electrodes 479S and 479D, third source / drain electrodes 434S and 434D and fourth source / drain electrodes 484S and 484D can be arranged on the same layer and can be formed simultaneously using the same material through a masking process.

[0173] All of the second gate electrode 478, the third gate electrode 433, and the fourth gate electrode 488 can be formed using the same material on the same insulating layer. In this case, the formation of the gate electrodes can be achieved through a masking process.

[0174] The third light shielding structure BSM-3 can be a light shielding structure that is set up only by means of a metal structure, unlike the second light shielding structure BSM-2.

[0175] This means that the first switching thin-film transistor ST-1 shows an increase in the threshold voltage because the first switching thin-film transistor ST-1 has the second light-shielding structure BSM-2, which has the semiconductor material layer, whereas the second switching thin-film transistor ST-2 does not show any change in the threshold voltage caused by the third light-shielding structure BSM-3, because the third light-shielding structure BSM-3 is only provided by a metal material layer.

[0176] Accordingly, among the switching thin-film transistors that establish the internal compensation circuit of the pixel, the thin-film transistor that requires an increase in the threshold voltage can have a light-shielding structure that includes a semiconductor material layer, as in the first switching thin-film transistor ST-1, and the thin-film transistor that does not require a change in the threshold voltage can have a light-shielding structure that is established only by a metal layer, as in the second switching thin-film transistor ST-2.

[0177] For example, the first switching thin-film transistor ST-1 can be a sampling transistor, and the second switching thin-film transistor ST-2 can be an initialization transistor.

[0178] The second light-shielding structure BSM-2 and the third light-shielding structure BSM-3 can be formed simultaneously on a first gate-insulating layer 442. Accordingly, a first gate electrode 416, a first electrode 450A of a storage capacitor, the second light-shielding structure BSM-2, and the third light-shielding structure BSM-3 can be formed simultaneously using a mask.

[0179] Since the second light-shielding structure BSM-2 comprises the first layer BSM-2a and the second layer BSM-2b, which is made up of the semiconductor material layer, the masking process can be a process that uses a halftone mask. The halftone masking process can be carried out using a known method, and therefore no detailed description of it is given. - Third embodiment -

[0180] The following refers to Fig. 6 A third embodiment of the present disclosure is described. The third embodiment is characterized in that a second light-shielding structure BSM-2 has a semiconductor material layer doped with P-type impurity ions and is arranged close to a second oxide semiconductor structure 432 in order to increase a threshold voltage of a first switching thin-film transistor ST-1.

[0181] With reference to Fig. 6. The configurations of a control thin-film transistor GT and a storage capacitor Cst can be identical to those of the first embodiment, which is based on Fig. 4A refers to its function. Therefore, the following description does not provide a detailed description of the gate-driven thin-film transistor GT and the storage capacitor Cst.

[0182] A first switching thin-film transistor ST-1 has a second light-shielding structure BSM-2 arranged on a first intermediate insulating layer 443, a second oxide semiconductor structure 432 arranged above the second light-shielding structure BSM-2 and overlapping the second light-shielding structure BSM-2, a third gate electrode 433 arranged above the second oxide semiconductor structure 432 and overlapping the second oxide semiconductor structure 432, as well as a third source electrode 434S and a third drain electrode 434D, which are electrically connected to the second oxide semiconductor structure 432.

[0183] An upper buffer layer 445 is arranged between the second oxide semiconductor structure 432 and the second light shielding structure BSM-2.

[0184] The upper buffer layer 445 is deposited on an upper surface of the first intermediate insulating layer 443, and thus the first intermediate insulating layer 443 can function as a first upper partial buffer layer 445a. Accordingly, the upper buffer layer 445 can only be configured by a second upper partial buffer layer 445b and a third upper partial buffer layer 445c. However, the configuration of the upper buffer layer 445 is not limited to the one described in Fig. The configuration shown is limited to 6.

[0185] The third embodiment proposes a configuration for increasing the threshold voltage of the first switching thin-film transistor ST-1 by reducing the thickness of an inorganic insulating layer placed between the second light-shielding structure BSM-2 and the second oxide semiconductor structure 432.

[0186] If the distance between the second light-shielding structure BSM-2 and the second oxide semiconductor structure 432 is reduced, the parasitic capacitance generated between the two layers increases, and thus the threshold voltage of the first switching thin-film transistor ST-1 may be increased. Furthermore, since the second light-shielding structure BSM-2 has a semiconductor material layer doped with positive p-type ions, the threshold voltage may be increased even further.

[0187] Accordingly, if the first switching thin-film transistor ST-1 disclosed in the third embodiment is used as a sampling transistor, it may be possible to increase the threshold voltage of the sampling transistor in a simple manner.

[0188] Furthermore, the second light shielding structure BSM-2 can be arranged on the same layer as a first light shielding structure BSM-1 and have the same stacking structure as the first light shielding structure BSM-1, unlike the first embodiment, and in this way the number of mask processes can be reduced.

[0189] The first light-shielding structure BSM-1 and the second light-shielding structure BSM-2, together with a second electrode 450B of a storage capacitor, can be arranged on the first intermediate insulating layer 443. Accordingly, the first light-shielding structure BSM-1, the second light-shielding structure BSM-2, and the second electrode 450B of the storage capacitor can be formed simultaneously using a mask. Furthermore, the first light-shielding structure BSM-1 and the second light-shielding structure BSM-2 can be formed simultaneously in a masking process using a halftone mask, provided that a metal material layer and a semiconductor material layer are deposited sequentially. Consequently, the number of masking processes can be reduced.

[0190] In the third embodiment, the second light shielding structure BSM-2 can be electrically connected to the third gate electrode 433, thereby forming a double gate.

[0191] In this case, a control thin-film transistor DT can have a configuration identical to the configuration disclosed in the first embodiment, except that the first light-shielding structure BSM-1 is arranged on the first intermediate insulation layer 443 and the upper buffer layer 445 has a stacked structure consisting of the second upper partial buffer layer 445b and the third upper partial buffer layer 445c.

[0192] In short, the third embodiment proposes a configuration in which the first light-shielding structure BSM-1 and the second light-shielding structure BSM-2 are arranged on the same layer, thereby reducing the number of manufacturing processes and increasing the threshold voltage of the first switching thin-film transistor ST-1.

[0193] As described above, each pixel of the display device, according to each embodiment of the present disclosure, comprises a driver thin-film transistor and a switching thin-film transistor, thereby blocking leakage current in an off state. Accordingly, a reduction in power consumption can be achieved. Furthermore, the driver thin-film transistor can have a structure capable of increasing its s-factor, and thus a thin-film transistor matrix substrate can be provided that is capable of achieving free grayscale representation at low gray levels. Additionally, a thin-film transistor can be provided that is capable of increasing the threshold voltage of the driver thin-film transistor in the pixel to a predetermined target value or higher.Furthermore, a plurality of switching thin-film transistors arranged in the pixel can each have different threshold voltages, and thus each of the switching thin-film transistors can have suitable properties that are appropriate for a function of it.

[0194] The effects of this disclosure are not limited to those described above. Further effects not described in this disclosure can be readily understood by a person skilled in the art from the attached claims.

Claims

[1] A thin-film transistor matrix substrate comprising: a substrate (410) having an active region (AA) and a non-active region (NA) arranged around the active region (AA); and a first thin-film transistor (DT) arranged on the substrate (410), the first thin-film transistor (DT) exhibits: an upper buffer layer (445) arranged on the substrate (410) and comprising at least one inorganic insulating layer; a first oxide semiconductor structure (474) arranged on the upper buffer layer (445); a first gate electrode (478) arranged above the first oxide semiconductor structure (474) and overlapping the first oxide semiconductor structure (474), and a first source electrode (479S) and a first drain electrode (479D) electrically connected to the first oxide semiconductor structure (474); a first light shielding structure (BSM-1) arranged below the first oxide semiconductor structure (474) and overlapping the first oxide semiconductor structure (474), wherein the first light shielding structure (BSM-1) has a semiconductor material layer; a first insulating layer (446) arranged between the first oxide semiconductor structure (474) and the first gate electrode (478); and a second insulating layer (445b, 445c) that is positioned between the first oxide semiconductor structure (474) and the first light shielding structure (BSM-1) and is part of the upper buffer layer (445), where a first parasitic capacity (C buf ), which is generated between the first light shielding structure (BSM-1) and the first oxide semiconductor structure (474), is larger than a second parasitic capacitance (C gi ), which is generated between the first gate electrode (478) and the first oxide semiconductor structure (474), and where a permittivity of the second insulating layer (445, 445a, 445b) is greater than a permittivity of the first insulating layer (446). [2] The thin-film transistor matrix substrate according to claim 1, further comprising: a second thin-film transistor (ST1) located on the upper buffer layer (445), the second thin-film transistor (ST1) has: a second oxide semiconductor structure (432) arranged on the substrate (410); a second gate electrode (433) arranged above and overlapping the second oxide semiconductor structure (432), and a second source electrode (434S) and a second drain electrode (434D) electrically connected to the second oxide semiconductor structure (432); and a second light shielding structure (BSM-2) arranged below the second oxide semiconductor structure (432) and overlapping the second oxide semiconductor structure (432), wherein the second light shielding structure (BSM-2) has a semiconductor material layer. [3] The thin-film transistor matrix substrate according to claim 2, further comprising: a third thin-film transistor (ST2) which is arranged on the substrate (410), the third thin-film transistor (ST2) features: a third oxide semiconductor structure (482) arranged on the upper buffer layer (445); a third gate electrode (488) arranged above and overlapping the third oxide semiconductor structure (482), and a third source electrode (484S) and a third drain electrode (484D) electrically connected to the third oxide semiconductor structure (482); and a third light shielding structure (BSM-3) which is positioned below and overlaps the third oxide semiconductor structure (482). [4] The thin-film transistor matrix substrate according to any one of claims 1 to 3, further comprising: a fourth thin-film transistor (GT) arranged on the substrate (410), the fourth thin-film transistor (GT) features: a lower buffer layer (411) arranged on the substrate (410) and comprising at least one insulating layer; a polycrystalline semiconductor structure (414) arranged on the lower buffer layer (411); and a fourth gate electrode (416) which is arranged above the polycrystalline semiconductor structure (414) and overlaps the polycrystalline semiconductor structure (414), and a fourth source electrode (417S) and a fourth drain electrode (417D) which are electrically connected to the polycrystalline semiconductor structure (414). [5] The thin-film transistor matrix substrate according to any one of claims 1 to 4, wherein the thickness of the first insulating layer (446) is greater than the thickness of the second insulating layer (445b, 445c). [6] The thin-film transistor matrix substrate according to claim 3, wherein: each is formed from an N-type semiconductor material consisting of the first oxide semiconductor structure (474), the second oxide semiconductor structure (432), and the third oxide semiconductor structure (482); and The semiconductor material layer of the first light shielding structure (BSM-1) and the semiconductor material layer of the second light shielding structure (BSM-2) are made from a P-type semiconductor material. [7] The thin-film transistor matrix substrate according to claim 3, wherein: has at least one of the first light shielding structure (BSM-1), the second light shielding structure (BSM-2) or the third light shielding structure (BSM-3): a metal structure; and a semiconductor material layer that is layered onto the metal structure. [8] The thin-film transistor matrix substrate according to claim 7, wherein the second light-shielding structure (BSM-2) has a structure in which the metal structure and the semiconductor material layer are stacked, and the third light-shielding structure (BSM-3) is provided only by the metal structure. [9] The thin-film transistor matrix substrate according to any one of claims 3 and 4 to 8 insofar as they refer back to claim 3, further comprising: at least one intermediate insulating layer (443, 444, 445a) arranged between the first light shielding structure (BSM-1) and the second light shielding structure (BSM-2), wherein the second light shielding structure (BSM-2) and the third light shielding structure (BSM-3) are arranged on the same layer. [10] The thin-film transistor matrix substrate according to claim 2, wherein the first light-shielding structure (BSM-1) and the second light-shielding structure (BSM-2) are arranged on the same layer. [11] The thin-film transistor matrix substrate according to claim 3, wherein the first thin-film transistor (DT) is a driver thin-film transistor (DT) configured to drive a pixel, and each of the second thin-film transistor (ST1) and the third thin-film transistor (ST2) is a switching thin-film transistor. [12] The thin-film transistor matrix substrate according to any one of claims 1 to 11, wherein the first light-shielding structure (BSM-1) is embedded in the upper buffer layer (445). [13] The thin-film transistor matrix substrate according to claim 12, wherein the upper buffer layer (445) comprises a plurality of upper partial buffer layers (445a, 445b, 445c) and the upper partial buffer layers (445a, 445b, 445c) are arranged at an upper and a lower end of the first light-shielding structure (BSM-1), respectively. [14] The thin-film transistor matrix substrate according to claim 8, wherein the second thin-film transistor (ST1) is a switching thin-film transistor electrically connected to the first gate electrode (478) of the first thin-film transistor (DT). [15] The thin-film transistor matrix substrate according to claim 4, wherein the fourth thin-film transistor (GT) is arranged in at least one of the non-active region (NA) or the active region (AA) and the first thin-film transistor (DT) is arranged at a pixel in the active region (AA). [16] The thin-film transistor matrix substrate according to any one of claims 1 to 15, wherein the first light shielding structure (BSM-1) is electrically connected to one of the first source electrode (479S) and the first drain electrode (479D). [17] The thin-film transistor matrix substrate according to claim 7, wherein the reflectivity of the semiconductor material layer is lower than the reflectivity of the metal structure. [18] The thin-film transistor matrix substrate according to claim 4, wherein the polycrystalline semiconductor structure (414) and the semiconductor material layer are doped with P-type impurity ions. [19] A thin-film transistor matrix substrate comprising: a substrate (410) having an active region (AA) and a non-active region (NA) arranged around the active region (AA); and a switching thin-film transistor (ST1, ST2) arranged on the substrate (410), the switching thin-film transistor (ST1, ST2) has: a buffer layer (445) arranged on the substrate (410); an oxide semiconductor structure (432, 482) arranged on the buffer layer (445); a gate electrode (433, 488) which is arranged above the oxide semiconductor structure (432, 482) and overlaps the oxide semiconductor structure (432, 482); a source electrode (434S, 484S) and a drain electrode (434D, 484D) that are electrically connected to the oxide semiconductor structure (432, 482); a light shielding structure (BSM-2, BSM3) arranged beneath the oxide semiconductor structure (432, 482) and comprising a semiconductor material layer; a first insulating layer (446) arranged between the oxide semiconductor structure (432, 482) and the gate electrode (433, 488); and a second insulating layer (445b, 445c) that is arranged between the oxide semiconductor structure (432, 482) and the light shielding structure (BSM-2, BSM-3) and is part of the buffer layer (445), where a first parasitic capacity (C buf), which is generated between the light shielding structure (BSM-2, BSM-3) and the oxide semiconductor structure (432, 482), is larger than a second parasitic capacitance (C gi ), which is generated between the gate electrode (433, 488) and the oxide semiconductor structure (432, 482), and where a permittivity of the second insulating layer (445, 445a, 445b) is greater than a permittivity of the first insulating layer (446). [20] A display device comprising: the thin-film transistor matrix substrate according to any one of claims 1 to 19; and a light-emitting device part (460) comprising an anode (456) arranged on the substrate (410), a cathode (463) opposite the anode (456), and a light-emitting layer (462) arranged between the anode (456) and the cathode (463).

Images