Test signal circuit for testing a high-frequency receiver circuit, a semiconductor chip and a system comprising the test signal circuit

Abstract

Test signal circuit (TSC) for testing a radio frequency receiver circuit (RX), comprising: a test signal generator (TSG) configured to generate a baseband test signal (BTS), a modulator (QAM, MI, MQ) configured to modulate a local oscillator signal with the baseband test signal (BTS) to generate a test signal (TS), a first transmission element (TE1) coupled between the modulator and an input of an impedance transformation element (MN), a second transmission element (TE2) coupled to an output of the impedance transformation element (MN), wherein the impedance transformation element (MN) is configured to reduce a first impedance level of the first transmission element (TE1) to a second impedance level of a second transmission element (TE2), at least one voltage level detector (VLD, IVLD, QVLD) coupled to the first transmission element (TE1), wherein the at least one voltage level detector (VLD, IVLD, QVLD) is configured to detect a voltage level of the test signal (TS).

Description

AREA

[0001] The present disclosure relates to a test signal circuit, a semiconductor chip and a system comprising the test signal circuit. BACKGROUND

[0002] Radar systems (radar: radio detection and ranging) consist of a transmitter and a receiver. The transmitter emits radio waves that strike an object and are reflected. The reflected radio waves are received by the receiver. This makes it possible to determine the distance, speed, and / or direction of the object relative to the radar system. Radar systems operate in the microwave GHz range and have a wide range of applications, including aviation, weather, marine, etc. Radar systems are increasingly used in the automotive sector for, for example, autonomous driving and / or other advanced driver assistance systems such as adaptive cruise control, lane change assistance, blind spot detection, and the like. Automotive radars can be used to detect the speed, distance, and / or direction of objects near the car.For example, automotive radars can use a frequency band around 24 GHz for short-range radar or a frequency band around 77 GHz, e.g. from 76 GHz to 81 GHz, for long-range radar.

[0003] A radio transceiver is an electronic device that combines a radio transmitter and a radio receiver. Its radio frequency (RF) circuitry is sometimes referred to as an RF front end. Radar transceivers, for example, can be implemented on a single chip with highly integrated RF circuitry that combines RF front-end functions into a single package. An example of such a highly integrated design is a monolithic microwave integrated circuit (MMIC), where radar transceiver functions, including the transceiver's RF circuitry, can be implemented. Radar transceivers may include test signal circuitry that generates test signals applied to the radio receiver to test receiver characteristics, such as its gain.

[0004] Document DE 10 2017 129 330 B3 discloses a radio frequency (RF) receiving device having an antenna input of an RF signal source and a circuit for generating an RF test signal. A coupler is connected to the antenna input and an output of the circuit for generating an RF test signal. A first modulator (111a) is configured to generate a first RF signal by modulating the RF oscillator signal with a first signal; and a second modulator is configured to generate a second RF signal by modulating the RF oscillator signal with a second signal, wherein the first signal (s1(t)) and the second signal are single-tone signals that differ in their frequency and / or phase.

[0005] Document DE 10 2017 127 416 A1 describes a radar device comprising a test signal generator with a digital harmonic oscillator that generates a digital oscillator signal with a first spectral component, and a first digital-to-analog converter that generates an analog oscillator signal based on the digital oscillator signal. The radar device further comprises at least one radar channel that receives the analog oscillator signal during one or more self-tests.

[0006] Document US 2021 / 0 190 910 A1 discloses a radio-frequency circuit comprising an input terminal configured to receive a receive signal from an antenna; a receive signal path coupled to the input terminal and including a mixer and an analog-to-digital converter (ADC), the ADC generating a digital signal that is an input signal to the ADC. A test signal generator is provided that is configured to generate a test signal that is fed into the receive signal path while the receive signal propagates along the receive signal path. Further, a digital signal processor is provided that is configured to receive the digital signal from a digital portion of the receive signal path and to analyze a frequency response of the digital signal.A subtractor connected to the digital portion of the receive signal path is configured to remove test frequency components from the digital signal resulting from injection of the test signal into the receive signal path.

[0007] It would be desirable to provide a test signal circuit for testing a radio frequency receiver circuit that allows for chip-area-efficient implementation. This can be achieved by a test signal circuit according to claim 1, a semiconductor chip according to claim 10, and a system according to claim 11. SUMMARY

[0008] According to one aspect of the disclosure, a test signal circuit for testing a radio frequency receiver circuit comprises: a test signal generator configured to generate a baseband test signal, a modulator configured to modulate a local oscillator signal with the baseband test signal to generate a test signal, a first transmission element coupled between the modulator and an input of an impedance transformation element, a second transmission element coupled to an output of the impedance transformation element, wherein the impedance transformation element is configured to reduce a first impedance level of the first transmission element to a second impedance level of the second transmission element, at least one voltage level detector coupled to the first transmission element, wherein the at least one voltage level detector is configured to detect a voltage level of the test signal.

[0009] According to another aspect of the disclosure, a semiconductor chip includes the test signal circuit and the radio frequency receiver circuit.

[0010] According to another aspect of the disclosure, a system comprises a test signal circuit and a control circuit, the control circuit comprising: a first interface coupled to the radio frequency receiver circuit for receiving a signal indicating that the test signal is being processed by the radio frequency receiver circuit, a processor configured to generate a control signal in response to the signal, a second interface coupled to the test signal generator for transmitting the control signal to the test signal generator.

[0011] The test signal circuit, the semiconductor chip, and the system comprising the test signal circuit enable a highly efficient test signal circuit in terms of semiconductor chip area. Furthermore, energy savings can be realized.

[0012] A voltage level of the test signal can be used to monitor the characteristics of the receiver circuit to which the test signal can be applied. According to one aspect of the invention, a voltage level detector is used to detect a voltage level of the generated test signal. The power level of the test signal can be derived from the voltage level of the test signal. The voltage level detector can be capacitively coupled to a high-impedance node, resulting in a high voltage swing that enables the use of a sensitive region of the transfer function of a voltage level detector. The test signal circuit according to this application offers a very economical use of the semiconductor chip area.

[0013] The first and second transmission elements may be a transmission line, e.g., a transmission strip on the semiconductor chip.

[0014] Compared to conventional power level detectors that couple a portion of the power from the main signal line using low-impedance lines (such as a 50-ohm directional coupler), a voltage level detector capacitively coupled to a high-impedance RF node produces a higher output detection voltage and subsequently enables sensitive power detection even at power levels that are significantly too low for 50-ohm-based power level detection.

[0015] A test signal circuit according to this application is used to generate a test signal that is fed to the radio-frequency receiver circuit to check one or more properties, also called parameters, of this radio-frequency receiver circuit. Therefore, it is important to know the test signal fed to the radio-frequency receiver circuit. The test signal can then later be compared with the signal generated by the radio-frequency receiver circuit in response to the test signal. The test signal seen by the radio-frequency receiver circuit is like a received signal. By comparing the test signal with the signal output by the receiver circuit, it is possible to determine parameters such as the gain of this radio-frequency receiver circuit, for example.

[0016] The test signal circuit is typically implemented on a single semiconductor chip, but it is also possible to use several interconnected semiconductor chips or discrete electrical circuit elements to implement the test signal circuit. It is possible for at least part of the functionality of the test signal circuit to be implemented as a software program.

[0017] The test signal circuit generates the test signal at frequencies used to receive radio signals. The radio-frequency receiver circuit could also be implemented on a semiconductor chip. It could be the same semiconductor chip used to implement the test signal circuit. For example, the radio-frequency receiver circuit is configured to receive radar signals.

[0018] The test signal circuit includes a test signal generator configured to generate a baseband test signal. This test signal generator is supplied, for example, with a clock signal and extracts the baseband test signal from a memory to form the test signal. The baseband test signal could also be supplied by another component, for example, any other component connected to the test signal generator. The test signal is generated using a modulator configured to modulate a local oscillator signal with the baseband test signal to generate the test signal. The local oscillator is typically not part of the test signal circuit but a separate element. The local oscillator signal is used to generate the test signal using the baseband test signal. This means that the modulator transforms the baseband test signal into a high-frequency range.A first transmission element is provided between this modulator and an input of an impedance transformation element. This first transmission element could be a transmission line or any other electrical network matched to the impedance of the impedance transformation element. A second transmission element is coupled to an output of the impedance transformation element. The second transmission element could also be a transmission line or any other resistance network. The second transmission element is configured to match the input resistance of the receiver circuit, which may be, for example, 50 ohms.

[0019] The impedance transformation element is configured to transform the impedance of the first transmission line into the impedance of the second transmission line to match the impedance on both sides.

[0020] At least one voltage level detector, coupled to this first transmission element, is configured to detect a voltage level of the test signal. Conventional technologies could be implemented for this voltage level detector to measure the voltage level of the test signal. The voltage level detector is capacitively coupled to the first transmission element, so only a voltage swing is detected and no power transfer is required. Impedance transformation is not required in this case.

[0021] The semiconductor chip could be made of any other suitable semiconductor such as silicon, silicon carbide or gallium nitride or any other compound semiconductor.

[0022] In one embodiment, the test signal circuit includes first and second voltage level detectors. The modulator is configured as a quadrature amplitude modulator that generates the test signal as two components: a first component on an I path and a second component on a Q path. The first voltage level detector is connected to the I path, and the second voltage level detector is connected to the Q path. The outputs of I VLD and Q VLD can be combined in an analog manner (by connecting the two outputs together) or after an ADC. Both implementations provide suppression of amplitude modulation (AM) ripples at approximately the same level.

[0023] The impedance transformation element includes a power combiner that combines the first and second components. The quadrature amplitude modulator transmits two analog message signals or two digital bit streams using amplitude shift keying (ASK) or amplitude modulation (AM) schemes. This is achieved by modulating the amplitudes of two carrier waves that have the same frequency and are 90° out of phase with each other (a condition known as orthogonality or quadrature).

[0024] A power combiner is a passive device used in high-frequency circuit design. The power combiner combines the power of the I-path and the Q-path.

[0025] It is further proposed that a third voltage level detector be coupled to the second transmission element between the impedance transformation element and the radio-frequency receiver circuit. Using this additional voltage level detector, it is possible to detect ripples in the time-domain signals. It is possible to detect the sources of imbalances. This information can be used to optimize the phase of the digital modulating signal so that the residual peak-to-center signal swing is reduced below a predefined limit. In particular, the detected third voltage level can be evaluated together with the combined voltage levels as detected by the first and second voltage detectors on the I and Q paths. Using this information, the quality of the I / Q signal generation can be further improved. In particular, the imbalance can be reduced.

[0026] Furthermore, it is proposed that the at least one voltage level detector be coupled to the first transmission element between the impedance transformation element and a power combiner. This arrangement results in a high impedance seen by the voltage level detector, which is higher than the 50 ohm impedance used in conventional power level detection systems.

[0027] It is proposed that the impedance of the first transmission element be more than twice the impedance of the second transmission element. For example, with an impedance of 50 ohms for the second transmission element, the impedance of the first transmission element may be more than 100 ohms, preferably even more than 200 ohms.

[0028] In one embodiment, at least one voltage level detector is coupled to the first transmission element closer to the modulator than to the impedance transformation element, since the modulator has a high impedance at its output, which can be advantageously utilized by the voltage level detector. In embodiments, the at least one voltage level detector may be coupled to the first transmission element at a location close to the point of highest impedance of the first transmission element.

[0029] It is further proposed that the test signal generator include a digital test signal data generator and a digital-to-analog converter to generate the baseband test signal. This is an efficient and simple way to generate the baseband test signal.

[0030] It is further proposed that the test signal circuit be configured to test at least one of the following properties of the radio-frequency receiver circuit: the gain, the frequency response, the inter-channel amplitude and phase balance, and / or the inter-channel noise of the radio-frequency receiver circuit. These parameters allow for a thorough testing of the radio-frequency receiver circuit.

[0031] It is further proposed that an analog-to-digital converter be coupled to an output of the at least one voltage level detector, wherein the analog-to-digital converter is configured to convert a voltage level into a digital signal and output the digital signal to a control circuit connected to the test signal circuit. The control signal is used to optimize the test signal circuit during operation, for example, to optimize the generation of the test signal.

[0032] The control circuit comprises at least two interfaces for connecting to the test signal generator and transmitting the control signal to the test signal generator, as well as for receiving the signal indicating that the test signal is being processed by the radio-frequency receiver circuit. The processor, for example a microcontroller or a microprocessor or a digital signal processor, is configured to generate a control signal depending on the received signal.

[0033] It is further proposed that the control circuit comprises a third interface coupled to an output of the analog-to-digital converter to receive the digital signal, and wherein the processor is configured to generate the control signal in dependence on the digital signal and the signal.

[0034] It is further proposed that an output of the third voltage level detector is coupled to the analog-to-digital converter.

[0035] It is further proposed that the processor be configured to receive the digital signal and generate the control signal, thereby reducing modulator imperfections, such as I / Q imbalance. This improves the signal quality of the test signal. SHORT DESCRIPTION OF THE CHARACTERS

[0036] Embodiments will now be described, by way of example only, with reference to the accompanying drawing figures. Like reference numerals are used to refer to like elements throughout. The illustrated structures and devices are not necessarily drawn to scale. Fig. 1 shows a block diagram of a system including a test signal circuit, Fig. Figure 2 shows a block diagram of the test signal circuit comprising two voltage level detectors, Fig. 3 shows a block diagram of the test signal circuit including a voltage level detector, Fig. Figure 4 shows a fourth block diagram of the test signal circuit comprising three voltage level detectors, Fig. 5 shows a voltage-time diagram, Fig. 6 shows a voltage-time diagram, and Fig. Figure 7 shows a sensitivity-output power diagram. DETAILED DESCRIPTION

[0037] Fig. Figure 1 shows a block diagram of a system including a test signal circuit TSC, a radio frequency receiver circuit RX, and a control circuit CC. A local oscillator LO provides a local oscillator signal to the test signal circuit TSC and the radio frequency receiver circuit RX.

[0038] In the test signal circuit TSC, the signal provided by the local oscillator LO is received by the QAM modulator, for example, using quadrature amplitude modulation. This QAM modulator combines the signal from the local oscillator LO with the baseband test signal BTS provided by the test signal generator TSG to form the test signal TS. This is often referred to as modulation of the local oscillator signal with the baseband test signal BTS.

[0039] The test signal TS is provided to an impedance transformation element MN via the first transmission element TE1, wherein the first transmission element TE1 is coupled between the modulator QAM and the impedance transformation element MN. The impedance transformation element MN can, for example, be an impedance matching network. In addition, a voltage level detector VLD is connected to the first transmission element TE1 to measure the voltage level of the test signal TS. The impedance transformation element MN is connected to a second transmission element TE2, which transmits the test signal TS to the radio-frequency receiver circuit RX. The test signal is tapped by the voltage level detector VLD at the first transmission element TE1 because the first transmission element TE1 has a higher impedance level than the second transmission element TE2.In many applications, the second transmission element TE2 can be limited to standard characteristic impedances such as 50 ohms or 70 ohms. A higher impedance level at the first transmission element TE1 results in a correspondingly higher voltage, which is detected by the voltage level detector VLD.

[0040] The voltage level detector VLD may comprise an electrical circuit including diodes, resistors, and / or transistors. It may further comprise a current path and an associated mirror current path for detecting the voltage level.

[0041] The voltage level detector VLD transmits the voltage level to an analog-to-digital converter AD, which generates a digital signal DS using the detected voltage level. The analog-to-digital converter AD can, for example, be an analog-to-digital converter AD specifically designed for detecting different voltages. It offers high resolution and low loss, which is particularly useful for small signals. The digital signal DS is transmitted to a control circuit CC. The control circuit CC receives the digital signal DS via its interface IF3, which is connected to a processor P.

[0042] The impedance of the second transmission element TE2 is selected to match the input impedance of the receiver circuit RX, which can be 50 ohms, for example. The impedance of the first transmission element TE1 is therefore selected to be higher than the impedance of the second transmission element TE2. Coupling the voltage level detector VLD to the high-impedance first transmission element TE1 and outputting the test signal TS to the radio receiver RX via the low-impedance second transmission element TE2 has the advantage that the voltage level detector VLD can be operated with a high input impedance, while simultaneously matching the input impedance of the receiver circuit RX to a lower impedance.

[0043] The radio-frequency receiver circuit RX processes the test signal TS as it would process signals received via an antenna. Accordingly, the test signal TS is amplified, demodulated, and transformed into a signal S by the receiver circuit RX. The signal S is a digital signal and could, for example, be used to calculate the gain of the receiver circuit RX.

[0044] Fig. Figure 2 illustrates the elements of one embodiment of the test signal circuit TSC in more detail. The signal from the local oscillator LO is received by an amplifier LO-AMP, which amplifies the signal provided by the local oscillator LO. This amplified signal is fed to a coupler C, which provides signals to two mixers MI and MQ, which mix the signal provided by the coupler C with the baseband test signal BTS for the I path and the Q path. The mixer MI acts as a modulator for the I path. The mixer MQ acts as a modulator for the Q path. The coupler C operates as a 90-degree hybrid coupler, allocating a portion of the power to each of the two mixers.

[0045] The test signal generator TSG generates the baseband test signal BTS using a clock signal CLK and the control signal CS and provides the baseband test signal BTS as two components for quadrature amplitude modulation. One component is the I component and the other is the Q component. Both components are fed to a digital-to-analog converter IQ-DAC, which provides the respective components as analog signals to the mixers MI, MQ. The digital-to-analog converter IQ-DAC includes a gain selection GS input. Using the gain selection GS, it is possible to influence the respective amplitudes of the signals provided to the mixers MI, MQ. The two components of the baseband test signal BTS are then provided to the mixers MI, MQ. The thus modulated signals of the I and Q components are provided on the I path and a Q path, respectively.They are then fed via a first transmission element to a combination of a power combiner and the impedance transformation element PC + MN.

[0046] The mixers MI, MQ have a high complex impedance at their output. The first transmission element TE1, coupled to their output, is tapped by the respective voltage level detectors IVLD, QVLD. The respective voltage detectors IVLD, QVLD are preferably coupled to the first transmission element TE1 near the output of the respective mixer MI, MQ to benefit from the high output impedance of the mixers MI, MQ. The impedance of the first transmission element TE1 can typically decrease with increasing distance from the mixers MI, MQ.

[0047] The voltage level detectors IVLD, QVLD can both be connected to the analog-to-digital converter AD, which transforms the detected voltage levels into the digital signal DS. In the Fig. In the embodiment shown in Figure 2, the two analog output signals of the first and second voltage level detectors IVLD, QVLD are combined in the analog domain by connecting the output lines of the two voltage level detectors IVLD, QVLD. The combined analog signal is then fed to the analog-to-digital converter AD. The analog-to-digital converter AD generates the digital signal DS and provides it to the control circuit CC.

[0048] The second transmission element TE2 is coupled to the other side of the power combiner and the impedance transformation element PC+MN. The second transmission element TE2 connects the test signal circuit TSC to the radio-frequency receiver circuit RX. The impedance of the second transmission element TE2 is, for example, 50 ohms, which is a commonly used impedance of a radio-frequency receiver circuit RX input.

[0049] The power combiner PC of the power combiner and the impedance transformation element PC + MN can therefore be configured to combine the power of the I path and the Q path. The power combiner PC can combine the I and Q paths by connecting the lines to provide an analog combination.

[0050] The impedance matching element MN of the power combiner and the impedance transformation element PC + MN can be configured to match the impedance of the second transmission element TE2 to the input of the receiver circuit RX.

[0051] The impedance of the first transmission element TE1 is selected to be higher than the impedance of the second transmission element TE2. This allows the voltage level detector VLD to tap the test signal TS at a higher impedance node, resulting in a higher detected voltage. At the same time, the input impedance after transformation is matched to the typically lower characteristic impedance of the receiver circuit, such as 50 ohms.

[0052] Fig. Figure 3 shows a block diagram of another embodiment of a test signal circuit TSC. The first transmission element TE1 is coupled to the mixers MI, MQ and to the power combiner PC, which combines the power on the I and Q paths.

[0053] Another part of the first transmission element TE1 is further coupled between the power combiner PC and the impedance transformation element MN. This impedance transformation element MN is connected on the other side to the second transmission element TE2. A single voltage level detector VLD is connected to the first transmission element TE1 between the power combiner PC and the impedance transformation element MN. The impedance transformation element MN can be a matching network that matches the impedance of the first transmission element TE1 to the impedance of the second transmission element TE2.

[0054] In this embodiment, the voltage level detector VLD detects the voltage level of the combined I / Q path. In contrast to the embodiment of Fig. 2, only one voltage level detector (VLD) is required. However, the power combiner (PC) has additional loss before the signal is detected by the voltage level (VLD). Furthermore, after power combining, a sideband is suppressed, resulting in a lower peak voltage.

[0055] The voltage level detected by the voltage level detector VLD is then transmitted to the analog-to-digital converter AD, which generates the digital signal DS, as explained above. The impedance of the first transmission element TE1 is chosen to be higher than the impedance of the second transmission element TE2. This allows the voltage level detector VLD to operate with a high input impedance while simultaneously adapting the input impedance of the receiver circuit RX to a lower impedance. In this embodiment, a typical value of the absolute impedance value of the first transmission element TE1 can be 75 ohms. A typical value of the absolute impedance value of the second transmission element TE2 is 50 ohms. This embodiment still works well with the impedance of the first transmission element TE1 being approximately 50% higher than the impedance of the second transmission element TE2.

[0056] Fig. Figure 4 shows a block diagram of another embodiment of a test signal circuit TSC. The power combiner PC and the impedance transformation element MN are again combined into one element PC+MN. Separate voltage detectors IVLD and QVLD are connected to the I path and the Q path, respectively. Both voltage level detectors IVLD and QVLD are connected to the analog-to-digital converter AD.

[0057] The voltage level detectors IVLD, QVLD are both connected to the analog-to-digital converter AD, which transforms the detected voltage levels into the digital signal DS. Fig. In the embodiment shown in Figure 4, the two analog output signals of the first and second voltage level detectors IVLD, QVLD are separately fed to the analog-to-digital converter AD. The analog-to-digital converter AD converts them to the digital domain and combines them in the digital domain.

[0058] A third voltage level detector AVLD is connected to the second transmission element TE2. This third voltage level, detected by the third voltage level detector AVLD, is also transmitted to the analog-to-digital converter AD. It is converted to the digital domain in the analog-to-digital converter AD.

[0059] Using the analog signals received from the voltage level detectors IVLD, QVLD, AVLD, the analog-to-digital converter AD generates the digital signal DS and provides it to the control circuit CC.

[0060] Fig. Figure 5 shows a voltage-time diagram, where the dotted lines represent an envelope of the input to the power combiner PC of Fig. 4 on the Q-path. The diagram shows the output voltage in volts over time in microseconds. The dashed lines are the envelope of the input to the power combiner PC of Fig. 4 on the I path. The combined output of the power combiner PC is shown in solid lines. It is shown to be quite stable, with slow, low-amplitude oscillations compared to the I and Q inputs, which oscillate at higher amplitudes.

[0061] The combined signal in solid lines nevertheless exhibits small variations in its amplitude, which can be described as ripple. The ripple is due to certain imbalances in the I / Q signal generation.

[0062] Fig. Figure 6 shows a graph showing the I output signal of the first voltage level detector IVLD in dashed lines and the Q output signal of the second voltage level detector QVLD in dotted lines. The graph shows the output voltage in volts over time in microseconds. These I and Q output signals both exhibit significant ripples. In addition, a combined signal of the I output signal and the Q output signal is shown in a solid line. These ripples can be significantly suppressed by combining the two outputs I and Q of the first and second voltage level detectors IVLD, QVLD. By using this combination, e.g., through the analog-to-digital converter AD as described above, it is possible to significantly suppress the ripples.

[0063] Ripple represents an error in voltage level detection. Lower ripple is desirable because it increases voltage level detection accuracy. This ripple can be addressed by low-pass filtering the combined output signal of the voltage level detector (VLD). Such a low-pass filter does not need to be of very high quality, nor does it need to have a very low cutoff frequency. Nevertheless, the circuit can produce a faster response if no low-pass filtering is applied, because the filtering takes time.

[0064] There may be embodiments where no low-pass filter is required and where the accuracy of the combined output signal of the voltage level detector VLD is good enough even without low-pass filtering. The choice depends on the required overall accuracy.

[0065] The embodiment of Fig. 4 allows for the treatment of ripple in the combined signal using the third voltage level detected by the third voltage level detector AVLD. In conjunction with the combined signal from the first and second voltage level detectors IVLD and QVLD, it can be used to obtain information about the imbalance of the test signal TS and influence the generation of the I / Q signal, with the goal of generating a more balanced I / Q signal.

[0066] Fig.Figure 7 shows a sensitivity-output power diagram comparing the proposal of this application, shown by the dashed curve, with the solid curve resulting, for example, when using a power level detector instead of a voltage level detector. The diagram shows the sensitivity in mV / dBm versus the output power in dBm. The power level detector can be operated on a 50-ohm output line of a test signal circuit TSC. A voltage level detector is better for tapping a line with a higher impedance. The described embodiments make it possible to use a voltage level detector VLD instead of a power level detector.

[0067] It is shown that the proposed test signal circuit TSC exhibits significantly higher sensitivity. This means that the high impedance of the voltage level detectors VLD, IVLD, QVLD results in a higher voltage swing. Both sidebands of the modulating signal are present at each of the I and Q branches, resulting in a higher peak voltage of, for example, approximately 3 dB compared to the output of the power combiner PC. The voltage level detectors VLD, IVLD, QVLD see a higher input voltage compared to the case when used at the output of the power combiner PC, which has its own insertion loss.

Claims

[1] Test signal circuit (TSC) for testing a radio frequency receiver circuit (RX), comprising: a test signal generator (TSG) configured to generate a baseband test signal (BTS), a modulator (QAM, MI, MQ) configured to modulate a local oscillator signal with the baseband test signal (BTS) to generate a test signal (TS), a first transmission element (TE1) coupled between the modulator and an input of an impedance transformation element (MN), a second transmission element (TE2) coupled to an output of the impedance transformation element (MN), wherein the impedance transformation element (MN) is configured to reduce a first impedance level of the first transmission element (TE1) to a second impedance level of a second transmission element (TE2), at least one voltage level detector (VLD, IVLD, QVLD) coupled to the first transmission element (TE1), wherein the at least one voltage level detector (VLD, IVLD, QVLD) is configured to detect a voltage level of the test signal (TS). [2] The test signal circuit of claim 1, wherein the at least one voltage level detector comprises a first voltage level detector (IVLD) and a second voltage level detector (QVLD), and wherein the modulator is configured to be an IQ modulator generating the test signal (TS) in two components, a first component (I) on an I path and a second component (Q) on a Q path, wherein the first voltage level detector (IVLD) is coupled to the I path and the second voltage level detector (QVLD) is coupled to the Q path, wherein the impedance transformation element (MN) comprises a power combiner (PC) combining the first component (I) and the second component (Q). [3] Test signal circuit according to claim 1 or 2, wherein a third voltage level detector (AVLD) is coupled to the second transmission element (TE2) between the impedance transformation element (MN) and the radio frequency receiver circuit (RX). [4] Test signal circuit according to one of claims 1 to 3, wherein the at least one voltage level detector (VLD) is coupled to the first transmission element (TE1) between the impedance transformation element (MN) and a power combiner (PC). [5] Test signal circuit according to one of the preceding claims, wherein the impedance of the first transmission element (TE1) is more than 2 times higher than the impedance of the second transmission element (TE2). [6] Test signal circuit according to one of the preceding claims, wherein the at least one voltage level detector (VLD, IVLD, QVLD) is coupled to the first transmission element (TE1) closer to the modulator than to the impedance transformation element (MN). [7] Test signal circuit according to one of the preceding claims, wherein the test signal generator (TSG) comprises a digital test signal data generator and a digital-to-analog converter to generate the baseband test signal (BTS). [8] Test signal circuit according to one of the preceding claims, wherein the test signal circuit (TSC) is configured to test at least one of the following: gain, frequency response, inter-channel amplitude and phase balance and / or inter-channel noise of the radio frequency receiver circuit (RX). [9] Test signal circuit according to one of the preceding claims, comprising an analog-to-digital converter (AD) coupled to an output of the at least one voltage level detector (VLD, IVLD, QVLD) and / or the third voltage level detector (AVLD), wherein the analog-to-digital converter (AD) is configured to convert the voltage level into a digital signal (DS) and to output the digital signal (DS) to a control circuit (CC) connected to the test signal circuit (TSC). [10] Semiconductor chip comprising the test signal circuit (TSC) according to one of the preceding claims. [11] System comprising a test signal circuit (TSC) according to one of claims 1 to 9 and a control circuit (CC), wherein the control circuit (CC) comprises a first interface (IF1) coupled to the radio frequency receiver circuit (RX) for receiving a signal (S) indicating that the test signal (TS) is being processed by the radio frequency receiver circuit (RX), a processor (P) configured to generate a control signal (CS), a second interface (IF2) coupled to the test signal generator (TSG) to transmit the control signal (CS) to the test signal generator (TSG). [12] System according to claim 11, wherein the control circuit comprises a third interface (IF3) coupled to an output of the analog-to-digital converter (AD) to receive the digital signal (DS), and wherein the processor (P) is configured to generate the control signal (CS) in dependence on the digital signal (DS). [13] The system of claim 12, comprising the test signal circuit (TSC) of any one of claims 3 to 9, wherein an output of the third voltage level detector is coupled to the analog-to-digital converter (AD). [14] The system of claim 13, wherein the processor (P) is configured to receive the digital signal (DS) and generate the control signal (CS) so that imperfections of the modulator (QAM, MI, MQ) are reduced.

Images