DISPLAY DEVICE

Abstract

A display device (100) comprises: a display panel (PN) in which several first pixel areas (UPA1) and several second pixel areas (UPA2), each containing several subpixels (SP), are defined; a pixel circuit (PC) located in each of the several subpixels (SP) and comprising a driver transistor (DT); and a welding transistor (WT) that selectively connects the pixel circuit (PC) of the first pixel area (UPA1) and that of a second pixel area (UPA2) that are adjacent to each other, among the several first pixel areas (UPA1) and the several second pixel areas (UPA2). Accordingly, the welding transistor (WT) is used to supply an additional drive current to the pixel circuit (PC) of the light-emitting diode (LED) of an adjacent subpixel (SP) to improve the luminance.

Description

BACKGROUND TECHNICAL AREA

[0001] The present disclosure relates to a display device, particularly, for example, without limitation, a display device using a light-emitting diode (LED). DESCRIPTION OF RELATED TECHNOLOGY

[0002] As display devices used for a monitor of a computer, a television, or a mobile phone, there are an organic light-emitting display (OLED) which is a self-emitting device, a plasma display (PDP), a field emission display (FED), a micro-LED (micro light-emitting diode) display, and a liquid crystal display (LCD) which requires a separate light source, etc.

[0003] An application range of the display device is extended to personal digital assistants and monitors of computers and televisions, and a display device with a large display area and reduced volume and weight is investigated.

[0004] Furthermore, a display device using a light-emitting diode (LED) has recently attracted attention as a next-generation display device. Since the LED is made of an inorganic material rather than an organic material, its reliability is excellent, so its service life is longer than that of a liquid crystal display device or an organic light-emitting display device. Furthermore, the LED has a fast luminous speed, excellent luminous efficiency, and high shock resistance, thus providing excellent stability and enabling the display of an image with high luminance.

[0005] The description provided in the description of the related art section should not be considered prior art simply because it is mentioned in or relates to the description of the related art section. The description of the related art section may include information describing one or more aspects of the subject art, and the description in that section does not limit the invention. OVERVIEW

[0006] The inventors have recognized the requirements and limitations of a display device's resolution. Accordingly, an object of the present disclosure is to provide a display device that can operate in both a high-resolution mode and a low-resolution mode.

[0007] Another object of the present disclosure is to provide a display device that can operate in both a high grayscale mode and a low grayscale mode in a low resolution model display device.

[0008] Another object of the present disclosure is to provide a display device implemented as a low resolution model of a display device designed for high resolution.

[0009] Another object of the present disclosure is to provide a display device capable of setting a resolution according to a specification of a tile display device.

[0010] Another object of the present disclosure is to provide a display device in which a display device exclusively dedicated to a high-resolution mode and a display device exclusively dedicated to a low-resolution mode are integrated to reduce manufacturing costs and process time.

[0011] Another object of the present disclosure is to provide a display device that selectively transmits a light-emitting diode to only some subpixels of the plurality of subpixels to be driven at a low resolution.

[0012] Another object of the present disclosure is to provide a display device capable of supplying a high current to a light-emitting diode by connecting a pixel circuit of a subpixel to which a light-emitting diode is not transferred to a light-emitting diode of another subpixel in a low-resolution model.

[0013] Another object of the present disclosure is to provide a display device that easily displays a high gray scale image by supplying a high current to a light emitting diode in a low resolution model.

[0014] The objects of the present disclosure are not limited to the objects mentioned above, and other objects not mentioned above can be clearly understood by those skilled in the art from the following descriptions.

[0015] In one aspect of the present disclosure, a display device according to claim 1 is provided. In another aspect of the present disclosure, a display device according to claim 17 is provided. Further aspects are described in the dependent claims. According to one aspect of the present disclosure, a display device comprises: a display panel in which a plurality of first pixel regions and a plurality of second pixel regions each having a plurality of sub-pixels are defined; a pixel circuit arranged in respective ones of the plurality of sub-pixels and having a driving transistor; and a welding transistor selectively connecting the pixel circuits of the first pixel region and a second pixel region adjacent to each other among the plurality of first pixel regions and the plurality of second pixel regions.Accordingly, the welding transistor is used to further conduct a driving current of the pixel circuit to the light-emitting diode of a neighboring subpixel to improve the luminance.

[0016] According to another aspect of the present disclosure, a display device comprises: a substrate in which a plurality of first pixel regions and a plurality of second pixel regions, each having a plurality of subpixels, are defined; a plurality of pixel circuits arranged in respective ones of the plurality of subpixels on the substrate and having a driving transistor; a plurality of reflection plates arranged in respective ones of the plurality of subpixels on the plurality of pixel circuits and electrically connected to the driving transistor of respective ones of the plurality of pixel circuits; and a plurality of welding transistors arranged between the plurality of first pixel regions and the plurality of second pixel regions and selectively connecting the plurality of reflection plates of the plurality of first pixel regions and the plurality of reflection plates of the plurality of second pixel regions.Accordingly, the reflection plate connected to the driver transistor is used to easily electrically connect driver transistors of adjacent pixel circuits.

[0017] Further details of the exemplary embodiments are set forth in the detailed description and drawings.

[0018] According to the present disclosure, the display device can be operated in one of a high resolution mode and a low resolution mode.

[0019] According to the present disclosure, the display device can be operated in a high grayscale mode and a low grayscale mode in a low resolution model display device.

[0020] According to the present disclosure, a resolution of the display device can be easily adjusted according to a specification of a tile display device.

[0021] According to the present disclosure, during driving in a low resolution mode, a pixel circuit of a subpixel that does not emit light is selectively connected to a light-emitting diode to display an image with a high luminance.

[0022] According to the present disclosure, the configurations of the low-resolution model display device and the high-resolution model display device are unified to optimize the process and reduce a process time and manufacturing cost.

[0023] According to the present disclosure, a light-emitting diode is selectively transferred to only some subpixels to easily form a low-resolution model display device.

[0024] According to the present disclosure, a pixel circuit in a region to which a light-emitting diode is not transferred is selectively connected to the light-emitting diode to easily display a high gray-scale image.

[0025] The effects according to the present disclosure are not limited to the contents exemplified above, and the present disclosure has other various effects.

[0026] Other systems, methods, features, and advantages will be or become apparent to a person of ordinary skill in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included in this description, within the scope of the present disclosure, and protected by the following claims. Nothing in this section should be construed as limiting those claims. Additional aspects and advantages are discussed below in connection with embodiments of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure; Fig. 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure; Fig. 2B is a perspective view of a tile display device according to an exemplary embodiment of the present disclosure; Fig. 3 is an enlarged plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure; Fig. 4 is a cross-sectional view of a subpixel of a display device according to an exemplary embodiment of the present disclosure; Fig. 5A is a cross-sectional view along the line Va-Va' of Fig. 3 is; Fig. 5B is a cross-sectional view along the line Vb-Vb' of Fig. 3 is; Fig. 6 and Fig. 7 are exemplary circuit diagrams of a pixel circuit of a subpixel of a display device according to an exemplary embodiment of the present disclosure; Fig. 8 is a drive timing diagram of a display device according to an exemplary embodiment of the present disclosure; Fig. 9 is an enlarged plan view of a display panel of a display device according to another exemplary embodiment of the present disclosure; Fig. 10 and Fig. 11 are exemplary circuit diagrams of a pixel circuit of a subpixel of a display device according to another exemplary embodiment of the present disclosure; and Fig. 12 is a drive timing diagram of a display device according to another exemplary embodiment of the present disclosure.

[0028] In the drawings and detailed description, unless otherwise noted, the same drawing reference numbers refer to the same elements, features, and structures. The relative size and representation of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, a detailed description of known functions or configurations related to this document will be omitted if it is determined that doing so would unnecessarily obscure the essence of the inventive concept. The described sequence of processing steps and / or operations is an example; however, the sequence of steps and / or operations is not limited to the sequence set forth herein and may be changed according to the prior art, except for steps and / or operations that necessarily occur in a particular order. Like reference numerals denote like elements throughout.The names of the respective elements used in the following explanations are chosen only for the sake of simplicity in writing the description and may therefore differ from those used in actual products.

[0030] Advantages and features of the present disclosure, and a method for achieving the advantages and features, will become apparent by reference to exemplary embodiments described in detail below along with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be embodied in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosures of the present disclosure and the scope of the present disclosure.

[0031] The shapes, sizes, areas, ratios, angles, numbers, and the like shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally denote like elements throughout the description. Furthermore, in the following description of the present disclosure, a detailed explanation of known related technologies may be omitted or provided only briefly in order not to unnecessarily obscure the subject matter of the present disclosure. The terms "comprise," "have," "comprise," "constitute," "made of," "formed of," and "consist of" as used herein are generally intended to allow the addition of other components unless the terms are used with the term "only."Any reference to the singular form may include the plural form unless expressly stated otherwise.

[0032] Any implementation described here as an “example” is not necessarily preferred or advantageous over other implementations.

[0033] When the terms "comprise," "hub," and "include" are used in this disclosure, another term may be added unless a more limiting term, such as "only," is used. Terms in the singular form may also include the plural form unless otherwise indicated.

[0034] Components are interpreted to have a common error margin, even if this is not explicitly stated.

[0035] When the positional relationship between two parts is described with terms such as "on", "above", "over", "below", "below", "next to", "near", "near", "adjacent to", "on one side of", "close to", one or more parts may be positioned between the two parts, unless the terms are used with the expression "immediate" or "direct".

[0036] Spatially relative terms such as "below," "beneath," "under," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. It should be understood that the spatially relative terms may encompass various orientations of an element in use or operation, in addition to the orientation illustrated in the figures. For example, if an element is inverted in the figures, elements described as being "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both a below and above orientation. Similarly, the exemplary term "above" or "over" may encompass both a above and below orientation.

[0037] When describing a temporal relationship, terms such as "after," "following," "subsequent," "next," "before," and the like may include cases where two events do not follow one another unless a term such as "immediately," "just," or "immediately" is explicitly used.

[0038] When one element or layer is placed "on top of" another element or layer, another layer or element can be placed directly on top of the other element or between them.

[0039] Although the terms "first," "second," "A," "B," "(a)," "(b)," and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.

[0040] Furthermore, terms such as first, second, A, B, (a), (b), or the like may be used herein when describing components of the present disclosure. Each of these terms is not used to define a nature, order, or sequence of a corresponding component, but merely serves to distinguish the corresponding component from other components. When a particular structural element or layer is described as being "connected," "coupled," "glued," or "joined" to another structural element or layer, this is typically interpreted to mean that another structural element or layer may be "connected," "coupled," "glued," or "joined" to the structural element or layer, directly or indirectly.

[0041] The term "at least one" should be understood to include all combinations of one or more of the listed elements. For example, the meaning of "at least one of a first element, a second element, and a third element" refers to the combination of all elements suggested by two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0042] The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include a light-emitting diode (LED) and the like. Furthermore, examples of the device may include a notebook computer, a television, a computer monitor, an automotive device, a portable device, and an automotive equipment device, as well as an electronic device (or appliance) or a device (or appliance), e.g., a mobile electronic device such as a smartphone or an electronic pad, which are complete products or finished products including an LED and the like, but embodiments of the present disclosure are not limited thereto.

[0043] Like reference numbers generally refer to like elements throughout the specification.

[0044] A size and a thickness of each component shown in the drawing are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated component.

[0045] The features of the various embodiments of the present disclosure may be partially or completely bonded or combined with each other and may be interconnected and operated in technically diverse ways, and the embodiments may be practiced independently of each other or in conjunction with each other.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person skilled in the art in a technical field to which the example embodiments belong. It is further understood that terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0047] In aspects of the present disclosure, a source electrode and a drain electrode are distinguished from each other for convenience of description. However, the source electrode and the drain electrode are used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. Also, the source electrode in any aspect of the present disclosure may be the drain electrode in another aspect of the present disclosure, and the drain electrode in any aspect of the present disclosure may be the source electrode in another aspect of the present disclosure.

[0048] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. For convenience of description, the scale of each element shown in the accompanying drawings differs from an actual scale and is therefore not limited to the scale shown in the drawings.

[0049] Fig. 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Fig. 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Fig. 2B is a perspective view of a tile display device according to an exemplary embodiment of the present disclosure. In Fig. In Figure 1, for the sake of simplicity, only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are shown among the various components of the display device 100, but the components of the display device 100 of the present disclosure are not limited thereto. Meanwhile, all components of each display device are operatively coupled and configured according to all embodiments of the present disclosure.

[0050] Referring to Fig. 1, the display device 100 comprises: a display panel PN having a plurality of subpixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0051] The gate driver GD supplies multiple scan signals to multiple scan lines SL in accordance with multiple gate control signals supplied by the timing controller TC. Even if Fig. 1 shows that one gate driver GD is spaced from one side of the display panel PN, the number of gate drivers GD and their arrangement are not limited thereto. For example, two gate drivers GD may be associated and spaced from the display panel PN. However, embodiments of the present disclosure are not limited thereto.

[0052] The data driver DD converts image data input from the timing controller TC into a data voltage using a reference gamma voltage in accordance with a plurality of data control signals supplied from the timing controller TC. The data driver DD can supply the converted data voltage to the plurality of data lines DL. The data driver DD can be implemented in the form of an integrated circuit (IC) or can be implemented in the display panel 110 in the form of a gate-in-panel (GIP) type.

[0053] The timing controller TC aligns externally input image data to supply the image data to the data driver DD. The timing controller TC may generate a gate control signal and a data control signal using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal synchronization / vertical synchronization signals. Where, the horizontal synchronization signal is a signal indicating the time required to display one horizontal line of a screen, and the vertical synchronization signal is a signal indicating the time required to display one screen of one frame. The data enable signal may correspond to a signal indicating a period of time during which a data voltage is supplied to the pixel PX.Furthermore, the timer control device TC supplies the generated gate control signal and the data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0054] The display panel PN is a configuration that displays images to the user and has a plurality of subpixels SP. In the display panel PN, the plurality of scan lines SL and the plurality of data lines DL intersect, and the plurality of subpixels SP are connected to the scan lines SL and the data lines DL, respectively. Furthermore, each of the plurality of subpixels SP may be connected to a high-potential power line, a low-potential power line, and a reference line, although not shown in the drawing.

[0055] In the display panel PN, an active area AA and a non-active area NA, which is located near the active area AA, surrounds the active area AA or is located around the active area AA, can be defined.

[0056] The active area AA is an area where images are displayed in the display device 100. In the active area AA, a plurality of pixel areas may be arranged in a matrix form along a plurality of row and column lines. The plurality of pixel areas may include pixel areas displaying different colors, such as red (R), green (G), and blue (B), or red (R), green (G), blue (B), and white (W). At this time, the red (R), green (G), and blue (B) pixel areas adjacent to each other, or the red (R), green (G), blue (B), and white (W) pixel areas adjacent to each other, may function as a unit pixel for displaying a color image. In the active area AA, a plurality of subpixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of subpixels SP may be arranged. The plurality of subpixels SP are a minimum unit that configures the active area AA, and n subpixels SP constitute a pixel PX.Each of the plurality of subpixels SP can emit light having different wavelengths. The plurality of subpixels can include first to third subpixels that emit light of different colors. For example, the plurality of subpixels SP can include a red subpixel SPR, which is a first subpixel, a green subpixel SPG, which is a second subpixel, and a blue subpixel SPB, which is a third subpixel. Furthermore, the plurality of subpixels SP can also include a white subpixel.

[0057] For example, the plurality of subpixels SP may include red, green, and blue subpixels, where the red, green, and blue subpixels may be arranged in a repeated manner. Alternatively, the plurality of subpixels SP may include red, green, blue, and white subpixels, where the red, green, blue, and white subpixels may be arranged in a repeating manner, or the red, green, blue, and white subpixels may be arranged in a quad type. For example, the red subpixel, the blue subpixel, and the green subpixel may be arranged sequentially along a row direction, or the red subpixel, the blue subpixel, the green subpixel, and the white subpixel may be arranged sequentially along the row direction.However, in the embodiment of the present disclosure, the color type, arrangement type, and arrangement order of the subpixels are not limited and can be configured in various forms according to the light-emitting characteristics, device lifetimes, and device specifications.

[0058] Meanwhile, the subpixels may have different light-emitting areas according to their light-emitting characteristics. For example, a subpixel that emits light of a different color than a blue subpixel may have a different light-emitting area than the blue subpixel. For example, the red subpixel, the blue subpixel, and the green subpixel, or the red subpixel, the blue subpixel, the white subpixel, and the green subpixel may each have a different light-emitting area.

[0059] A light-emitting diode and a thin-film transistor for driving the light-emitting diode may be arranged in each of the plurality of subpixels SP. The plurality of light-emitting diodes may be defined differently depending on the type of the display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel PN, the light-emitting diode may be a light-emitting diode (LED) or a micro-light-emitting diode (micro-LED). If the display panel PN is an organic light-emitting display panel, the light-emitting element may be an organic light-emitting diode (OLED). The embodiments of the present disclosure are not limited thereto.

[0060] In the active region AA, a plurality of wiring lines are arranged, which transmit various signals to the plurality of subpixels SP. For example, the plurality of wiring lines may include a plurality of data lines DL that supply a data voltage to each of the plurality of subpixels SP, and a plurality of scan lines SL that supply a scan signal to each of the plurality of subpixels SP. The plurality of scan lines SL extend in one direction in the active region AA to be connected to the plurality of subpixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active region AA to be connected to the plurality of subpixels SP. In addition, a low-potential power line and a high-potential power line may be further arranged in the active region AA, but are not limited thereto.

[0061] A subpixel SP constituting a unit pixel may include a switching thin film transistor SW, a driving thin film transistor DR, a storage capacitor Cst, a compensation circuit CC, and a light-emitting diode EL.

[0062] The switching thin-film transistor SW can perform a switching operation to store a data signal supplied via the first data line in the storage capacitor Cst as a data voltage in response to the scan signal supplied via the first gate line. The driving thin-film transistor DR can operate to flow a drive current between a first power line (e.g., high-potential voltage) and a second power line (e.g., low-potential voltage) in accordance with the data voltage stored in the storage capacitor Cst. The light-emitting diode EL can operate to emit light in accordance with the drive current generated by the driving thin-film transistor DR.

[0063] The compensation circuit CC is a circuit added within the subpixel for compensating the threshold voltage of the driver thin-film transistor DR. The compensation circuit CC can include one or more thin-film transistors. The compensation circuit CC can have various configurations depending on the compensation method, so its example is described as follows.

[0064] The non-active area NA is an area where no images are displayed, so the non-active area NA can be defined as an area extending from the active area AA. A connecting line that transmits a signal to the subpixel SP of the active area AA, a pad electrode, or a drive IC such as a gate driver IC or a data driver IC can be arranged in the non-active area NA.

[0065] However, the non-active area NA may be located on a rear surface of the display panel PN, that is, on a surface on which the subpixels SP are not arranged or can be omitted, and is not limited, as shown in the drawing.

[0066] Meanwhile, a driver, such as a gate driver GD, a data driver DD, and a timing controller TC, may be connected to the display panel PN in various ways. For example, the gate driver GD may be mounted in the non-active area NA in a gate-in-panel (GIP) manner or between the multiple subpixels SP in the active area AA in a gate-in-active-area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in a separate flexible film and a printed circuit board. The data driver DD and the timing controller TC are electrically connected to the display panel PN by connecting the flexible film and the printed circuit board to the pad electrode formed in the non-active area NA of the display panel PN. However, embodiments of the present disclosure are not limited thereto.

[0067] When the gate driver GD is mounted in a GIP configuration, and the data driver DD and the timing controller TC transmit a signal to the display panel PN via a pad electrode of the non-active area NA, a larger than predetermined area of ​​the non-active area NA is required for the arrangement of the gate driver GD and the pad electrode. Accordingly, an aperture can be increased.

[0068] In contrast, the gate driver GD is mounted in the active area AA in the GIA manner, and a side line SRL connecting the signal line on the front surface of the display panel PN to the pad electrode on a rear surface of the display panel PN is formed such that the flexible film and the printed circuit board on a rear surface of the display panel PN are connected. At this time, the non-active area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero aperture with essentially no aperture can be implemented or realized.

[0069] In particular with reference to Fig. 2A and Fig. 2B, a plurality of pad electrodes for transmitting various signals to the plurality of subpixels SP are arranged in the non-active region NA of the display panel PN. For example, a first pad electrode PAD1 is arranged in a non-active region NA on the front surface of the display panel PN, which transmits a signal to the plurality of subpixels SP. A second pad electrode PAD2 is arranged in a non-active region NA on the rear surface of the display panel PN and is electrically connected to a driving component such as a flexible film and the circuit board. That is, on the front surface of the display panel PN on which images are displayed, at least one pad region of the non-active region NA in which the first pad electrode PAD1 is arranged may be formed.

[0070] In this case, although not shown in the drawing, various signal lines connected to the plurality of subpixels SP, e.g., a scan line SL or a data line DL, extend from the active area AA to the non-active area NA to be electrically connected to the first pad electrode PAD1.

[0071] Furthermore, the side line SRL is arranged along a side surface of the display panel PN. The side line SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN can be transmitted to the plurality of subpixels SP via the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Accordingly, a signal transmission path is formed from the front surface of the display panel PN to the side surface and the rear surface to minimize an area of ​​the non-active region NA on the front surface of the display panel PN.

[0072] With reference to Fig. 2B, a tile display device TD having a large screen size can be implemented by connecting a plurality of display devices 100. At this time, as shown in Fig. As shown in Fig. 2A, when the tile display device TD is implemented using a display device 100 with a minimized frame, a seam area in which an image is not displayed between the display devices 100 is minimized, so that display quality can be improved.

[0073] For example, the plurality of subpixels SP constitute a pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to a display device may be implemented to be equal to a distance D1 between pixels PX in a display device 100. Accordingly, a constant distance D1 between pixels PX between the display devices 100 is configured to minimize the seam area.

[0074] Fig. 2A and Fig. 2B are illustrative, so the display device 100 according to the exemplary embodiment of the present disclosure may be, but is not limited to, a general display device having a bezel.

[0075] Fig. 3 is an enlarged plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure. Fig. 4 is a cross-sectional view of a subpixel of a display device according to an exemplary embodiment of the present disclosure. Fig. Figure 5A is a cross-sectional view along the line Va-Va' of Fig. 3. Fig. Figure 5B is a cross-sectional view along the line Vb-Vb' of Fig. 3. In particular Fig. 5A and Fig. 5B are cross-sectional views of a welding transistor WT according to an exemplary embodiment of the present disclosure. For ease of description, Fig. 3 only several reflection plates RF, several light-emitting diodes LED and several welding transistors WT are shown, and in Fig. 4 shows only one driver transistor among the configurations of a pixel circuit PC.

[0076] First, the display device 100 according to an exemplary embodiment of the present disclosure can be operated in one of a high-resolution mode and a low-resolution mode. In the high-resolution mode, all of the plurality of pixels PX are driven to display a high-resolution image, and in the low-resolution mode, only some of the plurality of pixels PX are driven to display a low-resolution image. The resolution varies depending on the number of pixels PX used to display an image. Therefore, the resolution of an image to be displayed can be adjusted by selectively driving a plurality of pixels PX. For example, the resolution of the image to be displayed increases as the number of driven pixels PX increases.

[0077] In Fig. 3, a plurality of pixel regions UPA are formed in the display panel PN. The plurality of pixel regions UPA are regions in which the plurality of pixels PX are arranged. The plurality of pixel regions UPA can be arranged by forming a plurality of rows and a plurality of columns. Each of the plurality of pixels PX arranged in the plurality of pixel regions UPA has a plurality of subpixels SP. Each of the plurality of subpixels SP has a light-emitting diode LED and a pixel circuit PC for independently emitting light.

[0078] The plurality of pixel regions UPA includes a plurality of first pixel regions UPA1 and a plurality of second pixel regions UPA2. When the display device 100 is driven, the plurality of first pixel regions UPA1 are always driven. That is, the plurality of first pixel regions UPA1 are regions where images are always displayed in both the high-resolution mode and the low-resolution mode. The plurality of second pixel regions UPA2 are selectively driven when the display device 100 is driven, and the plurality of second pixel regions UPA2 are driven in a high-resolution mode but not in a low-resolution mode. For example, in the high-resolution mode, both the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 are driven, and in the low-resolution mode, only the plurality of first pixel regions UPA1 are driven, but the plurality of second pixel regions UPA2 are not driven.However, the present disclosure is not limited thereto, and only the plurality of second pixel regions UPA2 may be controlled.

[0079] The arrangement of the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 can be designed in various forms depending on the resolution. For example, the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 can be arranged alternately in the row direction and the column direction, or alternately in one of the row direction and the column direction. Even if in Fig. 3 that the first pixel region UPA1 and the second pixel region UPA2 are arranged in different rows, this is only illustrative and the present disclosure is not limited thereto, for example, the first pixel region UPA1 and the second pixel region UPA2 may be arranged in different columns.

[0080] The plurality of subpixels SP constituting a pixel PX are arranged in each of the plurality of pixel regions UPA. For example, the plurality of subpixels SP may include a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel SP4 that emit light of different colors. For example, the first subpixel SP1 and the second subpixel SP2 are red subpixels, the third subpixel SP3 is a green subpixel, and the fourth subpixel SP4 is a blue subpixel, but not limited to these.

[0081] In the following description, it is assumed that a pixel PX has a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel SP4, i.e., two red subpixels, one green subpixel, and one blue subpixel. However, the configuration of the pixel PX is not limited to this.

[0082] With reference to Fig. 3 and Fig. 4 together, in each of the plurality of subpixels SP of the display panel PN of the display device 100 according to the exemplary embodiment of the present disclosure, there are arranged: a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a third interlayer insulating layer 115, a first planarization layer 116, an adhesive layer 117, a second planarization layer 118, a third planarization layer 119, a driving transistor DT, a light-emitting diode LED, a plurality of reflection plates RF, a first connection electrode CE1, a second connection electrode CE2, a light-shielding layer LS, and an auxiliary electrode LE.

[0083] First, the substrate 110 is a component for supporting various components present in the display device 100 and may be formed from an insulating material. For example, the substrate 110 may be formed from glass or resin. Furthermore, the substrate 110 may be configured to comprise a polymer or plastic, or may be formed from a flexible material. For example, the substrate 110 may be formed from a flexible polymer film. The flexible polymer film may be formed from, for example, any of the following materials: polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetylcellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto.

[0084] The light-shielding layer LS is disposed in each of the plurality of subpixels SP on the substrate 110. The light-shielding layer LS blocks light incident on a driver active layer ACT of the driver transistor DT, which will be described below, located beneath the substrate 110. Light incident on the driver active layer ACT of the driver transistor DT is blocked by the light-shielding layer LS to minimize leakage current.

[0085] The buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the permeation of moisture or contaminants through the substrate 110. The buffer layer 111 can be formed from a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the buffer layer 111 can be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film. Multi-layer inorganic films can be formed by alternately stacking one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more amorphous silicon (a-Si) films, but the present disclosure is not limited thereto.However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, but is not limited thereto.

[0086] A pixel circuit PC including the driver transistor DT is arranged on the substrate 110. The pixel circuit PC is a circuit including the driver transistor DT, some other transistors, and a capacitor for driving a light-emitting diode (LED). The pixel circuit PC may further include, for example, the driver transistor DT, a switching transistor, a sensing transistor, and an emission control transistor for supplying a drive current to the light-emitting diode (LED). The transistors other than the driver transistor DT among the plurality of transistors included in the pixel circuit PC and the capacitor may be configured in various forms depending on the configuration, and the present disclosure is not limited thereto.

[0087] The driver transistor DT is arranged on the buffer layer 111. The driver transistor DT has a driver active layer ACT, a driver gate electrode GE, a driver source electrode SE, and a driver drain electrode DE.

[0088] The driver active layer ACT is disposed on the buffer layer 111. The driver active layer ACT may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor.

[0089] The oxide semiconductor material can offer excellent leakage current prevention performance and relatively low manufacturing costs. The oxide semiconductor can be made of a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and its oxide. In particular, the oxide semiconductor may include, but is not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0090] The polycrystalline semiconductor material exhibits a high velocity of charge carriers, such as electrons and holes, and thus high mobility, as well as low power consumption and high reliability. The polycrystalline semiconductor can be made of, but is not limited to, polycrystalline silicon (poly-Si).

[0091] The amorphous semiconductor material may be made of, but is not limited to, amorphous silicon (a-Si).

[0092] Although not shown in the drawings, in addition to the driver transistor DT, other transistors such as a switching transistor, a sensing transistor, and an emission control transistor may be arranged on the buffer layer 111. The active layers of the transistors are also formed from a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon. Furthermore, the active layer of the transistor included in the pixel circuit PC, such as the driver transistor DT, the switching transistor, the sensing transistor, and the emission control transistor, may be formed from the same material or from different materials.

[0093] Further, the gate insulating layer 112 is disposed on the driver active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the driver active layer ACT from the driver gate electrode GE and may be configured by, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx). For example, the gate insulating layer 112 may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film. Multi-layer inorganic films may be formed by alternately stacking one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more amorphous silicon (a-Si) films, but the present disclosure is not limited to this.

[0094] The driver gate electrode GE is arranged on the gate insulating layer 112. The driver gate electrode GE may be formed from a conductive material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. The driver gate electrode GE may, for example, be formed from an alloy of two or more of these materials or from multiple layers thereof, but is not limited to this.

[0095] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the driver gate electrode GE. A contact hole is formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114, through which the driver source electrode SE and the driver drain electrode DE are connected to the driver active layer ACT. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting a device under the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and may be formed of, but are not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx).For example, each of the first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be formed by a single-layer or multi-layer inorganic film, e.g., the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and multi-layer inorganic films may be formed by alternately stacking one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0096] The driving source electrode SE and the driving drain electrode DE, which are electrically connected to the driving active layer ACT, are arranged on the second interlayer insulating layer 114. The driving source electrode SE and the driving drain electrode DE may be formed of a conductive material such as, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0097] Meanwhile, in the present disclosure, it is described that the first interlayer insulating layer 113 and the second interlayer insulating layer 114, that is, a plurality of insulating layers, are disposed between the driver gate electrode GE and the driver source electrode SE and the driver drain electrode DE. However, the present disclosure is not limited to this; only one insulating layer may be disposed between the driver gate electrode GE and the driver source electrode SE and the driver drain electrode DE.

[0098] As shown in the drawings, when multiple insulating layers, such as the first interlayer insulating layer 113 and the second interlayer insulating layer 114, are disposed between the driving gate electrode GE and the driving source electrode SE and the driving drain electrode DE, an electrode may be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode may form a capacitor with the other configuration, disposed below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0099] The auxiliary electrode LE is arranged on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to one of the driving source electrode SE or the driving drain electrode DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to the driving source electrode SE or the driving drain electrode DE via the auxiliary electrode LE, so it does not function as a floating gate. Therefore, fluctuations in the threshold voltage of the driving transistor DT caused by the floating light-shielding layer LS can be minimized. Although the light-shielding layer LS is connected to the driving source electrode SE in the drawing, the light-shielding layer LS may also be connected to the driving drain electrode DE, but is not limited thereto.

[0100] The third interlayer insulating layer 115 is disposed on the driver transistor DT. The third interlayer insulating layer 115 is disposed to cover the pixel circuit PC including the driver transistor DT to protect the pixel circuit PC. The third interlayer insulating layer 115 may be formed from a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the third interlayer insulating layer 115 may be formed from a single-layer or multi-layer inorganic film, e.g.the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and multilayer inorganic films may be formed by alternately stacking one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0101] The first planarization layer 116 is disposed on the third interlayer insulating layer 115. The first planarization layer 116 may planarize an upper portion of the substrate 110 on which the driver transistor DT is disposed. The first planarization layer 116 may be configured as a single layer or a double layer and may be formed of, for example, photoresist or an acrylic-based organic material, but is not limited thereto.

[0102] With reference to Fig. 3 and Fig. 4, a plurality of reflection plates RF are arranged on the first planarization layer 116. The reflection plate RF is a configuration that reflects light emitted by the plurality of light-emitting diodes LED above the substrate 110 and can be formed into a shape corresponding to each of the plurality of subpixels SP. A reflection plate RF can be arranged to cover the largest area of ​​a subpixel SP. The reflection plate RF reflects the light emitted by the light-emitting diode LED and can also be used as an electrode that electrically connects the light-emitting diode LED and the pixel circuit PC. Therefore, the reflection plate RF can have various conductive layers to consider light reflection efficiency and resistance.For example, the RF reflection plate may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, and a transparent conductive layer such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the structure of the RF reflection plate is not limited to this.

[0103] The reflection plate RF comprises: a first reflection plate RF1 corresponding to the first subpixel SP1, a second reflection plate RF2 corresponding to the second subpixel SP2, a third reflection plate RF3 corresponding to the third subpixel SP3, and a fourth reflection plate RF4 corresponding to the fourth subpixel SP4.

[0104] The first reflection plate RF1 overlaps the first subpixel SP1. The first reflection plate RF1 can reflect light emitted by the red LED 120 of the first subpixel SP1 above the red LED 120. Further, the first reflection plate RF1 is electrically connected to the driver transistor DT through a contact hole formed in the first planarization layer 116 and the third interlayer insulating layer 115 to transmit a drive current from the driver transistor DT to the red LED 120.

[0105] The second reflection plate RF2 overlaps the second subpixel SP2. The second reflection plate RF2 can reflect light emitted by the red LED 120 of the second subpixel SP2 above the red LED 120. Furthermore, the second reflection plate RF2 is electrically connected to the driver transistor DT through a contact hole formed in the first planarization layer 116 and the third interlayer insulation layer 115 to transmit a drive current from the driver transistor DT to the red LED 120.

[0106] The third reflection plate RF3 overlaps the third subpixel SP3. The third reflection plate RF3 can reflect light emitted by the green LED 130 of the third subpixel SP3 above the green LED 130. The third reflection plate RF3 is electrically connected to the driver transistor DT via a contact hole formed in the first planarization layer 116 and the third interlayer insulation layer 115 to transmit a drive current from the driver transistor DT to the green LED 130.

[0107] The fourth reflection plate RF4 overlaps the fourth subpixel SP4. The fourth reflection plate RF4 can reflect light emitted by the blue LED 140 of the fourth subpixel SP4 above the blue LED 140. The fourth reflection plate RF4 is electrically connected to the driver transistor DT via a contact hole formed in the first planarization layer 116 and the third interlayer insulation layer 115 to transmit a drive current from the driver transistor DT to the blue LED 140.

[0108] The adhesive layer 117 is disposed on the plurality of reflection layers RF. The adhesive layer 117 is formed on the front surface of the substrate 110 to fix the light-emitting diode (LED) disposed on the adhesive layer 117. The adhesive layer 117 may be formed from a light-curing adhesive material that is cured by light. For example, the adhesive layer 117 may be selected from, but is not limited to, adhesive polymer, epoxy resin, UV resin, polyimide, acrylate, urethane, and polydimethylsiloxane (PDMS).

[0109] Meanwhile, a first passivation layer may be disposed between the adhesive layer 117 and the plurality of reflection plates RF, although not shown in the drawing. The first passivation layer is an insulating layer that protects components beneath the first passivation layer and may be configured by, but is not limited to, a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx). For example, the first passivation layer may be formed by a single-layer or multi-layer inorganic film, e.g.the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and multilayer inorganic films may be formed by alternately stacking one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0110] Meanwhile, a second passivation layer may be disposed on the plurality of reflection plates RF. The second passivation layer is an insulating layer for protecting components under the second passivation layer and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. For example, the second passivation layer 117 may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film. Multi-layer inorganic films may be formed by alternately stacking one or more silicon oxide (SiOx) films, one or more silicon nitride (SiNx) films, and one or more amorphous silicon (a-Si) films, but the present disclosure is not limited thereto.

[0111] The plurality of light-emitting diodes (LEDs) are arranged in respective ones of the plurality of subpixels SP on the adhesive layer 117. The light-emitting diode (LED) is an element that emits light through a current. The light-emitting diode (LED) includes: a red light-emitting diode 120 that emits red light, a green light-emitting diode 130 that emits green light, and a blue light-emitting diode 140 that emits blue light, and generates light of various colors, including white, through a combination thereof. The light-emitting diode (LED) may be, for example, a light-emitting diode (LED) or a micro-LED, but is not limited to these.

[0112] A red LED 120 is arranged in each of the first subpixel SP1 and the second subpixel SP2, a pair of green LEDs 130 is arranged in the third subpixel SP3, and a pair of blue LEDs 140 is arranged in the fourth subpixel SP4. That is, two red LEDs 120, two green LEDs 130, and two blue LEDs 140 can be arranged in one pixel PX. At this time, each of the red LEDs 120 is connected to the driver transistor DT of the first subpixel SP1 and the second subpixel SP2, respectively, to be individually driven. In contrast, a pair of green LEDs 130 of the third subpixel SP3 and a pair of blue LEDs 140 of the fourth subpixel SP4 are each connected in parallel to a driver transistor DT to be driven.For example, a pair of green LEDs 130 of the third subpixel SP3 is connected in parallel to a driver transistor DT to be driven, and a pair of blue LEDs 140 of the fourth subpixel SP4 is connected in parallel to a driver transistor DT to be driven.

[0113] Hereinafter, the red LED 120 arranged in the first subpixel SP1 will be described as an example, and the green LED 130 and the blue LED 140 are also formed by substantially the same configuration as the red LED.

[0114] Among the plurality of light-emitting diodes (LEDs), the red light-emitting diode 120 includes a first semiconductor layer 121, an emission layer 122, a second semiconductor layer 123, a first electrode 124, and a second electrode 125.

[0115] The first semiconductor layer 121 is disposed on the adhesive layer 117, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping n-type and p-type impurities into a particular material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers doped with n-type and p-type impurities into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurity may be silicon (Si), germanium (Ge), and tin (Sn), but is not limited to these.

[0116] The emission layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The emission layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The emission layer 122 can be formed by a single layer or a multi-quantum well (MQW) structure and can be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0117] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driver transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with an n-type impurity, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on an upper surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be configured from a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as, but not limited to, titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0118] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode that electrically connects one of the high-potential power line VDD or a low-potential power line VSS and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with a p-type impurity, and the second electrode 125 may be an anode. The second electrode 125 may be configured from a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as, but not limited to, titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0119] Furthermore, an encapsulation layer 126 is arranged, which encloses the first semiconductor layer 121, the emission layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation layer 126 is formed from an insulating material for protecting the first semiconductor layer 121, the emission layer 122, and the second semiconductor layer 123. A contact hole is formed in the encapsulation layer 126, which exposes the first electrode 124 and the second electrode 125, in order to electrically connect a first connection electrode CE1 and a second connection electrode CE2 to the first electrode 124 and the second electrode 125.

[0120] Meanwhile, a part of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation layer 126. The LED fabricated on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the separation of the LED from the wafer, a part of the encapsulation layer 126 may be torn. For example, a part of the encapsulation layer 126 adjacent to a lower edge of the first semiconductor layer 121 of the LED is torn during the process of separating the LED from the wafer. Accordingly, a part of a lower side surface of the first semiconductor layer 121 may be exposed to the outside.Although the lower portion of the light-emitting diode (LED) is exposed from the encapsulation layer 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after the formation of the second planarization layer 118 and the third planarization layer 119, which cover the side surface of the first semiconductor layer 121. Accordingly, a short-circuit defect can be reduced.

[0121] Furthermore, the second planarization layer 118 and the third planarization layer 119 are arranged over the adhesive layer 117 and the light-emitting diode LED.

[0122] The second planarization layer 118 overlaps a portion of the side surfaces of the plurality of light-emitting diodes (LEDs) to fix and protect the plurality of light-emitting diodes (LEDs). A torn-off portion of the encapsulation layer 126, which protects the side surface of the first semiconductor layer 121 of the light-emitting diode (LED), is covered by the second planarization layer 118. In this way, contacts and short circuits between the terminal electrodes and the first semiconductor layer 121 can be suppressed thereafter.

[0123] The third planarization layer 119 is formed to cover upper portions of the second planarization layer 118 and the light-emitting diode (LED). A contact hole exposing the first electrode 124 and the second electrode 125 of the light-emitting diode (LED) may be formed in the third planarization layer 119. The first electrode 124 and the second electrode 125 of the light-emitting diode (LED) are exposed by the third planarization layer 119, and the third planarization layer 119 is partially disposed in a region between the first electrode 124 and the second electrode 125 to reduce a short-circuit defect. The second planarization layer 118 and the third planarization layer 119 may be configured by a single layer or a double layer, and may be formed of, for example, but not limited to, photoresist or an acrylic-based organic material.

[0124] The first connection electrode CE1 and the second connection electrode CE2 are arranged on the third planarization layer 119. The second connection electrode CE2 is an electrode that electrically connects the second electrode 125 of the light-emitting diode (LED) and the power line. The second connection electrode CE2 is electrically connected to the second electrode 125 of the light-emitting diode (LED) through a contact hole formed in the third planarization layer 119. However, embodiments of the present disclosure are not limited thereto.

[0125] The first connection electrode CE1 is an electrode that electrically connects the first electrode 124 of the light-emitting diode (LED) and the driver transistor DT. The first connection electrode CE1 can be connected to the first reflection plate RF1, the second reflection plate RF2, the third reflection plate RF3, and the fourth reflection plate RF4 of each of the plurality of subpixels SP via contact holes. The contact holes are formed in the third planarization layer 119, the second planarization layer 118, and the adhesive layer 117. At this time, the first reflection plate RF1, the second reflection plate RF2, the third reflection plate RF3, and the fourth reflection plate RF4 are also connected to the driver source electrode SE of the driver transistor DT, so that the driver source electrode SE of the driver transistor DT and the first electrode 124 of the light-emitting diode (LED) can be electrically connected to each other.However, embodiments of the present disclosure are not limited thereto.

[0126] In the drawing, the driving source electrode SE of the driving transistor DT and the first electrode 124 of the light-emitting diode LED are electrically connected via the reflection plate RF. However, the driving drain electrode DE of the driving transistor DT and the second electrode 125 of the light-emitting diode LED may be electrically connected via the reflection plate RF, depending on, but not limited to, the type of the driving transistor DT and the design of the pixel circuit PC.

[0127] Furthermore, a bank may be arranged on the first connection electrode CE1 and the second connection electrode CE2, although not shown in the drawing. The bank may be arranged to be spaced apart from the light-emitting diode LED by a predetermined distance and to at least partially overlap the reflection plate RF. For example, the bank may cover a part of the first connection electrode CE1 and the second connection electrode CE2 formed in the contact holes of the third planarization layer 119 and the second planarization layer 118. The bank may be formed of an opaque material to reduce color mixing between the plurality of subpixels SP, and may be formed of, for example, black resin, but is not limited thereto.

[0128] Meanwhile, in order to configure the image to be displayed to have different resolutions, the display device 100 must be configured to have different designs according to the resolution, so the manufacturing process of the display device 100 is not uniform, which may increase the manufacturing cost. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, a display device 100 displaying a high-resolution image is used as it is, and a low-resolution display device 100 can be implemented by only leaving some pixels PX undriven. For example, in the high-resolution mode, all the pixels arranged in the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 are driven.Furthermore, in the low-resolution mode, pixels of the plurality of first pixel regions UPA1 are driven, but pixels of the plurality of second pixel regions UPA2 are not driven to display the low-resolution image. Accordingly, the display device 100 designed to display a high-resolution image is used as is to display the low-resolution image, so the structure of the existing display device 100 for high-resolution display is used as is, and all manufacturing processes are unified to reduce manufacturing costs.

[0129] Meanwhile, when the display device 100 is operated in a low-resolution mode, the number of driven pixels PX is reduced, so that the luminance of the display device 100 can be lowered. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, in the low-resolution mode, a drive current is supplied from the pixel circuit PC of the pixel PX of the second pixel region UPA2 that is not driven to the pixel PX of the first pixel region UPA1. In this way, the luminance of the light emitted from each pixel PX is improved. A plurality of welding transistors WT connecting the first pixel region UPA1 and the second pixel region UPA2 are arranged to supply a drive current generated in the pixel PX of the second pixel region UPA2 to the light-emitting diode LED of the first pixel region UPA1.

[0130] With reference to Fig. 3 to Fig. 5B, a plurality of welding transistors WT are arranged between the first pixel region UPA1 and the second pixel region UPA2. The welding transistor WT can connect respective ones of the plurality of subpixels SP of the second pixel region UPA2 to respective ones of the plurality of subpixels SP of the first pixel region UPA1. A current generated in a respective one of the plurality of subpixels SP of the second pixel region UPA2 by the welding transistor WT can be transferred to a respective one of the plurality of subpixels SP of the first pixel region UPA1.

[0131] The welding transistor WT can connect a respective one of the plurality of subpixels SP of the first pixel region UPA1 to a respective one of the plurality of subpixels SP of the second pixel region UPA2. The welding transistor WT can connect reflection plates RF of the subpixels SP that emit light of the same color. For example, one welding transistor WT can connect the first subpixels SP1 of the first pixel region UPA1 and the second pixel region UPA2, and the other welding transistor WT can connect the second subpixels SP2 of the first pixel region UPA1 and the second pixel region UPA2.

[0132] As described above, the reflection plate RF is connected between the driver transistor DT and the light-emitting diode LED, allowing the drive current from the driver transistor DT to flow through the reflection plate RF to the light-emitting diode LED. Therefore, the welding transistor WT is connected to the reflection plate RF, through which the drive current flows from the driver transistor DT to transfer the drive current of one subpixel SP to the other subpixel SP. For example, a welding source electrode WSE and a welding drain electrode WDE of each of the plurality of welding transistors WT may be connected to the first reflection plate RF1 of the first pixel region UPA1 and the first reflection plate RF1 of the second pixel region UPA2, the second reflection plate RF2 of the first pixel region UPA1, and the second reflection plate RF2 of the second pixel region UPA2.Furthermore, a welding source electrode WSE and a welding drain electrode WDE of each of the plurality of welding transistors WT may be connected to the third reflection plate RF3 of the first pixel region UPA1 and the third reflection plate RF3 of the second pixel region UPA2, as well as to the fourth reflection plate RF4 of the first pixel region UPA1 and the fourth reflection plate RF4 of the second pixel region UPA2. For example, a welding source electrode WSE of one welding transistor WT of the plurality of welding transistors WT may be connected to the first reflection plate RF1 of the second pixel region UPA2, and a welding drain electrode WDE of one welding transistor WT may be connected to the first reflection plate RF1 of the first pixel region UPA1.For example, a welding source electrode WSE of a welding transistor WT of the plurality of welding transistors WT may be connected to the second reflection plate RF2 of the second pixel region UPA2, and a welding drain electrode WDE of the one welding transistor WT may be connected to the second reflection plate RF2 of the first pixel region UPA1. For example, a welding source electrode WSE of a welding transistor WT of the plurality of welding transistors WT may be connected to the third reflection plate RF3 of the second pixel region UPA2, and a welding drain electrode WDE of the one welding transistor WT may be connected to the third reflection plate RF3 of the first pixel region UPA1.For example, a welding source electrode WSE of one welding transistor WT of the plurality of welding transistors WT may be connected to the fourth reflection plate RF4 of the second pixel region UPA2, and a welding drain electrode WDE of the one welding transistor WT may be connected to the fourth reflection plate RF4 of the first pixel region UPA1b, but the present disclosure is not limited thereto.

[0133] The welding transistor WT has a welding active layer WACT, a first welding gate electrode WGE1, a second welding gate electrode WGE2, a welding source electrode WSE and a welding drain electrode WDE.

[0134] First, the first welding gate electrode WGE1 is disposed on the substrate 110 in a region between the first pixel region UPA1 and the second pixel region UPA2. The first welding gate electrode WGE1 may be disposed along a boundary between the first pixel region UPA1 and the second pixel region UPA2. An end portion of the first welding gate electrode WGE1 extends toward a welding control line WCL to be electrically connected to the welding control line WCL. The first welding gate electrodes WGE1 of the plurality of welding transistors WT are connected to each other. Therefore, the first welding gate electrode WGE1 serves as a gate electrode of each of the plurality of welding transistors WT and may also serve as an interconnection line connecting each of the plurality of welding transistors WT and the welding control line WCL.

[0135] The buffer layer 111 is disposed on the first welding gate electrode WGE1, and the welding active layer WACT is disposed on the buffer layer 111. The welding active layer WACT may be formed of a semiconductor material such as, but is not limited to, an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor.

[0136] The oxide semiconductor material can have excellent leakage current prevention or reduction properties and is relatively inexpensive to manufacture. The oxide semiconductor can be made from a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and its oxide. In particular, the oxide semiconductor may include, but is not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO).

[0137] The polycrystalline semiconductor material exhibits a high velocity of charge carriers, such as electrons and holes, and thus high mobility, as well as low power consumption and high reliability. The polycrystalline semiconductor can be made of, but is not limited to, polycrystalline silicon (poly-Si).

[0138] The amorphous semiconductor material may be made of, but is not limited to, amorphous silicon (a-Si).

[0139] The gate insulating layer 112 is disposed on the welding active layer WACT, and the second welding gate electrode WGE2 is disposed on the gate insulating layer 112. The second welding gate electrode WGE2 may be electrically connected to the first welding gate electrode WGE1 via a contact hole formed in the gate insulating layer 112 and the buffer layer 111. Therefore, the welding transistor WT may be a transistor with a dual-gate structure in which the first welding gate electrode WGE1 and the second welding gate electrode WGE2 are disposed on and below the welding active layer WACT. However, the welding transistor WT may include only one of the first welding gate electrode WGE1 and the second welding gate electrode WGE2, but is not limited thereto.

[0140] Further, the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the second welding gate electrode WGE2, and the welding source electrode WSE and the welding drain electrode WDE are disposed on the second interlayer insulating layer 114. One of the welding source electrode WSE and the welding drain electrode WDE is connected to the plurality of reflection plates RF of the first pixel region UPA1, and the other may be connected to the plurality of reflection plates RF of the second pixel region UPA2, depending on the type of the welding transistor WT. For example, when the welding transistor WT is a P-type transistor, the welding source electrode WSE is connected to the reflection plates RF of the second pixel region UPA2, and the welding drain electrode WDE is connected to the reflection plates RF of the first pixel region UPA1. Therefore, the drive current of the second pixel region UPA2 can be transmitted to the first pixel region UPA1.If the welding transistor WT is an N-type transistor, the welding source electrode WSE is connected to the reflection plates RF of the first pixel region UPA1, and the welding drain electrode WDE is connected to the reflection plates RF of the second pixel region UPA2. Therefore, the drive current of the second pixel region UPA2 can be transferred to the first pixel region UPA1.

[0141] The welding control line WCL is arranged between the plurality of pixel regions UPA. For example, the welding control line WCL may extend in a column direction between the plurality of pixel regions UPA. The welding control line WCL is a wiring line for applying a control signal to the plurality of welding transistors WT. The welding control line WCL applies a control signal to the first welding gate electrode WGE1 and the second welding gate electrode WGE2 of the welding transistor WT to turn the welding transistor WT on or off.

[0142] Furthermore, an auxiliary line WCLA may be arranged to connect the plurality of welding transistors WT and the welding control line WCL. For example, one end of the auxiliary line WCLA is electrically connected to the welding control line WCL, and the other end may be connected to the first welding gate electrode WGE1 of the welding transistor WT. However, the first welding gate electrode WGE1 of the welding transistor WT may also be directly connected to the welding control line WCL instead of using the auxiliary line WCLA, but this is not limited to this.

[0143] The auxiliary line WCLA can be configured in various shapes. For example, the auxiliary line WCLA can be configured in a rectangular shape with a closed loop structure. However, the auxiliary line WCLA can be configured in various shapes, but is not limited to these.

[0144] Hereinafter, a method for improving luminance using a welding transistor WT in a low resolution mode will be described with reference to Fig. 6 to Fig. 8 described.

[0145] Fig. 6 and Fig. 7 are exemplary circuit diagrams of a pixel circuit of a subpixel of a display device according to an exemplary embodiment of the present disclosure. Fig. 8 is a drive timing diagram of a display device according to an exemplary embodiment of the present disclosure.

[0146] With reference to Fig. 6 and Fig. 7, various pixel circuits PC having a driver transistor DT may be formed in a plurality of subpixels SP. For example, in the plurality of subpixels SP, a pixel circuit PC having a 3T1C structure as shown in Fig. 6, or a pixel circuit PC with a 7T3C structure as shown in Fig. 7. However, the present disclosure is not limited thereto; various configurations of internal compensation circuits are possible in the pixel circuit of the present disclosure. For example, the pixel circuit of the present disclosure may include three or more transistors, TFTs, and one or more capacitors. For example, the pixel circuit of the present disclosure may be a 3T2C pixel circuit with three TFTs and two capacitors, a 5T1C pixel circuit with five TFTs and one capacitor, a 5T2C pixel circuit with five TFTs and two capacitors, a 7T2C pixel circuit with seven TFTs and two capacitors, or the like.Furthermore, the plurality of light-emitting diodes LED may be configured with a common-cathode structure in which the cathode is commonly connected to the low-potential power line VSS, or with a common-anode structure in which the anode is commonly connected to the high-potential power line VDD.

[0147] For example, with reference to Fig. 6, the pixel circuit PC may have a 3T1 C structure, and the light-emitting diode LED may be connected to the pixel circuit PC in a common-cathode structure. Furthermore, the pixel circuit PC, which is arranged in a respective one of the subpixels SP of the first pixel region UPA1 and the second pixel region UPA2, may include a driver transistor DT, a first transistor T1 and a second transistor T2, which are N-type transistors, and a first capacitor C1.

[0148] The first transistor T1 has a first gate electrode, a first source electrode, and a first drain electrode. The first drain electrode is connected to the data line DL, the first source electrode is connected to the driver gate electrode GE, and the first gate electrode is connected to a scan line SL. The first transistor T1 of the first pixel region UPA1 is turned on by the first scan signal S1 from the scan line SL, and the first transistor T1 of the second pixel region UPA2 is turned on by the second scan signal S2 from the scan line SL. The turned-on first transistor T1 transmits a data voltage from the data line DL to the driver gate electrode GE of the driver transistor DT. Accordingly, the first transistor T1 can be referred to as a switching transistor.

[0149] The second transistor T2 has a second gate electrode, a second source electrode, and a second drain electrode. The second drain electrode is connected to a reference line, the second source electrode is connected to a driver source electrode SE, and the second gate electrode is connected to a scan line. The second transistor T2 is turned on by a scan signal Scan from the scan line and transmits a reference voltage Vref from the reference line to the driver source electrode SE of the driver transistor DT.

[0150] The driver transistor DT includes a driver gate electrode GE, a driver source electrode SE, and a driver drain electrode DE. The driver drain electrode DE is connected to a high-potential power line VDD, the driver source electrode SE is connected to a drain electrode of a first enable transistor ET1 or a second enable transistor ET2, and the driver gate electrode GE is connected to the first transistor T1. The driver transistor DT can control a drive current supplied to the light-emitting diode LED.

[0151] The first capacitor C1 has multiple capacitor electrodes. Some of the multiple capacitor electrodes are connected to the driver gate electrode GE, and the others may be connected to the driver source electrode SE. The first capacitor C1 maintains the voltage of the driver gate electrode GE constant to supply a constant drive current to the light-emitting diode LED.

[0152] The light-emitting diode (LED) has an anode and a cathode. For example, the first electrode 124 of the light-emitting diode (LED), which is connected to the first semiconductor layer 121 doped with an n-type impurity, is a cathode, and the second electrode 125, which is connected to the second semiconductor layer 123 doped with a p-type impurity, may be an anode. The anode is connected to a source electrode of the first enable transistor ET1 or the second enable transistor ET2, and the cathode may be connected to the low-potential power line VSS. The light-emitting diode (LED) of the first pixel region UPA1 is arranged between the first enable transistor ET1 and the low-potential power line VSS, and the light-emitting diode (LED) of the second pixel region UPA2 may be arranged between the second enable transistor ET2 and the low-potential power line VSS.

[0153] The anode may be formed in a multi-layer structure including a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer is formed of a material having a relatively large work function value, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive layer is formed of a single- or multi-layer structure containing Al, Ag, Cu, Pb, Mo, or Ti, or an alloy thereof. For example, the anode may be formed in a structure in which a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer are sequentially stacked, or in a structure in which a transparent conductive layer and an opaque conductive layer are sequentially stacked. However, embodiments of the present disclosure are not limited thereto.

[0154] With reference to Fig. 7, the pixel circuit PC may, for example, have a 7T3C structure, and the light-emitting diode LED is connected to the pixel circuit PC in a common anode manner. Further, the pixel circuit PC, which is arranged in each of the subpixels SP of the first pixel region UPA1 and the second pixel region UPA2, may include a driver transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, which are P-type transistors. Also, the pixel circuit PC, which is arranged in each of the subpixels SP of the first pixel region UPA1 and the second pixel region UPA2, may include a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0155] The first transistor T1 has a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to a scan line SL in an n-th row, and the first source electrode and the first drain electrode may be connected to the driver gate electrode GE and the driver drain electrode DE of the driver transistor DT, respectively. When a threshold voltage of the driver transistor DT is compensated, the first transistor T1 may connect the driver transistor DT in the form of a diode.

[0156] The second transistor T2 has a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to a scan line SL in the nth row, the second source electrode is connected to the data line DL, and the second drain electrode is connected to the first capacitor C1. The second transistor T2 of the first pixel region UPA1 is turned on by the nth first scan signal S1(n), and the second transistor T2 of the second pixel region UPA2 is turned on by the nth second scan signal S2(n) to transfer a data voltage from the data line DL to the first capacitor C1. Accordingly, the second transistor T2 can be referred to as a switching transistor.

[0157] The third transistor T3 has a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to an emission control signal EM line, and the third source electrode and the third drain electrode are connected to the reference line and the first capacitor C1, respectively. The third transistor T3 is turned on by the emission control signal EM to transmit a reference voltage Vref to the first capacitor C1.

[0158] The fourth transistor T4 has a fourth gate electrode, a fourth source electrode, and a fourth drain electrode. The fourth gate electrode is connected to the emission control signal EM line, and the fourth source electrode and the fourth drain electrode are connected to the driver drain electrode DE and the low-potential power line VSS, respectively. The fourth transistor T4 is turned on by the emission control signal EM to connect the driver transistor DT and the low-potential power line VSS.

[0159] The fifth transistor T5 has a fifth gate electrode, a fifth source electrode, and a fifth drain electrode. The fifth gate electrode is connected to the scan line SL in an n-1st row, and the fifth source electrode and the fifth drain electrode are connected to the reference line and the driver drain electrode DE, respectively. The fifth transistor T5 of the first pixel region UPA1 is turned on by the n-1st first scan signal S1(n-1), and the fifth transistor T5 of the second pixel region UPA2 is turned on by the n-1st second scan signal S2(n-1) to transmit a reference voltage Vref to the driver drain electrode DE.

[0160] The sixth transistor T6 has a sixth gate electrode, a sixth source electrode, and a sixth drain electrode. The sixth gate electrode is connected to the scan line SL in the nth row, the sixth source electrode is connected to the high-potential power line VDD, and the sixth drain electrode is connected to the drive source electrode SE and the cathode of the light-emitting diode LED. The sixth transistor T6 of the first pixel region UPA1 is turned on by the nth first scan signal S1(n), and the sixth transistor T6 of the second pixel region UPA2 is turned on by the nth second scan signal S2(n). The turned-on sixth transistor T6 can transmit a high-potential power voltage to the drive source electrode SE and the cathode.

[0161] The driver transistor DT has a driver gate electrode GE, a driver source electrode SE, and a driver drain electrode DE. The driver gate electrode GE is connected to a node between the first capacitor C1 and the third capacitor C3, the driver source electrode SE is connected to the cathode of the light-emitting diode LED, and the driver drain electrode DE is connected to a fourth source electrode of the fourth transistor T4.

[0162] The first capacitor C1 has multiple capacitor electrodes. Some of the multiple capacitor electrodes are connected to the driver gate electrode GE, and the others may be connected to the second transistor T2. The first capacitor C1 maintains the voltage of the driver gate electrode GE constant to supply a constant drive current to the light-emitting diode LED.

[0163] The second capacitor C2 is a capacitor formed between the high-potential power line VDD and the third capacitor C3. The second capacitor C2 includes a capacitor electrode connected to the high-potential power line VDD and a capacitor electrode connected to the third capacitor C3. The second capacitor C2 increases the intrinsic capacitance of the LED to emit light with higher luminance from the LED.

[0164] The third capacitor C3 is a capacitor formed between the first capacitor C1 and the second capacitor C2, and between the driving gate electrode GE and the driving source electrode SE. The third capacitor C3 includes a capacitor electrode connected to the first capacitor C1 and a capacitor electrode connected to the second capacitor C2. The third capacitor C3, connected in series with the first capacitor C1, is coupled to the first capacitor C1, and a part of the data voltage from the second drain electrode is transmitted to the driving gate electrode GE according to a capacitance ratio between the first capacitor C1 and the third capacitor C3. Therefore, a transmission rate of the data voltage transmitted to the driving gate electrode GE is reduced by means of the third capacitor C3.Furthermore, when the light-emitting diode LED is configured as a micro-LED having a large slope of the IV curve, the transmission rate of the data voltage is reduced using the third capacitor C3 to display finer gray levels.

[0165] The light-emitting diode (LED) has an anode and a cathode. The anode is connected to a source electrode of the first enable transistor ET1 or the second enable transistor ET2, and the cathode is connected to the driver transistor DT. The light-emitting diode (LED) of the first pixel region UPA1 is arranged between the first enable transistor ET1 and the driver transistor DT, and the light-emitting diode (LED) of the second pixel region UPA2 can be arranged between the second enable transistor ET2 and the driver transistor DT.

[0166] Furthermore, a plurality of enable transistors ET1 and ET2, which selectively supply a drive current to the light-emitting diode LED according to a high-resolution mode and a low-resolution mode, may be arranged in respective ones of the plurality of subpixels SP. For example, the first enable transistor ET1 is connected between the light-emitting diode LED and the pixel circuit PC in the subpixel SP of the first pixel region UPA1, and the second enable transistor ET2 may be connected between the light-emitting diode LED and the pixel circuit PC in the subpixel SP of the second pixel region UPA2. The first enable transistor ET1 is turned on or off to selectively supply a drive current to the light-emitting diode LED of the first pixel region UPA1. Furthermore, the second enable transistor ET2 is turned on or off to selectively supply a drive current to the light-emitting diode LED of the second pixel region UPA2.

[0167] The first enable transistor ET1 is used to control whether the subpixel SP of the first pixel region UPA1 should be driven. The first enable transistor ET1, which is arranged in the subpixel SP of the first pixel region UPA1, has a first enable gate electrode, a first enable source electrode, and a first enable drain electrode.

[0168] For example, in a common cathode structure, as in Fig. As shown in Figure 6, the first enable source electrode and the first enable drain electrode of the first enable transistor ET1 are connected between the light-emitting diode LED and the pixel circuit PC, and the first enable gate electrode may be connected to a first enable line EN1. Therefore, the turned-on first enable transistor ET1 connects the pixel circuit PC and the anode of the light-emitting diode LED in the first pixel region UPA1 to allow the drive current to flow to the light-emitting diode LED.

[0169] In the common anode structure as used in Fig. For example, as shown in Figure 7, the first enable source electrode and the first enable drain electrode of the first enable transistor ET1 may be connected between the high-potential power line VDD and the light-emitting diode LED. The turned-on first enable transistor ET1 connects the high-potential power line VDD and the light-emitting diode LED in the first pixel region UPA1 to allow the drive current to flow to the light-emitting diode LED.

[0170] The second enable transistor ET2 is used to control whether the subpixel SP of the second pixel region UPA2 should be driven. The second enable transistor ET2, which is arranged in the subpixel SP of the second pixel region UPA2, has a second enable gate electrode, a second enable source electrode, and a second enable drain electrode.

[0171] For example, in the common cathode structure, as in Fig. As shown in Figure 6, the second enable source electrode and the second enable drain electrode of the second enable transistor ET2 are connected between the light-emitting diode LED and the pixel circuit PC, and the second enable gate electrode may be connected to a second enable line EN2. Therefore, the turned-on second enable transistor ET2 connects the pixel circuit PC and the anode of the light-emitting diode LED in the second pixel region UPA2 to allow the drive current to flow to the light-emitting diode LED.

[0172] For example, in the common anode structure, as in Fig. As shown in Figure 7, the second enable source electrode and the second enable drain electrode of the second enable transistor ET2 are connected between the high-potential power line VDD and the light-emitting diode LED. The turned-on second enable transistor ET2 connects the high-potential power line VDD and the light-emitting diode LED in the second pixel region UPA2 to allow the drive current to flow to the light-emitting diode LED.

[0173] Meanwhile, in the drawing, it is shown that the first enable transistor ET1 is connected to the light-emitting diode LED of the first pixel area UPA1, but the first enable transistor ET1 may be omitted in the first pixel area UPA1, which is always driven in both the high-resolution mode and the low-resolution mode.

[0174] Finally, the welding transistor WT is arranged, which connects a subpixel SP of the first pixel area UPA1 and a subpixel SP of the second pixel area UPA2. The welding transistor WT can connect the nodes between the light-emitting diodes LEDs of the first pixel area UPA1 and the second pixel area UPA2 and the driver transistor DT.

[0175] In detail, the welding transistor WT has a welding gate electrode, a welding source electrode WSE and a welding drain electrode WDE.

[0176] For example, in the common cathode structure using the N-type transistor, as shown in Fig. 6, the welding gate electrode is connected to the welding control line WCL. Further, the welding source electrode WSE is connected to the first enable drain electrode of the first enable transistor ET1, which is a drive source electrode SE of the first pixel region UPA1. The welding drain electrode WDE may be connected to the drive source electrode SE and the second enable drain electrode of the second pixel region UPA2. When the welding transistor WT is turned on, the drive current of the second pixel region UPA2 may be transferred to a node between the drive source electrode SE and the first enable transistor ET1 of the first pixel region UPA1, and a high current may be supplied to the light-emitting diode LED.

[0177] In the common anode structure where the P-type transistor is used, as in Fig. For example, as shown in Figure 7, the welding gate electrode is connected to the welding control line WCL. The welding source electrode WSE is connected to a node between the cathode of the light-emitting diode LED of the second pixel region UPA2 and the driver transistor DT. The welding drain electrode WDE may be connected to a node between the cathode of the light-emitting diode LED and the driver transistor DT of the first pixel region UPA1. When the welding transistor WT is turned on, a drive current path of the second pixel region UPA2 is connected to the light-emitting diode LED of the first pixel region UPA1 to allow a high current to flow to the light-emitting diode LED of the first pixel region UPA1.

[0178] With reference to Fig. 8, the plurality of enable transistors ET1 and ET2 connected to a respective pixel circuit PC drive the display device 100 in one of the high-resolution mode and the low-resolution mode using the plurality of enable transistors ET1 and ET2 connected to a respective pixel circuit PC and the welding transistor.

[0179] In the high-resolution mode, the subpixels of the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 can be driven. Further, in the low-resolution mode, only the subpixel SP of the plurality of first pixel regions UPA1 among the subpixels of the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 can be driven, but the subpixel SP of the plurality of second pixel regions UPA2 among the subpixels of the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 is not driven. Further, in the low-resolution mode, the drive current generated in the pixel circuit PC of the subpixel SP of the plurality of second pixel regions UPA2 is supplied to the light-emitting diodes LED of the plurality of first pixel regions UPA1 to improve the luminance.

[0180] In the pixel circuit PC of Fig. 6, for example, in the high-resolution mode, an off-level voltage is applied to the welding control line WCL. The welding transistor WT is turned off by an off-level voltage from the welding control line WCL, and the pixel circuit PC of the first pixel region UPA1 and that of the second pixel region UPA2 can be disconnected. The welding transistor WT is turned off to interrupt a current path between the pixel circuit PC of the first pixel region UPA1 and the pixel circuit PC of the second pixel region UPA2. Therefore, the drive current generated in the pixel circuit PC of the first pixel region UPA1 is supplied only to the light-emitting diode LED of the first pixel region UPA1, and the drive current generated in the pixel circuit PC of the second pixel region UPA2 can be supplied only to the light-emitting diode LED of the second pixel region UPA2.

[0181] Furthermore, in the high-resolution mode, the turn-on voltage can be applied to both the first enable line EN1 and the second enable line EN2. The first enable transistor ET1 of the first pixel region UPA1 is turned on by the turn-on voltage from the first enable line EN1, and thus the drive current path between the pixel circuit PC and the light-emitting diode LED in the first pixel region UPA1 can be formed. The second enable transistor ET2 of the second pixel region UPA2 is turned on by the turn-on voltage from the second enable line EN2, and thus the drive current path between the pixel circuit PC and the light-emitting diode LED in the second pixel region UPA2 can be formed.

[0182] Therefore, in the high-resolution mode, the welding transistor WT is turned off and the first enable transistor ET1 and the second enable transistor ET2 are turned on to drive both the subpixel SP of the first pixel area UPA1 and the subpixel SP of the second pixel area UPA2.

[0183] In contrast, in the low-resolution mode, the turn-on voltage can be applied to the welding control line WCL. The welding transistor WT is turned on by a turn-on voltage from the welding control line WCL, and the pixel circuit PC of the first pixel region UPA1 and the pixel circuit PC of the second pixel region UPA2 can be connected to each other. The welding transistor WT is turned on to form a current path between the pixel circuit PC of the first pixel region UPA1 and the pixel circuit PC of the second pixel region UPA2. Therefore, the drive current generated in the second pixel region UPA2, which is configured not to emit light in the low-resolution mode, is not supplied to the light-emitting diode LED of the second pixel region UPA2 and can be supplied to the light-emitting diode LED of the first pixel region UPA1.

[0184] Furthermore, in the low-resolution mode, the on-level voltage is applied to the first enable line EN1, but the off-level voltage may be applied to the second enable line EN2. The first enable transistor ET1 of the first pixel region UPA1 is turned on by the on-level voltage from the first enable line EN1, and thus the drive current path between the pixel circuit PC and the light-emitting diode LED in the first pixel region UPA1 can be formed. The second enable transistor ET2 of the second pixel region UPA2 can be turned off by the off-level voltage from the second enable line EN2, and thus the drive current path between the pixel circuit PC and the light-emitting diode LED in the second pixel region UPA2 can be interrupted.That is, although the driving current is generated in the pixel circuit PC of the second pixel region UPA2, the driving current cannot be supplied to the light-emitting diode LED of the second pixel region UPA2.

[0185] Therefore, in the low resolution mode, the welding transistor WT and the first enable transistor ET1 are turned on and the second enable transistor ET2 is turned off to operate so that the subpixel SP of the second pixel area UPA2 does not display an image, but only the subpixel SP of the first pixel area UPA1 displays an image.

[0186] In Fig. 8, it is assumed that the welding transistor WT, the first enabling transistor ET1 and the second enabling transistor ET2 are N-type transistors, as in Fig. 6 to represent a high-level voltage as the on-level voltage and a low-level voltage as the off-level voltage. However, if the welding transistor WT, the first enable transistor ET1, and the second enable transistor ET2 are P-type transistors, as shown in Fig. As shown in Figure 7, the high level voltage is used as the off level voltage and the low level voltage is used as the on level voltage to select the high resolution mode and the low resolution mode.

[0187] Meanwhile, a plurality of display devices 100 according to the exemplary embodiment of the present disclosure are connected to each other to form a tile display device TD. Therefore, a plurality of display devices 100 having a certain size and resolution can be connected in accordance with a specification such as a size and resolution of the tile display device TD. However, when the size and resolution of the tile display device TD are changed, the display device 100 configuring the tile display device TD also needs to be designed to have a different specification. However, in the display device 100 according to the exemplary embodiment of the present disclosure, some subpixels SP are selectively driven to easily adjust a resolution of the display device 100.For example, a plurality of display devices 100 that drive all the subpixels SP of the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 to operate in a high-resolution mode are connected to form a tile display device TD having a specific resolution. To form a tile display device TD having a lower resolution than the specific resolution, a plurality of display devices 100 that operate in a low-resolution mode by driving only the subpixels SP in the plurality of first pixel regions UPA1 but not driving the subpixels SP in the plurality of second pixel regions UPA2 may be further connected. Therefore, a tile display device TD having different specifications can be formed using a display device 100 that adjusts the resolution by selectively driving the plurality of subpixels SP.Furthermore, it is not necessary to redesign the display device 100 for each tile display device TD of different models, and the design and process of the display device 100 can be unified to reduce the manufacturing cost and process time and optimize the process.

[0188] In the display device 100 according to the exemplary embodiment of the present disclosure, the plurality of first pixel regions UPA1 and the plurality of second pixel regions UPA2 are selectively driven to display an image in one of the high-resolution mode and the low-resolution mode. A resolution may vary depending on the density of the pixels PX, and the larger the number of pixels PX in the same region, the higher the resolution of the image to be displayed. Therefore, in the high-resolution mode, all the pixels PX included in the display device 100, e.g., both a pixel PX of the first pixel region UPA1 and a pixel PX of the second pixel region UPA2, are driven to display an image with high resolution. In contrast, in the low-resolution mode, only some of the plurality of pixels PX included in the display device 100, e.g.,Pixels in the first pixel area UPA1 are driven to display an image, but this is not limited to, for example, only pixels in the second pixel area UPA2 are driven to display an image. Accordingly, the display device 100 having a specification capable of displaying a high-resolution image can be used in the same way as the one used to display a low-resolution image. Therefore, there is no need to design and manufacture a new display device 100 having a specification that only displays a low-resolution image; instead, the existing high-resolution display device 100 is used, so that the manufacturing cost and process time can be reduced.

[0189] In the display device 100 according to the exemplary embodiment of the present disclosure, the luminance of the display device 100 can be improved in the low-resolution mode. In the low-resolution mode, only the pixel PX of the first pixel region UPA1 emits light to display the image, but the pixel PX of the second pixel region UPA2 does not emit light. At this time, various signals are applied to the second pixel region UPA2 in the same way to also generate a driving current in the pixel circuit PC of the second pixel region UPA2. The generated driving current flows to the light-emitting diode LED of the first pixel region UPA1 to supply a high current to the light-emitting diode LED of the first pixel region UPA1.Specifically, the welding transistor WT, which connects the pixel circuits PC of the first pixel region UPA1 and the second pixel region UPA2, is configured to pass a drive current generated in the pixel circuit PC of the second pixel region UPA2 to the first pixel region UPA1. Furthermore, the second enabling transistor ET2 is connected to the light-emitting diode LED of the second pixel region UPA2, so that the light-emitting diode LED of the second pixel region UPA2 cannot emit light. In this case, a large current can be supplied to the light-emitting diode LED while the range of various voltages applied to the display device is the same as in the related art.Therefore, in the low-resolution mode, both a drive current from the pixel circuit PC of the first pixel region UPA1 and a drive current from the pixel circuit PC of the second pixel region UPA2 are supplied to the light-emitting diode LED of the first pixel region UPA1. Therefore, the high current is supplied to the light-emitting diode LED of the first pixel region UPA1, and the luminance of the display device 100 can be improved.

[0190] Fig. 9 is an enlarged plan view of a display panel of a display device according to another exemplary embodiment of the present disclosure. Fig. 10 and Fig. 11 are exemplary circuit diagrams of a pixel circuit of a subpixel of a display device according to another exemplary embodiment of the present disclosure. Fig. 12 is a control timing diagram of a display device according to another exemplary embodiment of the present disclosure. A display device 900 of Fig. 9 to Fig. 12 is essentially the same as the display device 100 of Fig. 1 to Fig. 8, except that a light-emitting diode (LED) is not transferred to the second pixel area UPA2, and the first enable transistor ET1 and the second enable transistor ET2 are not arranged. Therefore, redundant description is omitted.

[0191] With reference to Fig. 9, in the display device 900 in which the plurality of pixel regions UPA are designed based on the high resolution, the light-emitting diode LED is transferred only to some of the pixel regions UPA to form a display device 900 exclusively for a low resolution mode. For example, after the pixel circuit PC, the plurality of reflection plates RF, and the adhesive layer 117 are completely formed in the plurality of pixel regions UPA, the plurality of light-emitting diodes LED are transferred to the adhesive layer 117. At this time, the light-emitting diode LED is transferred to the plurality of first pixel regions UPA1, and the light-emitting diode LED is not transferred to the plurality of second pixel regions UPA2. Accordingly, the pixel circuit PC is formed in the plurality of second pixel regions UPA2, but the light-emitting diode LED is not transferred, so the light is not emitted.For example, the pixel circuit PC and the light-emitting diode LED are provided in the plurality of first pixel regions UPA1, the pixel circuit PC is provided in the plurality of second pixel regions UPA2, but the light-emitting diode LED is provided in the plurality of second pixel regions UPA2.

[0192] Furthermore, the display device 900 according to another exemplary embodiment of the present disclosure can be operated in a low grayscale mode or a high grayscale mode. In the low grayscale mode, the light-emitting diode LED is driven only by the pixel circuit PC of the first pixel region UPA1, and in the high grayscale mode, both the pixel circuit PC of the first pixel region UPA1 and the pixel circuit PC of the second pixel region UPA2 are used to drive the light-emitting diode LED of the first pixel region UPA1. The grayscale expresses a difference in color concentration by steps, and at the low level of the grayscale, a relatively dark image is displayed, while at the high level of the grayscale, a relatively bright image can be displayed.Therefore, when an image to be displayed is a low grayscale image, only a driving current is supplied from the pixel circuit PC of the first pixel region UPA1 to the light-emitting diode LED to operate the display device 900 in a low grayscale mode. When the image to be displayed is a high grayscale image, all the driving currents from the pixel circuits PC of the first pixel region UPA1 and the second pixel region UPA2 are supplied to the light-emitting diode LED, so that the light-emitting diode LED is supplied with a high current to emit light with high luminance. Therefore, the display device 900 can operate in a high grayscale mode.

[0193] Referring to Fig. 10, for example, the pixel circuit PC has a 3T1 C structure, and the light-emitting diode LED is connected to the pixel circuit PC in a common-cathode manner. At this time, a pixel circuit PC and a light-emitting diode LED connected between the pixel circuit PC and the low-potential power line VSS are arranged in the subpixel SP of the first pixel region UPA1. Furthermore, in the subpixel SP of the second pixel region UPA2, the pixel circuit PC having a 3T1 C structure is arranged, but the light-emitting diode LED is not arranged.

[0194] Furthermore, a welding transistor WT is arranged, which connects the pixel circuit PC of the first pixel region UPA1 and the pixel circuit PC of the second pixel region UPA2. A welding source electrode WSE and a welding drain electrode WDE of the welding transistor WT can be connected to the same node of the pixel circuit PC of the first pixel region UPA1 and that of the second pixel region UPA2. The welding source electrode WSE and the welding drain electrode WDE can be connected to the node between the driver transistor DT and the light-emitting diode LED. For example, the welding source electrode WSE is connected to the node of the driver source electrode SE of the driver transistor DT of the first pixel region UPA1, and the welding drain electrode WDE is connected to the node of the driver source electrode SE of the driver transistor DT of the second pixel region UPA2.That is, the welding source electrode WSE and the welding drain electrode WDE can be connected to a path between the pixel circuit PC and the light-emitting diode LED through which a driving current flows.

[0195] Referring to Fig. 11, as another example, the pixel circuit PC has a 7T3C structure, and the light-emitting diode LED is connected to the pixel circuit PC in a common anode manner. At this time, a pixel circuit PC and a light-emitting diode LED connected between the pixel circuit PC and the low-potential power line VSS are arranged in the subpixel SP of the first pixel region UPA1. Furthermore, in the subpixel SP of the second pixel region UPA2, the pixel circuit PC having a 7T3C structure is arranged, but the light-emitting diode LED is not arranged.

[0196] Furthermore, a welding transistor WT is arranged, which connects the pixel circuit PC of the first pixel region UPA1 and the pixel circuit PC of the second pixel region UPA2. A welding source electrode WSE and a welding drain electrode WDE of the welding transistor WT can be connected to the same node of the pixel circuit PC of the first pixel region UPA1 and that of the second pixel region UPA2. The welding source electrode WSE and the welding drain electrode WDE can be connected to the node between the driver transistor DT and the light-emitting diode LED. For example, the welding drain electrode WDE is connected to the node of the driver source electrode SE of the driver transistor DT of the first pixel region UPA1, and the welding source electrode WSE can be connected to the node of the driver source electrode SE of the driver transistor DT of the second pixel region UPA2.That is, the welding source electrode WSE and the welding drain electrode WDE can be connected to a path between the pixel circuit PC and the light-emitting diode LED, through which a drive current flows. Therefore, the welding transistor WT is turned on to transfer the drive current from the pixel circuit PC of the second pixel region UPA2 to the light-emitting diode LED of the first pixel region UPA1.

[0197] The pixel circuit PC from Fig. 10 is described as an example. In the low grayscale mode, the welding transistor WT is turned off to isolate the pixel circuit PC of the second pixel area UPA2 and the light-emitting diodes LED of the first pixel area UPA1. For example, in Fig. 10 and Fig. 12, in the low grayscale mode, the off-level voltage is applied to the welding control line WCL to turn off the welding transistor WT. Therefore, the light-emitting diode LED of the first pixel area UPA1 is supplied with only the drive current from the pixel circuit PC of the first pixel area UPA1, but not with the drive current from the pixel circuit PC of the second pixel area UPA2 to emit light.

[0198] Furthermore, in the high grayscale mode, the welding transistor WT is turned on to connect the pixel circuit PC of the second pixel area UPA2 and the light-emitting diode LED of the first pixel area UPA1. Fig. 10 and Fig. 12, for example, in the high grayscale mode, the on-level voltage is applied to the welding control line WCL to turn on the welding transistor WT. Therefore, the light-emitting diode LED of the first pixel region UPA1 is supplied with both the drive current from the pixel circuit PC of the first pixel region UPA1 and the drive current from the pixel circuit PC of the second pixel region UPA2 to emit light. That is, the light-emitting diode LED of the first pixel region UPA1 is supplied with the high current from the pixel circuit PC of the first pixel region UPA1 and the pixel circuit PC of the second pixel region UPA2 to emit light with a high luminance. Therefore, the display device 900 can easily display a relatively bright image with a high grayscale.

[0199] Meanwhile, in Fig. 12, assume that the welding transistor WT is an N-type transistor to represent the high-level voltage as an on-level voltage and the low-level voltage as an off-level voltage. However, if the welding transistor is a P-type transistor, as in Fig. As shown in Figure 11, the high level voltage is used as the off level voltage and the low level voltage is used as the on level voltage to select the high gray scale mode and the low gray scale mode.

[0200] In the display device 900 according to another exemplary embodiment of the present disclosure, the display device 900 designed based on high resolution is used to implement a low-resolution display device 900. Specifically, in the display device 100 in which the plurality of pixel regions UPA are designed based on high resolution, when the light-emitting diode LED is transferred, the light-emitting diode LED is transferred only to some of the pixel regions UPA to form a display device 900 exclusively for a low-resolution mode. Therefore, a manufacturing process of a display device 900 exclusively for a high-resolution mode and a display device 900 exclusively for a low-resolution mode is performed in one process line, so that the process is unified.Furthermore, there is no need to develop a display device 900 exclusively for a low-resolution mode, so that the manufacturing cost and process time are reduced.

[0201] In the display device 900 according to another exemplary embodiment of the present disclosure, the pixel circuit PC of the pixel region UPA, into which the light-emitting diode LED is not transferred, is additionally connected to the light-emitting diode LED to supply a large current to the light-emitting diode LED. A range of a driving current generated in a pixel circuit PC is limited, so it is difficult to realize a predetermined level or higher of luminance of the light that can be emitted from the light-emitting diode connected to a pixel circuit. A low-grayscale image can be easily displayed, but to display a high-grayscale image that is relatively bright, a large current must be supplied to the light-emitting diode LED.Therefore, in the high grayscale mode, the welding transistor WT is used to connect the pixel circuit PC of the second pixel area UPA2, into which the LED is not transferred, to the LED of the first pixel area UPA1. The LED is connected to both the pixel circuits PC of the first pixel area UPA1 and the second pixel area UPA2 to be supplied with a high current and emit light with a high luminance. Accordingly, the pixel circuit PC of the pixel area UPA, into which the LED is not transferred, is temporally connected to the LED in the high grayscale mode to supply a high current to the LED, thereby easily displaying a high grayscale image.

[0202] The exemplary embodiments of the present disclosure may also be described as follows:

[0203] According to an exemplary embodiment of the present disclosure, a display device includes: a display panel in which a plurality of first pixel regions and a plurality of second pixel regions each having a plurality of sub-pixels are defined, a pixel circuit arranged in each of the plurality of sub-pixels and having a driving transistor, and a welding transistor selectively connecting the pixel circuit of a first pixel region and that of a second pixel region adjacent to each other among the plurality of first pixel regions and the plurality of second pixel regions.

[0204] The welding transistor according to an exemplary embodiment of the present disclosure may be arranged between the pixel circuit of the first pixel region and the pixel circuit of the second pixel region, and may selectively control a connection or disconnection between the pixel circuit of the first pixel region and the pixel circuit of the second pixel region.

[0205] The welding transistor according to an exemplary embodiment of the present disclosure may be arranged between the pixel circuit of the first pixel region and the pixel circuit of the second pixel region and may selectively control the display panel to operate in a high-resolution mode or a low-resolution mode.

[0206] The display device according to an exemplary embodiment of the present disclosure may further include a reflection plate disposed in each of the plurality of subpixels and electrically connected to the driver transistor of the pixel circuit.

[0207] The welding transistor according to an exemplary embodiment of the present disclosure may be arranged between the reflection plate of the first pixel region and the reflection plate of the second pixel region, and may selectively control a connection or disconnection between the reflection plate of the first pixel region and the reflection plate of the second pixel region.

[0208] The display device according to an exemplary embodiment of the present disclosure may further include a light-emitting diode arranged in at least some of the plurality of subpixels to be connected to the driver transistor of the pixel circuit. A welding source electrode or a welding drain electrode of the welding transistor may be connected to a node between the driver transistor and the light-emitting diode.

[0209] According to an exemplary embodiment of the present disclosure, in a high-resolution mode in which the display panel displays a high-resolution image, the light-emitting diodes of the plurality of first pixel regions and the light-emitting diodes of the plurality of second pixel regions may emit light, and in a low-resolution mode in which the display panel displays a low-resolution image, the light-emitting diodes of the plurality of first pixel regions may emit light and the light-emitting diodes of the plurality of second pixel regions may not emit light.

[0210] The display device according to an exemplary embodiment of the present disclosure may further include: a first enable transistor disposed in each of the plurality of subpixels of the plurality of first pixel regions and connected between the driver transistor and the light-emitting diode; and a second enable transistor disposed in each of the plurality of subpixels of the plurality of second pixel regions and connected between the driver transistor and the light-emitting diode. The welding transistor may selectively connect a node between the first enable transistor and the driver transistor and a node between the second enable transistor and the driver transistor.

[0211] According to an exemplary embodiment of the present disclosure, a source electrode of the first enable transistor may be connected to a driver drain electrode of the driver transistor, and a drain electrode of the first enable transistor may be connected to an anode of the light-emitting diode, and a source electrode of the second enable transistor may be connected to a driver drain electrode of the driver transistor, and a drain electrode of the second enable transistor may be connected to an anode of the light-emitting diode.

[0212] The display device according to an exemplary embodiment of the present disclosure may further include: a first enable transistor disposed in each of the plurality of subpixels of the plurality of first pixel regions and connected between the light-emitting diode and a high-potential power line; and a second enable transistor disposed in each of the plurality of subpixels of the plurality of second pixel regions and connected between the light-emitting diode and the high-potential power line. The welding transistor may selectively connect a node between the light-emitting diode of each of the plurality of subpixels of the plurality of first pixel regions and the driver transistor, and a node between the light-emitting diode of each of the plurality of subpixels of the plurality of second pixel regions and the driver transistor.

[0213] According to an exemplary embodiment of the present disclosure, in the low resolution mode, a drive current may be supplied from the pixel circuits of the plurality of second pixel regions to the light-emitting diodes of the plurality of first pixel regions.

[0214] According to an exemplary embodiment of the present disclosure, in high resolution mode, the first enable transistor and the second enable transistor may be turned on and the welding transistor may be turned off, and in low resolution mode, the first enable transistor and the welding transistor may be turned on and the second enable transistor may be turned off.

[0215] According to an exemplary embodiment of the present disclosure, the light-emitting diode may be transferred to a plurality of subpixels of the plurality of first pixel regions, but may not be transferred to a plurality of subpixels of the plurality of second pixel regions.

[0216] In a high grayscale mode in which the display panel displays a high grayscale image, the light-emitting diodes of the plurality of first pixel regions may be supplied with a driving current from the pixel circuits of the plurality of first pixel regions and the pixel circuits of the plurality of second pixel regions, and in a low grayscale mode in which the display panel displays a low grayscale image, the light-emitting diodes of the plurality of first pixel regions may be supplied with a driving current from the pixel circuits of the plurality of first pixel regions.

[0217] In the low grayscale mode, the light-emitting diodes of the plurality of first pixel regions are not supplied with a driving current from the pixel circuits of the plurality of second pixel regions.

[0218] In the high grayscale mode, the welding transistor may be turned on and electrically connect an anode of the light-emitting diode of the plurality of first pixel regions and the driver transistor of the pixel circuit of the plurality of second pixel regions, and in the low grayscale mode, the welding transistor may be turned off and disconnect the anode of the light-emitting diode of the plurality of first pixel regions from the driver transistor of the pixel circuit of the plurality of second pixel regions.

[0219] According to an exemplary embodiment of the present disclosure, a display device comprises: a substrate in which a plurality of first pixel regions and a plurality of second pixel regions each having a plurality of subpixels are defined; a plurality of pixel circuits arranged in respective ones of the plurality of subpixels on the substrate, each of the plurality of pixels having a driver transistor; a plurality of reflection plates arranged in respective ones of the plurality of subpixels on the plurality of pixel circuits and electrically connected to the driver transistor of a respective one of the plurality of pixel circuits; and a plurality of welding transistors arranged between the plurality of first pixel regions and the plurality of second pixel regions, the plurality of welding transistors selectively connecting the plurality of reflection plates of the plurality of first pixel regions and the plurality of reflection plates of the plurality of second pixel regions.

[0220] The display device may further include a plurality of light-emitting diodes arranged on the plurality of reflection plates in at least some subpixels of the plurality of subpixels. A respective one of the plurality of light-emitting diodes may be electrically connected to the driver transistor via a respective one of the plurality of reflection plates.

[0221] The plurality of subpixels may include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel. The plurality of reflection plates may include: a first reflection plate disposed in the first subpixel, a second reflection plate disposed in the second subpixel, a third reflection plate disposed in the third subpixel, and a fourth reflection plate disposed in the fourth subpixel. Each of the plurality of welding transistors may include the first reflection plates of the plurality of first pixel regions and the first reflection plates of the plurality of second pixel regions, the second reflection plates of the plurality of first pixel regions and the second reflection plates of the plurality of second pixel regions, the third reflection plates of the plurality of first pixel regions and the third reflection plates of the plurality of second pixel regions, respectively.connect the fourth reflection plates of the plurality of first pixel regions and the fourth reflection plates of the plurality of second pixel regions.

[0222] In a high-resolution mode, the welding transistor may be turned off and electrically separate a respective one of the plurality of reflection plates of the plurality of first pixel regions and a respective one of the plurality of reflection plates of the plurality of second pixel regions, and in a low-resolution mode, the welding transistor may be turned on and electrically connect a respective one of the plurality of reflection plates of the plurality of first pixel regions and a respective one of the plurality of reflection plates of the plurality of second pixel regions.

[0223] The display device may further comprise a plurality of first enable transistors connected to the plurality of light-emitting diodes of the plurality of first pixel regions, and a plurality of second enable transistors connected to the plurality of light-emitting diodes of the plurality of second pixel regions. In the high-resolution mode, the plurality of first enable transistors and the plurality of second enable transistors may be turned on to connect a path through which a drive current is supplied to the plurality of light-emitting diodes, and in the low-resolution mode, the enable transistors arranged in the plurality of second pixel regions may be turned off to disconnect a path through which the drive current is supplied to the plurality of light-emitting diodes of the plurality of second pixel regions.

[0224] The plurality of light-emitting diodes may be arranged only in the plurality of first pixel regions between the plurality of first pixel regions and the plurality of second pixel regions; in a low grayscale mode, the welding transistor may be turned off to electrically separate a respective one of the plurality of reflection plates of the plurality of first pixel regions and a respective one of the plurality of reflection plates of the plurality of second pixel regions; and in a high grayscale mode, the welding transistor may be turned on to electrically connect a respective one of the plurality of reflection plates of the plurality of first pixel regions and a respective one of the plurality of reflection plates of the plurality of second pixel regions.

[0225] The plurality of light-emitting diodes are not arranged in the plurality of second pixel regions between the plurality of first pixel regions and the plurality of second pixel regions.

[0226] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. It should therefore be understood that the exemplary embodiments described above are illustrative in all aspects and do not limit the present disclosure.

Claims

[1] Display device (100) comprising: a display panel (PN) in which a plurality of first pixel areas (UPA1) and a plurality of second pixel areas (UPA2), each having a plurality of subpixels (SP), are defined; a pixel circuit (PC) arranged in a respective one of the plurality of subpixels (SP), the pixel circuit (PC) comprising a driver transistor (DT); and a welding transistor (WT) that selectively connects the pixel circuits (PC) of the plurality of first pixel regions (UPA1) and the plurality of second pixel regions (UPA2) that are adjacent to each other among the plurality of first pixel regions (UPA1) and the plurality of second pixel regions (UPA2). [2] The display device (100) according to claim 1, wherein the welding transistor (WT) is arranged between the pixel circuit (PC) of the first pixel region (UPA1) and the pixel circuit (PC) of the second pixel region (UPA2) and selectively controls a connection or disconnection between the pixel circuit (PC) of the first pixel region (UPA1) and the pixel circuit (PC) of the second pixel region (UPA2). [3] The display device (100) according to claim 1 or 2, wherein the welding transistor (WT) is arranged between the pixel circuit (PC) of the first pixel region (UPA1) and the pixel circuit (PC) of the second pixel region (UPA2) and selectively controls the display panel (PN) to operate in a high-resolution mode or in a low-resolution mode. [4] The display device (100) according to any one of claims 1 to 3, further comprising a reflection plate (RF) disposed in a respective one of the plurality of subpixels (SP) and electrically connected to the driver transistor (DT) of the pixel circuit (PC). [5] The display device (100) according to claim 4, wherein the welding transistor (WT) is arranged between the reflection plate (RF) of the first pixel region (UPA1) and the reflection plate (RF) of the second pixel region (UPA2) and selectively controls a connection or disconnection between the reflection plate (RF) of the first pixel region (UPA1) and the reflection plate (RF) of the second pixel region (UPA2). [6] Display device (100) according to one of claims 1 to 5, further comprising: a light-emitting diode (LED) arranged in at least some of the plurality of subpixels (SP) to be connected to the driver transistor (DT) of the pixel circuit (PC), wherein a welding source electrode (WSE) or a welding drain electrode (WDE) of the welding transistor (WT) is connected to a node between the driver transistor (DT) and the light-emitting diode (LED). [7] The display device (100) according to claim 6, wherein in a high-resolution mode in which the display panel (PN) displays a high-resolution image, the light-emitting diodes (LED) of the plurality of first pixel areas (UPA1) and the light-emitting diodes (LED) of the plurality of second pixel areas (UPA2) emit light, and in a low-resolution mode in which the display panel (PN) displays a low-resolution image, the light-emitting diodes (LEDs) of the plurality of first pixel areas (UPA1) emit light and the light-emitting diodes (LEDs) of the plurality of second pixel areas (UPA2) do not emit light. [8] The display device (100) of claim 7, further comprising: a first enable transistor (ET1) arranged in a respective one of the plurality of subpixels (SP) of the plurality of first pixel regions (UPA1) and connected between the driver transistor (DT) and the light-emitting diode (LED); and a second enable transistor (ET2) arranged in a respective one of the plurality of subpixels (SP) of the plurality of second pixel regions (UPA2) and connected between the driver transistor (DT) and the light-emitting diode (LED), wherein the welding transistor (WT) selectively connects a node between the first enabling transistor (ET1) and the driving transistor (DT) and a node between the second enabling transistor (ET2) and the driving transistor (DT). [9] Display device (100) according to claim 8, wherein a source electrode of the first enable transistor (ET1) is connected to a driver drain electrode (DE) of the driver transistor (DT) and a drain electrode of the first enable transistor (ET1) is connected to an anode of the light-emitting diode (LED), and wherein a source electrode of the second enable transistor (ET2) is connected to a driver drain electrode (DE) of the driver transistor (DT), and a drain electrode of the second enable transistor (ET2) is connected to an anode of the light-emitting diode (LED). [10] The display device (100) of claim 7, further comprising: a first enable transistor (ET1) arranged in a respective one of the plurality of subpixels (SP) of the plurality of first pixel regions (UPA1) and connected between the light-emitting diode (LED) and a high-potential power line (VDD); and a second enable transistor (ET2) arranged in a respective one of the plurality of subpixels (SP) of the plurality of second pixel regions (UPA2) and connected between the light-emitting diode (LED) and the high-potential current line (VDD), wherein the welding transistor (WT) selectively connects a node between the light-emitting diode (LED) of a respective one of the plurality of subpixels (SP) of the plurality of first pixel regions (UPA1) and the driver transistor (DT) and a node between the light-emitting diode (LED) of a respective one of the plurality of subpixels (SP) of the plurality of second pixel regions (UPA2) and the driver transistor (DT). [11] The display device (100) according to claim 10, wherein in the low resolution mode, a drive current is supplied from the pixel circuits (PC) of the plurality of second pixel areas (UPA2) to the light-emitting diodes (LED) of the plurality of first pixel areas (UPA1). [12] The display device (100) according to claim 10 or 11, wherein in the high-resolution mode, the first enable transistor (ET1) and the second enable transistor (ET2) are turned on and the welding transistor (WT) is turned off, and in the low resolution mode, the first enable transistor (ET1) and the welding transistor (WT) are turned on and the second enable transistor (ET2) is turned off. [13] The display device (100) according to any one of claims 6 to 12, wherein the light-emitting diode (LED) is provided in the plurality of subpixels (SP) of the plurality of first pixel areas (UPA1), but is not provided in the plurality of subpixels (SP) of the plurality of second pixel areas (UPA2). [14] The display device (100) according to claim 13, wherein in a high grayscale mode in which the display panel (PN) displays a high grayscale image, the light-emitting diodes (LED) of the plurality of first pixel areas (UPA1) are supplied with a drive current from the pixel circuits (PC) of the plurality of first pixel areas (UPA1) and the pixel circuits (PC) of the plurality of second pixel areas (UPA2), and in a low grayscale mode in which the display panel (PN) displays a low grayscale image, the light-emitting diodes (LEDs) of the plurality of first pixel areas (UPA1) are supplied with a drive current from the pixel circuits (PC) of the plurality of first pixel areas (UPA1). [15] The display device (100) according to claim 14, wherein the light-emitting diodes (LED) of the plurality of first pixel areas (UPA1) are not supplied with a drive current from the pixel circuits (PC) of the plurality of second pixel areas (UPA2) in the low gray scale mode. [16] The display device (100) according to claim 14 or 15, wherein in the high gray scale mode, the welding transistor (WT) is turned on to electrically connect an anode of the light-emitting diode (LED) of the plurality of first pixel regions (UPA1) and the driver transistor (DT) of the pixel circuit (PC) of the plurality of second pixel regions (UPA2), and in the low grayscale mode, the welding transistor (WT) is turned off to separate the anode of the light-emitting diode (LED) of the plurality of first pixel areas (UPA1) from the driver transistor (DT) of the pixel circuit (PC) of the plurality of second pixel areas (UPA2). [17] Display device (100) comprising: a substrate (110) in which a plurality of first pixel regions (UPA1) and a plurality of second pixel regions (UPA2), each having a plurality of subpixels (SP), are defined; a plurality of pixel circuits (PC) on the substrate (110), each pixel circuit (PC) being arranged in an associated one of the plurality of subpixels (SP) and having a driver transistor (DT); a plurality of reflection plates (RF) on the plurality of pixel circuits (PC), each reflection plate (RF) being arranged in an associated one of the plurality of subpixels (SP) and being electrically connected to the driver transistor (DT) of an associated one of the plurality of pixel circuits (PC); and a plurality of welding transistors (WT) arranged between the plurality of first pixel regions (UPA1) and the plurality of second pixel regions (UPA2) and selectively connecting the plurality of reflection plates (RF) of the plurality of first pixel regions (UPA1) and the plurality of reflection plates (RF) of the plurality of second pixel regions (UPA2). [18] The display device (100) of claim 17, further comprising: a plurality of light-emitting diodes (LEDs) arranged on the plurality of reflection plates (RF) in at least some subpixels (SP) of the plurality of subpixels (SP), wherein a respective one of the plurality of light-emitting diodes (LED) is electrically connected to the driver transistor (DT) via a respective one of the plurality of reflection plates (RF). [19] The display device (100) according to claim 18, wherein the plurality of subpixels (SP) comprise a first subpixel (SP1), a second subpixel (SP2), a third subpixel (SP3) and a fourth subpixel (SP4), the plurality of reflection plates (RF) comprise: a first reflection plate (RF1) arranged in the first subpixel (SP1), a second reflection plate (RF2) arranged in the second subpixel (SP2), a third reflection plate (RF3) arranged in the third subpixel (SP3), and a fourth reflection plate (RF4) arranged in the fourth subpixel (SP4), and a respective one of the plurality of welding transistors (WT) connects in an associated manner: the first reflection plates (RF1) of the plurality of first pixel areas (UPA1) and the first reflection plates (RF1) of the plurality of second pixel areas (UPA2), the second reflection plates (RF2) of the plurality of first pixel areas (UPA1) and the second reflection plates (RF2) of the plurality of second pixel areas (UPA2), the third reflection plates (RF3) of the plurality of first pixel areas (UPA1) and the third reflection plates (RF3) of the plurality of second pixel areas (UPA2), and the fourth reflection plates (RF4) of the plurality of first pixel areas (UPA1) and the fourth reflection plates (RF4) of the plurality of second pixel areas (UPA2). [20] The display device (100) according to claim 19, wherein in a high-resolution mode, the welding transistor (WT) is turned off and electrically separates a respective one of the plurality of reflection plates (RF) of the plurality of first pixel regions (UPA1) and a respective one of the plurality of reflection plates (RF) of the plurality of second pixel regions (UPA2), and in a low resolution mode, the welding transistor (WT) is turned on and electrically connects a respective one of the plurality of reflection plates (RF) of the plurality of first pixel regions (UPA1) and a respective one of the plurality of reflection plates (RF) of the plurality of second pixel regions (UPA2). [21] The display device (100) of claim 20, further comprising: a plurality of first enable transistors (ET1) connected to the plurality of light-emitting diodes (LEDs) of the plurality of first pixel regions (UPA1); and a plurality of second enable transistors (ET2) connected to the plurality of light-emitting diodes (LEDs) of the plurality of second pixel areas (UPA2), wherein in the high-resolution mode, the plurality of first enable transistors (ET1) and the plurality of second enable transistors (ET2) are turned on and connect a path through which a drive current is supplied to the plurality of light-emitting diodes (LED), and in the low-resolution mode, the enable transistors arranged in the plurality of second pixel areas (UPA2) are switched off and interrupt a path via which the drive current is supplied to the plurality of light-emitting diodes (LEDs) of the plurality of second pixel areas (UPA2). [22] Display device (100) according to one of claims 19 to 21, wherein the plurality of light-emitting diodes (LED) are arranged in the plurality of first pixel regions (SP) among the plurality of first pixel regions (UPA1) and the plurality of second pixel regions (UPA2), in a low grayscale mode, the welding transistor (WT) is turned off and electrically separates a respective one of the plurality of reflection plates (RF) of the plurality of first pixel regions (UPA1) and a respective one of the plurality of reflection plates (RF) of the plurality of second pixel regions (UPA2), and in a high grayscale mode, the welding transistor (WT) is turned on and electrically connects a respective one of the plurality of reflection plates (RF) of the plurality of first pixel regions (UPA1) and a respective one of the plurality of reflection plates (RF) of the plurality of second pixel regions (UPA2). [23] The display device (100) according to any one of claims 18 to 22, wherein the plurality of light-emitting diodes (LED) are not arranged in the plurality of second pixel regions (UPA2) among the plurality of first pixel regions (UPA1) and the plurality of second pixel regions (UPA2).

Images