Thin-layer transistor substrate, method for its production and display device using it

Abstract

A thin-film transistor substrate for a display device can comprise a light-blocking layer arranged on a substrate, an active layer overlapping the light-blocking layer, a first lower hole penetrating the active layer, a gate electrode overlapping the active layer, a source electrode penetrating the active layer and contacting the light-blocking layer, an insulating layer arranged on the active layer, and a first upper hole penetrating the insulating layer. The source electrode also comprises a first lower electrode located in the first lower hole and a first upper electrode located in the first upper hole, the width of the first upper electrode being greater than the width of the first lower electrode.

Description

[0001] This application claims priority over Korean patent application No. 10-2023-0081683, which was filed in the Republic of Korea on June 26, 2023. BackgroundTechnical area

[0002] The present disclosure relates to a thin-film transistor substrate, a method for its fabrication and a display device that uses it. Description of the state of the art

[0003] Since thin-film transistors can be manufactured on glass or plastic substrates, they are frequently used as switching or driving elements of display devices such as liquid crystal displays or organic light-emitting devices.

[0004] Depending on the material of the active layer, thin-film transistors can be divided into amorphous silicon thin-film transistors, in which amorphous silicon is used as the active layer, polycrystalline silicon thin-film transistors, in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin-film transistors, in which oxide semiconductors are used as the active layers.

[0005] Among them, oxide semiconductor thin-film transistors (oxide semiconductor TFTs) have the advantage of easily achieving desired physical properties due to their high mobility and ability to exhibit a large resistance variation depending on the oxygen content. Furthermore, manufacturing costs are low because the oxide forming the active layer can be created at a relatively low temperature during the thin-film transistor fabrication process. The nature of the oxide also makes it advantageous to implement a transparent display device, as the oxide semiconductor itself is transparent.

[0006] Recently, pixel sizes have been further reduced to implement high-resolution displays. To implement such a display, it is desirable to minimize or reduce the size of the thin-film transistor within the pixel. To express the grayscale levels of the driver thin-film transistor for driving the pixel, a method for electrically connecting the active layer, the source electrode, and the light-blocking layer can be used, thereby increasing the capacitor size. However, in this situation, the size of the source electrode connecting the active layer and the light-blocking layer often presents challenges regarding the ability to provide sufficient space for implementing a high-resolution display.

[0007] Accordingly, there is a need for a thin-film transistor with a configuration that can better reduce the space requirement, while still being able to express good grayscale levels and offering more design freedom for the implementation of higher resolutions. Summary of Revelation

[0008] One or more of these problems are solved by the features of the independent claims. Further embodiments are specified below and in the dependent claims.

[0009] The present disclosure provides a thin-film transistor substrate with a thin-film transistor which can better reproduce grayscale levels by connecting the source electrode, an active layer and a light-blocking layer through a lower hole arranged in the active layer of the thin-film transistor, and a display device containing it.

[0010] According to one aspect of the present disclosure, a thin-film transistor substrate is provided comprising: a light-blocking layer arranged on a substrate; an active layer; a bottom hole in / on one side of the active layer and / or through the active layer; a gate electrode; a source electrode contacting or electrically connected to the active layer; and an insulating layer arranged on top of or between the active layer and the source electrode, wherein the insulating layer has a top hole, and wherein the source electrode has a bottom electrode located in the bottom hole and a top electrode located in the top hole. The active layer and the light-blocking layer may be electrically connected to each other through / by means of the bottom electrode.The area (or cross-sectional area) of a lower surface of the upper electrode can be larger than the area (or cross-sectional area) of an upper surface of the lower electrode, or the width of the (first) upper electrode can be larger than the width of the (first) lower electrode. The width of the (first) upper electrode in any direction parallel to the substrate can be larger than the width of the (first) lower electrode in the same direction. The maximum width of the (first) upper electrode can be greater than the maximum width of the (first) lower electrode.

[0011] The substrate can be the thin-film transistor substrate, or the thin-film transistor substrate can encompass the substrate. The active layer can be located on / above the light-blocking layer and / or the active layer can overlap with the light-blocking layer. The active layer can have the bottom hole. The active layer can have the bottom hole on one side of the active layer, or the bottom hole can extend through the active layer. The bottom hole can be a first bottom hole. The gate electrode can be located on the active layer and / or overlap with the active layer. The source electrode can be electrically connected to both the active layer and the light-blocking layer. The source electrode can extend through the active layer. The top hole can extend through the insulating layer. The top hole can be a first top hole. The bottom electrode can be a first bottom electrode.The lower electrode can be positioned in the lower hole in the active layer. The upper electrode can be a first upper electrode. The upper electrode can be positioned in the upper hole in the insulating layer. The upper surface of the lower electrode can be the upper end of the lower electrode. The lower surface of the upper electrode can be the lower end of the upper electrode.

[0012] According to another aspect of the present disclosure, a thin-film transistor substrate comprises a substrate, a light-blocking layer arranged on the substrate, an active layer arranged on the light-blocking layer and having a lower hole on one side, a gate electrode arranged on the active layer, a source electrode arranged on the gate electrode and electrically connected to the light-blocking layer, and an insulating layer arranged between the active layer and the source electrode and having an upper hole, wherein the source electrode has a lower electrode arranged in the lower hole and an upper electrode arranged in the upper hole.The area (or cross-sectional area) of a lower surface (end surface) of the upper electrode can be larger than the area (or cross-sectional area) of an upper surface (end surface) of the lower electrode.

[0013] According to another aspect of the present disclosure, a method for fabricating a thin-film transistor substrate comprises: a step for forming a light-blocking layer on the substrate, a step for forming an active layer on the light-blocking layer, and a step for forming an active hole in the active layer. The active hole can be formed in / on one side of the active layer. The method can include a step for forming a gate insulating layer on the active layer (in which the active hole can be formed), a step for forming a gate electrode on the gate insulating layer, and a step for forming an interlayer insulating layer on the gate electrode. The method can include a step for forming a top hole in (through) the interlayer insulating layer.The method may include a step to form a lower hole that exposes a portion of the light-blocking layer. The lower hole may be formed by enlarging the active hole, in particular by enlarging the active hole at its lower end. Thus, the lower hole may encompass the active hole. The active hole may also be referred to as the active layer hole. The method may include a step to form a source electrode within the lower hole and within the upper hole. The step to form an upper hole may be a step to form an upper hole in (or through) the gate insulating layer and the interlayer insulating layer. The thin-film transistor substrate may be a thin-film transistor substrate according to any of the aspects of the disclosure mentioned herein.According to another aspect of the present disclosure, a display device comprises: a substrate having a display region and a non-display region, a first thin-film transistor arranged on the substrate, and a second thin-film transistor. The second thin-film transistor may have a different structure than the first thin-film transistor. In particular, among the first and second thin-film transistors, only the first thin-film transistor may have a source electrode electrically connected to both the active layer of the transistor and a light-blocking layer. The display device may comprise the thin-film transistor substrate according to any of the aspects described herein, and the substrate thereof may be the substrate of the display device. The first thin-film transistor may comprise the active layer, the gate electrode, the source electrode, and / or the drain electrode.The first thin-film transistor can comprise a (first) light-blocking layer, a (first) active layer arranged on the (first) light-blocking layer and having a lower hole on one side thereof, a (first) gate electrode arranged on the (first) active layer, a (first) source electrode arranged on the (first) gate electrode and electrically connected to the (first) active layer and the (first) light-blocking layer, and an insulating layer arranged between the (first) active layer and the (first) source electrode and having an upper hole. The (first) source electrode can have a lower electrode located in the lower hole and an upper electrode located in the upper hole. The (first) active layer and the (first) light-blocking layer can be electrically connected through the lower electrode.The area (or cross-sectional area) of a lower surface of the upper electrode can be larger than the area (or cross-sectional area) of an upper surface of the lower electrode.

[0014] According to another aspect of the disclosure, a thin-film transistor substrate comprises: a light-blocking layer arranged on a substrate; an active layer overlapping the light-blocking layer; a first lower hole penetrating the active layer; a gate electrode overlapping the active layer; a source electrode penetrating the active layer and contacting the light-blocking layer; an insulating layer arranged on top of the active layer; and a first upper hole penetrating the insulating layer, the source electrode having a first lower electrode located in the first lower hole and a first upper electrode located in the first upper hole. The width of the first upper electrode may be greater than the width of the first lower electrode.

[0015] One or more of the aspects of the revelation described above may exhibit one or more of the following characteristics.

[0016] The upper hole and the lower hole can be connected.

[0017] The upper electrode can contact the entire upper surface of the lower electrode. The upper electrode can contact a section of an upper surface of the active layer. The upper electrode can contact a section of an upper surface of the active layer, with the upper end of the lower electrode located within that section.

[0018] The entire cross-sectional area of ​​the lower electrode can overlap with the upper electrode and / or be located within the outer boundaries of the active layer.

[0019] The distance from one end (or edge) of the lower surface of the upper electrode to the lower hole can be greater than the distance from another end (or edge) of the lower surface of the upper electrode to the lower hole.

[0020] In embodiments, a center (or midpoint) of the upper hole does not overlap with a center (or midpoint) of the lower hole.

[0021] The thin-film transistor substrate can comprise: a drain hole located in the insulating layer; and a drain electrode connected through the drain hole to one side of the active layer. The drain electrode can be located on top of or above the gate electrode. The size of the top hole can be larger than the size of the drain hole.

[0022] The thin-film transistor substrate can include: a gate insulating layer located between the active layer and the gate electrode. One end (or edge) of the gate insulating layer can correspond to one end (or edge) of the gate electrode, and another end (or edge) of the gate insulating layer can correspond to another (e.g., opposite) end (or edge) of the gate electrode. The insulating layer can include the gate insulating layer. The insulating layer can include an intermediate insulating layer. The intermediate insulating layer can contact a portion of an upper surface of the active layer. The intermediate insulating layer can contact a portion of an upper surface of the gate insulating layer.

[0023] The insulating layer can comprise: a gate insulating layer located between the active layer and the gate electrode, and an intermediate insulating layer located on top of the gate insulating layer. The gate insulating layer can be located on / over the entire surface or on / over an entire surface area of ​​the substrate.

[0024] The lower hole can comprise an active hole and a buffer hole, and the lower electrode can comprise: a first part located in the active hole and a second part located in the buffer hole. The area (or cross-sectional area) of a lower surface of the first part can be larger than the area (or cross-sectional area) of an upper surface of the second part. The thin-film transistor substrate can include a buffer layer, with the buffer hole located within the buffer layer. The buffer hole can extend through the buffer layer.

[0025] In some embodiments, the lower hole and the upper hole do not overlap with the gate electrode.

[0026] The active layer can comprise a channel section, a first connection section located on one side of the channel section, and a second connection section located on the other side of the channel section. The lower electrode can be located within either the first or the second connection section. The full cross-sectional area of ​​the lower electrode can be located within the outer boundaries of either the first or the second connection section.

[0027] The active layer can contain an IZO-based (InZnO-based) oxide semiconductor material, an IGZO-based (InGaZnO-based) oxide semiconductor material, an IZTO-based (InZnSnO-based) oxide semiconductor material and / or a ZnO-based oxide semiconductor material.

[0028] The lower electrode can comprise multiple lower electrodes, each spaced apart from the others. In other words, the thin-film transistor substrate can have multiple lower electrodes spaced apart from each other. Each of the multiple lower electrodes can exhibit one of the lower electrode features described above.

[0029] The upper electrode can have multiple upper electrodes, each of which can correspond one-to-one to the multiple lower electrodes. In other words, the thin-film transistor substrate can have multiple upper electrodes, each upper electrode being connected to multiple lower electrodes. Each of the multiple upper electrodes can have any of the upper electrode features described above. Each upper electrode and its associated lower electrode can have any of the upper and lower electrode features described above, including features relating to area, width, size, or center / center point.

[0030] The multiple upper electrodes can be connected. The upper electrode(s) can extend continuously over at least two adjacent lower electrodes from the multiple lower electrodes.

[0031] The multiple lower electrodes can be of different sizes.

[0032] The area of ​​a lower surface of the upper hole can be larger than the area of ​​an upper surface of the lower hole.

[0033] The step of forming the active hole in / on (one side of) the active layer can include forming multiple active holes. The step of forming the bottom hole can include forming multiple bottom holes that expose the light-blocking layer. The bottom holes can be formed by expanding the multiple active holes, in particular by expanding the multiple active holes at the bottom ends of the respective active holes.

[0034] The method can include: forming a drain hole in the intermediate layer insulation, where the size of the drain hole is smaller than the size of the upper hole. The drain hole can be formed in the gate insulation layer and the intermediate layer insulation layer.

[0035] The first thin-film transistor can be a driver thin-film transistor located in the display area. The second thin-film transistor can be a switching thin-film transistor located in the display area, or any thin-film transistor located in a gate driver located in the non-display area.

[0036] The center of the (first) upper hole can be aligned with the center of the (first) lower hole.

[0037] The thin-film transistor substrate can comprise: a second lower hole passing through the active layer; a third lower hole passing through the active layer; and a second upper hole passing through the insulating layer, with the source electrode located in the first, second, and third lower holes and the first and second upper holes.

[0038] The thin-film transistor substrate may further comprise: a third upper hole passing through the insulating layer, with the source electrode positioned in the first, second and third lower holes and the first, second and third upper holes.

[0039] The first upper hole can be connected to both the first lower hole and the second lower hole.

[0040] The thin-film transistor substrate can include: a second lower hole passing through the active layer; and a second upper hole passing through the insulating layer, with the source electrode located in the first and second lower holes and the first and second upper holes. Brief description of the drawings

[0041] The above and other objectives, features and further advantages of the present disclosure will become clearer from the following detailed description in conjunction with the accompanying drawings; they show: Fig. 1 a top view of a thin-film transistor substrate according to an embodiment of the present disclosure; Fig. 2A is a cross-sectional view of a thin-film transistor substrate according to an embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 2A the cross-section along line II' of Fig. 1 according to one embodiment of the present disclosure; Fig. 2B a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 2B the cross-section along line II' of Fig. 1; Fig. 3 a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 4 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 4 the cross-section along line II-II' of Fig. 3; Fig. 5 a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 6 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 6 the cross-section along line III-III' of Fig. 5; Fig. 7 a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 8 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 8 the cross-section along line IV-IV' of Fig. 7; Fig. 9 a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 10 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 10 the cross-section of VV' of Fig. 9; Fig. 11 a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 12 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 12 corresponds to the cross-section of VI-VI' of Fig. 11; Fig. 13 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 14 a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 15A to 15E Cross-sectional views showing a method for forming a thin-film transistor substrate according to an embodiment of the present disclosure; Fig. 16 a cross-sectional view of a display device comprising a thin-film transistor substrate according to a further embodiment of the present disclosure; Fig. 17 a schematic view of a display device according to an embodiment of the present disclosure; Fig. 18 a circuit diagram of a pixel contained in a display device according to an embodiment of the present disclosure; Fig. 19 a circuit diagram of a pixel contained in a display device according to a further embodiment of the present disclosure; and Fig. 20 a circuit diagram of a pixel contained in a display device according to a further embodiment of the present disclosure. Detailed description of the embodiments

[0042] Advantages and features of the present disclosure, as well as implementation methods thereof, are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the present disclosure can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is defined only by the scope of the claims.

[0043] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings illustrating embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the details shown. The same reference numerals refer throughout to the same elements. In the following description, a detailed description is omitted where it is determined that a detailed description of the relevant known function or configuration would unnecessarily obscure the essential point of this disclosure.

[0044] In situations where the terms "comprise," "have," and "exhibit" are used in this document, a further component may also be present, unless "only" is used. Singular terms may include plural forms unless otherwise indicated.

[0045] When designing an element, the element is designed to include an error range, even if there is no explicit description of it.

[0046] For example, if the positional sequence is described as "on", "above", "below", "below" and "next to", the situation without contact in between can be included unless "immediately" or "directly" is used.

[0047] When it is mentioned that a first element is positioned "on" a second element, this does not mean that the first element must be positioned above the second element in the figure. The upper and lower parts of an object in question can change depending on the object's orientation. Consequently, the situation in which a first element is positioned "on" a second element, in the figure or in an actual configuration, encompasses both the situation in which the first element is positioned "below" the second element and the situation in which the first element is positioned "above" the second element.

[0048] When describing a temporal relationship, if the temporal sequence is described as, for example, "after", "subsequently", "next" and "before", a situation that is not continuous may be included unless "immediately" or "directly" is used.

[0049] It is important to understand that, although the terms "first," "second," etc., may be used herein to describe different elements, these elements are not meant to be restricted by these terms. These terms are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and likewise, a second element could be referred to as a first element.

[0050] It is important to understand that the term "at least one" encompasses all combinations belonging to any given element. For example, "at least one of a first element, a second element, and a third element" can include all combinations of two or more elements selected from the first, second, and third elements, as well as each element of the first, second, and third elements.

[0051] Features of different embodiments of the present disclosure can be partially or completely coupled or combined and can cooperate and be controlled in various ways. The embodiments of the present disclosure can be implemented independently of one another or can be implemented together in a dependent relationship.

[0052] In the drawings, the same or similar elements are designated with the same reference symbols, even if they are shown in different drawings.

[0053] In the embodiments of the present disclosure, for the sake of simplicity, a source electrode and a drain electrode are distinguished from one another. However, the source electrode and the drain electrode are used interchangeably. Thus, the source electrode can be the drain electrode and the drain electrode can be the source electrode. Furthermore, the source electrode in any embodiment of the present disclosure can be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure can be the source electrode in another embodiment of the present disclosure.

[0054] In one or more embodiments of the present disclosure, for the sake of simplicity, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, embodiments of the present disclosure are not limited to this structure. For example, a source region can be a source electrode, and a drain region can be a drain electrode. Furthermore, a source region can be a drain electrode, and a drain region can be a source electrode.

[0055] Fig. Figure 1 is a top view of a thin-film transistor substrate according to an embodiment of the present disclosure.

[0056] As it is in Fig. As shown in Figure 1, the thin-film transistor substrate according to an embodiment of the present disclosure can comprise a light-blocking layer 110, an active layer 130, a gate electrode 150, a source electrode 170 and a drain electrode 180.

[0057] The light-blocking layer 110 and the active layer 130 can extend in a first direction, e.g., a horizontal direction, and the gate electrode 150 can extend in a second direction, e.g., a vertical direction. In this situation, the first and second directions can be orthogonal to each other.

[0058] A drain hole DH can be located on one side of the active layer 130, e.g., on its left side, and an upper hole TH (e.g., top hole) and a lower hole BH (e.g., bottom hole) can be located on the other side of the active layer 130, e.g., on its right side. In this situation, the lower hole BH and the upper hole TH can overlap or be connected to each other.

[0059] One side of the active layer 130 can be electrically connected to the drain electrode 180 via the drain hole DH, the other side of the active layer 130 can be electrically connected to the light-blocking layer 110 via the lower hole BH, and the other side of the active layer 130 can be electrically connected to the source electrode 170 via the upper hole TH. In this configuration, the light-blocking layer 110, the active layer 130, and the source electrode 170 can be electrically connected through the upper hole TH and the lower hole BH, thereby enabling the grayscale representation of the thin-film transistor substrate according to an embodiment of the present disclosure, which is described in Fig. 2A is described in detail, which makes it easier.

[0060] Fig. Figure 2A is a cross-sectional view of a thin-film transistor substrate according to an embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 2A the cross-section along line II' of Fig. 1.

[0061] As it is in Fig. As shown in Figure 2A, the thin-film transistor substrate according to an embodiment of the present disclosure can comprise a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an intermediate insulating layer 160, a source electrode 170 and a drain electrode 180.

[0062] Substrate 100 can be made of glass or plastic. Specifically, substrate 100 can be made of a transparent plastic with flexible properties, such as polyimide. If polyimide is used as substrate 100, heat-resistant polyimide, capable of withstanding high temperatures, can be used because a high-temperature deposition process is performed on the substrate 100.

[0063] The light-blocking layer 110 can be arranged on the substrate 100. The light-blocking layer 110 can contain a metal or a metal oxide and can consist of a single metal layer or a single metal oxide layer, or it can consist of two or more metal layers or metal oxide layers.

[0064] The light-blocking layer 110 is arranged beneath and overlaps the active layer 130, thus preventing light entering the thin-film transistor substrate from the outside from entering the active layer 130 and preventing potential damage to the active layer 130. In particular, the light-blocking layer 110 can prevent external light from entering the channel portion 131 of the active layer 130. Furthermore, a separate insulating layer can be arranged between the light-blocking layer 110 and the substrate 100.

[0065] The buffer layer 120 is formed on the substrate 100 and the light-blocking layer 110. The buffer layer 120 protects the active layer 130 by blocking air and moisture. The buffer layer 120 can consist of an inorganic insulating material such as silicon dioxide, silicon nitride, or metal oxide, but is not limited to this and can also consist of an organic insulating material. The buffer layer 120 can consist of a single layer or multiple layers.

[0066] The active layer 130 can be arranged on the buffer layer 120.

[0067] The active layer 130 can contain a semiconductor material, e.g., an oxide semiconductor material. The oxide semiconductor material can be... B. an IZO-based (InZnO-based) oxide semiconductor material, an IGO-based (InGaO-based) oxide semiconductor material, an ITO-based (InSnO)-based oxide semiconductor material, an IGZO-based (InGaZnO-based) oxide semiconductor material, an IGZTO-based (InGaZnSnO-based) oxide semiconductor material, a GZTO-based (GaZnSnO-based) oxide semiconductor material, a GZO-based (GaZnO-based) oxide semiconductor material, an ITZO-based (InSnZnO-based) oxide semiconductor material and / or a FIZO-based (FeInZnO-based) oxide semiconductor material.

[0068] In this situation, the active layer 130 can preferably contain an IZO-based (InZnO-based) oxide semiconductor material, an IGZO-based (InGaZnO-based) oxide semiconductor material, an IZTO-based (InZnSnO-based) oxide semiconductor material, and / or a ZnO-based oxide semiconductor material. If the active layer 130 is configured to contain the material described above, a bottom hole BH can be more easily formed on one side of the active layer 130.

[0069] The active layer 130 comprises a channel part 131, a first connection part 132a connected to one side of the channel part 131, and a second connection part 132b connected to the other side of the channel part 131. The first connection part 132a and the second connection part 132b can exhibit conductivity properties through a conductivity enhancement process of ion doping or plasma treatment on a semiconductor material using the gate electrode 150 as a mask.

[0070] The conductivity enhancement process can be defined as a process in which conductive properties are imparted to an oxide semiconductor material. The oxide semiconductor material in which the conductivity enhancement process is performed can exhibit conductive properties. The conductivity enhancement process can, for example, include a doping process using dopant ions and a plasma process in which plasma is applied to form a conductor. Through the conductivity enhancement process, a subregion of the active layer 130 can be made conductive, so that it has conductive properties.In this situation, the first connecting part 132a and the second connecting part 132b can be made conductive by the conductivity enablement process, so that they have conductivity properties, and the first connecting part 132a and the second connecting part 132b can have better conductivity than the channel part 131 and can each serve as a wiring or source / drain electrode.

[0071] A bottom hole bra can be arranged on one side of the active layer 130. In particular, an area of ​​one side of the active layer 130 can be structured to form the bottom hole bra.

[0072] The lower hole BH can be located in the first junction 132a of the active layer 130. The lower hole BH is formed by structuring a portion of the active layer 130 and a portion of the buffer layer 120, and the lower hole BH can expose a portion of the upper surface of the light-blocking layer 110, which is provided beneath the active layer 130. By forming the lower hole BH, the source electrode 170 can penetrate the lower hole BH to electrically connect the first junction 132a of the active layer 130 to the light-blocking layer 110.

[0073] The gate insulating layer 140 can be arranged on the active layer 130. Specifically, the gate insulating layer 140 can be arranged over the entire surface of the substrate 100 and can be arranged on the active layer 130 and the buffer layer 120, but embodiments are not limited to these (see, e.g., Fig. 2B). As a result, the active layer 130 can be surrounded by the buffer layer 120 and the gate insulating layer 140.

[0074] In the gate insulation layer 140, an upper hole TH and a drain hole DH can be arranged.

[0075] The gate insulating layer 140 can comprise, but is not limited to, a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx). The gate insulating layer 140 can be formed from a single layer or multiple layers comprising an inorganic insulating material and / or an organic insulating material.

[0076] The gate electrode 150 can be arranged on the gate insulating layer 140. The gate electrode 150 can be arranged on the active layer 130. In particular, the gate electrode 150 can overlap the channel portion 131 of the active layer 130.

[0077] The gate electrode 150 can contain an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and / or titanium (Ti). The gate electrode 150 can have a single-layer metal structure or a multi-layer structure with at least two metal layers, each with different physical properties.

[0078] The interlayer insulating layer 160 can insulate the gate electrode 150 from the source electrode 170 and further insulate the gate electrode 150 from the drain electrode 180. The interlayer insulating layer 160 can be formed from a single layer or multiple layers containing an inorganic insulating material and / or an organic insulating material.

[0079] The upper hole TH and the drain hole DH can be arranged in the intermediate insulating layer 160. Accordingly, a section of the upper surface of the first connecting part 132a of the active layer 130 can be exposed through the upper hole TH, and the lower hole BH of the active layer 130 can be exposed through the upper hole TH. Furthermore, a section of the upper surface of the second connecting part 132b of the active layer 130 can be exposed through the drain hole DH.

[0080] The source electrode 170 and the drain electrode 180 can be arranged on the intermediate insulating layer 160. The source electrode 170 and the drain electrode 180 can be made of the same material as the gate electrode 150, but are not limited to this and can be made of a material according to the knowledge in the field.

[0081] The source electrode 170 can be electrically connected to one side of the active layer 130, e.g., the first connection part 132a, and the drain electrode 180 can be electrically connected to another side of the active layer 130, e.g., the second connection part 132b. In particular, the source electrode 170 can be connected to the first connection part 132a of the active layer 130 via the upper hole TH, which is located in the gate insulating layer 140 and the intermediate insulating layer 160, and the drain electrode 180 can be connected to the second connection part 132b of the active layer 130 via the drain hole DH, which is located in the gate insulating layer 140 and the intermediate insulating layer 160.

[0082] According to one embodiment of the present disclosure, the source electrode 170 can be electrically connected to the first connecting part 132a of the active layer 130 and the light-blocking layer 110 via the upper hole TH, which is arranged in the gate insulating layer 140 and the intermediate insulating layer 160, and the lower hole BH, which is arranged in the buffer layer 120 and the first connecting part 132a of the active layer 130, which is described below with reference to the relationship between the upper hole TH, the lower hole BH and the source electrode 170, which is arranged in the upper hole TH and in the lower hole BH.

[0083] As described above, the upper hole TH can be formed by etching a section of the gate insulating layer 140 and the intermediate insulating layer 160 from the upper surface of the active layer 130, in particular the first connecting part 132a, and the lower hole BH can be formed by etching a section of the buffer layer 120 and the first connecting part 132a of the active layer 130 from the upper surface of the light-blocking layer 110.

[0084] The upper hole TH can overlap with the lower hole BH, and the two holes can be connected or interconnected. In particular, the entire lower hole BH can overlap with the upper hole TH. Furthermore, the upper hole TH and the lower hole BH can be continuous and interconnected. Accordingly, a section of the upper surface of the light-blocking layer 110 can be exposed through the upper hole TH and the lower hole BH.

[0085] The upper hole TH and the lower hole BH can be configured to have differently sized surfaces, and in this situation, the upper hole TH can be larger than the lower hole BH. In particular, the lower surface of the upper hole TH can be larger than the upper surface of the lower hole BH. This configuration allows the upper hole TH to expose a portion of the upper surface of the first connecting part 132a. Specifically, a portion of the upper surface of the first connecting part 132a that overlaps with the upper hole TH without overlapping with the lower hole BH can be exposed through the upper hole TH.

[0086] According to one embodiment of the present disclosure, since the upper hole TH and the lower hole BH are continuous and connected to each other, the source electrode 170 can be electrically connected to the first connecting part 132a through the upper hole TH and to the light-blocking layer 110 through the lower hole BH. Therefore, the light-blocking layer 110 and the first connecting part 132a can be electrically connected through the upper hole TH and the lower hole BH.

[0087] According to one configuration of the present disclosure, since the source electrode 170 passes through the upper hole TH and the lower hole BH through a section of the active layer 130, thus being electrically connected to the light-blocking layer 110 and the active layer 130, the total area of ​​the thin-film transistor substrate can be reduced, the amount of wiring decreased, the space requirement reduced, and more components can be packed more densely to better enable the implementation of higher resolutions. If the source electrode, the active layer, and the light-blocking layer are electrically connected without the upper hole TH and the lower hole BH, the total area of ​​the thin-film transistor substrate can be larger by the area in which the connecting electrode is formed.

[0088] The source electrode 170 can comprise an upper electrode 171 and a lower electrode 172. In this situation, the upper electrode 171 can be defined as a section of the source electrode 170 located in the upper hole TH and on the interlayer insulating layer 160, and the lower electrode 172 can be defined as a section of the source electrode 170 located in the lower hole BH. Similarly, the upper electrode 171 can be defined as a section of the source electrode 170 located in the gate insulating layer 140 and the interlayer insulating layer 160, extending from the upper surface of the active layer 130 onto the interlayer insulating layer 160. The lower electrode 172 can be defined as a section of the source electrode 170 that extends from the upper surface of the light-blocking layer 110 into the buffer layer 120 and into the first connecting part 132a.

[0089] According to one embodiment of the present disclosure, the size of the upper electrode 171 can be larger than the size of the lower electrode 172, since the size of the upper hole TH is larger than the size of the lower hole BH. In particular, the lower surface of the upper electrode 171 can be larger than the upper surface of the lower electrode 172.

[0090] Since the lower surface area of ​​the upper electrode 171 is larger than the upper surface area of ​​the lower electrode 172, the entire lower electrode 172 can be overlapped by the upper electrode 171 in a top view. Furthermore, the upper electrode 171 can be in contact with the lower electrode 172 and with a section of the upper surface of the first connecting part 132a of the active layer 130.

[0091] Since the lower electrode 172 can be located in the lower hole BH, the lower electrode 172 can be in contact with the inside of the first connecting part 132a of the active layer 130. In this situation, the inside of the first connecting part 132a can be defined as an area of ​​the first connecting part 132a that is exposed through the lower hole BH. Furthermore, as shown in Fig. As shown in 2B, the lower hole BH is evenly centered below it and aligned with the center of the upper hole TH, but the embodiments are not limited to this.

[0092] Since the upper electrode 171 is in contact with a section of the upper surface of the first connecting part 132a and the lower electrode 172 is in contact with the inside of the first connecting part 132a, the contact area between the source electrode 170 and the active layer 130, in particular the first connecting part 132a, can increase, and thus the contact resistance between the active layer 130 and the source electrode 170 can decrease (e.g., better electrical contact can be established between the active layer 130 and the source electrode 170 because the source electrode 170 can completely penetrate the active layer 130).In this situation, by reducing the contact resistance between the active layer 130 and the source electrode 170, an inrush current can be increased when the thin-film transistor substrate is driven according to an embodiment of the present disclosure, and the brightness of a corresponding subpixel can be improved while simultaneously reducing the power consumption.

[0093] Fig. Figure 2B is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 2B the cross-section along line II' of Fig. 1. Since the thin-film transistor substrate is made of Fig. 2B, with the exception of the gate insulating layer and interlayer insulating layer configurations, is the same as that of the thin-film transistor substrate of Fig. 2A (e.g., the gate insulating layer can have an island shape), mainly differing configurations are described below.

[0094] As it is in Fig. As shown in Figure 2B, the gate insulating layer 140 may not be arranged over the entire surface of the substrate 100, but may be structured such that it coincides with one end and the other end of the gate electrode 150. In particular, one end of the gate insulating layer 140, e.g., a right end, may coincide with one end of the gate electrode 150, and another end of the gate insulating layer 140, e.g., a left end, may coincide with the other end of the gate electrode 150.

[0095] Since the gate insulating layer 140 is designed as described above, the upper hole TH and the drain hole DH may not be located in the gate insulating layer 140, but may only be located in the intermediate insulating layer 160.

[0096] The intermediate insulating layer 160 can be arranged on the active layer 130 and the gate electrode 150 and can be in contact with a section of an upper surface of the active layer 130. As a result, the active layer 130 and the gate electrode 150 can be surrounded by the buffer layer 120 and the intermediate insulating layer 160.

[0097] However, the configuration of the gate insulating layer and the interlayer insulating layer can be determined according to Fig. 2B is applied to a thin-film transistor substrate according to a further embodiment described later.

[0098] Fig. Figure 3 is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. However, mainly different configurations are described below, since the thin-film transistor substrate according to Fig. 3 except for the configuration of the upper hole TH equal to the thin-film transistor substrate according to Fig. 1 is (e.g., the upper hole TH can be according to Fig. 3. The hole should be designed to be larger than the upper hole TH according to Fig. 1).

[0099] As it is in Fig. As shown in Figure 3, the thin-film transistor substrate according to a further embodiment of the present disclosure can comprise a light-blocking layer 110, an active layer 130, a gate electrode 150, a source electrode 170 and a drain electrode 180.

[0100] One end of the active layer 130 can be electrically connected to the source electrode 170 via the upper hole TH, and the other end of the active layer 130 can be electrically connected to the light-blocking layer 110 via the lower hole BH. In this situation, since the upper hole TH and the lower hole BH overlap, the light-blocking layer 110, the active layer 130, and the source electrode 170 can be electrically connected.

[0101] According to a further embodiment of the present disclosure, one side of the upper hole TH, e.g., the right end, can coincide with one side of the active layer 130, e.g., the right end. In other words, an end section of the upper hole TH can be flush with an end section of the active layer 130, and an end section of the source electrode 170 can be flush with an end section of the active layer 130 to further enhance the electrical contact. This configuration increases the contact area between the source electrode 170 and the active layer 130 formed in the upper hole TH, so that the contact resistance between the active layer 130 and the source electrode 170 can be reduced even further. Fig. Figure 3 shows only one embodiment in which one side of the upper hole TH coincides with one side of the active layer 130, but the present disclosure is not limited to this. A similar configuration can also be applied to the drain electrode 180.

[0102] Fig. Figure 4 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 4 the cross-section of II-II' of Fig. 3. Since the thin-film transistor substrate is made of Fig. 4, with the exception of the configuration of the top hole and the top electrode, which is the same as that of the thin-film transistor substrate of Fig. 2A, mainly differing configurations are described below.

[0103] As it is in Fig. As shown in Figure 4, a thin-film transistor substrate according to a further embodiment of the present disclosure can comprise a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an intermediate insulating layer 160, a source electrode 170 and a drain electrode 180.

[0104] According to a further embodiment of the present disclosure, the upper hole TH can be asymmetrically formed with respect to the center of the lower hole BH, while the upper hole TH overlaps with the lower hole BH (e.g., the center of the lower hole BH can be offset from the center of the upper hole TH). In particular, while the upper hole TH overlaps with the lower hole BH, an end of the lower surface of the upper hole TH, e.g., a right end, can coincide with an end of the first connecting part 132a. By the configuration described above, an end of the upper electrode 171, which is arranged in the upper hole TH, e.g., a right end, can coincide with an end of the active layer 130. More precisely, the right end of the lower surface of the upper electrode 171 can coincide with the right end of the upper surface of the active layer 130.In the drawing, however, without restriction, only one end of the upper electrode 171 coincides with one end of the active layer 130.

[0105] Since the upper hole TH is asymmetrically shaped with respect to the center of the lower hole BH, the distance from one end of the upper electrode 171, e.g., a right end, to the lower hole BH can be different from the distance from the other end of the upper electrode 171, e.g., a left end, to the lower hole BH, which, with reference to the enlarged view of Fig. 4 is described.

[0106] As can be seen from the enlarged view of Fig. As can be seen in Figure 4, the distance from one end of the upper electrode 171 to the lower hole BH can be defined as the second distance d2, and the distance from the other end of the upper electrode 171 to the lower hole BH can be defined as the first distance d1. In short, the first distance d1 and the second distance d2 can be defined as the distance from the center of the lower hole BH to one end of the upper electrode 171 and the other end of the upper electrode 171, respectively. In this situation, the first distance d1 can be smaller than the second distance d2 (e.g., d1 < d2), but embodiments are not limited to this. Furthermore, the first distance d1 can be larger than the second distance d2.

[0107] Although one end of the upper electrode 171 coincides with one end of the active layer 130, one end of the drain electrode 180, e.g., a left end, may not coincide with the other end of the active layer 130. In this situation, the size of the upper hole TH, which is arranged with the upper electrode 171, may be larger than the size of the drain hole DH in which the drain electrode 180 is arranged.

[0108] According to a further embodiment of the present disclosure, since one end of the upper electrode 171 and one end of the active layer 130 coincide, the contact area between the upper electrode 171 and the active layer 130 can be increased, and the contact resistance between the active layer 130 and the source electrode 170 of the thin-film transistor substrate can be further reduced, and the brightness and response time of the corresponding subpixel can be further improved.

[0109] Fig. Figure 5 is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Since the thin-film transistor substrate according to Fig. 5 except for the configuration of the lower hole, which is the same as that of the thin-film transistor substrate according to Fig. 1. The following section mainly describes differing configurations.

[0110] As it is in Fig. As shown in Figure 5, a thin-film transistor substrate according to a further embodiment of the present disclosure can comprise a light-blocking layer 110, an active layer 130, a gate electrode 150, a source electrode 170 and a drain electrode 180.

[0111] An upper hole TH and a lower hole BH are arranged on one side of the active layer 130. One side of the active layer 130 and the source electrode 170 can be electrically connected through the upper hole TH, and one side of the active layer 130 and the light-blocking layer 110 can be electrically connected through the lower hole BH. Since the upper hole TH and the lower hole BH overlap in this configuration, the light-blocking layer 110, the active layer 130, and the source electrode 170 can be electrically connected.

[0112] According to another embodiment of the present disclosure, the lower hole BH can have an active hole AH and a buffer hole BufH. In this situation, the active hole AH, the buffer hole BufH, and the upper hole TH can overlap. Furthermore, the upper hole TH can be larger than the active hole AH, and the active hole AH can be larger than the buffer hole BufH (e.g., TH > AH > BufH), but embodiments are not limited to these. Additionally, the centers of the upper hole TH, the active hole AH, and the buffer hole BufH can all be aligned and overlap, but embodiments are not limited to these.

[0113] Fig. Figure 6 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 6 the cross-section along line III-III' of Fig. 5. Since the thin-film transistor substrate according to Fig. 6 except for the configuration of the lower hole and the lower electrode, which is the same as the thin-film transistor substrate according to Fig. 2A is, the following mainly describes differing configurations.

[0114] As it is in Fig. As shown in Figure 6, a thin-film transistor substrate according to a further embodiment of the present disclosure can comprise a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an intermediate insulating layer 160, a source electrode 170 and a drain electrode 180.

[0115] According to a further embodiment of the present disclosure, the lower hole BH can have an active hole AH and a buffer hole BufH, and the lower electrode 172 can have a first section 172p1 and a second section 172p2.

[0116] The buffer hole BufH can be defined as an area formed by etching a section of the buffer layer 120 from the upper surface of the light-blocking layer 110, and the active hole AH can be defined as an area formed by etching a section of the active layer 130 from the upper surface of the buffer layer 120. The buffer hole BufH can overlap with the active hole AH, and the size of the buffer hole BufH can be smaller than the size of the active hole AH.

[0117] In particular, the area of ​​an upper surface of the buffer hole BufH can be smaller than the area of ​​a lower surface of the active hole AH.

[0118] The first section 172p1 of the lower electrode 172 can be defined as a section of the source electrode 170 located in the active hole AH, and the second section 172p2 of the lower electrode 172 can be defined as a section of the source electrode 170 located in the buffer hole BufH. In this situation, the size of the first section 172p1 can be larger than the size of the second section 172p2 (e.g., 172p1 > 172p2). Thus, a section of the lower surface of the first section 172p1 can be in contact with a section of the buffer layer 120 exposed through the active hole AH.

[0119] Fig. Figure 7 is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Since the thin-film transistor substrate according to Fig. 7 with the exception of the configurations of the upper and lower holes (e.g. three through holes may be provided) equal to the thin-film transistor substrate according to Fig. Since 1 is the case, mainly differing configurations are described below.

[0120] As it is in Fig. As shown in Figure 7, the thin-film transistor substrate according to a further embodiment of the present disclosure can comprise a light-blocking layer 110, an active layer 130, a gate electrode 150, a source electrode 170 and a drain electrode 180.

[0121] According to a further embodiment of the present disclosure, one side of the active layer 130 can be electrically connected to the source electrode 170 and the light-blocking layer 110 via several upper holes TH and several lower holes BH. In particular, one side of the active layer 130 can be electrically connected to the source electrode 170 via the first upper hole THa, the second upper hole THb, and the third upper hole THc, and one side of the active layer 130 can be electrically connected to the light-blocking layer 110 via the first lower hole BHa, the second lower hole BHb, and the third lower hole BHc.

[0122] The above-described design allows the contact area between the active layer 130 and the source electrode 170 to be increased, thus reducing the contact resistance between the active layer 130 and the source electrode 170.

[0123] The first upper hole THa and the second upper hole THb can be spaced apart by a third distance d3, and the second upper hole THb and the third upper hole THc can be spaced apart by a fourth distance d4. In this situation, the third distance d3 and the fourth distance d4 can be the same or different.

[0124] Although Fig. Figure 7 shows that the multiple upper holes TH and the multiple lower holes BH are arranged in a line in a first direction, e.g., a horizontal direction. The multiple upper holes TH and the multiple lower holes BH can also be arranged in a line in a second direction, orthogonal to the first direction, e.g., a vertical direction. Furthermore, n upper holes TH and lower holes BH can be arranged in the first direction, and m upper holes TH and lower holes BH in the second direction. Finally, the multiple upper holes TH and the multiple lower holes BH can be arranged in a multidimensional arrangement, matrix, or lattice formation (e.g., 2x2, 4x4, 3x2, etc.).

[0125] Fig. Figure 8 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 8 the cross-section IV-IV' of Fig. 7. However, the thin-film transistor substrate is of Fig. 8 with the exception of the configurations of the top hole, bottom hole, top electrode and bottom electrode equal to the thin-film transistor substrate of Fig. 2A, and therefore mainly differing configurations are described below.

[0126] As it is in Fig. As shown in Figure 8, the first connecting part 132a of the active layer 130 can be electrically connected to the source electrode 170 via several upper holes TH, and the first connecting part 132a of the active layer 130 can be electrically connected to the light-blocking layer 110 via the source electrode 170 arranged in several lower holes BH.

[0127] The multiple upper holes TH can include a first upper hole THa, a second upper hole THb and a third upper hole THc, and the multiple lower holes BH can include a first lower hole Bha, a second lower hole BHb and a third lower hole BHc.

[0128] The multiple upper holes TH can be formed by etching a section of the gate insulating layer 140 and a section of the intermediate insulating layer 160 from the upper surface of the active layer 130, and the multiple lower holes BH can be formed by etching a section of the buffer layer 120 and a section of the active layer 130 from the upper surface of the light-blocking layer 110.

[0129] The first upper hole Tha can be connected to the first lower hole Bha, the second upper hole THb can be connected to the second lower hole BHb, and the third upper hole THc can be connected to the third lower hole BHc. In other words, each of the multiple upper holes THs can correspond one-to-one to the multiple lower holes BH. However, the present disclosure is not limited to this, and an upper hole can be, as in an embodiment described with reference to Fig. As described in section 10, this corresponds to several lower holes (e.g., in a one-to-many relationship). This will be explained in detail with reference to Fig. 10 described.

[0130] Since the upper hole TH and the lower hole BH are formed multiple times, the upper electrode 171 and the lower electrode 172 can also be formed multiple times. For illustrative purposes, the drawing shows the upper electrode 171 and the lower electrode 172 each formed three times, but the present disclosure is not limited to this.

[0131] In particular, the upper electrode 171 can comprise a first upper electrode 171a, a second upper electrode 171b, and a third upper electrode 171c, and the lower electrode 172 can comprise a first lower electrode 172a, a second lower electrode 172b, and a third lower electrode 172c. In this situation, each of the multiple upper electrodes 171a, 171b, and 171c can be defined as a section of the source electrode 170 located in the multiple upper holes THa, THb, and THc, and can be defined as a section of the source electrode 170 located on the intermediate insulating layer 160. Each of the multiple lower electrodes 172a, 172b, and 172c can be defined as a section of the source electrode 170 located in the multiple lower holes BHa, BHb, and BHc.

[0132] According to another embodiment of the present disclosure, since the source electrode 170 comprises the multiple upper electrodes 171a, 171b and 171c and the multiple lower electrodes 172a, 172b and 172c, the contact area between some of the lower surfaces of the multiple upper electrodes 171a, 171b and 171c and the first connecting part 132a of the active layer 130 can be further increased. Since the contact resistance between the active layer 130 and the source electrode 170 is further reduced, an improved inrush current can be achieved when the thin-film transistor substrate is driven according to another embodiment of the present disclosure, and the brightness and response time of a corresponding subpixel can be improved while maintaining a small footprint.

[0133] Fig. Figure 9 is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Since the thin-film transistor substrate according to Fig. 9 except for the configuration of the upper hole, which is the same as that of the thin-film transistor substrate according to Fig. 7, the following mainly describes differing configurations.

[0134] As it is in Fig. As shown in Figure 9, the multiple upper holes TH and the multiple lower holes BH may not correspond one-to-one. In particular, the multiple upper holes THs may include a first upper hole THa and a second upper hole THb, and the multiple lower holes BH may include a first lower hole BHa, a second lower hole BHb, and a third lower hole BHc. In this situation, the first upper hole THa may overlap with the first lower hole BHa and the second lower hole BHb, and the second upper hole THb may overlap with the third lower hole BHc.

[0135] According to a further embodiment of the present disclosure, since the multiple upper holes TH and the multiple lower holes BH are arranged as in the embodiment of Fig. Since the dimensions 7 do not correspond one-to-one, the contact area between the active layer 130 and the source electrode 170 is increased compared to a situation where the multiple upper holes and the multiple lower holes overlap one-to-one. Accordingly, the contact resistance between the active layer 130 and the source electrode 170 can be reduced even further.

[0136] Fig. Figure 10 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 10 the cross-section VV' of Fig. 9. Since the thin-film transistor substrate is made of Fig. 10 with the exception of the configuration of the top hole and the top electrode, the same as the thin-film transistor substrate of Fig. Since version 8 is the most common configurations described below, the following section mainly describes differing configurations.

[0137] As it is in Fig. As shown in Figure 10, the first connecting part 132a of the active layer 130 can be electrically connected to the source electrode 170 via several upper holes TH, and the first connecting part 132a of the active layer 130 can be electrically connected to the light-blocking layer 110 via the source electrode 170 arranged in several lower holes BH.

[0138] The multiple upper holes TH can include a first upper hole THa and a second upper hole THb, and the multiple lower holes BH can include a first lower hole BHa, a second lower hole BHb, and a third lower hole BHc.

[0139] According to a further embodiment of the present disclosure, the first upper hole THa can be connected to the first lower hole BHa and the second lower hole BHb, and the second upper hole THb can be connected to the third lower hole BHc. In other words, the upper holes THs may not correspond one-to-one to the multiple lower holes BH (e.g., a one-to-many relationship may be provided in which one upper hole is connected to two or more lower holes, etc.).

[0140] Since the upper hole TH and the lower hole BH are formed multiple times, the upper electrode 171 and the lower electrode 172 can also be formed multiple times.

[0141] In particular, the upper electrode 171 can comprise a first upper electrode 171a and a second upper electrode 171b, and the lower electrode 172 can comprise a first lower electrode 172a, a second lower electrode 172b, and a third lower electrode 172c.

[0142] Since the first upper hole THa is connected to the first lower hole BHa and the second lower hole BHb, the first upper electrode 171a can overlap and be electrically connected to the first lower electrode 172a and the second lower electrode 172b.

[0143] The lower surface of the first upper electrode 171a can be in contact with a section of the upper surface of the first connecting part 132a of the first active layer 130, the upper surface of the first lower electrode 172a, and the upper surface of the second lower electrode 172b. In this situation, the lower surface of the first upper electrode 171a, which is in contact with a section of the upper surface of the first connecting part 132a, can be in contact with the upper surface of the first connecting part 132a outside the first lower electrode 172a, e.g., on the left side, with the upper surface of the first connecting part 132a outside the second lower electrode 172b, e.g., on the right side, and furthermore, with a section of the upper surface of the first connecting part 132a between the first lower electrode 172a and the second lower electrode 172b.

[0144] In this situation, it can be said that a section of the lower surface of the first upper electrode 171a, which is in contact with the first connecting part 132a between the first lower electrode 172a and the second lower electrode 172b, is continuously connected to the adjacent lower electrodes 172a and 172b among the multiple lower electrodes 172 that are in contact with a section of the upper surface of the first connecting part. For example, the upper electrode 171 can have a multi-pronged fork structure that penetrates the active layer 130, which can create an even better electrical contact. Furthermore, the first upper electrode 171a and the adjacent lower electrodes 172a and 172b form a kind of two-pronged fork structure, but embodiments are not limited to this, and an upper electrode can form a fork-like structure with three or more lower electrodes.

[0145] Since a section of the lower surface of the first upper electrode 171a contacts a section of the upper surface of the first connecting part 132a between the first lower electrode 172a and the second lower electrode 172b, the contact area between a section of the upper surface of the first connecting part 132a of the active layer 130 and the lower surface of the upper electrode 171 can be increased. Accordingly, according to a further embodiment of the present disclosure, since the contact resistance between the active layer 130 and the source electrode 170 is further reduced when the thin-film transistor substrate is driven, an improved inrush current can be achieved while maintaining a small footprint.

[0146] Since the second upper electrode 171b and the third lower electrode 172c are the same as the configurations of the upper electrode and the lower electrode in Fig. 2A or Fig. Since there are 8 items that correspond to each other one-to-one, as described above, a detailed description is omitted.

[0147] Fig. Figure 11 is a top view of a thin-film transistor substrate according to a further embodiment of the present disclosure. Since the thin-film transistor substrate according to Fig. 11 except for the configurations of the upper and lower holes equal to the thin-film transistor substrate according to Fig. Since 1 is the case, mainly differing configurations are described below.

[0148] As it is in Fig. As shown in Figure 11, a thin-film transistor substrate according to a further embodiment of the present disclosure can comprise a light-blocking layer 110, an active layer 130, a gate electrode 150, a source electrode 170 and a drain electrode 180.

[0149] According to a further embodiment of the present disclosure, one side of the active layer 130 can be electrically connected to the source electrode 170 and the light-blocking layer 110 via several upper holes TH and several lower holes BH. In particular, one side of the active layer 130 can be electrically connected to the source electrode 170 via a first upper hole THa and a second upper hole THb, and one side of the active layer 130 can be electrically connected to the light-blocking layer 110 via a first lower hole Bha and a second lower hole BHb.

[0150] By forming the device as described above, the contact area between the active layer 130 and the source electrode 170 can be increased, and thus the contact resistance between the active layer 130 and the source electrode 170 can be reduced.

[0151] According to a further embodiment of the present disclosure, the area of ​​each of the several upper holes THs can be different, and the area of ​​each of the several lower holes BH can be different (e.g., the sizes of the upper holes can be different from each other, and the sizes of the lower holes can be different from each other). In particular, the area of ​​the second upper hole THb can be larger than the area of ​​the first upper hole THa, and the area of ​​the second lower hole BHb can be larger than the area of ​​the first lower hole BHa. By such a configuration, the contact area between the active layer 130 and the source electrode 170 can be increased compared to the situation in which the area of ​​each of the several upper holes THs is the same and the area of ​​each of the several lower holes BH is the same.Accordingly, the contact resistance between the active layer 130 and the source electrode 170 can be reduced.

[0152] Fig. Figure 12 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. In this situation, the cross-sectional view corresponds to Fig. 12 the cross-section VI-VI' of Fig. 11. However, the thin-film transistor substrate of Fig. 12 with the exception of the configurations of the top hole, the bottom hole, the top electrode and the bottom electrode equal to the thin-film transistor substrate of Fig. 2A and therefore mainly differing configurations are described below.

[0153] As it is in Fig. As shown in Figure 12, the first connecting part 132a of the active layer 130 can be electrically connected to the source electrode 170 via several upper holes TH, and the first connecting part 132a of the active layer 130 can be electrically connected to the light-blocking layer 110 via the source electrode 170 arranged in several lower holes BH.

[0154] The multiple upper holes TH can include a first upper hole THa and a second upper hole THb, and the multiple lower holes BH can include a first lower hole BHa and a second lower hole BHb.

[0155] The multiple upper holes TH can be formed by etching a section of the gate insulating layer 140 and a section of the intermediate insulating layer 160 from the upper surface of the active layer 130, and the multiple lower holes BH can be formed by etching a section of the buffer layer 120 and a section of the active layer 130 from the upper surface of the light-blocking layer 110.

[0156] The first upper hole THa can be connected to the first lower hole BHa, and the second upper hole THb can be connected to the second lower hole BHb. In other words, each of the multiple upper holes THs can correspond one-to-one to the multiple lower holes BH.

[0157] According to a further embodiment of the present disclosure, since the contact area between the second upper electrode 171b and a section of the upper surface of the first connecting part 132a of the active layer 130 is larger than the contact area between the first upper electrode 171a and a section of the upper surface of the first connecting part 132a of the active layer 130, the contact area between the active layer 130 and the source electrode 170 can be increased and the contact resistance between the active layer 130 and the source electrode 170 can be reduced. Accordingly, an improved inrush current can be achieved when the thin-film transistor substrate is driven according to a further embodiment of the present disclosure.

[0158] Fig. Figure 13 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure.

[0159] As it is in Fig. As shown in Figure 13, the thin-film transistor substrate according to a further embodiment of the present disclosure can comprise the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0160] The display device can have a display area and a non-display area; several pixels can be arranged in the display area, and a gate control circuit can be arranged in the non-display area.

[0161] Each of the multiple pixels comprises multiple thin-film transistors; each of these thin-film transistors can include a driver thin-film transistor for controlling pixels; and another thin-film transistor among the multiple thin-film transistors can include a switching thin-film transistor for transmitting a data signal to the driver thin-film transistor. Furthermore, the gate drive circuit can also comprise multiple thin-film transistors.

[0162] As it is in Fig. As shown in Figure 13, the thin-film transistor substrate according to a further embodiment of the present disclosure can comprise the first thin-film transistor TR1 and the second thin-film transistor TR2, wherein the first thin-film transistor TR1 can be a drive thin-film transistor arranged in any one of the multiple pixels and the second thin-film transistor TR2 can be a switching thin-film transistor arranged in any one of the multiple pixels or several thin-film transistors arranged in the gate drive circuit.

[0163] The first thin-film transistor TR1 can comprise a substrate 100, a first light-blocking layer 110, a buffer layer 120, a first active layer 130, a gate insulating layer 140, a first gate electrode 150, an intermediate insulating layer 160, a first source electrode 170, and a first drain electrode 180. The first light-blocking layer 110, the first active layer 130, the first gate electrode 150, the first source electrode 170, and the first drain electrode 180 of the first thin-film transistor are the same as those of the thin-film transistor substrate according to one embodiment of Fig. 8 above, and therefore repeated descriptions of it are omitted.

[0164] The second thin-film transistor TR2 can comprise a substrate 100, a buffer layer 120, a second active layer 230, a gate insulating layer 140, a second gate electrode 250, an interlayer insulating layer 160, a second source electrode 270, and a second drain electrode 280. The substrate 100, the buffer layer 120, the gate insulating layer 140, and the interlayer insulating layer 160 are the same as those in Fig. The configurations described in section 8 are therefore mainly differing.

[0165] The second active layer 230 can be arranged on the buffer layer 120.

[0166] The second active layer 230 can contain a semiconductor material, e.g., an oxide semiconductor material. The oxide semiconductor material can be an IZO-based (InZnO-based) oxide semiconductor material, an IGO-based (InGaO-based) oxide semiconductor material, an ITO-based (InSnO) oxide semiconductor material, an IGZO-based (InGaZnO-based) oxide semiconductor material, an IGZTO-based (InGaZnSnO-based) oxide semiconductor material, a GZTO-based (GaZnSnO-based) oxide semiconductor material, a GZO-based (GaZnO-based) oxide semiconductor material, an ITZO-based (InSnZnO-based) oxide semiconductor material, and / or an FIZO-based (FeInZnO-based) oxide semiconductor material.

[0167] The second active layer 230 can comprise a channel part 231, a first connection part 232a connected to one side of the channel part 231, e.g., a right side, and a second connection part 232b connected to another side of the channel part 231, e.g., a left side. The first connection part 232a and the second connection part 232b can be made conductive by a conductivity enhancement process in which a semiconductor material is ion-doped or plasma-treated using the second gate electrode 250 as a mask. The first connection part 232a and the second connection part 232b exhibit better conductivity than the channel part 231 and can each serve as a wiring or source / drain electrode.

[0168] The second gate electrode 250 can be arranged on the gate insulating layer 140. The second gate electrode 250 can be arranged on the second active layer 230. In particular, the second gate electrode 250 can overlap with the channel portion 231 of the second active layer 230.

[0169] The second gate electrode 250 can contain an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and / or titanium (Ti). The second gate electrode 250 can have a single-layer metal structure or a multi-layer structure with at least two metal layers, each with different physical properties.

[0170] A first contact hole CH1 and a second contact hole CH2 can be arranged in the interlayer insulating layer 160 and accordingly a section of the upper surface of the first connecting part 232a of the second active layer 230 can be exposed through the first contact hole CH1 and a section of the upper surface of the second connecting part 232b of the second active layer 230 can be exposed through the second contact hole CH2.

[0171] The second source electrode 270 and the second drain electrode 280 can be arranged on the interlayer insulating layer 160. The second source electrode 270 and the second drain electrode 280 can be made of the same material as the second gate electrode, but are not limited to this and can be made of a material according to the knowledge in the field.

[0172] The second source electrode 270 can be electrically connected via the first contact hole CH1 to the first connecting part 232a of the second active layer 230 and the second drain electrode 280 can be electrically connected via the second contact hole CH2 to the second connecting part 232b of the second active layer.

[0173] According to a further configuration of the present disclosure, if the first thin-film transistor TR1 can be one of the drive thin-film transistors arranged in the multiple pixels and the second thin-film transistor TR2 can be one of the switching thin-film transistors arranged in the multiple pixels or of the multiple thin-film transistors arranged in the gate drive circuit, the drive thin-film transistor consisting of the first thin-film transistor TR1 can easily express grayscale levels by means of a large capacitor, and the switching thin-film transistor consisting of the second thin-film transistor TR2 or the thin-film transistor arranged in the gate drive circuit can retain the inrush current characteristics.

[0174] Fig. Figure 14 is a cross-sectional view of a thin-film transistor substrate according to a further embodiment of the present disclosure. However, an embodiment of Fig. 14 equivalent to an embodiment of Fig. 13, except that the first buffer layer and the second light-blocking layer are arranged in the second thin-film transistor, and therefore mainly differing configurations are described below.

[0175] As it is in Fig. As shown in Figure 14, the second thin-film transistor TR2 can comprise a substrate 100, a second light-blocking layer 210, a first buffer layer 120a, a second buffer layer 120b, a second active layer 230, a gate insulating layer 140, a second gate electrode 250, an intermediate insulating layer 160, a second source electrode 270 and a second drain electrode 280.

[0176] The second light-blocking layer 210 can be arranged on the substrate 100. The second light-blocking layer 210 can be made of a metal or a metal oxide, and can consist of a single metal layer or a single metal oxide layer, or of two or more metal layers or metal oxide layers. The second light-blocking layer 210 can be made of a different material than the first light-blocking layer 110, but is not limited to this.

[0177] The second light-blocking layer 210 can be arranged below and overlap the second active layer 230, thus preventing light entering the second active layer 230 from outside the thin-film transistor substrate and preventing potential damage to the second active layer 230. In particular, the second light-blocking layer 210 can prevent external light from entering the channel portion 231 of the second active layer 230. Furthermore, the second light-blocking layer 210 can be electrically connected to the second gate electrode 250. When the second light-blocking layer 210 is electrically connected to the second gate electrode 250, the second thin-film transistor TR2 can have a dual-gate structure in which gate electrodes are arranged above and below the second active layer 230 (e.g.,The second light-blocking layer 210 can be used as one of the gate electrodes of a double-gate electrode structure).

[0178] The first buffer layer 120a can be arranged on the second light-blocking layer 210. The first buffer layer 120a can be formed from an inorganic insulating material such as silicon dioxide, silicon nitride, or metal oxide, but is not limited to this and can be formed from an organic insulating material. The first buffer layer 120a can be formed from a single layer or from multiple layers.

[0179] The second buffer layer 120b can be arranged on top of the first buffer layer 120a and the first light-blocking layer 110. The second buffer layer 120b has the same configuration as the one in Fig. 2a, Fig. 2b, Fig. 4, Fig. 6, Fig. 8, Fig. 10 and Fig. The 12 buffer layers described above are therefore omitted in detail.

[0180] According to a further configuration of the present disclosure, the second thin-film transistor TR2 can be any switching thin-film transistor arranged in the multiple pixels, and in this situation the inrush current characteristics can be further improved because the second thin-film transistor TR2 has the double-gate structure. Consequently, the drive thin-film transistor of any of the multiple pixels consists of the first thin-film transistor TR1, and the switching thin-film transistor of any of the multiple pixels consists of the second thin-film transistor TR2, so that the thin-film transistor substrate, according to the configuration of the present disclosure, can easily express grayscale levels and improve the inrush current characteristics.

[0181] Fig. Figures 15A to 15E are cross-sectional views showing a method for forming a thin-film transistor substrate according to an embodiment of the present disclosure.

[0182] First, as it is in Fig. Figure 15A shows that a light-blocking layer 110 is formed on the substrate 100, a buffer layer 120 is formed on the light-blocking layer 110, and then an oxide semiconductor layer 130a is formed to form an active layer on the buffer layer 120.

[0183] Next, as it says in Fig. As shown in Figure 15B, the active layer 130 is formed by structuring the oxide semiconductor layer 130a using the mask 130b. In this situation, the mask 130b is arranged with an opening OP, and then, when the active layer 130 is structured, an active hole AH can be formed in a region on the active layer 130 corresponding to the opening OP. The active hole AH can expose an inner region of the active layer 130 and a section of the upper surface of the buffer layer 120.

[0184] Next, as it says in Fig. Figure 15C shows that a gate insulating layer 140 is formed on the active layer 130, a gate electrode 150 is formed on the gate insulating layer 140, and an intermediate insulating layer 160 is formed on the gate electrode 150.

[0185] Then, after the intermediate insulating layer 160 has been formed, the active layer 130 undergoes a conductivity enablement process using the gate electrode 150 as a mask, thus enabling conductivity properties to be arranged in a sub-region of the active layer 130. Therefore, the active layer 130 can comprise a channel part 131, a first connection part 132a arranged on one side of the channel part 131, and a second connection part 132b arranged on the other side of the channel part 131.

[0186] Following the conductive capability process of the active layer 130, an upper hole TH can be formed by etching a section of the gate insulating layer 140 and a section of the intermediate insulating layer 160 located on the first connecting part 132a, and a drain hole DH can be formed by etching a section of the gate insulating layer 140 and a section of the intermediate insulating layer 160 located on the second connecting part 132b. The upper hole TH can expose a section of the upper surface of the first connecting part 132a of the active layer 130, the active hole AH, and a section of the buffer layer 120 to the outside, and the drain hole DH can expose a section of the upper surface of the second connecting part 132b of the active layer 130 to the outside.

[0187] Next, as it says in Fig. As shown in Figure 15D, a lower hole BH is formed by dry etching a section of the buffer layer 120 exposed by the upper hole TH and the active hole AH. In this situation, forming the lower hole BH by dry etching allows precise control over a portion of the etched buffer layer 120. In particular, if the lower hole BH is formed by wet etching, the size of the active hole AH of the active layer 130 can be changed, and by dry etching, a portion of the buffer layer 120 can be etched while keeping the size of the active hole AH constant. Accordingly, different etching techniques (e.g., wet etching followed by dry etching) can be used to form the upper hole TH and the lower hole BH.

[0188] When the lower hole BH is formed, a portion of the upper surface of the light-blocking layer 110 can be exposed to the outside.

[0189] Next, as it says in Fig. As shown in Figure 15E, a source electrode 170 is formed in the upper hole TH and in the lower hole BH and a drain electrode 180 is formed in the drain hole DH to form a thin-film transistor substrate according to an embodiment of the present disclosure.

[0190] Fig. Figure 16 is a cross-sectional view of a display device comprising a thin-film transistor substrate according to an embodiment of the present disclosure.

[0191] As it is in Fig. As shown in Figure 16, the display device according to an embodiment of the present disclosure can comprise a substrate 100, a light-blocking layer 110, a buffer layer 120, an active layer 130, a gate insulating layer 140, a gate electrode 150, an intermediate insulating layer 160, a source electrode 170, a drain electrode 180, a planarization layer 190, a first electrode 300, a bank layer 310, a light-emitting layer 320 and a second electrode 330.

[0192] The substrate 100, the light-blocking layer 110, the buffer layer 120, the active layer 130, the gate insulating layer 140, the gate electrode 150, the interlayer insulating layer 160, the source electrode 170 and the drain electrode 180 are the same as those described above and repeated descriptions thereof are omitted.

[0193] A third contact hole CH3 may be provided on the planarization layer 190, so that the source electrode 170 is exposed through the third contact hole CH3. In some situations, however, the drain electrode 180 may be exposed through the third contact hole CH3.

[0194] The first electrode 300 can be formed on the planarization layer 190 and connected to the source electrode 170 or the drain electrode 180 via the third contact hole CH3. The first electrode 300 can function as the anode.

[0195] The bench layer 310 can be provided such that it covers an edge of the first electrode 300 to define a light emission region. Accordingly, an upper surface region of the first electrode 300 that is exposed, without being covered by the bench layer 310, becomes a light emission region.

[0196] The light-emitting layer 320 can be provided on the first electrode 300. The light-emitting layer 320 can comprise red, green, and blue light-emitting layers structured for each pixel, or it can be formed from a white light-emitting layer connected to all pixels. If the light-emitting layer 320 is formed from a white light-emitting layer, it can, for example, include, but is not limited to, a first stack with a blue light-emitting layer, a second stack with a yellow-green light-emitting layer, and a charge-generating layer between the first and second stacks.

[0197] The second electrode 330 can be provided on the light-emitting layer 320. The second electrode 330 can function as a cathode.

[0198] In addition, an encapsulation layer can be formed on the second electrode 330, which prevents the penetration of moisture or oxygen.

[0199] Fig. Figure 17 is a schematic representation of a display device according to an embodiment of the present disclosure.

[0200] As it is in Fig. As shown in Figure 17, the display device according to an embodiment of the present disclosure can comprise a display panel 410, a gate driver 420, a data driver 430 and a controller 440.

[0201] The display panel 410 comprises gate lines GLs and data lines DLs, and pixels P are arranged at the respective intersections of the gate lines GLs and data lines DLs. An image is displayed by activating pixel P. The gate lines GLs, the data lines DLs, and the pixels P can be arranged on substrate 100.

[0202] The controller 440 controls the gate driver 420 and the data driver 430. Using a signal supplied by an external system, the controller 440 outputs a gate control signal (GCS) to control the gate driver 420 and a data control signal (DCS) to control the data driver 430. Additionally, the controller 440 samples video data input from the external system, rearranges the sampled input video data, and outputs the rearranged RGB digital video data to the data driver 430.

[0203] The gate control signal GCS comprises a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. Additionally, control signals for controlling a shift register may be included in the gate control signal GCS.

[0204] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0205] The data driver 430 supplies a data voltage to the data lines DL of the display panel 410. In particular, the data driver 430 converts the RGB video data input from the controller 440 into an analog data voltage and supplies the data voltage to the data lines DL.

[0206] The gate driver 420 can be mounted on the display panel 410. As described above, a structure in which the gate driver 420 is mounted directly on the display panel 410 is called a gate-in-panel (GIP) structure. In particular, in the gate-in-panel (GIP) structure, the gate driver 420 can be arranged on the substrate 100.

[0207] The gate driver 420 can include a shift register 450.

[0208] The shift register 450 sequentially supplies gate pulses to the gate lines GL during a single frame, using a start signal and a gate clock sent from the controller 440. The single frame refers to a period during which an image is displayed on the display panel 410. The gate pulse has a turn-on voltage that can switch on a switching device (a thin-film transistor) located in pixel P.

[0209] During the remaining time of a single frame in which the gate pulse is not delivered, the shift register 450 also delivers a gate-off signal, which can switch off the switching device, to the gate line GL. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as the gate signal GS.

[0210] Fig. Figure 18 is a circuit diagram of a pixel provided in a display device according to an embodiment of the present disclosure.

[0211] As it is in Fig. As shown in Figure 18, the display device according to an embodiment of the present disclosure comprises a first to second thin-film transistor T1 and T2 and capacitors Cst.

[0212] The first thin-film transistor T1 is a driver thin-film transistor, and the second thin-film transistor T2 is a switching thin-film transistor. At least one of the first thin-film transistors T1 and T2 can be formed from the different thin-film transistors described above.

[0213] The first thin-film transistor T1 is switched according to the data voltage Vdata supplied from the second thin-film transistor T2, generates a data stream from the drive voltage Vdd supplied by the power line PL, and delivers the data stream to the organic light-emitting diode OLED.

[0214] The second thin-film transistor T2 is switched according to the gate signal GS supplied to the gate line GL and supplies the data voltage Vdata supplied from the data line DL to the first thin-film transistor T1.

[0215] The capacitor Cst serves to maintain the data voltage supplied to the first thin-film transistor T1 for a single image and is provided between the gate electrode and the source electrode of the first thin-film transistor T1.

[0216] The organic light-emitting diode (OLED) emits predetermined light according to a data stream supplied from the first thin-film transistor T1.

[0217] Fig. Figure 19 is a circuit diagram of a pixel provided in a display device according to a further embodiment of the present disclosure.

[0218] As it is in Fig. As shown in Figure 19, the display device according to a further embodiment of the present disclosure comprises a first to third thin-film transistor T1, T2, T3 and a capacitor Cst.

[0219] The first thin-film transistor, T1, is a driver thin-film transistor, and the second and third thin-film transistors, T2 and T3, are switching thin-film transistors. At least one of the first, third, and third thin-film transistors, T1, T2, and T3, can be formed from the different thin-film transistors described above.

[0220] The first thin-film transistor T1 is switched according to the data voltage Vdata supplied from the second thin-film transistor T2, generates a data stream from the drive voltage Vdd supplied by the power line PL, and delivers the data stream to the organic light-emitting diode OLED.

[0221] The second thin-film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata, supplied by the data line DL, to the first thin-film transistor T1.

[0222] The third thin-film transistor T3, in response to the SENSE detection control signal supplied by the SCL scanning line, supplies the current of the first thin-film transistor T1 to the reference line RL. A reference voltage Vref is supplied to the reference line RL.

[0223] The capacitor Cst serves to maintain the data voltage supplied to the first thin-film transistor T1 for a single image and is provided between the gate electrode and the source electrode of the first thin-film transistor T1.

[0224] The organic light-emitting diode (OLED) emits predetermined light according to a data stream supplied from the first thin-film transistor T1.

[0225] Fig. 20 is a circuit diagram of a pixel provided in a display device according to a further embodiment of the present disclosure.

[0226] As it is in Fig. As shown in Figure 20, the display device according to a further embodiment of the present disclosure comprises a first to fourth thin-film transistor T1, T2, T3 and T4 and a capacitor Cst.

[0227] The first thin-film transistor, T1, is a driver thin-film transistor, and the second through fourth thin-film transistors, T2 through T4, are switching thin-film transistors. At least one of the first through fourth thin-film transistors, T1, T2, T3, and T4, can be formed from the different thin-film transistors described above.

[0228] The first thin-film transistor T1 is switched according to the data voltage Vdata supplied from the second thin-film transistor T2, generates a data stream from the drive voltage Vdd supplied by the power line PL, and delivers the data stream to the organic light-emitting diode OLED.

[0229] The second thin-film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and supplies the data voltage Vdata, supplied by the data line DL, to the first thin-film transistor T1.

[0230] The third thin-film transistor T3, in response to the sensing control signal SENSE supplied by the scanning line SCL, supplies the current of the first thin-film transistor T1 to the reference line RL. A reference voltage Vref is supplied to the reference line RL.

[0231] The fourth thin-film transistor T4 is switched according to the light emission control signal EM supplied to the light emission control line EML and supplies the drive voltage Vdd, supplied by the power line PL, to the first thin-film transistor T1.

[0232] The capacitor Cst serves to maintain the data voltage supplied to the first thin-film transistor T1 for a single image and is provided between the gate electrode and the source electrode of the first thin-film transistor T1.

[0233] The organic light-emitting diode (OLED) emits predetermined light according to a data stream supplied from the first thin-film transistor T1.

[0234] Accordingly, the present disclosure may have the following advantages.

[0235] According to one embodiment of the present disclosure, since a lower hole is provided on one side of the active layer and a source electrode is designed to penetrate the lower hole, the active layer, the source electrode and the light-blocking layer arranged below the active layer are connected to each other, so that the active layer and the light-blocking layer can be electrically connected without a connecting electrode.

[0236] According to one embodiment of the present disclosure, the active layer and the light-blocking layer are electrically connected by the source electrode, which is located in the lower hole that is arranged on one side of the active layer, thereby reducing the size of the thin-film transistor and ensuring additional space for forming other wiring and electrodes.

[0237] According to one embodiment of the present disclosure, since the active layer and the light-blocking layer are electrically connected by the source electrode located in the lower hole, the S-factor of the driving thin-film transistor can be improved to facilitate grayscale representation.

[0238] According to one embodiment of the present disclosure, since the lower surface of the upper electrode is in contact with a section of the upper surface of the active layer and the lower electrode is in contact with the side surface of the active layer, the contact area between the active layer and the source electrode is increased, thereby reducing the contact resistance between the active layer and the source electrode and improving the brightness of a corresponding subpixel.

[0239] It is apparent to those skilled in the art that various substitutions, modifications, and variations are possible within the scope of this disclosure without departing from its original scope. Therefore, the scope of this disclosure is represented by the following claims, and any changes or modifications derived from the meaning, scope, and equivalence concept of the claims shall be interpreted as being contained within the scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0081683

[0001]

Claims

[1] Thin film transistor substrate comprising: a light blocking layer (110) disposed on a substrate (100); an active layer (130) disposed on the light blocking layer (110), the active layer having a bottom hole (BH); a gate electrode (150) disposed on the active layer (130); a source electrode (170) electrically connected to both the active layer (130) and the light blocking layer (110); and an insulating layer (140; 160) disposed between the active layer (130) and the source electrode (170), the insulating layer having an upper hole (TH), wherein the source electrode (170) comprises a lower electrode (172) arranged in the lower hole (BH) and an upper electrode (171) arranged in the upper hole (TH), wherein an area of a lower surface of the upper electrode (171) is larger than an area of an upper surface of the lower electrode (172). [2] Thin film transistor substrate comprising: a light blocking layer (110) disposed on a substrate (100); an active layer (130) overlapping the light blocking layer (110); a lower hole (BH) passing through the active layer (130); a gate electrode (150) overlapping with the active layer (130); a source electrode (170) penetrating the active layer (130) and contacting the light blocking layer (110); an insulating layer (140; 160) disposed on the active layer (130); and an upper hole (TH) passing through the insulating layer (140; 160), wherein the source electrode (170) comprises a lower electrode (172) arranged in the lower hole (BH) and an upper electrode (171) arranged in the upper hole (TH), and wherein a width of the upper electrode (171) is greater than a width of the lower electrode (172). [3] A thin film transistor substrate according to claim 1 or 2, wherein the upper hole (TH) and the lower hole (BH) communicate with each other. [4] Thin film transistor substrate according to one of the preceding claims, wherein the upper electrode (171) contacts an entire upper surface of the lower electrode (172) and a portion of an upper surface of the active layer (130), and / or wherein a center of the upper hole (TH) is aligned with a center of the lower hole (BH). [5] Thin film transistor substrate according to one of claims 1 to 3, wherein a distance from one end of the lower surface of the upper electrode (171) to the lower hole (BH) is greater than a distance from another end of the lower surface of the upper electrode (171) to the lower hole (BH) and / or wherein a center of the upper hole (TH) does not overlap with a center of the lower hole (BH). [6] A thin film transistor substrate according to any one of the preceding claims, further comprising: a drain hole (DH) arranged in the insulating layer (140; 160); and a drain electrode (180) connected to one side of the active layer (130) through the drain hole (DH), where a size of the top hole (TH) is larger than a size of the drain hole (DH). [7] A thin film transistor substrate according to any one of claims 1 to 6, further comprising: a gate insulating layer (140) disposed between the active layer (130) and the gate electrode (150), wherein one end of the gate insulating layer (140) corresponds to one end of the gate electrode (150) and another end of the gate insulating layer (140) corresponds to another end of the gate electrode (150), and wherein the insulating layer (140; 160) comprises an interlayer insulating layer (160) contacting a portion of a top surface of the active layer (130). [8] A thin film transistor substrate according to any one of claims 1 to 6, wherein the insulating layer (140; 160) comprises: a gate insulating layer (140) disposed between the active layer (130) and the gate electrode (150) and disposed on an entire surface of the substrate (100); and an interlayer insulating layer (160) disposed on the gate insulating layer (140). [9] Thin-film transistor substrate according to one of the preceding claims, wherein the lower hole (BH) and the upper hole (TH) do not overlap with the gate electrode (150), and / or wherein the active layer (130) comprises a channel part (131), a first connection part (132a) arranged on one side of the channel part (131), and a second connection part (132b) arranged on another side of the channel part (131), and wherein the lower electrode (172) is arranged in one of the first connection part (132a) and the second connection part (132b). [10] A thin film transistor substrate according to any one of the preceding claims, wherein the lower electrode (172) comprises a plurality of lower electrodes (172a; 172b, 172c) spaced apart from each other. [11] Thin film transistor substrate according to one of claims 1 to 10, wherein the lower electrode (172) comprises a plurality of lower electrodes (172a; 172b, 172c), wherein the upper electrode (171) comprises a plurality of upper electrodes (171a; 171b; 171c), and wherein the plurality of upper electrodes each correspond one-to-one to the plurality of lower electrodes, and / or wherein the thin-film transistor substrate further comprises a second lower hole (BHb) passing through the active layer (130) and a second upper hole (THb) passing through the insulating layer (140; 160), and wherein the source electrode (171) is arranged in the first and second lower holes (Bha; BHb) and the first and second upper holes (THa; THb), and / or wherein the thin film transistor substrate further comprises a second lower hole (BHb) passing through the active layer (130), a third lower hole (BHc) passing through the active layer (130), a second upper hole (THb) passing through the insulating layer (140; 160), and a third upper hole (THc) passing through the insulating layer (140; 160), and wherein the source electrode (171) is arranged in the first, second and third lower holes (Bha; BHb; BHc) and the first, second and third upper holes (THa; THb; THc). [12] Thin film transistor substrate according to one of claims 1 to 10, wherein the lower electrode (172) comprises a plurality of lower electrodes (172a; 172b, 172c) spaced apart from one another, wherein the upper electrode (171) extends continuously over at least two adjacent lower electrodes (172a; 172b) of the plurality of lower electrodes, and / or wherein the thin-film transistor substrate has a second lower hole (BHb) passing through the active layer (130); a third lower hole (BHc) passing through the active layer (130); and a second upper hole (THb) passing through the insulating layer (140; 160), wherein the source electrode (170) is arranged in the first, second and third lower holes (Bha; BHb; BHc) and the first and second upper holes (THa; THb), and / or wherein the thin-film transistor substrate has a second lower hole (BHb) passing through the active layer (130); a third lower hole (BHc) passing through the active layer (130); and a second upper hole (THb) passing through the insulating layer (140; 160), wherein the first upper hole (THa) communicates with both the first lower hole (Bha) and the second lower hole (BHb), and wherein the source electrode (170) is arranged in the first, second, and third lower holes (Bha; BHb; BHc) and the first and second upper holes (THa; THb). [13] A thin film transistor substrate according to any one of claims 10 to 12, wherein the plurality of lower electrodes (172a; 172b, 172c) have different sizes. [14] A method of manufacturing a thin film transistor substrate, the method comprising: Forming a light blocking layer (110) on a substrate (100); Forming an active layer (130) on the light blocking layer (110); Forming an active hole (AH) in the active layer (130); Forming a gate insulating layer (140) on the active layer (130); Forming a gate electrode (150) on the gate insulating layer (140); Forming an interlayer insulating film (160) on the gate electrode (150); forming an upper hole (TH) extending through the interlayer insulating layer (160); Forming a lower hole (BH) exposing a portion of the light blocking layer (110) by expanding the active hole (AH); and Forming a source electrode (170) within the lower hole (BH) and within the upper hole (TH). [15] The method according to claim 14, wherein an area of a lower surface of the upper hole (TH) is larger than an area of an upper surface of the lower hole (BH). [16] The method of claim 14 or 15, wherein forming the active hole (AH) in the active layer (130) comprises: Formation of multiple active holes (AH); and wherein forming the lower hole (BH) comprises forming a plurality of lower holes (BH), wherein the light blocking layer (110) is exposed by expanding the plurality of active holes (AH). [17] Display device comprising: a display area and a non-display area on a substrate (100); a first thin-film transistor (TR1) arranged on the substrate (100); and a second thin-film transistor (TR2), wherein the first thin-film transistor (TR1) comprises: a first light blocking layer (110); a first active layer (130) disposed on the first light blocking layer (110), the first active layer (130) having a bottom hole (BH); a first gate electrode (150) disposed on the first active layer (130); a first source electrode (170) electrically connected to both the first active layer (130) and the first light blocking layer (110); and an insulating layer (140; 160) disposed between the first active layer (130) and the first source electrode (170), the insulating layer having an upper hole (TH), wherein the first source electrode (170) comprises a lower electrode (172) arranged in the lower hole (BH) and an upper electrode (171) arranged in the upper hole (TH), wherein the first active layer (130) and the first light blocking layer (110) are electrically connected to each other by the lower electrode (172), and wherein an area of a lower surface of the upper electrode (171) is larger than an area of an upper surface of the lower electrode (172). [18] A display device according to claim 17, wherein the first thin film transistor (TR1) is a driving thin film transistor arranged in the display region, and wherein the second thin film transistor (TR2) is a switching thin film transistor arranged in the display region or a thin film transistor arranged in a gate driver (420) arranged in the non-display region.

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