MOTHER SUPTRAT AND INDICATOR USING THE SAME

Abstract

A mother substrate for a display panel and a display panel using the same substrate are disclosed. A mother substrate (1100) for a display panel (100) has a conductive ring (300) arranged in a non-display area (NA) outside the display area (AA) and surrounding each of the display areas (AA), and one or more dummy pixel driver circuits (20a) arranged in a non-display area (NA) outside the display area (AA). An electrostatic discharge (ESD) prevention structure within the dummy pixel driver circuit (20a) can prevent defects of display panels (100) due to ESD occurring during the manufacturing process of the display panel (100).

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the priority and benefit of Korean patent application No. 10 2023 0 096 834, filed on July 25, 2023. BACKGROUND

[0002] This application relates to a parent substrate and a display device using the same. AREA

[0003] Electroluminescent display devices can be broadly divided into organic light-emitting display devices, in which organic light-emitting diodes (OLEDs) are arranged in pixels, and inorganic light-emitting display devices, in which inorganic light-emitting diodes (hereinafter referred to as "LEDs") are arranged in pixels.

[0004] Since electroluminescent displays use self-illuminating elements to display images, they do not require a separate light source, such as a backlight unit, and can be implemented in thin and diverse forms. Electroluminescent displays not only offer excellent power consumption, response time, brightness, and viewing angle, but also excellent contrast ratio and color reproduction, as they can display shades of black as true black.

[0005] Organic light-emitting display devices must be designed in such a way as to prevent the ingress of oxygen and moisture, as the ingress of moisture and oxygen can lead to oxidation between the organic light-emitting layer and the electrode.

[0006] One example of inorganic light-emitting display devices attracting attention as next-generation displays are micro-LED displays, in which micro-LEDs are arranged in pixels. These micro-LEDs can be inorganic LEDs with a size of 100 µm or less. The micro-LEDs are fabricated in a separate semiconductor process and transferred to the pixel positions on the substrate of the display panel, allowing them to be positioned in each subpixel for each color. OVERVIEW OF THE INVENTION

[0007] Electrostatic discharge (ESD) can occur during the manufacturing process of a display panel. Such ESD can cause problems, such as insulation breakdowns or short circuits, between thin layers of the display panel.

[0008] This application is intended to address the needs and / or problems mentioned above.

[0009] The present application provides a parent substrate capable of blocking electrostatic discharges affecting a display panel, and a display panel comprising the same.

[0010] The problems or limitations that are to be solved or addressed by the present disclosure are not limited to those mentioned above, and any other problems or limitations not mentioned will be clearly understood by those skilled in the art from the following description.

[0011] In accordance with one aspect of the present disclosure, a mother substrate according to claim 1 is provided. Furthermore, in accordance with other aspects of the present disclosure, a mother substrate according to claim 15, a display panel according to claim 16, and a display panel according to claim 17 are provided. Further embodiments are described in the dependent claims.

[0012] In accordance with one aspect of the present description, a mother substrate is provided comprising a plurality of display areas, which comprise a plurality of light-emitting areas in which a light-emitting element is arranged, a plurality of circuits, and a plurality of pads connected to the plurality of circuits. The substrate also includes a pixel driver circuit located within the display area and incorporating an electrostatic suppression structure, a conductive ring located in a non-display area outside the display area and surrounding each of the plurality of display areas, and one or more dummy pixel driver circuits located in a non-display area outside the display area. The dummy pixel driver circuit may incorporate the same electrostatic suppression structure as the pixel driver circuit.

[0013] In accordance with another aspect of the present application, a parent substrate is provided comprising a control driver with one or more pixel control circuits arranged in a display area, a conductive ring arranged in a non-display area outside the display area and surrounding the display area, and a dummy driver arranged in a non-display area outside the display area, wherein the control driver of the display area and the dummy driver of the non-display area have identical electrostatic protection circuits. The conductive ring can be electrically connected to the electrostatic protection circuit of the dummy driver by means of wiring.

[0014] The display panel can have a display area and can be separated from the mother substrate.

[0015] In accordance with the present application, the dummy pixel driver circuit, which has essentially the same function and structure as the pixel driver circuit arranged in the display panel on the mother substrate, is arranged outside the display panel, and an electrostatic discharge (ESD) protection structure is used inside the dummy pixel driver circuit, so that defects of display panels due to ESD generated in the manufacturing process of the display panel can be prevented.

[0016] In accordance with this application, it is possible to increase the yield of the display panel, optimize the manufacturing process of the display panel, and reduce the production energy.

[0017] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be obviously understood by those skilled in the art from the following description and the attached claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other tasks, features and advantages of the present disclosure will become clearer to those skilled in the art by the detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which: Fig. 1 a diagram that represents a display device according to an embodiment of the present application; Fig. 2 an enlarged view of area A of the Fig. 1 is; Fig. 3. A diagram is a representation of a portion of a pixel; Fig. 4 a cross-sectional view along a line II' in Fig. 3 is; Fig. 5 a cross-sectional view along a line II-II' in Fig. 3 is; Fig. 6 a cross-sectional view along a line III-III' in Fig. 3 is; Fig. Figure 7 is a cross-sectional view illustrating an example in which a light-emitting element and a light-emitting sub-element are electrically connected to a pixel driver circuit; Fig. 8 is a diagram that represents a display device according to a further embodiment of the present application; Fig. 9 a cross-sectional view along a line IV-IV' in Fig. 8 is; Fig. 10 is a cross-sectional view of a display panel, which schematically represents an example of multi-layer wiring structures; Fig. 11A and Fig. 11B Diagrams are those that represent one or two display panels arranged on a mother substrate; Fig. 12 is a cross-sectional view showing a longitudinal cross-sectional structure of an electrostatic blocking area along a line VV' in Fig. 11A represents; Fig. 13 is a view that schematically represents a structure of a control driver according to an embodiment of the present application; and Fig. 14 and Fig. 15 circuit diagrams are shown, representing an electrostatic discharge (ESD) protection circuit. DETAILED DESCRIPTION OF EXAMPLE EXECUTIONS

[0019] The advantages and features of the present disclosure and methods for implementing it will become more readily apparent with reference to the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in several different forms. Rather, the present embodiments complete the disclosure and enable those skilled in the art to fully grasp the scope of the present disclosure. The present disclosure is defined only within the scope of the claimed claims.

[0020] The shapes, sizes, ratios, angles, numbers, and the like shown in the accompanying drawings to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited to them. The same reference numerals generally denote the same elements throughout the present application. Furthermore, when describing the present disclosure, detailed descriptions of known related technologies may be omitted in order not to obscure the subject matter of the present disclosure unnecessarily.

[0021] The terms used herein, such as "indicating," "containing," "with," and "including," are generally to be understood as allowing the addition of other components, unless the terms are used with the word "only." Any references to the singular may include the plural unless explicitly stated otherwise.

[0022] Components are interpreted as having a normal error range, even if this is not explicitly stated.

[0023] When describing a positional or connection relationship between two components, such as "on", "above", "below", "next to", "connect or couple with", "cross", "intersect" or similar, one or more other components may be inserted between them unless "immediately" or "directly" is used.

[0024] When describing a temporal predecessor relationship, such as "after", "subsequent", "next to", "before" or similar, this cannot be continuous on a time basis unless "immediately" or "directly" is used.

[0025] The terms “first”, “second”, and the like can be used to distinguish elements from one another, however, the functions or structures of the components are not restricted by ordinal numbers or component names preceding the components.

[0026] The following embodiments can be partially or fully interconnected or combined and can be linked and operated in technically different ways. The embodiments can be implemented independently or in association with one another.

[0027] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

[0028] A display device according to an embodiment of the present application comprises a display panel, which includes a display area or screen on which an image is displayed, and a pixel control circuit for controlling pixels on the display panel. The display area includes a pixel area in which pixels are arranged. The pixel area includes a plurality of light-emitting areas. A light-emitting element is arranged in each of the light-emitting areas. The pixel control circuit can be integrated into the display panel.

[0029] Fig. 1 is a diagram representing a display device according to an embodiment of the present application; Fig. Figure 2 is an enlarged view of area A of the Fig. 1; Fig. Figure 3 is a diagram that represents a portion of a pixel.

[0030] Referring to Fig. 1 and Fig. 2. A display device according to an embodiment of the present application has a display panel 100 that visually reproduces an input image. The display panel 100 can have a display area AA in which an image is displayed and a non-display area NA in which the image is not displayed. Various wiring and control circuits can be located in the non-display area NA, and a pad section PAD can be arranged therein, to which integrated circuits, printed circuits, etc., are connected.

[0031] A plurality of light-emitting elements 10, arranged in the display area AA such that they form pixels PXL, can be micro-sized inorganic light-emitting elements. The light-emitting elements can be grown on a silicon wafer and then attached to the display panel by a transfer process.

[0032] The transmission process of the light-emitting element 10 can be carried out for each previously subdivided area. In Fig. The display area AA is divided into nine transmission areas ST, however, the size or number of subdivisions of the transmission areas is not limited here. The transmission process can be carried out sequentially or simultaneously for the first through ninth transmission areas ST. Blue, green, and red light-emitting elements 10 can be transmitted sequentially within the transmission area ST.

[0033] In the non-display area NA, a data drive circuit or a gate drive circuit may be located, and lines for supplying control signals to control these drive circuits may be provided. These control signals may include various timing signals, such as a clock signal, an input data enable signal, and a synchronization signal, and may be received via the pad section PAD.

[0034] The pixels PXL can be driven by a pixel drive circuit. The pixel drive circuit can receive a drive voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc., and output an anode voltage and a cathode voltage of the light-emitting element 10 to drive a plurality of pixels. The drive voltage can be a high-potential voltage (EVDD). The cathode voltage can be a low-potential voltage (EVSS), which is commonly applied to the pixels. The anode voltage can be a voltage corresponding to the pixel data value of the image signal. The pixel drive circuit can be located in the non-display area NA or in a lower section of the display area AA.

[0035] Each pixel PXL can contain a plurality of subpixels, each of a different color. For example, the plurality of pixels can contain a red subpixel, in which the light-emitting element 10, which emits light at a red wavelength, is located; a green subpixel, in which the light-emitting element 10, which emits light at a green wavelength, is located; and a blue subpixel, in which the light-emitting element 10, which emits light at a blue wavelength, is located. The plurality of pixels can also contain white pixels.

[0036] Referring to Fig. 2 and Fig. 3. The majority of pixels PXL can be arranged sequentially in a first direction (X-axis direction) and a second direction (Y-axis direction). Within the pixels of the display area AA, a majority of subpixels of the same color can be arranged.For example, each of the plurality of pixels can have a first red subpixel in which a first-first light-emitting element 11a is arranged, which emits light at a red wavelength, a second red subpixel in which a first-second light-emitting element 11b is arranged, which emits light at a red wavelength, a first green subpixel in which a second-first light-emitting element 12a is arranged, which emits light at a green wavelength, a second green subpixel in which a second-second light-emitting element 12b is arranged, which emits light at a green wavelength, a first blue subpixel in which a third-first light-emitting element 13a is arranged, which emits light at a blue wavelength, and a second blue subpixel in which a third-second light-emitting element 13b is arranged, which emits light at a blue wavelength.The first light-emitting element 11a, the second light-emitting element 12a, and the third light-emitting element 13a can be interpreted as primary light-emitting elements. The first two light-emitting elements 11b, the second two light-emitting elements 12b, and the third two light-emitting element 13b can be interpreted as sub-elements.

[0037] A subpixel contains one or more light-emitting elements, and if one light-emitting element becomes defective, the brightness of another light-emitting element can be increased to adjust the brightness of the subpixel. However, it is not necessarily limited to this, and a subpixel can contain only one light-emitting element.

[0038] Each of a plurality of first electrodes 161 can be arranged in a lower section of the light-emitting element 10 and can be selectively connected to a plurality of signal wires TL1 to TL6 via extension sections 161a. A high-potential voltage can be applied to the pixel control circuit via the signal wires TL1 to TL6. The signal wires TL1 to TL6 and the first electrode 161 can be formed as a single electrode structure, which is formed in one piece in an electrode structuring process.

[0039] Visually, the first signal wire TL1 can be connected to an anode electrode of the first red subpixel, and the second signal wire TL2 can be connected to an anode electrode of the second red subpixel. The third signal wire TL3 can be connected to an anode electrode of the first green subpixel, and the fourth signal wire TL4 can be connected to an anode electrode of the second green subpixel. The fifth wire TL5 can be connected to an anode electrode of the first blue subpixel, and the sixth wire TL6 can be connected to an anode electrode of the second blue subpixel. If a subpixel has only one light-emitting element, the number of signal wires TL can be reduced by half.

[0040] A second electrode 170 can be a cathode electrode arranged in each row such that a cathode voltage is applied to the light-emitting element 10, which is continuously arranged in the first direction (X-axis direction). A plurality of second electrodes 170 can be arranged such that they are spaced apart from one another in the second direction (Y-axis direction). The plurality of second electrodes 170 can be connected to the cathode voltage via a contact electrode 163. Each of the plurality of second electrodes 170 can be electrically connected to the contact electrode 163. However, this is not necessarily limited to the connection, and the second electrode 170 can have a single electrode layer instead of being divided into a plurality of electrodes to function as a common electrode.

[0041] Fig. 4 is a cross-sectional view along a line II' in Fig. 3. Fig. 5 is a cross-sectional view along a line II-II' in Fig. 3. Fig. 6 is a cross-sectional view along a line III-III' in Fig. 3. Fig. Figure 7 is a cross-sectional view showing an example in which two light-emitting elements are connected to a pixel control circuit.

[0042] Referring to Fig. 3 to Fig. 5 a display device according to one embodiment comprises a plurality of first electrodes 161 and a contact electrode 163 arranged on a substrate 110, a plurality of light-emitting elements 10 arranged on a plurality of first electrodes 161, a first optical layer 141 arranged between the plurality of light-emitting elements 10, and a second electrode 170 arranged on the plurality of light-emitting elements 10.

[0043] Substrate 110 can be made of a flexible plastic. For example, substrate 110 can consist of a single-layer or multi-layer substrate made of a material selected from, but not limited to, polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone and polyarylate, polysulfone and cyclic olefin copolymer. For example, substrate 110 can be a ceramic substrate or a glass substrate.

[0044] A pixel driver circuit 20 can be arranged in the display area AA on the substrate 110. The pixel driver circuit 20 can comprise a plurality of thin-film transistors using an amorphous silicon semiconductor, a polycrystalline silicon semiconductor, or an oxide semiconductor.

[0045] The pixel control circuit 20 can comprise at least one control thin-film transistor, at least one switching thin-film transistor, and at least one storage capacitor. If the pixel control circuit 20 comprises a plurality of thin-film transistors, it can be formed on the substrate 110 by a thin-film transistor (TFT) fabrication process. In embodiments, the pixel control circuit 20 can be a collective term for a plurality of thin-film transistors that are electrically connected to the light-emitting element 10.

[0046] The pixel driver circuit 20 can be a driver fabricated using a metal oxide silicon field-effect transistor (MOSFET) fabrication method on a single-crystal semiconductor substrate 110. The driver can include a plurality of pixel driver circuits for driving a plurality of subpixels. If the pixel driver circuit 20 is implemented as a driver after an adhesive layer has been deposited on the substrate 110, the driver can be applied to the adhesive layer by a transfer process.

[0047] A buffer layer 121, which covers the pixel control circuit 20, can be arranged on the substrate 110. The buffer layer 121 can consist of an organic insulating material, for example photosensitive photoacrylic or photosensitive polyimide, but is not limited to this.

[0048] The buffer layer 121 can be used by stacking an inorganic insulating material, for example silicon nitride (SiNx) or silicon oxide (SiO2), in several layers, and can be used by stacking an organic insulating material and an inorganic insulating material in several layers.

[0049] An insulating layer 122 can be arranged on the buffer layer 121. The insulating layer 122 can be made of an organic insulating material, such as photosensitive photoacrylic or photosensitive polyimide, but is not limited to this. Interconnect wires RT1 and RT2 can be arranged on the buffer layer 121. The interconnect wires RT1 and RT2 can be connected by the corresponding signal wires TL1 to TL6 or can be connected to the signal wires TL1 to TL6. The interconnect wires RT1 and RT2 can have a plurality of wiring structures arranged on different layers, with one or more insulating layers inserted between them. The wiring structures arranged on the different layers can be electrically connected via contact holes that pass through the insulating layers.

[0050] Multiple dam structures 130 can be arranged on the insulating layer 122. At least one light-emitting element 10 can be arranged on each dam structure 130. For example, a first light-emitting element 11 can be arranged on a first dam structure 130, a second light-emitting element 12 is arranged on a second dam structure 130, and a third light-emitting element 13 can be arranged on a third dam structure 130.

[0051] The dam structures 130 can consist of an organic insulating material, for example, photosensitive acrylic or photosensitive polyimide, but are not limited to this. The dam structure 130 can specify a position at which the light-emitting element 10 is to be placed during the light-emitting element 10 transfer process. The dam structure 130 can be omitted.

[0052] A solder structure 162 can be arranged on the first electrode 161. The solder structure 162 can be made of indium (In), tin (Sn), or an alloy thereof, but is not limited to this.

[0053] The majority of light-emitting elements 10 can be placed on the solder structure 162. A pixel can have light-emitting elements 10 in three colors. The first light-emitting element 11 can be red, the second light-emitting element 12 can be green, and the third light-emitting element 13 can be blue. Two light-emitting elements can be placed in each subpixel.

[0054] A first optical layer 141 can cover the majority of light-emitting elements 10 and the dam structure 130. Accordingly, the first optical layer 141 can cover areas between the majority of light-emitting elements 10 and between the majority of dam structures 130. The first optical layer 141 can extend in the first direction (X) and be spaced at a distance in the second direction (Y) such that it is separated between rows of pixels.

[0055] The first optical layer 141 can comprise an organic insulating material in which fine metal particles, such as titanium dioxide particles, are dispersed. Light emitted by the majority of light-emitting elements 10 can be scattered by fine metal particles dispersed in the first optical layer 141 in such a way that it is emitted outwards.

[0056] The second electrode 170 can be arranged on the majority of light-emitting elements 10. The second electrode 170 can be connected to the majority of pixels PXL. The second electrode 170 can be a thin electrode through which light passes. The second electrode 170 can be a translucent electrode material, for example indium tin oxide (ITO), but is not limited to this.

[0057] The second electrode 170 can extend in the first direction (X-axis direction) and be arranged at a distance in the second direction (Y-axis direction). The second electrode 170 can have a first region 171, which is arranged on a top surface of the light-emitting element 10 and on a top surface of the first optical layer 141; a second region 172, which is in contact with and electrically connected to the contact electrode 163; and a third region 173, which is arranged on a side of the first optical layer 141 and connects the first region 171 and the second region 172.

[0058] In one plane, each of the majority of second electrodes 170 can overlap the first optical layer 141, and the second area 172 can cover a plane outside the first optical layer 141.

[0059] The second optical layer 142 can be an organic insulating material surrounding the first optical layer 141. The second optical layer 142 can be arranged together with the first optical layer 141 on the insulating layer 122. The first optical layer 141 and the second optical layer 142 can be made of the same material (for example, siloxane). For example, the first optical layer 141 can be siloxane containing titanium oxide (TiOx), and the second optical layer 142 can be siloxane that does not contain titanium oxide (TiOx). However, this is not necessarily limited, and the first optical layer 141 and the second optical layer 142 can be made of the same material or they can be made of different materials.

[0060] In accordance with one embodiment, since the second area 172 of the second electrode 170 is connected to the contact electrode 163 in an overall flat state, no excessive stress is concentrated at the point of connection with the contact electrode 163. Therefore, it is possible to effectively prevent cracks from forming in the second electrode 170.

[0061] The second optical layer 142 can cover the second region 172 and the third region 173 of the second electrode 170. The top surface of the second optical layer 142 and the top surface of the first region 171 of the second electrode 170 can be coplanar. In other words, the first optical layer 141 and the second optical layer 142 can act as planar layers. Consequently, a black matrix 190 structure can be easily formed on the first optical layer 141 and the second optical layer 142, since there is no step on the surface where the black matrix 190 is formed. However, this is not necessarily limited, and the top surfaces of the second optical layer 142 and the second electrode 170 can have different heights.

[0062] The black matrix 190 can be an organic insulating material to which a black pigment has been added. The second electrode 170 can be in contact with the contact electrode 163 beneath the black matrix 190. A transmission hole 191 can be formed between the structures of the black matrix 190, through which light emitted by the light-emitting element 10 is radiated outwards. The black matrix 190 can improve the problem of the mixing of light emitted by neighboring light-emitting elements 10 through the first optical layer 141.

[0063] The cover layer 180 can be an organic insulating material for covering the black matrix 190 and the second electrode 170. In Fig. Figure 3 does not show the design of the black matrix 190 and the cover layer 180.

[0064] The contact electrode 163 is electrically connected to the first connecting wire RT1, which is located on a lower section of it, and the first connecting wire RT1 can be connected to the pixel control circuit 20. Accordingly, a cathode voltage can be applied to the second electrode 170 via the contact electrode 163. The first electrode 161 can be electrically connected to the second connecting wire RT2. This will be described later.

[0065] Referring to Fig. 5. The contact electrode 163 and the signal wires TL1 to TL6 can be arranged on the same plane. The pixel control circuit 20 can be arranged on a lower section of the contact electrode 163 and the signal wires TL1 to TL6. If the pixel control circuit 20 is a control driver, a plurality of control drivers can be arranged in the display panel.

[0066] A passivation layer 133 can expose the contact electrode 163 in such a way that the contact electrode 163 and the second electrode 170 are electrically connected. Furthermore, the passivation layer 133 can insulate the signal wires TL2 to TL5 and the second electrode 170.

[0067] Referring to Fig. 6 a connecting section 161a of the first electrode 161 extends to a side surface 131 of the dam structure 130 and is electrically connected to the connecting wiring RT2 arranged on the insulating layer 122.

[0068] The first electrode 161, the connection section 161a, the signal wiring TL and / or the connection wires RT1 and RT2 can have a single or multilayer metal layer selected from titanium (Ti), molybdenum (Mo) and aluminum (Al). The first electrode 161, the connection section 161a, the signal wiring TL and / or the connection wires RT1 and RT2 can be formed in a multilayer structure comprising a first layer ML1, a second layer ML2, a third layer ML3 and a fourth layer ML4.

[0069] The first layer ML1 and the third layer ML3 can consist of titanium (Ti) or molybdenum (Mo). The second layer ML2 can consist of aluminum (Al). The fourth layer ML4 can consist of a translucent conductive oxide layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO), which exhibits good adhesion to the solder structure 162, corrosion resistance, and acid resistance.

[0070] The first layer ML1, the second layer ML2, the third layer ML3 and the fourth layer ML4 can be deposited one after the other and then structured by a photolithography process and an etching process.

[0071] The passivation layer 133 can be arranged on the first electrode 161 and the signal wiring TL and can have an opening hole 133a that exposes the solder structure 162.

[0072] The light-emitting element 10 can have a semiconductor layer of a first conductive type 10-1, an active layer 10-2 arranged on the semiconductor layer of the first conductive type 10-1, and a semiconductor layer of a second conductive type 10-3 arranged on the active layer 10-2. A first control electrode 15 can be arranged on a lower section of the semiconductor layer of the first conductive type 10-1, and a second control electrode 14 can be arranged on an upper section of the semiconductor layer of the second conductive type 10-3.

[0073] The light-emitting element 10 can be formed on a silicon wafer using methods such as metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor epitaxy (HVPE), sputtering and the like.

[0074] The first conductive type 10-1 semiconductor layer can be implemented as a compound semiconductor, such as group III-V, group II-VI, etc., and can be doped with a first dopant. The first conductive type 10-1 semiconductor layer can be made from any or more of the semiconductor materials with the composition formula Al x1 In y1 Ga (1-x1-y1)The semiconductor layers can be formed from the following types: N (0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), InAlGaN, AlGaAs, GaP, GaAs, and AlGaInP, but this is not limited to them. If the first dopant is an n-type dopant, such as Si, Ge, Sn, Se, Te, etc., the first conductive type 10⁻¹ semiconductor layer can be an n-type nitride semiconductor layer. However, if the first dopant is a p-type dopant, the first conductive type 10⁻¹ semiconductor layer can be a p-type nitride semiconductor layer.

[0075] The active layer 10-2 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 10-1 collide with holes (or electrons) injected through the second conductive semiconductor layer 10-3. The active layer 10-2 can generate light, which, upon recombination of electrons and holes, transitions to lower energy levels and has a corresponding wavelength.

[0076] The active layer 10-2 can have any single-pot structure, multi-pot structure, single-quantum-pot structure, multi-quantum-pot (MQW) structure, quantum dot structure, or quantum line structure, and the structure of the active layer 10-2 is not limited to these. The active layer 10-2 can generate light in a wavelength band of visible light. Intuitively, the active layer 10-2 can emit light in any of the blue, green, and red wavelength ranges.

[0077] The second conductive semiconductor layer 10-3 can be arranged on the active layer 10-2. The second conductive semiconductor layer 10-3 can be implemented as a compound semiconductor, such as group III-V, group II-VI, etc., and the second conductive semiconductor layer 10-3 can be doped with a second dopant. The second conductive semiconductor layer 10-3 can be made of semiconductor materials with a composition formula In x2 Al y2 Ga 1-x2+y2N (0≤x2≤1, 0≤y2≤1, 0≤x2 +y2≤1) or can be formed from materials selected from AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP. If the second dopant is a p-type dopant, such as Mg, Zn, Ca, Sr, Ba, etc., the second conductive semiconductor layer doped with the second dopant can be a p-type semiconductor layer. If the second dopant is an n-type dopant, the second conductive semiconductor layer can be an n-type nitride semiconductor layer.

[0078] A reflective layer 16 can be arranged on a side face and a lower section of the light-emitting element 10. The reflective layer 16 can have a structure in which a reflective material is dispersed in a resin layer, but is not necessarily limited to this. Visually, the reflective layer 16 can be manufactured as a reflector with various structures. Light emitted by the active layer 10-2 can be reflected upwards by the reflective layer 16 to increase the light extraction efficiency.

[0079] Although the embodiment is described as a vertical structure in which the control electrodes 14 and 15 are arranged on the upper and lower sections of the light-emitting structure, the light-emitting device may also have a lateral structure or a flip-chip structure in addition to the vertical structure.

[0080] Referring to Fig. 7. A light-emitting main element 12a and a light-emitting sub-element 12b of the subpixel can be arranged on the dam structure 130. The second light-emitting element 12 is described in detail. A first-first electrode 161-1, which is connected to the light-emitting main element 12a, can extend to one side face of the dam structure 130 such that it is electrically connected to the second-first connecting wire RT21, which is arranged on a lower section thereof. The first-second electrode 161-2, which is connected to the light-emitting sub-element 12b, can extend to the other side face of the dam structure 130 such that it is electrically connected to the second-second connecting wire RT22, which is arranged on a lower section thereof.

[0081] The pixel control circuit 20 can apply an anode voltage to the light-emitting main element 12a via the second-first connection RT21 and can apply a control voltage to the light-emitting sub-element 12b via the second-second connection RT22. The pixel control circuit 20 can apply a cathode voltage to the light-emitting main element 12a and the light-emitting sub-element 12b via the first connection RT1 and the second electrode 170.

[0082] The pixel control circuit 20 can adjust the brightness by controlling only the main light-emitting element 12a, or it can adjust the brightness by controlling both the main light-emitting element 12a and the sub-light-emitting element 12b simultaneously. If the main light-emitting element 12a is dimmed, the brightness can be adjusted by controlling only the sub-light-emitting element 12b.

[0083] Fig. Figure 8 is a diagram illustrating a display device according to a further embodiment of the present application. Fig. 9 is a cross-sectional view along a line IV-IV' in Fig. 8.

[0084] Referring to Fig. 8 and Fig. 9. The second electrode 170 can be electrically connected to the contact electrode 163 via a contact hole TH1 formed in the second optical layer 142. The second optical layer 142 can have the contact hole TH1, which exposes the contact electrode 163. The second electrode 170 can be inserted into the contact hole TH1 of the second optical layer 142 and can be in contact with an upper surface of the contact electrode 163. The contact hole TH1 can be formed in an outer region of the pixel.

[0085] In the manufacturing process of the display panel, the thin layers of a plurality of display panels are formed simultaneously on a mother substrate, and then the display areas can be separated into individual display panel units using a scribing process.

[0086] Fig. Figure 10 is a cross-sectional view of a display panel, which schematically represents an example of multilayer layers with wiring structures that may be applied in an embodiment of the present disclosure.

[0087] Referring to Fig. Ten insulating layers (INS1 to INS5) can be stacked on the substrate 110. The wiring of the display panel contained in the parent substrate 1100 can have multiple wiring structures arranged in different layers.

[0088] At least one control driver 20 can be arranged on the substrate 110. The control driver 20 can be at least partially embedded in the first insulating layer INS1. A first wiring structure M1 can be arranged on the first insulating layer INS1. The first insulating layer INS1 can have a single layer or multiple insulating layers. The second insulating layer INS2 has contact holes that expose the output terminals of the control driver 20 and / or the first wiring structure M1. A second wiring structure M2 can be arranged on the second insulating layer INS2. A section of the second wiring structure M2 can be in contact with the output terminals of the control driver 20 and / or the first wiring structure M1 via contact holes that extend through the second insulating layer INS2.The third insulating layer INS3 may have contact holes that expose a section of the second wiring structure M2. A third wiring structure M3 may be arranged on the third insulating layer INS3. A section of the third wiring structure M3 may be in contact with the second structure M2 via the contact holes that pass through the third insulating layer INS3.

[0089] The fourth insulating layer INS4 may have contact holes that expose a section of the third wiring structure M3. A fourth wiring structure M4 may be arranged on the fourth insulating layer INS4. A section of the fourth wiring structure M4 may be in contact with the third wiring structure M3 via contact holes that pass through the fourth insulating layer INS4. The fifth insulating layer INS5 may have contact holes that expose a section of the fourth wiring structure M4. A fifth wiring structure M5 may be arranged on the fifth insulating layer INS5. A section of the fifth wiring structure M5 may be in contact with the fourth wiring structure M4 via contact holes that pass through the fifth insulating layer INS5.The fifth wiring structure M5 can have a metal structure electrically connected to the first electrode of the light-emitting element and a metal structure connected to the second electrode of the light-emitting element.

[0090] The wiring structure of the display panel, which is contained in the mother substrate 1100, is not shown. Fig. 10. For example, the third wiring structure M3 can be connected to the first wiring structure M1 via the contact holes that pass through the two insulating layers INS2 and INS3 stacked beneath the third wiring structure M3. The first electrode and the second electrode of the light-emitting element can be electrically connected to a predefined metal structure from the first wiring structure to the fourth wiring structure via contact holes that pass through the insulating layers.

[0091] In the manufacturing process of the display panel, thin film layers of a plurality of display panels are formed simultaneously on a mother substrate, and then the display areas can be separated into individual display panel units in a scribing process.

[0092] Fig. Figure 11A is a top view showing an example of a display panel mounted on a mother substrate.

[0093] Referring to Fig. In 11A, a mother substrate 1100 has a plurality of display panels 100. After the pixel control circuit, the thin-film layers and the light-emitting elements are arranged on the mother substrate 1100 and the inspection process is completed, each of the display panels 100 is separated from the mother substrate 1100 in the scribing process along a scribing line 190.

[0094] A conductive ring 300 is arranged in the non-display area of ​​the mother substrate 1100, so that electrostatic discharges (ESD) generated during the manufacturing process of the display panel contained in the mother substrate 1100 do not affect the display panel contained in the mother substrate 1100. The conductive ring 300 is electrically connected to each of the display panels 100 such that it is at the same potential as the display panels 100. The conductive ring 300 has a ring-shaped wiring structure that surrounds each of the display panels 100. A scribed line 190 can be arranged between the display area of ​​the display panel 100 contained in the mother substrate 1100 and the conductive ring 300.

[0095] The display panel embedded in the mother substrate 1100 has a plurality of pads 200 that are arranged outside the display area, where pixels are located, and are exposed to the outside. The pads 200 are electrically connected to the wiring structures in the display area. A host system can transmit a signal required to drive the pixels through the pads 200 to the pixel driver circuit. A flexible circuit film, such as a flexible printed circuit (FPC), can be connected to the pads 200 by means of an anisotropic conductive film (ACF). A mainboard of the host system can be connected to one end of the flexible circuit film, and the pads 200 of the display panel embedded in the mother substrate 1100 can be connected to the other end.

[0096] The pads 200 can be connected to a shorting strip 210, which is arranged in a non-indication area on the mother substrate 1100. The shorting strip 210 can be connected to the conductive ring 300 by a connecting section 220. The conductive ring 300, the connecting section 220, the shorting strip 210, and the pads 200 can be made of at least one of the components described in Fig. The wiring structures shown in Figure 10 are formed. The connection structure of the conductive ring 300, the connecting section 220, the shorting strip 210 and the pads 200 allows the wiring of the display panel, which is contained in the mother substrate 1100, to be at the same potential as the conductive ring 310.

[0097] In the manufacturing process of the display panel, which is contained in the mother substrate 1100, a large number of electrical charges can be generated in a thin-film deposition process, for example, in a process for depositing a metal layer structured to a solder structure 316. The solder structure 316 can be essentially the same as that in Fig. 6. Solder structure 162 shown. Since the conductive ring 300 is connected to the pads 200 and the shorting strip 210 on the mother substrate 1100, a large number of electrical charges can be attracted to one or more of the display panels on the mother substrate 1100 if ESD is generated during the process of forming the solder structure 316 on the mother substrate 1100. Since the wiring of the display panel contained in the mother substrate 1100 has the same potential as the conductive ring 310, a large number of electrical charges can flow through the pads 200 or the solder structure 316 into the display panel contained in the mother substrate 1100, leading to damage of the display panel due to ESD.

[0098] Fig. Figure 11B is a top view showing two display panels arranged on a mother substrate. Fig. Figure 12 is a cross-sectional view showing a partial longitudinal cross-sectional structure of the display panel along a line VV' in Fig. 11A. Fig. Figure 12 is a diagram assuming that an insulating layer stack structure of the parent substrate 1100 comprises a first insulating layer INS1, a second insulating layer INS2, and a fifth insulating layer INS5, which are in Fig. Figure 10 shows that, even when an insulating layer is added, the planar wiring connection structure between a Z1 area having a conductive ring 300, a Z2 area having a dummy pixel driver circuit 20a, a Z3 area having a pad 200, and a Z4 area having a pixel driver circuit 20 is essentially the same.

[0099] Referring to Fig. 11B and Fig. 12. The mother substrate 1100 can have a plurality of display panels according to an embodiment of the present disclosure. After the pixel control circuit, the thin-film layers and the light-emitting elements are arranged on the mother substrate 1100 and the inspection process is completed, each of the display panels 100 is separated from the mother substrate 1100 in a scribing process along a scribing line 190.

[0100] On the mother substrate 1100, the conductive ring 300 is arranged in a non-display area outside the display area AA of the display panel 100. The conductive ring 300 has a ring-shaped wiring structure that surrounds each of the display panels 100. The scribe line 190 can be arranged between the display area AA of the display panel 100, which is contained in the mother substrate 1100, and the conductive ring 300. The adjacent conductive rings 300 are not connected to each other. The adjacent conductive rings 300 are not electrically connected because they are separated from each other without being connected by a conductor.If a connection between the adjacent conductive rings 300 in the manufacturing process of the display panels 100 contained in the mother substrate 1100 is interrupted, a large number of electrical charges generated in the process of depositing a metal layer, which is to be structured as a solder structure 316, may be prevented from flowing to the adjacent display panels 100 on the mother substrate 1100.

[0101] The pads 200 can be connected to a shorting strip 210 located in a non-display area on the mother substrate 1100. Since a structure and wiring for directly connecting the shorting strip 210 and the conductive ring 300 are not required, a current path through which charges could move through the pad 200 into the display panel can be blocked, thus preventing ESD-induced damage from propagating to other display panels 100.

[0102] On the mother substrate 1100, one or more dummy pixel driver circuits 20a can be arranged in a non-display area outside the display area AA of the display panel 100. The dummy pixel driver circuit 20a can be arranged between the conductive ring 300 and the display panel 100 on the mother substrate 1100, but is not limited to this location. The dummy pixel driver circuit 20a can also be arranged in a non-display area outside the conductive ring 300.

[0103] One or more dummy pixel control circuits 20a can be integrated into a dummy driver DDR, which is in Fig. Figure 13 shows that the dummy driver DDR can be essentially identical to the control driver PDR, which is located in the display area AA of the display panel 100 on the mother substrate 1100, and can be located in the same layer together with the control driver PDR on the mother substrate 1100. The dummy driver DDR can be embedded on the mother substrate 1100 together with the control driver PDR in the same operation.

[0104] In one embodiment of the present disclosure according to Fig. 11 B and Fig. 12. The conductive ring 300 can be arranged in a non-display area of ​​the mother substrate 1100 of the display panel contained in the mother substrate 1100. The conductive ring 300 can have an annular wiring structure surrounding each of the display panels 100. The conductive ring 300 can have a first wiring structure M1 arranged on the first insulating layer INS1, and a second wiring structure M2 directly connected to the first wiring structure M1 via a plurality of contact holes formed in the second insulating layer INS2.

[0105] At least one dummy driver DDR, which has the same structure as the control driver PDR, can be arranged between the conductive ring 300 and the display panel 100, which is contained in the mother substrate 1100. The dummy driver DDR can be at least partially embedded in the first insulating layer INS1 in Fig. The first wiring structure M1 may be embedded in the first insulating layer INS1. The first insulating layer INS1 may have multiple insulating layers. The second insulating layer INS2 has contact holes that expose the output terminals of the dummy driver DDR and / or the first wiring structure M1. In the display area AA of the display panel 100, the second wiring structure M2 may be arranged on the second insulating layer INS2. A section of the second wiring structure M2 may be in contact with the first wiring structure M1 and / or the output terminal of the control driver 20 via contact holes that pass through the second insulating layer INS2. The fifth insulating layer INS5 may be arranged on the second insulating layer INS2 and the second wiring structure M2.The fifth insulating layer INS5 may have contact holes that expose a section of the second wiring structure M2. A dam structure 130 may be formed on the fifth insulating layer INS5. A section of the fifth wiring structure M5 may be in contact with the second wiring structure M2 via contact holes that pass through the fifth insulating layer INS5.

[0106] After the fifth wiring structure M5 is formed, a photoresist can be layered onto the entire surface of the mother substrate 1100. The layered photoresist is developed to form an opening PO in an area where a solder structure 316 is to be formed.

[0107] A top metal layer is deposited over the entire surface of the mother substrate 1100 on which the photoresist aperture PO is formed. The top metal layer comprises a first metal layer 314, which covers an upper section of the photoresist PR, and the solder structure 316, which is located in the display area AA and the non-display area NA of the display panel 100.

[0108] In the display area AA and the non-display area NA, the photoresist aperture PO can have an inverted conical shape, i.e., an upper surface can be wider than a lower surface, but is not limited to this.

[0109] When the photoresist PR is removed in a lift-off process, the first metal layer 314 covering the photoresist PR is also removed.

[0110] Referring to Fig. 10 and Fig. The mother substrate 1100 has a Z1 area, a Z2 area, a Z3 area, and a Z4 area. The Z1 area specifies a sub-area of ​​the conductive ring 300. The Z2 area specifies an area in which the dummy pixel driver circuit 20a is located. The Z3 area has a shorting strip 210 and pads 200. The Z4 area specifies an area in which the pixel driver circuit 20 is located within the display area AA of the display panel 100.

[0111] Area Z2 can further include a light-emitting element of a dummy pixel connected to the dummy pixel driver circuit 20a. The dummy pixel driver circuit 20a has essentially the same function and structure as the pixel driver circuit 20 in the display panel 100. The difference is that the dummy pixel driver circuit 20a drives a dummy pixel, whereas the pixel driver circuit 20 drives pixels within the display area of ​​the display panel 100. The light-emitting element of the dummy pixel can be configured to have essentially the same structure as the light-emitting element of the pixel located in the display panel 100.Accordingly, the light-emitting element of the dummy pixel, like the pixel in the display panel 100, has the dam structure and the solder structure 316, which is arranged on the dam structure and is in contact with the light-emitting element, as shown in . Fig. 12 shown. Since Fig. 12 a cross-sectional structure of the mother substrate before the process of transferring the light-emitting element, is the solder structure 316 in Fig. 12 omitted.

[0112] In the thickness direction (Z-axis direction) of the mother substrate 1100, the solder structure 316 and the light-emitting element of the dummy pixel can overlap the dummy pixel control circuit 20a in the Z2 region. In the Z4 region, the solder structure and the light-emitting element of the pixel located in the display area AA of the display panel 100 can overlap with the pixel control circuit 20.

[0113] The conductive ring 300, located in the non-display area of ​​the mother substrate 1100, can have a first wiring structure M1 arranged on the first insulating layer INS1, and a second wiring structure M2 directly connected to the first wiring structure M1 via one or more contact holes formed in the second insulating layer INS2. The conductive ring 300 can further have one or more additional wiring structures electrically connected to the second wiring structure M2.

[0114] The dummy pixel driver circuit 20a can be connected to the second wiring structure M2 via one or more contact holes formed in the second insulating layer INS2, and can be connected to a fifth wiring structure M5 that is in contact with the second wiring structure M2. The fifth wiring structure M5, which is electrically connected to the dummy pixel driver circuit 20a, can extend to an upper section of the area where the conductive ring 300 is positioned such that it overlaps the dummy pixel driver circuit 20a, but is not electrically connected to the conductive ring 300.

[0115] The second wiring structure M2 can have a first connection section M21, which is connected to a first terminal of the dummy driver DDR, and a second connection section M22, which is connected to a second terminal of the dummy driver DDR and the conductive ring 300. The conductive ring 300 can be electrically connected via the second connection section M22 to the electrostatic discharge structure (or electrostatic prevention structure or electrostatic protection circuit) of the dummy pixel drive circuit 20a. The first connection section M21 and the second connection section M22 are not directly connected to each other. The wiring structures arranged in the Z2 area cannot be electrically connected to the wiring structures arranged in the Z3 area.

[0116] The in Fig. 11A and Fig. The pads 200 shown in Figure 11B can be connected to the pixel driver circuit 20 located in the display area by at least one of the remaining wiring structures from the wiring structures connected in the display area AA, excluding the fifth wiring structure M5. In the example of Fig. 12, the pad 200 is connected to the pixel control circuit 20 via the second wiring structure M2, but is not limited to this.

[0117] In one embodiment of the present disclosure according to Fig. 11A to Fig. 12, when in the process of manufacturing the display panel contained in the mother substrate 1100 a number of electrical charges are generated during the process of applying a solder structure 316 and the first metal layer 314, the conductive ring 300 and the fifth wiring structure M5 are electrically separated from each other so that electrical charges are not concentrated on the conductive ring 300.

[0118] During the process of applying the solder structure 316 and the first metal layer 314, a large number of electrical charges can flow into the dummy pixel driver circuit 20a through wiring structures connected to the dummy pixel driver circuit 20a. The dummy driver DDR has the same ESD prevention structure as the driver PDR, which is located in the display area AA of the display panel 100. The ESD prevention structure may include an ESD protection circuit connected to the output terminals of the pixel driver circuits 20 and 20a. When ESD is generated, the ESD protection circuit protects the pixel drive circuits 20 and 20a from ESD by discharging the ESD to the wiring connected to the conductive ring 300 or ground GND using a switched-on switching element, such as a transistor or diode.When ESD is generated during the application of the solder structure 316 and the first metal layer 314, it is discharged to ground by the ESD protection circuit built into the dummy driver DDR, thus protecting the dummy pixel drive circuit 20a and the display panel 100 mounted on the mother substrate 1100 from ESD. Furthermore, when ESD is generated, after the amount of electrical charge is first reduced in a process where the electrical charge flows through the solder structure 316 and the wiring structures M2 and M5 into the dummy driver DDR, the amount of electrical charge in the dummy driver DDR is further reduced.

[0119] Fig. Figure 13 is a view that schematically represents a structure of a control driver according to an embodiment of the present application.

[0120] Referring to Fig. 13 The display area AA of the display panel 100 has one or more control drivers PDR, into which a plurality of pixel control circuits 20 are integrated. The non-display area of ​​the mother substrate 110 has one or more dummy drivers DDR, into which a plurality of pixel control circuits 20a are integrated.

[0121] The control driver PDR and the dummy driver DDR have essentially the same structure. Each of the control driver PDR and the dummy driver DDR features an ESD protection circuit EDC, which is connected to the input / output terminals of the pixel control circuits 20 and 20a. When an ESD occurs, as charges flow to the input / output terminals of the control driver PDR and the dummy driver DDR, they are discharged by the EDC ESD protection circuit to a ground wire GR, thus protecting the pixel control circuits 20 and 20a from ESD.

[0122] A first terminal 201 of the dummy driver DDR can be connected to a first connection section M21, and a second terminal 202 of the dummy driver DDR can be connected to a second connection section M22.

[0123] The EDC (Electronic Discharge Protection) circuit can be implemented in various structures. For example, the EDC can be implemented as a circuit, as in... Fig. 14 is shown, but is not limited to this.

[0124] Fig. 14 and Fig. 15 are circuit diagrams that represent an ESD protection circuit.

[0125] Referring to Fig. Figure 14 of the ESD protection circuit includes a transistor T1 connected between a first node 203 and a second node 204, a first capacitor C1 connected between the first node 203 and a third node 205, and a second capacitor C2 connected between the second node 204 and a third node 205. The input / output terminal of the dummy driver DDR can be connected to the first node 203, and the second node 204 can be connected to a ground wire GR.

[0126] Transistor T1 has a drain electrode connected to the first node 203, a source electrode connected to the second node 204, and a gate electrode connected to the third node 205.

[0127] When ESD is generated and electrical charges flow into the dummy driver DDR through its input / output terminal, the voltage of the first node 203 increases, and the gate voltage of transistor T1 is increased by capacitor C1, thus turning transistor T1 on. Therefore, a large number of electrical charges generated by ESD can be dissipated through the ground wire GR.

[0128] Referring to Fig.Figure 15 of the ESD protection circuit comprises a first transistor T01 connected between a first node 207 and a second node 208, a second transistor T02 connected between the second node 208 and a third node 209, and a third transistor T03 connected between the first node 207 and the third node 209. The input / output terminal of the dummy driver DDR can be connected to the first node 207, and the third node 209 can be connected to a ground wire GR.

[0129] The first transistor, T01, has a drain electrode and a gate electrode connected to the first node, 207, and a source electrode connected to the second node, 208. The second transistor, T02, has a drain electrode connected to the second node, 208, and a source electrode and a gate electrode connected to the third node, 209. The third transistor, T03, has a drain electrode connected to the first node, 207, a gate electrode connected to the second node, 208, and a source electrode connected to the third node, 209.

[0130] When ESD is generated and electrical charges flow into the dummy driver DDR through its input / output terminal, the voltage of the first node 207 is increased, thus turning on transistors T01, T02, and T03. Therefore, a large number of electrical charges generated by ESD can be dissipated through the ground wire GR.

[0131] In accordance with one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smartwatches, watch phones, portable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, sliding devices, variable devices, electronic organizers, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation devices, vehicle navigation devices, vehicle display devices, vehicle devices, theater devices, theater display devices, television sets, screen background devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders and household appliances, etc.Additionally, the display device according to one or more embodiments of the present disclosure can be applied to organic light-emitting devices or inorganic light-emitting devices.

[0132] In accordance with one or more embodiments of the present disclosure, a parent substrate and a display panel can be described as follows.

[0133] In accordance with one or more embodiments of the present disclosure, a mother substrate for the display panel may have a plurality of display areas, each comprising a plurality of light-emitting areas in which a light-emitting element is arranged, a plurality of wiring connections, and a plurality of pads connected to the plurality of wiring connections; a pixel driver circuit arranged within the display area and comprising an electrostatic suppression structure; a conductive ring arranged in a non-display area outside the display area and surrounding each of the plurality of display areas; and one or more dummy pixel driver circuits arranged in the non-display area outside the display area. The dummy pixel driver circuit may have the same electrostatic suppression structure as the pixel driver circuit.

[0134] The dummy pixel driver circuit can be located in a non-display area between the conductive ring and the display area.

[0135] Conductive rings surrounding each of the majority of display areas can be separated from one another.

[0136] The mother substrate may further comprise a first insulating layer covering at least a section of the pixel control circuit and the dummy pixel control circuit; a first wiring structure arranged on the first insulating layer; a second insulating layer formed on the first wiring structure; and a second wiring structure present on the second insulating layer and electrically connected to the dummy pixel control circuit and the conductive ring via a plurality of contact holes arranged in the second insulating layer.

[0137] The second wiring structure can have a first connection section connected to the dummy pixel driver circuit and a second connection section connected to the conductive ring. The first and second connection sections of the second wiring structure can be separate from each other without a direct connection.

[0138] The mother substrate may further comprise a third insulating layer formed on the second wiring structure; and a third wiring structure arranged on the third insulating layer and electrically connected to the first connection section via at least one contact hole formed in the third insulating layer.

[0139] The mother substrate can further comprise a dam structure arranged on the third insulating layer. The third wiring structure can be formed such that the dam structure is covered. The mother substrate can further comprise a solder structure formed on the dam structure.

[0140] At least one section of the third wiring structure can overlap the conductive ring.

[0141] The mother substrate may further include a dummy pixel in which a dummy light-emitting element is arranged, which is located in the non-display area and connected to the dummy pixel drive circuit.

[0142] The dummy pixel can have a dummy pixel dam structure and a solder structure that is arranged on the dummy pixel dam structure and is in contact with the dummy light-emitting element.

[0143] At least one section of the dummy pixel can overlap the dummy pixel control circuit in one thickness direction of the parent substrate.

[0144] The mother substrate may further comprise a dummy driver in which one or more of the dummy pixel drive circuits are integrated; a first interconnection section connecting a solder structure of the dummy pixel to a first terminal of the dummy driver; and a second interconnection section connecting the conductive ring to a second terminal of the dummy driver.

[0145] The solder structure of the dummy pixel can overlap the dummy pixel driver circuit in the thickness direction of the mother substrate.

[0146] At least one section of the second connection section can overlap the dummy pixel control circuit in the thickness direction of the mother substrate.

[0147] In accordance with one or more embodiments of the present disclosure, a mother substrate for the display panel may comprise a driver comprising one or more pixel driver circuits arranged in a display area; a conductive ring arranged in a non-display area outside the display area and surrounding the display area; and a dummy driver arranged in a non-display area outside the display area. The driver of the display area and the dummy driver of the non-display area may have identical electrostatic protection circuits. The conductive ring may be electrically connected to the electrostatic protection circuit of the dummy driver via wiring.

[0148] In accordance with one or more embodiments of the present disclosure, a display panel can be separated from the mother substrate for the display panel in the final manufacturing stage and can have the display area and the pixel control circuit without the conductive ring and the dummy pixel control circuit.

[0149] In accordance with one or more embodiments of the present disclosure, a display panel can be separated from the mother substrate for the display panel in the final manufacturing stage and has the display area and the control driver without the conductive ring and the dummy driver.

[0150] The objectives to be achieved by the present disclosure, the means of achieving the objectives and the effects of the present disclosure described above do not define any essential features of the claims, and therefore the scope of the claims is not limited to the disclosure of the present disclosure.

[0151] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. It should therefore be understood that the embodiments described above are illustrative in all aspects and do not limit the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] KR 10 2023 0 096 834

[0001]

Claims

[1] A mother substrate (1100) comprising: a plurality of display areas (AA) comprising a plurality of light-emitting areas in which a light-emitting element (10) is arranged, a plurality of wirings, and a plurality of pads (200) connected to the plurality of wirings; a pixel driving circuit (20) arranged within the display area (AA) and having an electrostatic prevention structure; a conductive ring (300) disposed in a non-display area (NA) outside the display area (AA) and surrounding each of the plurality of display areas (AA); and one or more dummy pixel drive circuits (20a) arranged in the non-display area (NA) outside the display area (AA), wherein the dummy pixel driving circuit (20a) has the same electrostatic prevention structure as the pixel driving circuit (20). [2] The mother substrate (1100) according to claim 1, wherein the dummy pixel driving circuit (20a) is arranged in a non-display region (NA) between the conductive ring (300) and the display region (AA). [3] The mother substrate (1100) according to claim 1, wherein the dummy pixel driving circuit (20a) is arranged in a non-display area (NA) outside the conductive ring (300). [4] The mother substrate (1100) according to any one of claims 1 to 3, wherein conductive rings (300) surrounding each of the plurality of display areas (AA) are separated from each other. [5] The mother substrate (1100) according to any one of claims 2 to 4, further comprising: a first insulating layer (INS1) covering at least a portion of the pixel driving circuit (20) and the dummy pixel driving circuit (20a); a first wiring structure (M1) arranged on the first insulating layer (INS1); a second insulating layer (INS2) formed on the first wiring structure (M1); and a second wiring structure (M2) arranged on the second insulating layer (INS2) and electrically connected to the dummy pixel drive circuit (20a) and the conductive ring (300) through a plurality of contact holes formed in the second insulating layer (INS2), wherein the second wiring structure (M2) comprises: a first connection section (M21) connected to the dummy pixel driving circuit (20a); and a second connecting portion (M22) connected to the conductive ring (300), and the first connecting section (M21) and the second connecting section (M22) of the second wiring structure (M2) are separated from each other without a direct connection. [6] The mother substrate (1100) according to claim 5, further comprising: a third insulating layer (INS3) formed on the second wiring structure (M2); and a third wiring structure (M3) arranged on the third insulating layer (INS3) and electrically connected to the first connecting portion (M21) via at least one contact hole formed in the third insulating layer (INS3). [7] The mother substrate (1100) according to claim 6, further comprising: a dam structure (130) arranged on the third insulating layer (INS3), wherein the third wiring structure (M3) is formed to cover the dam structure (130), and the mother substrate (1100) further comprises a solder structure (162, 316) formed on the dam structure (130). [8] The mother substrate (1100) according to claim 6, wherein at least a portion of the third wiring pattern (M3) overlaps the conductive ring (300). [9] The mother substrate (1100) according to any one of claims 1 to 8, further comprising: a dummy pixel in which a dummy light-emitting element is arranged, which is arranged in the non-display area (NA) and connected to the dummy pixel driving circuit (20a). [10] The mother substrate (1100) according to claim 9, wherein the dummy pixel comprises a dummy pixel dam structure and a solder structure (162, 316) disposed on the dummy pixel dam structure and in contact with the dummy light-emitting element. [11] The mother substrate (1100) according to claim 9 or 10, wherein at least a portion of the dummy pixel overlaps the dummy pixel driving circuit (20a) in a thickness direction of the mother substrate (1100). [12] The mother substrate (1100) according to any one of claims 9 to 11, further comprising: a dummy driver (DDR) in which one or more of the one or more dummy pixel drive circuits (20a) are integrated; a first connection portion (M21) connecting a solder pattern (162, 316) of the dummy pixel to a first terminal of the dummy driver (DDR); and a second connection portion (M22) connecting the conductive ring (300) to a second terminal of the dummy driver (DDR). [13] The mother substrate (1100) according to claim 12, wherein the solder pattern (162, 316) of the dummy pixel overlaps the dummy pixel driving circuit (20a) in the thickness direction of the mother substrate (1100). [14] The mother substrate (1100) according to claim 12 or 13, wherein at least a portion of the second connecting portion (M22) overlaps the dummy pixel driving circuit (20a) in the thickness direction of the mother substrate (1100). [15] A mother substrate (1100) comprising: a drive driver (PDR) comprising one or more pixel drive circuits (20) arranged in a display area (AA); a conductive ring (300) arranged in a non-display area (NA) outside the display area (AA) and surrounding the display area (AA); and a dummy driver (DDR) located in a non-display area (NA) outside the display area (AA), wherein the drive driver (PDR) of the display area (AA) and the dummy driver (DDR) of the non-display area (NA) have an electrostatic protection circuit which are identical to each other, and the conductive ring (300) is electrically connected to the electrostatic protection circuit of the dummy driver (DDR) via a wiring. [16] A display panel (100), wherein the display panel (100) is separated from the mother substrate (1100) for the display panel (100) according to any one of claims 1 to 14 in the final manufacturing stage and comprises the display area (AA) and the pixel driving circuit (20) without the conductive ring (300) and the dummy pixel driving circuit (20a). [17] A display panel (100), wherein the display panel (100) is separated from the mother substrate (1100) for the display panel (100) according to claim 15 in the final manufacturing stage and comprises the display area (AA) and the drive driver (PDR) without the conductive ring (300) and the dummy driver (DDR).

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