Display device

Abstract

A display device (100) is disclosed. An exemplary display device (100) according to an embodiment of the present disclosure has a substrate (110) configured to define a plurality of pixel areas (UPA) arranged such that they are spaced apart from one another. The device (100) has a plurality of light-transmitting areas (TA) arranged between the plurality of pixel areas (UPA). The device (100) has a plurality of pixels (PX) arranged within the plurality of pixel areas (UPA), each of which has a plurality of subpixels (SP).The device (100) has a plurality of repair lines (WRL) arranged between the plurality of subpixels (SP) and made of a translucent conductive material, wherein the plurality of repair lines (WRL) are arranged on the same layer and spaced apart from one another. Therefore, the repair lines (WRL) used to repair the plurality of subpixels (SP) when the plurality of subpixels (SP) have a defect can be formed as a single-layer structure made of a translucent conductive material.

Description

CROSS REFERENCE TO RELATED APPLICATIONSThis application claims priority to Korean Patent Application No. 10-2023-0 099 347 filed on Jul. 31, 2023 in the Korean Intellectual Property Office.BACKGROUNDTECHNICAL FIELDThe present disclosure relates to a transmissive display device, and more particularly relates to a transmissive display device using a light emitting diode (LED).DESCRIPTION OF THE RELATED ARTAs display devices used for a computer monitor, a television, a mobile phone, and the like, there are an organic light emitting display (OLED) configured to emit autonomously and a liquid crystal display (LCD) that requires a separate light source.The field of application of the display devices is various, ranging from the computer monitor and the television to personal mobile devices, and studies are being made on display devices having large display areas and reduced volume and weight.Moreover, recently, a display device including a light emitting diode (LED) has attracted attention as a next generation display device. Since the LED is made of an inorganic material instead of an organic material, the LED is more reliable and has a longer lifetime than a liquid crystal display device or an organic light emitting display device. Moreover, the LED can be turned on or off quickly, has excellent luminous efficiency, high shock resistance and high stability, and can display images with high brightness.BRIEF OVERVIEWVarious embodiments of the present disclosure provide a light transmissive display device having a high transmission rate.Various embodiments of the present disclosure provide a display device in which a non-light transmissive line and a plurality of pixels are formed so as to overlap each other, thereby enlarging or maximizing an area of a light transmissive region.Various embodiments of the present disclosure provide a display device in which a repair line for repairing a plurality of subpixels is provided, thereby improving quality.Various embodiments of the present disclosure provide a display device in which a repair line is configured as a single-layer structure made of a light-transmissive conductive material, thereby simplifying the structure of the repair line.Various embodiments of the present disclosure provide a display device in which a repair line is made of only a light transmissive conductive material, thereby reducing or minimizing a decrease in transmission rate of a light transmissive region.Various embodiments of the present disclosure provide a display device in which a plurality of sub-pixels are arranged horizontally symmetrically such that a plurality of repair lines are arranged so as not to overlap each other.Various embodiments of the present disclosure provide a display device in which a plurality of repair lines are arranged so as not to overlap each other in plan view such that a plurality of repair lines are formed as a single-layer structure on the same layer.Various embodiments of the present disclosure provide a display device in which a plurality of repair lines and a first connection electrode are arranged together in a welding region on which laser beams are emitted during a repair process of a subpixel, thereby improving a yield of a repair process.Various embodiments of the present disclosure provide a display device in which a repair line is disposed in the same pixel region or in two adjacent pixel regions in consideration of a distance between a plurality of subpixels, thereby reducing or minimizing a length of the repair line.Various embodiments of the present disclosure provide a display device in which a repair line is disposed to have a shortest length for connecting a pair of adjacent subpixels, such that the display device can be operated with low power consumption.The technical advantages of the present disclosure are not limited to the above-mentioned advantages, and other advantages not mentioned above can be clearly understood by those skilled in the art from the following descriptions.Various embodiments of the present disclosure provide a display device according to claim 1 and a display device according to claim 18. Further embodiments are described in the dependent claims. A display device according to an embodiment of the present disclosure includes: a substrate configured to define a plurality of pixel regions arranged to be spaced apart from each other and a plurality of light transmissive regions arranged between the plurality of pixel regions; a plurality of pixels arranged in the plurality of pixel regions and each including a plurality of sub-pixels; and a plurality of repair lines arranged between the plurality of sub-pixels and made of a light transmissive conductive material, wherein the plurality of repair lines are arranged on the same layer and arranged spaced apart from each other. Therefore, the repair lines used for repairing the plurality of sub-pixels when the plurality of sub-pixels are defective can be formed as a single-layer structure made of a light transmissive conductive material, thereby simplifying the structure of the repair line and reducing or minimizing a decrease in transmission rate of the light transmissive region.Further detailed aspects of the exemplary embodiments are contained in the detailed description and the drawings.According to the present disclosure, it is possible to implement the light transmissive display device having the improved transmission rate.According to the present disclosure, among the components of the display device, the non-light transmissive components may be disposed so as to overlap each other, thereby ensuring the maximum area of the light transmissive region of the display device.According to the present disclosure, the non-light transmissive line and the plurality of pixels may be formed so as to overlap each other, thereby enlarging an area of the light transmissive region.According to the present disclosure, the repair line may be formed to repair the plurality of subpixels, thereby improving the yield of the display device.According to the present disclosure, the repair line may be configured as the single-layer structure made of a light-transmissive conductive material, thereby simplifying the structure of the repair line.According to the present disclosure, the repair line may be made of only a light transmissive conductive material, thereby reducing or minimizing the decrease in transmission rate of the light transmissive region.In accordance with the present disclosure, the plurality of subpixels are arranged to be horizontally symmetric such that the plurality of repair lines do not overlap each other.According to the present disclosure, the plurality of repair lines are arranged so as not to overlap each other, such that the plurality of repair lines may be formed as a single layer on the same layer.According to the present disclosure, the plurality of repair lines and the first connection electrode may be arranged together in the welding region on which laser beams are emitted during the process of repairing the subpixel, thereby improving the yield of the repair process.According to the present disclosure, the repair line may be disposed in the same pixel region or in two adjacent pixel regions in consideration of the distance between the plurality of sub-pixels, thereby reducing the length of the repair line.According to the present disclosure, the repair line may be arranged to have a shortest length for connecting the pair of adjacent sub-pixels, thereby reducing a resistance of the repair line and operating the display device with low power consumption.The effects according to the present disclosure are not limited to the contents exemplified above, and other various effects are included in the present disclosure.BRIEF DESCRIPTION OF THE VARIOUS VIEWS OF THE DRAWINGSThe above and other aspects, features and other advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a schematic configuration view of a display device according to an embodiment of the present disclosure; FIG. 2A is a partial cross-sectional view of the display device according to the embodiment of the present disclosure; FIG. 2B is a perspective view of a tiled display device according to the embodiment of the present disclosure; FIG. 3 is a schematic enlarged plan view of a display region of the display device according to the embodiment of the present disclosure; FIG. 4 is an enlarged plan view of a region A in FIG. 3 ; FIGS. 5A and 5B are cross-sectional views of subpixels of the display device according to the embodiment of the present disclosure; FIG. 6 is a cross-sectional view of a pair of subpixels of the display device according to the embodiment of the present disclosure; FIG. 7 is a schematic enlarged plan view of a display region of a display device according to another embodiment of the present disclosure; FIG. 8 is an enlarged plan view of a region B in FIG. 7 ; FIG. 9 is a cross-sectional view of a pair of subpixels of the display device according to another embodiment of the present disclosure; FIG. 10 is an enlarged plan view of a display device according to still another embodiment of the present disclosure; FIGS. 11A and 11B are cross-sectional views of subpixels of the display device according to still another embodiment of the present disclosure; FIG. 12 is a schematic enlarged plan view of the display device according to still another embodiment of the present disclosure; FIG. 13 is an enlarged plan view of a region C in FIG. 12 ; and FIG. 14 is an enlarged plan view of a region D in FIG. 12.DETAILED DESCRIPTIONAdvantages and characteristics of the present disclosure and a method for achieving the advantages and characteristics will be apparent by referring to the exemplary embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosures of the present disclosure and the scope of the present disclosure.The shapes, sizes, dimensions (for example, length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, numbers, numbers of elements, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.A dimension including a size and thickness of each component illustrated in the drawings is illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated component, but it should be noted that the relative dimensions including the relative size, location, and thickness of the components illustrated in various drawings filed herewith are part of the present disclosure.Like reference numerals generally designate like elements throughout the disclosure. Moreover, in the following description of the present disclosure, detailed explanation of known related technologies may be omitted so as not to unnecessarily obscure the subject matter of the present disclosure. The terms used herein, such as "comprising," "having," and "consisting of," are generally intended to allow other components to be added, unless the terms are used with the term "only.". Any reference to the singular may include the plural, unless expressly stated otherwise.Components are designed to have a common range of errors, although not expressly stated.When the spatial relationship between two parts is described using terms such as "on", "over", "under", and "next", one or more parts may be positioned between the two parts unless the terms are used with the term "immediately" or "directly".When an element or layer is disposed "on" another element or layer, another layer or element may be directly on or interposed between the other element.Although the terms "first / r / s", "second / r / s", and the like are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.When it is mentioned that a first element may be "connected or coupled to", "touched or overlapped", etc., a second element is "connected or coupled directly to" or "touched or overlapped", etc., it should be interpreted that not only the first element may be "directly connected or coupled to" or "directly overlapped", but also a third element may be interposed between the first element and the second element, or the first element and the second element may be connected or coupled to", touched or overlapped", etc. Here, the second element may be included in at least one of two or more elements that are connected or coupled to", touched or overlapped", etc.The features of various embodiments of the present disclosure may be partially or fully attached to each other or combined with each other, and may be connected and operated in a technically different manner, and the embodiments may be executed independently of each other or in association with each other.Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.FIG. 1 is a schematic configuration view of a display device according to an embodiment of the present disclosure. For convenience of description, FIG. 1 shows, among various constituent elements of a display device 100, only a display panel PN, a gate driving part GD, a data driving part DD, and a timing controller TC.Referring to FIG. 1, the display device 100 includes the display panel PN including a plurality of subpixels SP, the gate driving part GD configured to supply various kinds of signals to the display panel PN, and the timing controller TC configured to control the gate driving part GD and the data driving part DD.The gate driving part GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided from the timing controller TC. FIG. 1 illustrates that the single gate driving part GD is disposed to be spaced apart from one side of the display panel PN. However, the number and arrangement of the gate driving part GD are not limited thereto.The data driving part DD supplies data voltages to a plurality of data lines DL in response to a plurality of data control signals and image data provided from the timing controller TC. The data driving part DD may convert image data into data voltages using a reference gamma voltage and supply the converted data voltages to the plurality of data lines DL.The timing controller TC aligns image data input from the outside and supplies the image data to the data driving part DD. The timing controller TC may generate the gate control signals and the data control signals using synchronization signals such as pixel clock signals, data enable signals, and horizontal / vertical synchronization signals input from the outside. Further, the timing controller TC may control the gate driving part GD and the data driving part DD by supplying the generated gate control signals and data control signals to the gate driving part GD and the data driving part DD.The display panel PN is configured to display images for a user, and includes the plurality of subpixels SP. In the display panel PN, the plurality of scan lines SL and the plurality of data lines DL may overlap each other, and the plurality of sub-pixels SP may be formed at intersections between the scan line SL and the data line DL.A display area AA and a non-display area NA may be defined on the display panel PN.The display area AA is an area of the display device 100 in which images are displayed. The display area AA may include a plurality of subpixels SP that configure a plurality of pixels PX and a pixel circuit configured to operate the plurality of subpixels SP. The plurality of subpixels SP are minimum units that configure the display area AA. The n sub-pixels SP may establish a single pixel PX. Thin film transistors and the like for driving a plurality of light emitting elements 120 may be respectively disposed in the plurality of sub-pixels SP. The plurality of light emitting elements 120 may be defined differently depending on the type of the display panel PN. For example, in the case that the display panel PN is an inorganic light emitting display panel PN, the light emitting element 120 may be a light emitting diode (LED) or a micro light emitting diode (micro LED).A plurality of signal lines for transmitting various kinds of signals to the plurality of sub-pixels SP are arranged in the display area AA. For example, the plurality of signal lines may include the plurality of data lines DL for supplying data voltages to the plurality of subpixels SP and the plurality of scan lines SL for supplying scan signals to the plurality of subpixels SP. The plurality of scan lines SL may extend in one direction in the display area AA and may be connected to the plurality of subpixels SP. The plurality of data lines DL may extend in a direction different from a direction in the display area AA and may be connected to the plurality of subpixels SP. In addition, a low potential power line VSS, a high potential power line VDD, and the like may be disposed in the display area AA. However, the present disclosure is not limited thereto.The non-display area NA may be defined as an area in which an image is not displayed, for example, an area extending from the display area AA. The non-display area NA may include connection lines and pad electrodes for transmitting signals to the subpixels SP in the display area AA. Alternatively, the non-display area NA may include driving ICs such as gate driving ICs and data driving ICs.Here, the non-display area NA may be positioned on a rear side of the display panel PN, for example, on a surface on which the subpixel SP is not present. Alternatively, the non-display area NA may be excluded. However, the present disclosure is not limited to the configuration illustrated in the drawings.Here, the driving parts such as the gate driving part GD, the data driving part DD, and the timing controller TC may be connected to the display panel PN in various ways. For example, the gate driving part GD may be mounted in the non-display area NA by a gate-in-panel (GIP) method or mounted in the display area AA between the plurality of subpixels SP by a gate-in-active area (GIA) method.For example, the data driving part DD and the timing controller TC may be formed on a separate flexible film and a circuit board, and electrically connect the display panel PN, the data driving part DD, and the timing controller TC to a pad electrode formed in the non-display area NA of the display panel PN by a method of bonding the flexible film and the circuit board.As another example, in the case that the gate driving part GD is mounted in the display area AA by the GIA method and a side line SRL connecting a signal line on a front side of the display panel PN to the pad electrode on the rear side of the display panel PN is formed such that the flexible film and the circuit board are bonded to the rear side of the display panel PN, it is possible to reduce or minimize the non-display area NA on the front side of the display panel PN. Therefore, in the case that the gate driving part GD, the data driving part DD, and the timing controller TC are connected to the display panel PN by the above-mentioned method, a null bezel in which the bezel is not substantially present can be implemented. A more detailed description will be described with reference to FIGS. 2A and 2B.FIG. 2A is a partial cross-sectional view of the display device according to the embodiment of the present disclosure. FIG. 2B is a perspective view of a tiled display device according to the embodiment of the present disclosure.A plurality of pad electrodes for transmitting various kinds of signals to the plurality of sub-pixels SP are disposed in the non-display area NA of the display panel PN. For example, on the front side of the display panel PN in the non-display area NA, a first contact electrode PAD 1 configured to transmit signals to the plurality of subpixels SP is disposed. A second contact electrode PAD 2 electrically connected to driving components such as the flexible film and the circuit board is disposed in the non-display area NA on the back side of the display panel PN.In this case, although not illustrated in the drawings, various types of signal lines, for example, the scan line SL, the data line DL, or the like, connected to the plurality of subpixels SP may extend from the display area AA to the non-display area NA and may be electrically connected to the first pad electrode PAD 1.Further, the side line SRL is disposed along a side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD 1 on the front side of the display panel PN and the second pad electrode PAD 2 on the rear side of the display panel PN. Therefore, the signals received from the driving components on the rear side of the display panel PN may be transmitted to the plurality of subpixels SP through the second pad electrode PAD 2, the side line SRL, and the first pad electrode PAD 1. Therefore, the driving component is disposed on the rear side of the display panel PN, and a signal transmission path is defined between the front side and the rear side of the display panel PN, which can reduce or minimize an area of the non-display area NA on the front side of the display panel PN.Further, referring to FIG. 2B, by connecting a plurality of display devices 100, a tiled display device TD having a large screen may be implemented. In this case, as illustrated in FIG. 2A, in the case where the tiled display device TD is implemented using the display device 100 having the reduced or minimized surround, a seam area in which an image is not displayed between the display devices 100 may be reduced or minimized, thereby improving display quality.For example, the plurality of subpixels SP may form a single pixel PX. A pitch D 1 between an outermost peripheral pixel PX of one display device 100 and an outermost peripheral pixel PX of another display device 100 adjacent to the one display device 100 may be implemented to be equal to the pitch D 1 between the pixels PX in the one display device 100. Therefore, the seam area may be reduced or minimized when a constant pitch of the pixels PX is implemented between the display device 100 and the display device 100.However, as illustrated in FIGS. 2A and 2B, the display device 100 according to the embodiment of the present disclosure may be a general display device in which the bezel is provided. However, the present disclosure is not limited thereto.Hereinafter, the display panel PN of the display device 100 according to the embodiment of the present disclosure will be described in more detail with reference to FIGS. 3 to 6.FIG. 3 is a schematic enlarged plan view of the display region of the display device according to the embodiment of the present disclosure. FIG. 4 is an enlarged plan view of an area A in FIG. 3, FIGS. 5A and 5B are cross-sectional views of the subpixels of the display device according to the embodiment of the present disclosure. FIG. 6 is a cross-sectional view of the pair of subpixels of the display device according to the embodiment of the present disclosure. Specifically, FIG. 4 is an enlarged plan view illustrating a pixel PX, and FIGS. 5A and 5B are cross-sectional views for explaining a specific structure of the subpixel SP including a first contact hole CH 1 and a repair line WRL for repair. FIG. 6 is a cross-sectional view of a pair of first sub-pixels SP 1 that has been completely repaired. For convenience of description, in FIG. 3, only the plurality of light emitting elements 120, the plurality of repair lines WRL, a plurality of first connection electrodes CE 1, and a second connection electrode CE 2 are illustrated. In FIG. 4, the first connection electrode CE 1 and the second connection electrode CE 2 are represented by thick solid lines, and hatching is omitted. Further, FIGS. 5B and 6 exemplify a structure of the pair of first subpixels SP 1. A pair of second subpixels SP 2 and a pair of third subpixels SP 3 have substantially the same structure as the pair of first subpixels SP 1.Referring to FIG. 3, the display area AA includes a plurality of pixel areas UPA and a plurality of light transmissive areas TA.The plurality of pixel regions UPA are formed in the display region AA. The plurality of pixel regions UPA are regions in which the pixels PX are arranged and images are displayed. The plurality of pixel regions UPA may be arranged to be spaced apart from each other with the plurality of light transmissive regions TA interposed therebetween. For example, the plurality of pixel regions UPA may be arranged in a plurality of rows and a plurality of columns.The plurality of subpixels SP constituting the pixel PX are arranged in each of the plurality of pixel areas UPA. The plurality of subpixels SP may each include the light emitting element 120 and the pixel circuit and independently emit light. For example, the plurality of subpixels SP may include the first subpixels SP 1, the second subpixels SP 2, and the third subpixels SP 3 emitting light beams having different colors. For example, the first subpixel SP 1 may be a red subpixel, the second subpixel SP 2 may be a green subpixel, and the third subpixel SP 3 may be a blue subpixel. However, the present disclosure is not limited thereto.In the following, it is assumed in the description that a pixel PX has two first subpixels SP 1, two second subpixels SP 2 and two third subpixels SP 3, for example two red subpixels, two green subpixels and two blue subpixels. However, the configuration of the pixel PX is not limited thereto.The plurality of subpixels SP configuring one pixel PX are arranged in a line in a column direction. The plurality of sub-pixels SP may be arranged in the column direction and overlap a line extending in the column direction. For example, the plurality of subpixels SP may overlap the data line DL, a reference line RL, the high potential power line VDD, the low potential power line VSS, and the like extending in the column direction. The pixel region UPA may be formed in a region where a plurality of non-light transmissive lines are arranged such that an area of the light transmissive region TA may be secured in the entire display region AA. The pixel region UPA in which the plurality of subpixels SP are arranged may be a region having a low transmission rate and being substantially opaque due to the configurations of the pixel circuits, the light emitting elements 120, and the like arranged in the plurality of subpixels SP. Therefore, the plurality of subpixels SP may be disposed in the pixel area UPA so as to overlap the non-light transmissive lines extending in the column direction, for example, the data line DL, the reference line RL, the low-potential power line VSS, and the high-potential power line VDD. Therefore, the plurality of subpixels SP are arranged in the pixel area UPA so as to overlap the plurality of lines, such that an area of the non-light transmissive area in the entire display area AA can be reduced and a maximum area of the light transmissive area TA can be secured.Referring to FIGS. 3 and 4 together, the pair of first subpixels SP 1, the pair of second subpixels SP 2, and the pair of third subpixels SP 3 included in one pixel PX may be arranged to be horizontally symmetric with respect to the scan line SL. For example, one first subpixel SP 1 of the pair of first subpixels SP 1 may be disposed on one side of the scan line SL, and the other first subpixel SP 1 may be disposed on the other side of the scan line SL. One second subpixel SP 2 of the pair of second subpixels SP 2 may be disposed on one side of the scan line SL and the other second subpixel SP 2 may be disposed on the other side of the scan line SL. Further, each of the pair of second subpixels SP 2 is disposed farther from the scan line SL than the first subpixel SP 1 is disposed from the scan line SL, such that the first subpixel SP 1 may be disposed between the second subpixel SP 2 and the scan line SL. Finally, a third subpixel SP 3 of the pair of third subpixels SP 3 may be disposed on one side of the scan line SL, and the other third subpixel SP 3 may be disposed on the other side of the scan line SL. Further, each of the pair of third subpixels SP 3 may be disposed to be farther from the scan line SL than the second subpixel SP 2 of the scan line SL, such that the second subpixel SP 2 may be disposed between the third subpixel SP 3 and the first subpixel SP 1.Therefore, a group of the first subpixel SP 1, the second subpixel SP 2, and the third subpixel SP 3 disposed on one side of the scan line SL and a group of the first subpixel SP 1, the second subpixel SP 2, and the third subpixel SP 3 disposed on the other side of the scan line SL may be horizontally symmetrically disposed. For example, the plurality of subpixels SP included in one pixel PX may be arranged in the row order of the third subpixel SP 3, the second subpixel SP 2, the first subpixel SP 1, the first subpixel SP 1, the second subpixel SP 2, and the third subpixel SP 3. In the display device 100 according to the embodiment of the present disclosure, the groups of the first subpixels SP 1, the second subpixels SP 2, and the third subpixels SP 3 respectively disposed on the one side and the other side of the scan line SL are disposed to be horizontally symmetric, such that the repair lines WRL may be configured as a single-layer structure made of a light transmissive conductive material. A more detailed description will be given below with reference to FIGS. 5A to 6.The plurality of light transmissive regions TA are regions excluding the region in which the plurality of lines and the plurality of pixel regions UPA are arranged in the display region AA. The plurality of light transmissive regions TA have a relatively high transmission rate. The light transmissive region TA allows light to pass therethrough such that a background located on the rear side of the display device 100 is visible from the front side of the display device 100. The plurality of light transmissive regions TA may be arranged to be spaced apart from each other with the plurality of lines and the plurality of pixel regions UPA interposed therebetween. The plurality of light transmissive regions TA may be disposed so as to surround the plurality of pixel regions UPA. Therefore, the display device 100 according to the embodiment of the present disclosure may be implemented as the transmissive display device 100 including the plurality of transmissive regions TA.Referring to FIGS. 4 to 5B, each of the plurality of subpixels SP includes the pixel circuit and the light emitting element 120. The pixel circuit may include a plurality of transistors T 1, T 2, and DT and a storage capacitor Cst and operate the light emitting element 120. For example, the pixel circuit may include a first transistor T 1, a second transistor T 2, a driving transistor DT, and the storage capacitor Cst. In addition, the plurality of subpixels SP arranged in a pixel area UPA may be connected to the scan line SL, the plurality of data lines DL, the reference line RL, the high potential power line VDD, and the low potential power line VSS, and may be supplied with various kinds of signals.First, a substrate 110 is a component for supporting various constituent elements included in the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, or the like. Moreover, the substrate 110 may include plastic such as polymer and be made of a material having flexibility.A light blocking layer LS is disposed on each of the plurality of subpixels SP on the substrate 110. The light blocking layer LS blocks light entering a driving active layer DACT of the driving transistor DT described below from a lower side of the substrate 110. The light blocking layer LS may block light entering the driving active layer DACT of the driving transistor DT, thereby reducing or minimizing a leakage current.A buffer layer 111 is disposed on the substrate 110 and the light blocking layer LS. The buffer layer 111 may reduce penetration of moisture or contaminants through the substrate 110. For example, the buffer layer 111 may be configured as a single-layer or multi-layer of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto. However, the buffer layer 111 may be excluded in accordance with the type of the substrate 110 or the type of the transistor. However, the present disclosure is not limited thereto.The driving transistor DT, the first transistor T 1, and the second transistor T 2 are disposed on the buffer layer 111 in each of the plurality of subpixels SP.The driving transistor DT, the first transistor T 1, and the second transistor T 2 of each of the plurality of subpixels SP may be P-type thin film transistors or N-type thin film transistors. For example, in the P-type thin film transistor, positive holes move from a source electrode to a drain electrode such that current can flow from the source electrode to the drain electrode. In the N-type thin film transistor, electrons move from a source electrode to a drain electrode so that current can flow from the drain electrode to the source electrode. Hereinafter, in the description, it is assumed that the driving transistor DT, the first transistor T 1, and the second transistor T 2 are the P-type thin film transistors in which the current flows from the source electrodes to the drain electrodes. However, the present disclosure is not limited thereto.First, the driving transistor DT is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The driving transistor DT is a transistor for controlling a driving current to be supplied to the light emitting element 120. In a pixel region UPA, the driving transistors DT of the plurality of subpixels SP may be arranged in a line in the column direction. The plurality of driving transistors DT of the plurality of subpixels SP may be arranged in a line while overlapping the regions in which the reference lines RL and the data lines DL are arranged.The driving transistor DT includes the driving active layer DACT, a driving gate electrode DGE, a driving source electrode DSE, and a driving drain electrode DDE.The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon. However, the present disclosure is not limited thereto.A gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer for insulating the driving active layer DACT and the driving gate electrode DGE. The gate insulating layer 112 may be configured as a single layer or a multi-layer layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.The drive gate electrode DGE is disposed on the gate insulating layer 112. The drive gate electrode DGE may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.A first interlayer insulating layer 113 ais disposed on the drive gate electrode DGE. A contact hole through which the driving source electrode DSE is connected to the driving active layer DACT is formed in the first interlayer insulating layer 113 a. The first interlayer insulating layer 113 ais an insulating layer for protecting components disposed under the first interlayer insulating layer 113 a. The first interlayer insulating layer 113 amay be configured as a single-layer layer or a multi-layer layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.The driving source electrode DSE is disposed on the first interlayer insulating layer 113 a. The driving source electrode DSE is electrically connected to the driving active layer DACT through contact holes formed in the first interlayer insulating layer 113 aand the gate insulating layer 112. Further, the driving source electrode DSE may be electrically connected to the second transistor T 2. The driving source electrode DSE may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.A second interlayer insulating layer 113 band a first passivation layer 114 aare disposed on the first interlayer insulating layer 113 a, and the drive drain electrode DDE is disposed on the first passivation layer 114 a. The driving drain electrode DDE is electrically connected to the driving active layer DACT through contact holes formed in the first passivation layer 114 a, the second insulating layer 113 b, the first intermediate insulating layer 113 a, and the gate insulating layer 112. Further, the driving drain electrode DDE may be electrically connected to the low-potential power line VSS through a contact hole formed in the first passivation layer 114 a. The drive drain electrode DDE may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.Next, the first transistor T 1 is disposed on the buffer layer 111 in each of the plurality of subpixels SP. The first transistor T 1 may be a transistor configured to transmit a data voltage to the drive gate electrode DGE of the drive transistor DT. The first transistor T 1 may be referred to as a switching transistor. In this case, in a pixel region UPA, the plurality of first transistors T 1 of the plurality of subpixels SP may be arranged in a line in a row direction, overlapping the scan line SL.Specifically, the scan line SL may extend on the gate insulating layer 112 in the row direction and be disposed so as to cross the plurality of pixel regions UPA. Further, from the left side, the first transistor T 1 of the first subpixel SP 1 on the other side of the scan line SL, the first transistor T 1 of the first subpixel SP 1 on one side of the scan line SL, the first transistor T 1 of the second subpixel SP 2 on the other side of the scan line SL, the first transistor T 1 of the second subpixel SP 2 on one side of the scan line SL, the first transistor T 1 of the third subpixel SP 3 on the other side of the scan line SL, and the first transistor T 1 of the third subpixel SP 3 on one side of the scan line SL may be sequentially arranged.In this case, the first transistors T 1 of the pair of first subpixels SP 1 may be disposed adjacent to each other and share one data line DL. Further, the first transistors T 1 of the pair of second subpixels SP 2 may also be arranged adjacent to each other and share a data line DL. Finally, the first transistors T 1 of the pair of third sub-pixels SP 3 may also be arranged adjacent to each other and share a data line DL.The first transistor T 1 includes a first active layer ACT 1, a first gate electrode GE 1, a first source electrode SE 1, and a first drain electrode DE 1.The first active layer ACT 1 is disposed on the buffer layer 111. The first active layer ACT 1 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon. However, the present disclosure is not limited thereto.The first gate electrode GE 1 is disposed on the gate insulating layer 112. The first gate electrode GE 1 may be electrically connected to the scan line SL. For example, the first gate electrode GE 1 may be integral with the scan line SL. The first gate electrode GE 1 may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.The first drain electrode DE 1 is disposed on the first interlayer insulating layer 113 a. The first drain electrode DE 1 is electrically connected to the first active layer ACT 1 through contact holes formed in the first interlayer insulating layer 113 aand the gate insulating layer 112. Further, the first drain electrode DE 1 may also be electrically connected to a second gate electrode GE 2 of the second transistor T 2 through the contact hole of the first interlayer insulating layer 113 a. The first drain electrode DE 1 may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.The second interlayer insulating layer 113 bis disposed on the first drain electrode DE 1. The second interlayer insulating layer 113 bis an insulating layer for protecting components disposed below the second interlayer insulating layer 113 b. The second interlayer insulating layer 113 bmay be configured as a single-layer layer or a multi-layer layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.The first passivation layer 114 ais disposed on the second interlayer insulating layer 113 b. The first passivation layer 114 ais an insulation layer for protecting components disposed under the first passivation layer 114 a. The first passivation layer 114 amay be configured as a single-layer structure or multi-layer layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.The first source electrode SE 1 is disposed on the first passivation layer 114 a. The first source electrode SE 1 is electrically connected to the first active layer ACT 1 through the contact holes of the first passivation layer 114 a, the second interlayer insulating layer 113 b, and the first interlayer insulating layer 113 a. Further, the first source electrode SE 1 may be electrically connected to the data line DL. For example, the first source electrode SE 1 may be integral with the data line DL. The first source electrode SE 1 may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.Next, the second transistor T 2 is disposed on the buffer layer 111 in each of the plurality of subpixels SP. The second transistor T 2 may be a transistor configured to compensate a threshold voltage of the driving transistor DT. The second transistor T 2 may be referred to as a sense transistor. The second transistors T 2 of the plurality of subpixels SP may be respectively disposed on the left sides of the plurality of subpixels SP and arranged in a line in the column direction.For example, the scan line SL may include a portion protruding in the column direction from a portion extending in the row direction. A part of the scan line SL protruding in the column direction may be disposed adjacent to the left sides of the plurality of sub-pixels SP and overlap the plurality of second transistors T 2. The portion of the scan line SL protruding in the column direction may serve as the second gate electrode GE 2 of the second transistor T 2 of the plurality of sub-pixels SP. Therefore, the second transistors T 2 of the plurality of subpixels SP may be disposed on the protruding part of the scan line SL and arranged in a line in the column direction.The second transistor T 2 includes a second active layer ACT 2, the second gate electrode GE 2, a second source electrode SE 2, and a second drain electrode DE 2.The second active layer ACT 2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT 2 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon. However, the present disclosure is not limited thereto.In this case, the second active layers ACT 2 of the plurality of adjacent subpixels SP may be connected to each other. For example, the second active layers ACT 2 of the first subpixel SP 1, the second subpixel SP 2, and the third subpixel SP 3 disposed on one side of the scan line SL may extend in the column direction and be connected to each other, and the second active layers ACT 2 may be connected together with the second drain electrode DE 2 disposed in the first subpixel SP 1. Further, the second active layers ACT 2 of the first subpixel SP 1, the second subpixel SP 2, and the third subpixel SP 3 disposed on the other side of the scan line SL may also extend in the column direction and be connected to each other, and the second active layers ACT 2 may be connected together with the second drain electrode DE 2 disposed in the first subpixel SP 1.That is, connection parts for connecting the reference line RL and the channel regions of the second active layers ACT 2 of the plurality of sub-pixels SP are made of the light transmissive material of the second active layer ACT 2 instead of a non-light transmissive electrically conductive material, such that a transmission rate at an outermost edge portion of the pixel region UPA may be increased. In addition, the connection parts for connecting the reference line RL and the channel regions of the second active layers ACT 2 of the plurality of sub-pixels SP are made of the material of the second active layer ACT 2, such that the contact hole can be eliminated and the structure of the pixel region UPA can be simplified.The second gate electrode GE 2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113 a. The second gate electrode GE 2 may be electrically connected to the scan line SL. For example, the second gate electrode GE 2 may be integral with the protruding part of the scan line SL and electrically connected to the protruding part of the scan line SL. The second gate electrode GE 2 may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.The second source electrode SE 2 is disposed between the first interlayer insulating layer 113 aand the second interlayer insulating layer 113 b. The second source electrode SE 2 is electrically connected to the second active layer ACT 2 through the contact holes of the first interlayer insulating layer 113 aand the gate insulating layer 112. Further, the second source electrode SE 2 may be electrically connected to the driving source electrode DSE. The second source electrode SE 2 may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.The second drain electrode DE 2 is disposed between the first passivation layer 114 aand a second passivation layer 114 b. The second drain electrode DE 2 is electrically connected to the second active layer ACT 2 through contact holes formed in the first passivation layer 114 a, the second insulating layer 113 b, the first interlayer insulating layer 113 a, and the gate insulating layer 112. The second drain electrode DE 2 may be integral with the reference line RL and electrically connected to the reference line RL. The second drain electrode DE 2 may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.Next, the storage capacitor Cst is disposed on the gate insulating layer 112. The storage capacitor Cst may store a potential difference between the driving gate electrode DGE and the driving source electrode DSE of the driving transistor DT while the light emitting element 120 emits light, such that a constant driving current may be supplied to the light emitting element 120. The storage capacitor Cst may include a first capacitor electrode C 1 electrically connected to the drive gate electrode DGE and a second capacitor electrode C 2 electrically connected to the drive source electrode DSE. The storage capacitor Cst can maintain constant voltages of the drive gate electrode DGE and the drive source electrode DSE.Specifically, the first capacitor electrode C 1 is disposed on the gate insulating layer 112. The first capacitor electrode C 1 may be integral with the drive gate electrode DGE. The second capacitor electrode C 2 is disposed on the first interlayer insulating layer 113 a. The first capacitor electrode C 1 and the second capacitor electrode C 2 may be disposed so as to overlap each other with the first interlayer insulating layer 113 aarranged therebetween. In this case, the second capacitor electrode C 2 may be integral with the drive source electrode DSE. The first capacitor electrode C 1 and the second capacitor electrode C 2 may each be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.Next, an auxiliary electrode AE is disposed on the first passivation layer 114 a. The auxiliary electrode AE is an electrode for electrically connecting the driving source electrode DSE and a first reflective electrode RE 1. The driving source electrode DSE and the first reflective electrode RE 1 may be electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.The low-potential power line VSS is disposed on the second interlayer insulating layer 113 b. The low potential power line VSS may be disposed in the column direction and overlap the plurality of pixel regions UPA. The low-potential power line VSS may be electrically connected to the drive drain electrode DDE. The low-potential power line VSS may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.The reference line RL is disposed on the first passivation layer 114 a. The reference line RL may be arranged in the column direction and overlap the plurality of pixel regions UPA. The reference line RL may be disposed adjacent to the plurality of second transistors T 2 and electrically connected to the plurality of second transistors T 2. The reference line RL may be made of an electrically conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.The plurality of data lines DL are disposed on the first passivation layer 114 a. The plurality of data lines DL may extend in the column direction and overlap the plurality of pixel areas UPA. The plurality of data lines DL may include the data line DL connected to the first transistors T 1 of the plurality of first subpixels SP 1, the data line DL connected to the first transistors T 1 of the plurality of second subpixels SP 2, and the data line DL connected to the first transistors T 1 of the plurality of third subpixels SP 3. For example, from the left side, the reference line RL, the data line DL connected to the first subpixel SP 1, the data line DL connected to the second subpixel SP 2, and the data line DL connected to the third subpixel SP 3 may be sequentially arranged.Next, the second passivation layer 114 bis disposed on the driving transistor DT, the first transistor T 1, the second transistor T 2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114 bmay be an isolation layer for protecting components disposed under the second passivation layer 114 b. The second passivation layer 114 bmay be configured as a single layer or a multi-layer layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.A first planarization layer 115 ais disposed on the second passivation layer 114 b. The first planarization layer 115 amay level an upper portion of the substrate 110 on which the plurality of transistors and the storage capacitor Cst are disposed. The first planarization layer 115 amay be configured as a single layer or a multi-layer, and may be made of, for example, a photo resin or an acrylic-based organic material. However, the present disclosure is not limited thereto.Here, although not illustrated in the drawings, an additional passivation layer may be further disposed on the first planarization layer 115 a. For example, the passivation layer configured as a single-layer or multi-layer made of silicon oxide (SiOx) or silicon nitride (SiNx) may be disposed on the first planarization layer 115 aand protect the components disposed under the passivation layer.Next, the plurality of first reflective electrodes RE 1 are disposed on the first planarization layer 115 a. The plurality of first reflective electrodes RE 1 may be disposed in the plurality of subpixels SP in an associated manner and electrically connect the driving transistors DT and the light emitting elements 120. At the same time, the plurality of first reflective electrodes RE 1 may reflect the light emitted from the light emitting elements 120 to the outside of the display device 100. The plurality of first reflective electrodes RE 1 may be disposed in the plurality of subpixels SP adjacent to the driving source electrode DSE. The plurality of first reflective electrodes RE 1 may be made of a non-light transmissive conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof with high reflection efficiency. However, the present disclosure is not limited thereto.Here, the first reflective electrode RE 1 disposed in some of the plurality of subpixels SP may overlap a welding area WA. A part of the first reflective electrode RE 1 disposed in a first subpixel SP 1 of the pair of first subpixels SP 1 may protrude toward the welding region WA and overlap the repair line WRL. In the subsequent repair process, the first reflective electrode RE 1 may be electrically and directly connected to the repair line WRL. A detailed description thereof will be described below with reference to FIG. 6.A second reflective electrode RE 2 or the high-potential power line VDD is disposed on the first planarization layer 115 a. The second reflective electrode RE 2 and the high-potential power line VDD may be integral and configured to supply a high-potential power voltage to the light emitting element 120 and reflect the light emitted from the light emitting element 120 to the outside of the display device 100. The second reflective electrodes RE 2 of the plurality of subpixels SP may be connected to each other and may be integral. The second reflective electrode RE 2 and the high-potential power line VDD may extend in the column direction and be disposed so as to overlap the light emitting element 120. The second reflective electrode RE 2 and the high-potential power line VDD may be disposed to overlap the plurality of data lines DL, the reference line RL, and the low-potential power line VSS. The second reflective electrode RE 2 and the high-potential power line VDD may be made of a non-light transmissive conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof with high reflection efficiency. However, the present disclosure is not limited thereto.A third passivation layer 114 cis disposed on the plurality of first reflective electrodes RE 1 and the second reflective electrode RE 2. The third passivation layer 114 cmay be an isolation layer for protecting components disposed under the third passivation layer 114 c. The third passivation layer 114 cmay be configured as a single-layer layer or a multi-layer layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.A bonding layer AD is disposed on the third passivation layer 114 c. The bonding layer AD may be formed on the front surface of the substrate 110 and fix the light emitting element 120 disposed on the bonding layer AD. The bonding layer AD may be made of a photo-curable bonding material that can be cured by light. For example, the bonding layer AD may be made of a material selected from adhesive polymer, epoxy resin, UV resin, polyimide-based material, acrylate-based material, urethane-based material, and polydimethylsiloxane (PDMS). However, the present disclosure is not limited thereto.The plurality of light emitting elements 120 is provided on the bonding layer AD and disposed in each of the plurality of subpixels SP. The light emitting elements 120 may be elements configured to emit light by the current, and include a red light emitting element 120R configured to emit red light, a green light emitting element 120G configured to emit green light, and a blue light emitting element 120B configured to emit blue light. A combination of the light emitting elements 120 may implement various colors including white. For example, the light emitting element 120 may be a light emitting diode (LED) or a micro LED. However, the present disclosure is not limited thereto.The red light emitting element 120R may be disposed in the first subpixel SP 1, the green light emitting element 120G may be disposed in the second subpixel SP 2, and the blue light emitting element 120B may be disposed in the third subpixel SP 3. The plurality of light emitting elements 120 arranged in a pixel region UPA may be arranged in a line in the column direction. Further, the plurality of light emitting elements 120 may be disposed in the plurality of sub-pixels SP in an associated manner and may be disposed to overlap the second reflective electrode RE 2.The plurality of light emitting elements 120 each include a first semiconductor layer 121, a light emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation layer 126.The first semiconductor layer 121 is disposed on the bonding layer AD, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with n-type and p-type impurities. Further, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), or the like. The n-type impurity may be silicon (Si), germanium, tin (Sn), or the like. However, the present disclosure is not limited thereto.The light emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 may emit light by receiving positive holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 may be configured as a single layer or a multi-quantum well structure (MQW). For example, the light emitting layer 122 may be made of indium gallium nitride (InGaN), gallium nitride (GaN), or the like. However, the present disclosure is not limited thereto.The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on a top surface of the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of an electrically conductive material, for example, a light transmissive conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a non-light transmissive conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on a top surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting the high-potential power line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of an electrically conductive material, for example, a light-transmissive conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a non-light-transmissive conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.Next, the encapsulation layer 126 is disposed so as to surround the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation layer 126 may be made of an insulating material and protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. Further, a contact hole through which the first electrode 124 and the second electrode 125 are exposed may be formed in the encapsulation layer 126 such that the first connection electrode CE 1, the second connection electrode CE 2, the first electrode 124, and the second electrode 125 may be electrically connected.Here, a part of a side surface of the first semiconductor layer 121 may be exposed from the encapsulation layer 126. The light emitting element 120 fabricated on a wafer may be separated from the wafer and transferred to the display panel PN. However, a part of the encapsulation layer 126 may be torn during a process of separating the light emitting element 120 from the wafer. For example, a portion of the encapsulation layer 126 adjacent to a lower edge of the first semiconductor layer 121 of the light emitting element 120 may be torn during the process of separating the light emitting element 120 from the wafer such that a portion of a lower side surface of the first semiconductor layer 121 may be exposed to the outside. Although the lower portion of the light emitting element 120 is exposed from the encapsulation layer 126, the first connection electrode CE 1 and the second connection electrode CE 2 are formed after the second planarization layer 115 band the third planarization layer 115 ccoating the side surface of the first semiconductor layer 121 are formed, thereby reducing a short-circuit defect.Next, the second planarization layer 115 band the third planarization layer 115 care disposed on the bonding layer AD and the light emitting element 120.The second planarization layer 115 bmay partially overlap the side surfaces of the plurality of light emitting elements 120 and fix and protect the plurality of light emitting elements 120. The second planarization layer 115 bmay cover a cracked portion of the encapsulation layer 126 protecting the side surface of the first semiconductor layer 121 of the light emitting element 120. Therefore, it is possible to suppress contact between the connection electrode and the first semiconductor layer 121 and a later short-circuit defect.The third planarization layer 115 cis formed so as to cover upper surfaces of the second planarization layer 115 band the light emitting element 120. A contact hole through which the first electrode 124 and the second electrode 125 of the light emitting element 120 are exposed may be formed in the third planarization layer 115 c. The first electrode 124 and the second electrode 125 of the light emitting element 120 may be exposed from the third planarization layer 115 c. However, the third planarization layer 115 cis partially disposed in a region between the first electrode 124 and the second electrode 125, thereby reducing a short-circuit defect. The second planarization layer 115 band the third planarization layer 115 cmay each be configured as a single-layer layer or a multi-layer layer, and consist of, for example, a photo resin or an acrylic-based organic material. However, the present disclosure is not limited thereto.The first connection electrode CE 1 and the second connection electrode CE 2 are disposed on the third planarization layer 115 c.The first connection electrode CE 1 is an electrode that electrically connects the driving transistor DT and the first electrode 124 of the light emitting element 120. The first connection electrode CE 1 may be electrically connected to the first electrode 124 exposed from the third planarization layer 115 cand simultaneously electrically connected to the first reflective electrode RE 1 through contact holes formed in the third planarization layer 115 c, the second planarization layer 115 b, and the third passivation layer 114 c. Therefore, the first electrode 124 and the driving source electrode DSE may be electrically connected by the first connection electrode CE 1, the first reflective electrode RE 1, and the auxiliary electrode AE.The second connection electrode CE 2 is an electrode that electrically connects the high-potential power line VDD and the second electrode 125 of the light emitting element 120. The second connection electrode CE 2 may be electrically connected to the second electrode 125 exposed from the third planarization layer 115 cand electrically connected to the second reflective electrode RE 2 or the high-potential power line VDD through contact holes formed in the third planarization layer 115 c, the second planarization layer 115 b, and the third passivation layer 114 c. Therefore, the second electrode 125 and the high-potential power line VDD may be electrically connected through the second connection electrode CE 2.The first connection electrode CE 1 and the second connection electrode CE 2 may be made of a light-transmissive conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.Here, the figures show that the driving source electrode DSE of the driving transistor DT and the first electrode 124 of the light emitting element 120 are electrically connected. However, the driving drain electrode DDE of the driving transistor DT and the second electrode 125 of the light emitting element 120 may be electrically connected in accordance with the type of the driving transistor DT and the configuration of the pixel circuit. However, the present disclosure is not limited thereto.Next, a bank BB is disposed in the pixel region UPA on the third planarization layer 115 c, the first connection electrode CE 1, and the second connection electrode CE 2. The bank BB may be disposed to be spaced apart from the light emitting element 120 by a predetermined distance. The bank BB may be disposed at a boundary between the plurality of subpixels SP and partially cover the first connection electrode CE 1 and the second connection electrode CE 2. The bank BB may be disposed to be spaced apart from the light transmissive region TA. The bank BB may be made of a non-light transmissive material, for example, black resin, for reducing color mixture between the plurality of subpixels SP. However, the present disclosure is not limited thereto.A protection layer 116 is disposed on the first connection electrode CE 1, the second connection electrode CE 2, and the bank BB. The protective layer 116 is a layer for protecting components disposed under the protective layer 116. The protective layer 116 may be configured as a single-layer or multi-layer consisting of, for example, benzocyclobutene, light-transmissive epoxy, a photo resin, an acrylic-based organic material or an inorganic material, silicon oxide (SiOx), or silicon nitride (SiNx). However, the present disclosure is not limited thereto.Here, during a process of manufacturing the display device 100, a lighting test method for detecting a defective subpixel SP may be performed. For example, a defective subpixel SP that does not emit light may be detected by operating the plurality of light emitting elements 120 in the state where the plurality of light emitting elements 120, the first connection electrode CE 1, and the second connection electrode CE 2 are formed. For example, the defective subpixel SP may be caused by a defect of the pixel circuit, a transmission error of the light emitting element 120, or foreign matter. Therefore, in the display device 100 according to the embodiment of the present disclosure, a repair process of the defective subpixel SP can be performed, thereby improving the quality of the display device 100.Specifically, when a defect occurs at any one of the plurality of subpixels SP, the repair line WRL may be used to connect the light emitting element 120 of the defective subpixel SP to a pixel circuit of a normal subpixel SP such that the light emitting element 120 of the defective subpixel SP may be operated by the pixel circuit of the normal subpixel SP. Therefore, in the display device 100, the plurality of repair lines WRL for repair are arranged.Referring to FIGS. 3, 4, and 5B together, the plurality of repair lines WRL are disposed in the plurality of pixel regions UPA on the third planarization layers 115 c. The plurality of repair lines WRL may be arranged to connect the same types of sub-pixels SP. For example, the repair lines WRL may be respectively disposed between the pair of first subpixels SP 1, between the pair of second subpixels SP 2, and between the pair of third subpixels SP 3.One end of the repair line WRL may be disposed to overlap the first reflective electrode RE 1 of one of the pair of sub-pixels SP, and the other end of the repair line WRL may be connected to the first connection electrode CE 1 of the other of the pair of sub-pixels SP. For example, one end FE of the repair line WRL may be disposed to overlap the first reflective electrode RE 1 of the first subpixel SP 1 disposed on one side of the scan line SL, and the other end SE of the repair line WRL may be connected to the first connection electrode CE 1 of the first subpixel SP 1 disposed on the other side of the scan line SL. In this case, the first connection electrode CE 1 and the repair line WRL may be disposed on the same layer and may be integral. For example, the repair line WRL may extend continuously and continuously from the first connection electrode CE 1 and is disposed on a same layer (i.e., both the first connection electrode CE 1 and the repair line WRL are disposed on the same layer, the third planarization layer 115 c). The other end SE of the repair line WRL is continuously and continuously connected to the first connection electrode CE 1. Therefore, the repair line WRL may be connected to the first connection electrode CE 1 of one of the pair of sub-pixels SP without being connected to the first connection electrode CE 1 of the other sub-pixel SP, instead, the repair line WRL may be disposed to overlap the first reflective electrode RE 1 of the other sub-pixel SP in a plan view. In some embodiments, the first connection electrode CE 1 and the repair line WRL are made of the same material and are manufactured during the same process.In this case, a region where the first reflective electrode RE 1 and the repair line WRL overlap each other in a plan view may be defined as the welding region WA irradiated with laser beams during the repair operation. The first reflective electrode RE 1 and the repair line WRL may be connected by irradiating the welding region WA with laser beams. A detailed description thereof will be described with reference to FIG. 6.Next, referring to FIGS. 5A and 6, when a defect occurs at any one of the plurality of subpixels SP, the repair process may be performed by separating the pixel circuit of the defective subpixel SP and the light emitting element 120 and connecting the light emitting element 120 of the defective subpixel SP to the pixel circuit of the normal subpixel SP.First, the pixel circuit of the defective subpixel SP and the light emitting element 120 may be separated. When the defective subpixel SP and the light emitting element 120 are not electrically disconnected, a defect in the form of a bright spot or the like may occur because the light emitting elements 120 of some of the defective subpixels SP operate abnormally. For example, the light emitting element 120 of the defective subpixel SP continuously emits light regardless of images, which may result in a defect in which a bright spot is detected. Therefore, the pixel circuit of the defective subpixel SP and the light emitting element 120 may be separated so that the driving current is not supplied from the pixel circuit of the defective subpixel SP to the light emitting element 120.In this case, a driving current transmission path between the light emitting element 120 and the pixel circuit of the defective subpixel SP can be eliminated by destroying the connection portion between the light emitting element 120 and the driving source electrode DSE of the driving transistor DT. For example, the light emitting element 120 and the driving transistor DT may be electrically connected to each other through the first reflective electrode RE 1 and the first connection electrode CE 1. Further, any of the connection portions between the first reflective electrode RE 1 and the first connection electrode CE 1 may be destroyed by irradiation with laser beams. For example, referring to FIG. 5A, the first reflective electrode RE 1 may include a portion overlapping the first connection electrode CE 1 and a portion not overlapping the first connection electrode CE 1. The first reflective electrode RE 1 and the driving transistor DT may be electrically connected through the first contact hole CH 1 formed so as to correspond to the portion not overlapping the first connection electrode CE 1. That is, the first contact hole CH 1 may overlap the first reflective electrode RE 1 without overlapping the first connection electrode CE 1. Further, the first contact hole CH 1 may be irradiated with laser beams such that the connection portion of the first contact hole CH 1 connecting the first reflective electrode RE 1 and the driving transistor DT may be destroyed. Therefore, since the connection portion between the first reflective electrode RE 1 and the driving source electrode DSE is damaged, the driving transistor DT and the light emitting element 120 can be separated and a defect in the form of a bright spot can be suppressed.Here, FIG. 5B shows the region where the first connection electrode CE 1 and the repair line WRL are formed, but does not represent the first contact hole CH 1. However, as illustrated in FIG. 5A, the first contact hole CH 1 may be present in a region where the first connection electrode CE 1 and the repair line WRL are not formed.Next, referring to FIG. 6, the welding process for connecting the repair line WRL and the first reflective electrode RE 1 may be performed by irradiating the welding region WA with laser beams. For example, when a defect occurs at any one of the pair of first subpixels SP 1, the first contact hole CH 1 of the defective subpixel SP may be broken, and then the welding region WA formed in any one of the pair of first subpixels SP 1 may be irradiated with laser beams.In the welding region WA, one end of the repair line WRL and the first reflective electrode RE 1 are disposed so as to overlap each other with the third planarization layer 115 c, the second planarization layer 115 b, the bonding layer AD, and the third passivation layer 114 cbeing interposed therebetween. When the welding region WA is irradiated with laser beams, the third planarization layer 115 c, the second planarization layer 115 b, the bonding layer AD, and the third passivation layer 114 cmay be broken, such that the repair line WRL and the first reflective electrode RE 1 may be connected to each other. The insulating layers between the repair line WRL and the first reflective electrode RE 1 may be destroyed in an atypical shape such that the first reflective electrode RE 1 and the repair line WRL may be electrically connected to each other. Therefore, after the welding process, the first connection electrode CE 1 of the defective subpixel SP and the first connection electrode CE 1 of the normal subpixel SP may be electrically connected to each other through the repair line WRL and the first reflective electrode RE 1.Therefore, the driving transistor DT of the normal subpixel SP may be electrically connected to both the first connection electrode CE 1 of the normal subpixel SP and the first connection electrode CE 1 of the defective subpixel SP, and the light emitting element 120 of the defective subpixel SP and the light emitting element 120 of the normal subpixel SP may be connected in parallel to the driving transistor DT of the normal subpixel SP. Therefore, the light emitting element 120 of the defective subpixel SP and the light emitting element 120 of the normal subpixel SP may be connected in parallel to the pixel circuit of the normal subpixel SP and operated together.Therefore, in the display device 100 according to the embodiment of the present disclosure, the plurality of subpixels SP that configure one pixel PX are arranged to be horizontally symmetrical with respect to the scan line SL, such that the plurality of repair lines WRL may be formed so as not to overlap each other. For example, the repair line WRL connecting the pair of first subpixels SP 1 with the smallest distance from each other may be disposed to be closest to the reference line RL. Further, the repair line WRL connecting the pair of third subpixels SP 3 with the largest distance from each other may be disposed to be farthest from the reference line RL. The repair line WRL connecting the pair of second subpixels SP 2 may be disposed between the repair line WRL connecting the first subpixels SP 1 and the repair line WRL connecting the third subpixels SP 3. Therefore, the repair line WRL connecting the third sub-pixels SP 3 may be disposed to surround the repair line WRL connecting the first sub-pixel SP 1 and the second sub-pixel SP 2. The repair line WRL connecting the second subpixels SP 2 may be disposed to surround the repair line WRL connecting the first subpixels SP 1. Therefore, the repair line WRL connecting the subpixels SP located at the closest distance from each other may have a shorter length, and the repair line WRL connecting the subpixels SP located at the closest distance from each other may have a longer length.Therefore, the positions of the repair lines WRL connecting the plurality of sub-pixels SP do not overlap, so that the repair lines WRL may be configured as a single layer on the same layer. When the traces of the repair lines WRL overlap each other, some of the repair lines WRL need to be replaced with conductive layers on other layers in order to suppress interference between the repair lines WRL. In this case, the repair lines WRL need to be configured as a plurality of conductive layers disposed on different layers, which may make it difficult to design the repair lines WRL and the subpixels SP. However, in the display device 100 according to the embodiment of the present disclosure, the repair line WRL connecting the pair of subpixels SP at a large distance from each other may be disposed to surround the repair line WRL connecting the pair of subpixels SP at a small distance from each other, such that the two repair lines WRL may be prevented from interfering with each other, and the repair lines WRL may be formed as a single conductive layer on the same layer.In addition, in the display device 100 according to the embodiment of the present disclosure, the plurality of subpixels SP may be arranged to be horizontally symmetrical, whereby interference between the plurality of repair lines WRL may be suppressed. When the plurality of subpixels SP are not arranged to be horizontally symmetric, at least some of the traces between the plurality of repair lines WRL inevitably overlap. For example, when the plurality of subpixels SP are arranged in one pixel area UPA in the row order of the first subpixel SP 1, the second subpixel SP 2, the third subpixel SP 3, the first subpixel SP 1, the second subpixel SP 2, and the third subpixel SP 3, the repair line WRL connecting the second subpixels SP 2 and the repair line WRL connecting the pair of the first subpixels SP 1 may forcibly overlap one or more times. That is, in order to connect one pair of subpixels SP, one repair line WRL necessarily needs to pass through the repair line WRL connecting the other pair of subpixels SP. Therefore, the repair lines WRL must be formed as a plurality of conductive layers in order to suppress interference at the point where the repair lines WRL overlap each other. In contrast, according to the display device 100 according to the embodiment of the present disclosure, the plurality of sub-pixels SP are arranged to be horizontally symmetrical, such that a repair line WRL connecting the sub-pixels SP may be arranged to surround another repair line WRL, and the plurality of repair lines WRL may be arranged not to overlap each other. Therefore, the traces between the plurality of repair lines WRL may be configured not to overlap each other, such that the plurality of repair lines WRL may be formed as a single layer on the same layer. Therefore, the structures of the plurality of repair lines WRL can be simplified, and the decrease in the transmission rate of the light transmissive region TA caused by the repair lines WRL can be reduced or minimized.Further, in the display device 100 according to the embodiment of the present disclosure, the plurality of repair lines WRL are formed as a single-layer layer made of a light transmissive conductive material, thereby reducing or minimizing the decrease in transmission rate caused by the plurality of repair lines WRL. For example, the first connection electrode CE 1 and the second connection electrode CE 2 may be made of a light transmissive conductive material, so that the first connection electrode CE 1 and the second connection electrode CE 2 may transmit the light emitted from the light emitting element 120 to the outside of the display device 100. Further, in the case that the repair lines WRL are formed by the same process as the first connection electrode CE 1, the repair lines WRL may be formed as a single-layer structure made of a light transmissive conductive material. The plurality of repair lines WRL may connect the plurality of subpixels SP at the outermost edge portion of the pixel area UPA. That is, at least some of the plurality of repair lines WRL may be disposed in the light transmissive region TA. In this case, since the plurality of repair lines WRL are made of only a light transmissive conductive material, the decrease in transmission rate caused by the plurality of repair lines WRL can be reduced or minimized. Moreover, as described above, the plurality of subpixels SP are arranged to be horizontally symmetric such that the plurality of repair lines WRL may be formed as a single-layer structure of a light transmissive conductive material. Therefore, in the display device 100 according to the embodiment of the present disclosure, the plurality of repair lines WRL are made of only a light transmissive conductive material, so that the decrease in transmission rate caused by the plurality of repair lines WRL can be reduced or minimized.FIG. 7 is a schematic enlarged plan view of a display region of a display device according to another embodiment of the present disclosure. FIG. 8 is an enlarged plan view of a region B in FIG. 7, FIG. 9 is a cross-sectional view of a pair of subpixels of the display device according to another embodiment of the present disclosure. A display device 700 illustrated in FIGS. 7 to 9 is substantially identical in configuration to the display device 100 illustrated in FIGS. 1 to 6 except for a connection relationship between the repair lines WRL. Therefore, repeated descriptions of the identical components will be omitted.Referring to FIGS. 7 and 8, the repair line WRL is disposed between the pixels PX adjacent in the column direction. For example, the plurality of pixel regions UPA may be arranged in a plurality of rows and a plurality of columns. The repair lines WRL may be arranged in the same column and between the pixel regions UPA arranged in the adjacent rows.For example, the repair line WRL may be arranged to connect the subpixel SP of the plurality of subpixels SP of the pixel PX(N) arranged in the N-th row arranged on the other side of the scan line SL and the subpixel SP of the plurality of subpixels SP of the pixel PX(N+1) arranged in the (N+1)-th row arranged on one side of the scan line SL. That is, when a defect occurs, the plurality of subpixels SP disposed on the other side of the scan line SL may be connected to the plurality of subpixels SP in the pixel area UPA in the next row through the repair lines WRL. Further, the plurality of subpixels SP disposed on one side of the scan line SL may be connected to the plurality of subpixels SP in the pixel area UPA in the previous row through the repair lines WRL.One end of each of the plurality of repair lines WRL may be disposed to overlap the first reflective electrode RE 1 of each of the plurality of subpixels SP in the pixel area UPA in the Nth row. The other end of each of the plurality of repair lines WRL may be connected to the first connection electrode CE 1 of each of the plurality of subpixels SP in the pixel area UPA in the (N+1)-th row. In this case, the welding region WA to be irradiated with laser beams is a region where the first reflective electrode RE 1 and an end of the repair line WRL overlap, and the welding region WA may be disposed in the pixel region UPA in the Nth row. That is, the welding region WA may be formed in any of the pixel regions UPA in the N-th row and the pixel regions UPA in the (N+1)-th row.However, one end of the repair line WRL may be connected to the first connection electrode CE 1 in the pixel area UPA in the N-th row, and the other end of the repair line WRL may be disposed to overlap the first reflective electrode RE 1 in the (N+1)-th row, such that the welding area WA may be formed in the pixel area UPA in the (N+1)-th row. However, the arrangement of the welding region WA is not limited thereto.In this case, the plurality of subpixels SP in the adjacent pixel regions UPA may also be arranged to be horizontally symmetric with respect to the boundary between the pixel regions UPA. For example, the subpixels SP of the plurality of subpixels SP in the Nth row disposed on the other side of the scan line SL may be disposed from above in the row order of the first subpixel SP 1, the second subpixel SP 2, and the third subpixel SP 3. The subpixels SP of the plurality of subpixels SP in the (N+1)-th row disposed on one side of the scan line SL may be disposed from above in the row order of the third subpixel SP 3, the second subpixel SP 2, and the first subpixel SP 1. Therefore, the plurality of subpixels SP are arranged to be horizontally symmetrical with respect to the boundary between the pixel areas UPA, such that the plurality of repair lines WRL may be formed so as not to overlap each other.Therefore, in the display device 700 according to another embodiment of the present disclosure, the plurality of repair lines WRL may be formed between the adjacent pixel regions UPA, and the repair process may be performed. For example, in the case that some of the subpixels SP included in one pixel area UPA are defective, the repair line WRL may be used to electrically connect the light emitting element 120 of the defective subpixel SP to the pixel circuit of the subpixel SP in the adjacent pixel area UPA. When both of the pair of subpixels SP that are of the same type and included in one pixel area UPA have a defect, the repair operation may be performed by connecting the pair of subpixels SP to the subpixels SP in the different pixel areas UPA, which may improve the yield of the repair operation.FIG. 10 is an enlarged plan view of a display device according to still another embodiment of the present disclosure. FIGS. 11A and 11B are cross-sectional views of subpixels of the display device according to still another embodiment of the present disclosure. A display device 1000 illustrated in FIGS. 10 to 11B is substantially identical in configuration to the display device 700 illustrated in FIGS. 7 to 9 except for the repair lines WRL. Therefore, repeated descriptions of the identical components will be omitted. Here, in FIG. 11B, only a part of the first reflective electrode RE 1 overlapping the first connection electrode CE 1 is illustrated for convenience of description, but FIG. 11B does not illustrate the first contact hole CH 1 between the driving source electrode DSE and the first reflective electrode RE 1 not overlapping the first connection electrode CE 1. However, as described above with reference to FIG. 5A, the first contact hole CH 1 through which the first reflective electrode RE 1 and the driving source electrode DSE are connected may be formed in the region where the first connection electrode CE 1 is not disposed.Referring to FIGS. 10 to 11B, the plurality of repair lines WRL are disposed between the second planarization layer 115 band the third planarization layer 115 c. The plurality of repair lines WRL may be disposed between the second planarization layer 115 band the third planarization layer 115 cand disposed between the first connection electrodes CE 1 of the pair of subpixels SP. The plurality of repair lines WRL may be made of a light-transmissive conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).One end of each of the plurality of repair lines WRL may be disposed in the pixel region UPA in the N-th row and disposed to overlap the first reflective electrode RE 1 and the first connection electrode CE 1 of each of the plurality of subpixels SP. That is, a region where one end of each of the plurality of repair lines WRL is disposed may be defined as the welding region WA to be irradiated with laser beams.When the defective subpixel SP does not occur, one end of each of the plurality of repair lines WRL may be disposed to overlap the first reflective electrode RE 1 and the first connection electrode CE 1 of each of the plurality of subpixels SP in the pixel area UPA in the Nth row, while the plurality of repair lines WRL may be separated from the first reflective electrode RE 1 and the first connection electrode CE 1, wherein the third planarization layer 115 c, the second planarization layer 115 b, the bonding layer AD and the third passivation layer 114 care interposed between the plurality of repair lines WRL and the first reflective electrode RE 1 and between the plurality of repair lines WRL and the first connection electrode CE 1.In contrast, in the case that a defective subpixel SP occurs, the welding region WA disposed at one end of each of the plurality of repair lines WRL may be irradiated with laser beams such that the plurality of repair lines WRL may be connected to at least any one of the first connection electrode CE 1 above the repair line WRL and the first reflective electrode RE 1 below the repair line WRL. For example, the laser beams may destroy the third planarization layer 115 cbetween the first connection electrode CE 1 and the repair line WRL, and the third planarization layer 115 cmay be removed such that the first connection electrode CE 1 and the repair line WRL may be connected to each other. Further, the second planarization layer 115 b, the bonding layer AD, and the third passivation layer 114 cbetween the repair line WRL and the first reflective electrode RE 1 may also be destroyed by the laser beams, such that the repair line WRL and the first reflective electrode RE 1 may be connected to each other. Therefore, the welding process can be performed in the welding region WA such that the repair line WRL can be electrically connected to the first connection electrode CE 1 and the first reflective electrode RE 1.Further, the other end of each of the plurality of repair lines WRL may be disposed in the pixel region UPA in the (N+1)-th row, electrically connected to the first connection electrode CE 1 of each of the plurality of subpixels SP through the third planarization layer 115 c, and simultaneously electrically connected to the first reflective electrode RE 1 through the contact holes of the second planarization layer 115 b, the bonding layer AD, and the third passivation layer 114 c. That is, the plurality of repair lines WRL may electrically connect the first connection electrodes CE 1 and the first reflective electrodes RE 1 in the plurality of subpixels SP in the pixel area UPA in the (N+1)-th row.Here, the structure of the repair line WRL illustrated in FIGS. 10 to 11B may also be applied to the display device 100 illustrated in FIGS. 1 to 6, in which the repair line WRL is disposed in a pixel area UPA. However, the present disclosure is not limited thereto.Therefore, in the display device 1000 according to still another embodiment of the present disclosure, the first connection electrode CE 1, the repair line WRL, and the first reflective electrode RE 1 are arranged to overlap each other in the welding region WA, thereby reducing or minimizing a defect in which the repair line WRL is not connected. The repair line WRL may be disposed in the welding region WA between the first connection electrode CE 1 and the first reflective electrode RE 1. Even if the intensity of the laser beams is low and the second planarization layer 115 b, the bonding layer AD, and the third passivation layer 114 cdisposed below the repair line WRL are not at least partially removed, the repair line WRL and the first connection electrode CE 1 disposed above the repair line WRL can be connected to each other, thereby reducing or minimizing the defect in which the repair line WRL is not connected. In addition, only a third planarization layer 115 cis disposed between the repair line WRL and the first connection electrode CE 1 instead of a plurality of insulating layers, such that the third planarization layer 115 cmay be removed more easily during the welding process and the repair line WRL and the first connection electrode CE 1 may be connected easily. Therefore, in the welding region WA, the first connection electrode CE 1, the repair line WRL, and the first reflective electrode RE 1 are arranged in the shape of a three-layer structure, so that the repair line WRL can be more easily connected to at least one of the first connection electrode CE 1 and the first reflective electrode RE 1 during the welding process, which can improve the yield of the repair process.FIG. 12 is a schematic enlarged plan view of the display device according to still another embodiment of the present disclosure. FIG. 13 is an enlarged plan view of a region C in FIG. 12, FIG. 14 is an enlarged plan view of a region D in FIG. 12, A display device 1200 illustrated in FIGS. 12 to 14 is substantially identical in configuration to the display devices 100 and 700 illustrated in FIGS. 1 to 9 except for a connection relationship between the repair lines WRL. Therefore, repeated descriptions of the identical components will be omitted.Referring to FIG. 12, the plurality of subpixels SP may be repaired using different subpixels SP arranged in the same pixel area UPA or using the subpixels SP arranged in the adjacent pixel areas UPA. That is, the plurality of repair lines WRL are disposed between the pair of subpixels SP arranged in the same pixel area UPA or between the pair of subpixels SP arranged in the different pixel areas UPA.For example, referring to FIGS. 12 and 13, in a pixel area UPA, the repair line WRL may be disposed between the pair of first subpixels SP 1 that are the closest distance from each other. That is, the first subpixel SP 1 can be repaired using the other first subpixel SP 1 disposed in the same pixel area UPA.As another example, referring to FIGS. 12 and 14, a repair line WRL may be disposed between the second subpixel SP 2 in one pixel area UPA and the second subpixel SP 2 in another pixel area UPA adjacent to the one pixel area UPA. When the defective subpixel SP occurs, the repair line WRL may be used to connect the second subpixels SP 2 arranged in the different pixel areas UPA. Further, the repair line WRL may be disposed between the third subpixel SP 3 in one pixel area UPA and the third subpixel SP 3 of another pixel area UPA adjacent to the one pixel area UPA. When the defective subpixel SP occurs, the repair line WRL may be used to connect the third subpixels SP 3 disposed in the different pixel areas UPA.Here, it is illustrated in the drawings that the repair line WRL is disposed between the second sub-pixels SP 2 in the different pixel areas UPA. However, the repair line WRL may be disposed between the second subpixels SP 2 in the same pixel area UPA. However, the present disclosure is not limited thereto.In the display device 1200 according to still another embodiment of the present disclosure, the repair line WRL may be disposed in consideration of a distance between the plurality of subpixels SP. The repair line WRL may be connected between the pair of sub-pixels SP with a slight interval, so that a length of the repair line WRL may be reduced. For example, the repair line WRL may be disposed between the first subpixels SP 1 of the plurality of subpixels SP disposed in the same pixel region UPA disposed at a small distance from each other. That is, a distance from a first subpixel SP 1 to the first subpixel SP 1 in the same pixel area UPA is much shorter than a distance from a first subpixel SP 1 to the first subpixel SP 1 in another pixel area UPA. Therefore, the repair line WRL having the shortest length may be formed between the pair of first subpixels SP 1 arranged in the same pixel area UPA. In contrast, a distance from a third subpixel SP 3 to the third subpixel SP 3 in another adjacent pixel region UPA is shorter than a distance from a third subpixel SP 3 to the third subpixel SP 3 in the same pixel region UPA. Therefore, the repair line WRL may be disposed between the third subpixels SP 3 disposed in the different pixel regions UPA, such that the length of the repair line WRL may be reduced. Moreover, according to an embodiment, the second subpixel SP 2 may be connected to another second subpixel SP 2 disposed in the same pixel area UPA or connected to the second subpixel SP 2 in another adjacent pixel area UPA. Therefore, in consideration of the distance between the plurality of subpixels SP, the repair line WRL may be disposed between the subpixels SP disposed in the same pixel region UPA or the two adjacent pixel regions UPA, such that the length of the repair line WRL may be reduced. Therefore, the reduction in the length of the repair line WRL can reduce the resistance of the repair line WRL and reduce the power consumption, so that the display device 1200 can be operated with low power consumption.The exemplary embodiments of the present disclosure may also be described as follows:In accordance with an aspect of the present disclosure, a display device includes a substrate configured to define a plurality of pixel regions arranged to be spaced apart from each other and a plurality of light transmissive regions arranged between the plurality of pixel regions, a plurality of pixels arranged in the plurality of pixel regions and each including a plurality of sub-pixels, and a plurality of repair lines arranged between the plurality of sub-pixels and made of a light transmissive conductive material. The plurality of repair lines are disposed on the same layer and spaced apart from each other.The display device may further include at least some of the plurality of repair lines overlapping the plurality of light transmissive regions.The display device may further include a plurality of scan lines extending in a row direction and arranged to cross the plurality of pixel regions. The plurality of pixels may each include a pair of first sub-pixels arranged to be horizontally symmetric with respect to the plurality of scan lines, a pair of second sub-pixels arranged to be horizontally symmetric with respect to the plurality of scan lines, and a pair of third sub-pixels arranged to be horizontally symmetric with respect to the plurality of scan lines, and of the plurality of sub-pixels, the pair of first sub-pixels may be arranged to be closest to the plurality of scan lines, and the pair of third sub-pixels may be arranged to be farthest from the plurality of scan lines.The plurality of repair lines may be disposed between the pair of first sub-pixels, between the pair of second sub-pixels, and between the pair of third sub-pixels, and the repair line of the plurality of repair lines disposed between the pair of third sub-pixels may be disposed so as to surround the repair line disposed between the pair of first sub-pixels and the repair line disposed between the pair of second sub-pixels.One end and the other end of each of the plurality of repair lines may be arranged in the same pixel region of the plurality of pixel regions.One end of each of the plurality of repair lines may be disposed in a pixel region of the plurality of pixel regions, and the other end of each of the plurality of repair lines may be disposed in a pixel region adjacent to the one pixel region.One end and the other end of some of the plurality of repair lines may be arranged in the same pixel region of the plurality of pixel regions, and one end and the other end of the remaining repair lines may be arranged in different pixel regions of the plurality of pixel regions.The display device may further include a first reflective electrode disposed in each of the plurality of subpixels and disposed on the substrate, a light emitting element disposed in each of the plurality of subpixels is disposed on the first reflective electrode, and a first electrode, a planarization layer disposed on the light emitting element, and a first connection electrode disposed on the planarization layer and electrically connected to the first electrode and the first reflective electrode.One end of each of the plurality of repair lines may overlap the first reflective electrode of each of any one of the pair of first sub-pixels, any one of the pair of second sub-pixels, and any one of the pair of third sub-pixels, and the other end of each of the plurality of repair lines may be connected to the first connection electrode of each of the other one of the pair of first sub-pixels, the other one of the pair of second sub-pixels, and the other one of the pair of third sub-pixels.An end of each of the plurality of repair lines may be connected to the first reflective electrode in some of the plurality of sub-pixels, and an end of each of the plurality of repair lines may be separated from the first reflective electrode in some of the remaining sub-pixels.The plurality of repair lines may be disposed on the same layer as the first connection electrode and may be integral with the first connection electrode.The display device may further include a bonding layer disposed between the first reflective electrode and the light emitting element. The plurality of repair lines may be disposed on the bonding layer and disposed between the first reflective electrode and the first connection electrode.One end of each of the plurality of repair lines may overlap the first connection electrode of each of any one of the pair of first sub-pixels, any one of the pair of second sub-pixels, and any one of the pair of third sub-pixels, and the other end of each of the plurality of repair lines may be connected to the first connection electrode of each of the other of the pair of first sub-pixels, the other of the pair of second sub-pixels, and the other of the pair of third sub-pixels through a contact hole of the planarization layer.An end of each of the plurality of repair lines may be connected to at least any one of the first reflective electrode and the first connection electrode in some of the plurality of sub-pixels, and an end of each of the plurality of repair lines may be separated from the first reflective electrode and the first connection electrode in some of the remaining sub-pixels.The first reflective electrode in each of the plurality of subpixels may include a portion overlapping the first connection electrode and a portion not overlapping the first connection electrode.The display device may further include a driving transistor disposed between the substrate and the first reflective electrode in each of the plurality of subpixels, and an insulating layer disposed between the driving transistor and the first reflective electrode. The first reflective electrode may be electrically connected to the driving transistor through a first contact hole of the insulating layer, and the first contact hole may overlap the portion of the first reflective electrode that does not overlap the first connection electrode.The display device may further include a plurality of data lines extending in a column direction on the substrate. The plurality of pixel regions may overlap a region in which the plurality of data lines are arranged.Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only, but are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the exemplary embodiments described above are illustrative only in all aspects and do not limit the present disclosure.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedKR 10 - 2023 - 0 099 347

[0001]

Claims

A display device (100) comprising: a substrate (110) having a plurality of pixel regions (UPA) and a plurality of light transmissive regions (TA) thereon, wherein the plurality of pixel regions (UPA) are arranged to be spaced apart from each other, and the plurality of light transmissive regions (TA) are arranged between the plurality of pixel regions (UPA); a plurality of pixels (PX) arranged in the plurality of pixel regions (UPA), each of the plurality of pixels (PX) including a plurality of subpixels (SP); and a plurality of repair lines (WRL) arranged between the plurality of subpixels (SP), the plurality of repair lines (WRL) comprising a light-transmissive conductive material, wherein the plurality of repair lines (WRL) are arranged on a same layer and are arranged at a distance from one another.The display device (100) according to claim 1, further comprising: at least some of the plurality of repair lines (WRL) overlap the plurality of light transmissive regions (TA) in a plan view.The display device (100) according to claim 1 or 2, further comprising: a plurality of scan lines (SL) extending in a row direction and arranged to cross the plurality of pixel regions (UPA), wherein each of the plurality of pixels (PX) comprises: a pair of first sub-pixels (SP1) arranged to be horizontally symmetric with respect to the plurality of scan lines (SL); a pair of second sub-pixels (SP2) arranged to be horizontally symmetric with respect to the plurality of scan lines (SL); and a pair of third subpixels (SP 3) arranged to be horizontally symmetric with respect to the plurality of scan lines (SL), and wherein, of the plurality of subpixels, the pair of first subpixels (SP 1) is arranged to be closest to the plurality of scan lines (SL), and the pair of third subpixels (SP 3) is arranged to be farthest from the plurality of scan lines (SL).The display device (100) according to claim 3, wherein the plurality of repair lines (WRL) are disposed between the pair of first sub-pixels (SP1), between the pair of second sub-pixels (SP2), and between the pair of third sub-pixels (SP3), and wherein the repair line (WRL) of the plurality of repair lines (WRL) disposed between the pair of third sub-pixels (SP3) is disposed to surround the repair line (WRL) disposed between the pair of first sub-pixels (SP1) and the repair line (WRL) disposed between the pair of second sub-pixels (SP2).The display device (100) according to claim 3 or 4, wherein one end and the other end of each of the plurality of repair lines (WRL) are arranged in the same pixel area (UPA) of the plurality of pixel areas (UPA).The display device (100) according to claim 3 or 4, wherein one end of each of the plurality of repair lines (WRL) is disposed in one pixel region (UPA) of the plurality of pixel regions (UPA), and the other end of each of the plurality of repair lines (WRL) is disposed in one pixel region (UPA) adjacent to the one pixel region (UPA).The display device (100) according to claim 3 or 4, wherein one end and the other end of some of the plurality of repair lines (WRL) are arranged in the same pixel region (UPA) of the plurality of pixel regions (UPA), and one end and the other end of the remaining repair lines (WRL) are arranged in different pixel regions (UPA) of the plurality of pixel regions (UPA).The display device (100) according to any one of claims 3 to 7, further comprising: a first reflective electrode (RE1) disposed in each of the plurality of subpixels (SP) and disposed on the substrate (110); a light emitting element (120) disposed in each of the plurality of subpixels (SP), disposed on the first reflective electrode (RE1), and having a first electrode (124); a planarization layer (115b, 115c) disposed on the light emitting element (120); and a first connection electrode (CE1) disposed on the planarization layer (115b, 115c) and electrically connected to the first electrode (124) and the first reflective electrode (RE1).The display device (100) according to claim 8, wherein one end of each of the plurality of repair lines (WRL) overlaps the first reflective electrode (RE1) of each of any one of the pair of first sub-pixels (SP1), any one of the pair of second sub-pixels (SP2), and any one of the pair of third sub-pixels, and wherein the other end of each of the plurality of repair lines (WRL) is connected to the first connection electrode (CE1) of each of the other of the pair of first sub-pixels (SP1), the other of the pair of second sub-pixels (SP2), and the other of the pair of third sub-pixels (SP3).The display device (100) according to claim 9, wherein an end of each of the plurality of repair lines (WRL) is connected to the first reflective electrode (RE1) in some of the plurality of subpixels (SP), and wherein an end of each of the plurality of repair lines (WRL) is separated from the first reflective electrode (RE1) in some of the remaining subpixels (SP).The display device (100) according to claim 9 or 10, wherein the plurality of repair lines (WRL) are disposed on a same layer as the first connection electrode (CE1) and are integral with the first connection electrode (CE1).The display device (100) according to any one of claims 9 to 11, further comprising: a bonding layer (AD) disposed between the first reflective electrode (RE1) and the light emitting element (120), wherein the plurality of repair lines (WRL) are disposed on the bonding layer (AD) and are disposed between the first reflective electrode (RE1) and the first connection electrode (CE1).The display device (100) according to claim 12, wherein one end of each of the plurality of repair lines (WRL) overlaps the first connection electrode (CE1) of each of any one of the pair of first sub-pixels (SP1), any one of the pair of second sub-pixels (SP2), and any one of the pair of third sub-pixels (SP3), and wherein the other end of each of the plurality of repair lines (WRL) is connected through a contact hole of the planarization layer (115b, 115c) to the first connection electrode (CE1) of each of the other of the pair of first sub-pixels (SP1), the other of the pair of second sub-pixels (SP2), and the other of the pair of third sub-pixels (SP3).The display device (100) according to claim 13, wherein an end of each of the plurality of repair lines (WRL) in some of the plurality of subpixels (SP) is connected to at least one of the first reflective electrode (RE1) and the first connection electrode (CE1), and wherein an end of each of the plurality of repair lines (WRL) in some of the remaining subpixels (SP) is separated from the first reflective electrode (RE1) and the first connection electrode (CE1).The display device (100) according to any one of claims 8 to 14, wherein the first reflective electrode (RE1) includes, in each of the plurality of subpixels (SP), a portion overlapping the first connection electrode (CE1) and a portion not overlapping the first connection electrode (CE1).The display device (100) according to claim 15, further comprising: a driving transistor (DT) disposed in each of the plurality of subpixels (SP) between the substrate (110) and the first reflective electrode (RE1); and an insulating layer (114b) disposed between the driving transistor (DT) and the first reflective electrode (RE1), wherein the first reflective electrode (RE1) is electrically connected to the driving transistor (DT) through a first contact hole (CH1) of the insulating layer (114b), and wherein the first contact hole (CH1) overlaps the portion of the first reflective electrode (RE1) that does not overlap the first connection electrode (CE1).The display device (100) according to any one of claims 1 to 16, further comprising: a plurality of data lines (DL) extending on the substrate (110) in a column direction, wherein the plurality of pixel regions (UPA) overlap a region in which the plurality of data lines (DL) are arranged.A display device (100) comprising: a substrate (110) having a first subpixel (SP) and a second subpixel (SP) adjacent to the first subpixel (SP) thereon; a first light emitting element (120) included in the first subpixel (SP), the first light emitting element (120) comprising: a first electrode; and a second electrode adjacent to the first electrode; a second light emitting element (120) included in the second subpixel (SP); a thin film transistor electrically connected to the second light emitting element in the second subpixel (SP); a reflective electrode between the thin film transistor and the second light emitting element (120) in the second subpixel (SP), the reflective electrode electrically connecting the thin film transistor and the second light emitting element (120); a connection electrode extending from the first subpixel (SP) to the second subpixel (SP), the connection electrode being electrically connected to one of the first electrode and the second electrode of the first light emitting element (120); and a repair line (WRL) having a first end and a second end opposite to the first end, the first end of the repair line (WRL) extending from the connection electrode in the first subpixel (SP) and the second end of the repair line (WRL) extending toward the second subpixel (SP), the second end of the repair line (WRL) overlapping the reflective electrode in the second subpixel (SP) in a plan view.The display device (100) according to claim 18, wherein the repair line (WRL) extends continuously and continuously from the connection electrode and is disposed on a same layer as the connection electrode.The display device (100) according to claim 18, wherein the repair line (WRL) extends from the connection electrode and is disposed on a layer other than the connection electrode, and wherein the repair line (WRL) is located between the connection electrode and the reflective electrode.The display device (100) according to any one of claims 18 to 20, wherein the repair line (WRL) is entirely made of a light transmissive conductive material.The display device (100) according to any one of claims 18 to 21, wherein the first subpixel (SP) and the second subpixel (SP) are a pair of subpixels (SP) of a same type.The display device (100) according to any one of claims 18 to 22, wherein the repair line (WRL) is configured to be electrically and directly connected to the reflective electrode of the second subpixel (SP) during a repair operation.The display device (100) according to any one of claims 18 to 22, wherein during a repair operation, the repair line (WRL) is electrically and directly connected to the reflective electrode of the second subpixel (SP) and operatively connected to the thin film transistor of the second subpixel (SP) such that the first light emitting element (120) is operated based on the thin film transistor of the second subpixel (SP).

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