SCENE GENERATION WITH NEURAL RADIATION FIELDS

Abstract

Devices, systems, and methods for generating an image of an environment are disclosed. In at least one embodiment, one or more neural networks are used to identify one or more static and dynamic features of the environment, which are used to generate a representation of the environment.

Description

TECHNICAL AREA

[0001] At least one embodiment relates to processing resources used to generate representations of an environment. For example, at least one embodiment relates to the use of a neural network to generate images that include representations of static and / or dynamic objects. BACKGROUND

[0002] Determining a suitable way for an autonomous machine to maneuver in an environment requires significant memory, time, or computing resources when considering aspects related to the immediate operating environment. The amount of memory, time, or computing resources required by an autonomous machine to represent a dynamic environment can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows an example of a scene rendering system in accordance with at least one embodiment; Fig. 2 shows an example of the decomposition of a scene according to at least one embodiment; Fig. Figure 3 shows an example of image generation according to at least one embodiment; Fig. Figure 4 shows an example of hybrid scene generation in accordance with at least one embodiment; Fig. Figure 5 shows an example of a composition of a scene into a static and a dynamic part in accordance with at least one embodiment; Fig. Figure 6 shows an example of a decomposition into a static and a dynamic component according to at least one embodiment; Fig. Figure 7 shows an exemplary flowchart illustrating a method for generating an image in accordance with at least one embodiment; Fig. Figure 8 shows an example of a processor according to at least one embodiment; Fig. 9A illustrates a logic according to at least one embodiment; Fig. 9B illustrates a logic according to at least one embodiment; Fig. Figure 10 illustrates the training and use of a neural network according to at least one embodiment; Fig. 11 illustrates an example of a data center system according to at least one embodiment; Fig. Figure 12A shows an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 12B shows an example of camera positions and fields of view for the autonomous vehicle of Fig. 12A according to at least one embodiment; Fig. 12C is a block diagram that shows an exemplary system architecture for the autonomous vehicle of Fig. 12A illustrated according to at least one embodiment; Fig. 12D is a diagram that represents a system for communication between one or more cloud-based servers and the autonomous vehicle. Fig. 12A represents at least one embodiment; Fig. 13 is a block diagram representing a computer system according to at least one embodiment; Fig. 14 is a block diagram representing a computer system according to at least one embodiment; Fig. 15 illustrates a computer system according to at least one embodiment; Fig. 16 illustrates a computer system according to at least one embodiment; Fig. 17A illustrates a computer system according to at least one embodiment; Fig. 17B illustrates a computer system according to at least one embodiment; Fig. 17C illustrates a computer system according to at least one embodiment; Fig. Figure 17D illustrates a computer system according to at least one embodiment; Fig. 17E and Fig. 17F illustrate a common programming model according to at least one embodiment; Fig. Figure 18 illustrates exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. Figures 19A - 19B illustrate exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. Figures 20A - 20B illustrate an additional exemplary graphics processor logic according to at least one embodiment; Fig. 21 illustrates a computer system according to at least one embodiment; Fig. 22A illustrates a parallel processor according to at least one embodiment; Fig. 22B illustrates a partition unit according to at least one embodiment; Fig. Figure 22C illustrates a processing cluster according to at least one embodiment; Fig. Figure 22D illustrates a graphics multiprocessor according to at least one embodiment; Fig. Figure 23 illustrates a multi-graphics processing unit (GPU) system according to at least one embodiment; Fig. 24 illustrates a graphics processor according to at least one embodiment; Fig. 25 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. Figure 26 illustrates a deep learning application processor according to at least one embodiment; Fig. Figure 27 is a block diagram showing an exemplary neuromorphic processor according to at least one embodiment; Fig. 28 illustrates at least sections of a graphics processor according to one or more embodiments; Fig. 29 illustrates at least sections of a graphics processor according to one or more embodiments; Fig. 30 illustrates at least sections of a graphics processor according to one or more embodiments; Fig. 31 is a block diagram of a graphics processing machine of a graphics processor according to at least one embodiment; Fig. 32 is a block diagram of at least sections of a graphics processor core according to at least one embodiment; Fig. Figures 33A - 33B illustrate, according to at least one embodiment, a thread execution logic that includes an arrangement of processor elements of a graphics processor core; Fig. Figure 34 illustrates a parallel processing unit (“PPU”) according to at least one embodiment; Fig. 35 illustrates a general processing cluster (“GPC”) according to at least one embodiment; Fig. Figure 36 illustrates a storage partition unit of a parallel processing unit (“PPU”) according to at least one embodiment; Fig. Figure 37 illustrates a streaming multiprocessor according to at least one embodiment; Fig. Figure 38 is an exemplary data flow diagram for an advanced computing pipeline according to at least one embodiment; Fig. According to at least one embodiment, 39 is a system representation for an exemplary system for training, adapting, instantiating and deploying machine learning models in an advanced computing pipeline; Fig. According to at least one embodiment, 40 includes an exemplary illustration of a further developed computing pipeline for processing imaging data; Fig. 41A includes, according to at least one embodiment, an exemplary data flow diagram of a virtual instrument that supports an ultrasound device; Fig. According to at least one embodiment, 41B includes an exemplary data flow diagram of a virtual instrument that supports a CT scanner; Fig. 42A illustrates, according to at least one embodiment, a data flow diagram for a method for training a machine learning model; Fig. According to at least one embodiment, 42B is an exemplary illustration of a client-server architecture for extending annotation tools with pre-trained annotation models. Fig. Figure 43 shows the components of a system for accessing a large language model according to at least one embodiment. DETAILED DESCRIPTION

[0003] With reference to Fig. 1 is Fig. Figure 1 is an example of a scene rendering system 100 (“System 100”) according to some embodiments of the present disclosure. It is clear that this and other arrangements described herein are presented only as examples. Other arrangements and elements (e.g., machines, interfaces, functions, arrays, groupings of functions, etc.) may be used in addition to or instead of those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional units that may be implemented as single or distributed components, or in conjunction with other components, in any suitable combination and location. Various functions described herein, which are performed by units, may be executed by hardware, firmware, and / or software.For example, different functions can be performed by a processor that executes instructions stored in memory.

[0004] In at least one embodiment, a module comprises any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, a module comprises one or more circuits that are part of a larger system (e.g., an integrated circuit (IC), a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc.). In at least one embodiment, a control unit comprises any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. In at least one embodiment, the software comprises software packages, code, programming languages, drivers, instructions, instruction sets, or a combination thereof.In at least one embodiment, the hardware comprises hard-wired circuits, programmable circuits, state machine circuits, fixed-function circuits, execution units, firmware with stored instructions executed by programmable circuits, or a combination thereof.

[0005] In at least one embodiment, a logic unit comprises firmware logic, hardware logic, or a combination thereof, configured to provide any function described herein. In at least one embodiment, a logic unit comprises circuitry that is part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). In at least one embodiment, a logic unit comprises logic circuitry for implementing firmware and / or hardware.

[0006] In at least one embodiment, a motor comprises a module and / or a logic unit as further described herein. In at least one embodiment, a component comprises a module and / or a logic unit as further described herein. In at least one embodiment, a motor comprises software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function as further described herein. In at least one embodiment, a component comprises software logic, firmware logic, hardware logic, or a combination thereof, configured to provide any function as described herein. In at least one embodiment, operations performed by the hardware and / or firmware may alternatively be implemented via a software module, which may be designed as a software package, code, and / or instruction set.In at least one embodiment, a logic unit can also use part of the software to implement its function.

[0007] The system 100 can comprise a scene rendering facility 102 (“facility 102”) and / or a network 160. The facility 102 can include one or more static hash encoders 104, a dynamic hash encoder 106, a history hash encoder or flow hash encoder 108, one or more machine learning models 110, a rendering module 120, an RGB mesh 130, a gaze direction module 112, a display 122, a communications manager 124, a processor 140, and / or a storage device 150.

[0008] In at least one embodiment, the system 100 is configured to generate a representation of a three-dimensional (3D) environment (e.g., a scene). In some examples, the system 100 is configured to generate a 4D representation of an environment, wherein the representation depicts a 3D environment over a specific period of time (e.g., over time). In at least one embodiment, a 3D environment can contain one or more objects that may or may not move relative to the 3D environment. For example, a 3D environment can represent a scene that includes a roadway, one or more vehicles, one or more people, one or more animals, one or more structures, one or more environmental features, and / or one or more other objects. A generated 3D environment can be accessed by an autonomous machine (such as the vehicle 1200). Fig. 12A-D) can be used to understand and / or interact with an environment represented by the 3D environment. For example, the generated 3D environment can be used to identify and / or track one or more static and / or dynamic objects within the environment. In at least one embodiment, an autonomous machine (e.g., a vehicle, a robot, etc.) can be equipped with one or more sensors (e.g., cameras, LiDAR, etc.) and navigate within an environment (e.g., a street and / or roadway, etc.) using a 4D representation generated using measurements from the one or more sensors. Based on the sensor observations, the autonomous machine is designed to reconstruct a 4D representation of the environment. In some embodiments, the environment can be modeled separately by separately modeling static scene components (e.g.,Buildings and / or trees) and dynamic objects are generated. The representation (e.g., 3D or 4D) of the environment can be a Neural Radiance Field (NeRF). An NeRF can be generated as a volumetric representation of an environment. In some examples, an NeRF can have a space representing an environment, with each point in the space (e.g., x, y, z) assigned a radiance and / or density for each viewing direction. In at least one embodiment, an NeRF representing an environment can be used to reconstruct a 3D image of the environment using the radiance and / or density values ​​of the NeRF. For example, a NeRF representation of an environment can be represented by a function that takes as input a point in the environment (e.g., an x,y,z position), the viewing direction, and / or time, and a color value (e.g.,The system outputs an RGB value and / or a volume density for the specified point in the environment. Using the volume density and color values, a rendering of the environment represented by the NeRF can be created. In at least one embodiment, the system is configured to generate a hybrid static-dynamic world representation using a density-controlled approach to capture dynamic components and utilize observations at multiple time steps for self-monitoring of static elements of the environment. In some examples, the system is configured to predict 3D scene progressions and use them to aggregate time-shifted features.

[0009] In at least one embodiment, the system 100 is configured to generate a representation (e.g., a 3D representation) of an environment using one or more two-dimensional (2D) images. For example, a set of 2D RGB images can be used to generate a 3D representation of the environment. In at least one embodiment, a set of 2D images can contain one or more images representing the environment that were taken from different positions, so that each image in the set can have a different perspective of the environment than other images in the set. In at least one embodiment, the system 100 is configured to generate a representation (e.g., a 3D representation) of the environment using one or more 2D images and / or one or more sets of sensor measurements (e.g., LiDAR data, point clouds, etc.).

[0010] In at least one embodiment, terms such as "module" and nominalized verbs (e.g., static hash encoder 104, dynamic hash encoder 106, history hash encoder 108, rendering module 120, gaze direction module 112, communication manager 124, processor 140 and / or other terms), as used in each implementation described herein, refer in each case to any combination of software logic, firmware logic, hardware logic and / or circuitry configured to provide the functions described herein, unless the context implies otherwise or something else is explicitly stated.In at least one embodiment, software can be implemented as a software package, code, and / or instruction set or instructions, and "hardware" as used in each implementation described herein can, for example, comprise individually or in any combination hardwired circuits, programmable circuits, state machine circuits, fixed-function circuits, execution units, and / or firmware that stores instructions executed by programmable circuits. In at least one embodiment, modules can be implemented collectively or individually as circuits that are part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), and so on.

[0011] In at least one embodiment, the device 102, the static hash encoder 104, the dynamic hash encoder 106, the history hash encoder 108, the machine learning model(s) 110, the rendering module 120, the RGB mesh 130, the gaze direction module 112, the display 122, the communication manager 124, the processor 140, and / or the storage device 150 communicate with each other via a connection (not shown), such as a bus. In at least one embodiment, the processor 140 is implemented, for example, by a central processing unit (“CPU”), one or more microprocessors, one or more microcontrollers, one or more graphics processing units (“GPU(s)”), one or more data processing units (“DPU(s)”), and / or other components. In at least one embodiment, the storage device 150 comprises a memory (e.g.,one or more non-volatile, processor-readable media) that stores processor-executable instructions which, when executed by the processor 140 of the device 102, implement the static hash encoder 104, the dynamic hash encoder 106, the history hash encoder 108, the machine learning model(s) 110, the rendering module 120, the RGB mesh 130, the gaze direction module 112, the display 122, and / or the communication manager 124. In at least one embodiment, as additional, non-limiting examples, memory (e.g., one or more non-volatile, processor-readable media) is implemented, e.g., using volatile memory (e.g., dynamic random-access memory ("DRAM")) and / or non-volatile memory (e.g., a hard disk, a solid-state device ("SSD"), and / or other components).

[0012] In at least one embodiment, the communication manager 124 can include one or more components and functions for communication over one or more networks, such as network 160. In at least one embodiment, the communication manager 124 is configured to communicate over any number of the networks described herein.

[0013] In at least one embodiment, the communication manager 124 is configured to manage communications received by its respective system (e.g., requests, queries, data, etc.) and / or provided by a respective system (e.g., requests, queries, data, etc.), such as between any device 102 and / or other components that may be included in the system 100. In at least one embodiment, the communication manager 124 can manage communication within the respective system.

[0014] In at least one embodiment, the system 100 comprises one or more processors, such as the processor 140. In at least one embodiment, the system 100 comprises a different number of processors (e.g., more than one processor 140) and / or one or more other suitable components (e.g., one or more user interface components and / or one or more other components), which are not shown for clarity. In at least one embodiment, the processor 140 is a processor as described below.

[0015] In at least one embodiment, the components of system 100 communicate via one or more networks, such as network 160 and / or other network types described herein. Network 160 comprises one or more networks of any number of network types. In some examples, network 160 includes a cellular network and / or the Internet.

[0016] The machine learning model(s) 110 can include one or more components for representing a 3D environment. For example, the machine learning model(s) 110 can include one or more components for implementing one or more NeRFs that represent one or more environments over a specific period of time. In at least one embodiment, the machine learning model(s) 110 is designed to generate a scene decomposition using self-monitoring, thereby avoiding the use of ground-truth labels or pre-trained models for dynamic object segmentation or optical progression. In at least one embodiment, the machine learning model(s) 110 is designed to model dynamic element correspondences over time throughout the scene progression.In some examples, the machine learning model(s) 110 is / are designed to obtain a mutually reinforcing representation where static-dynamic decomposition and process estimation mutually benefit each other. In some examples, the machine learning model(s) 110 is / are designed to improve the semantics of scene representations by using feature lifting and distillation / separation, and to enable a range of perceptual tasks.

[0017] In at least one embodiment, the model(s) 110 is / are configured as a machine learning model(s) to decompose an environment. For example, the model(s) 110 is / are configured for machine learning to generate a hybrid spatiotemporal representation of an environment. A 4D scene can be decomposed into a static field. and a dynamic field are broken down by self-learning hash grids HS or HD They can be parameterized (e.g., with the static hash encoder 104 and / or the dynamic hash encoder 106). The decomposition into a static and a dynamic field enables a 4D representation of time-independent features. hs=Hs(x) and time-variable characteristics hd=Hd(x,t), where x = (x, y, z) is the 3D position of a query point and t denotes the time. These features can be further processed using one or more MLPs (g s and g d ) in g s and g d be transformed and used to predict a point density σ s and σ d be used: gs,σs=gs(Hs(x)) and gd,σd=gs(Hd(x,t)).

[0018] In at least one embodiment, the machine learning model(s) 110 is / are configured to access a position (x, y, z) in an environment, a viewing direction (θ, ϕ), and / or a time specification (t). In at least one embodiment, the machine learning model(s) 110 is / are configured to output radiation, color, and / or density corresponding to one or more points in the environment (e.g., specified by the input position). In some examples, the machine learning model(s) 110 may include one or more multilayer perceptrons (MLPs) configured to receive features associated with the environment and to predict one or more attributes associated with those features, such as density and / or RGB values ​​for one or more points in the environment.For example, an MLP can receive features from the static hash encoder 104 and predict one or more static geometric features and / or static density values ​​associated with the environment. As another example, an MLP can receive features from a dynamic hash encoder 106 and predict one or more dynamic geometric features and / or dynamic density values ​​associated with the environment. The MLPs can use separate heads for color, sky, and / or shadow predictions. In at least one embodiment, the MLPs can have a color head, MLP. color , exhibit, the (g s , d) and (g d , d) receives as input and a color c s and c d outputs per point for static and dynamic elements, where d is the normalized viewing direction. In at least one embodiment, the MLPs can have a separate celestial head, MLP skyto use to predict the color of the sky from a viewing direction γ(d) embedded in a frequency, where γ(·) is a frequency-based positional embedding function. In at least one embodiment, the MLPs can be used to predict a shadow head, MLP shadow , to represent shadows corresponding to one or more dynamic objects. The shadow head can output a scalar ρ ∈ [0,1] for dynamic objects and modulate a color intensity predicted by the static field, where c s = MLP color (G s , γ(d)), c d = MLP color (G d , γ(d)), c sky = MLP sky (γ(d)), and ρ = MLP shadow (G d). In some examples, the MLPs can comprise one or more layers (e.g., 2 layers). In at least one embodiment, the static geometric features predicted by the MLP associated with the static hash encoder 104 can be made available to the MLP associated with the dynamic hash encoder 106, so that the static features can be used to generate one or more dynamic geometric features and / or one or more dynamic density values. Sharing the static geometric features with the MLP corresponding to the dynamic hash encoder 106 can reduce the number of parameters used by the dynamic hash encoder 106.

[0019] In at least one embodiment, the machine learning model(s) 110 can be used to perform scene history estimation to capture one or more correspondences between dynamic objects and / or to provide a connection through which time-shifted features can be aggregated. In at least one embodiment, the machine learning model(s) 110 can use a scene history field that contains a hash grid. V:=Hv(x,t) and a course predictor MLP v A process field can include a spatiotemporal query point (x, t) on a process vector v ∈ ℝ 3 map that transforms the query point into its position in the next time step, given by: v=MLPv(Hv(x,t)), x' = x + v . In some examples, a trend field can represent both a forward trend v fas well as a backward-directed course v b predicting, resulting in a 6-dimensional progression vector for each point. In at least one embodiment, the linkage provided by a predicted scene progression can be used to integrate features from nearby time steps using weighted summation: g'd=0.25⋅gd(Hd(x+vb,t−1))+0.5⋅gd(Hd(x,t))+0.25⋅gd(Hd(x+vf,t+1)). In some examples, g' d This is used by default when a history field is enabled. In at least one embodiment, feature aggregation is used to link a history field with scene reconstruction losses (e.g., RGB losses) for monitoring. In at least one embodiment, feature aggregation is designed to denoise temporal attributes to make more accurate predictions.

[0020] In at least one embodiment, the machine learning model(s) 110 comprises one or more static hash encoders 104, dynamic hash encoders 106 and / or flow hash encoders 108.

[0021] The static hash encoder 104 can contain one or more components configured to store and / or retrieve one or more coded features corresponding to a 3D environment. In at least one embodiment, the static hash encoder 104 can be queried to retrieve one or more static features (e.g., from the storage device 150) of a static field. For example, a query with 3D coordinates (e.g., x, y, z) can be sent to the static hash encoder 104 to cause it to use one or more hash functions and / or hash tables to retrieve static features corresponding to static aspects of the environment. Once the static features (e.g. feature codings) have been retrieved by the static hash encoder 104, they can be made available to one or more MLPs of the model(s) 110 for machine learning.

[0022] The dynamic hash encoder 106 can include one or more components configured to store and / or retrieve one or more coded features corresponding to the 3D environment. In at least one embodiment, the dynamic hash encoder 106 can be queried to retrieve one or more dynamic features (e.g., from the storage device 150) of a dynamic field. For example, a query containing 4D coordinates (e.g., x, y, z, t) can be submitted to the dynamic hash encoder 106 to cause it to use one or more hash functions and / or hash tables to retrieve dynamic features corresponding to dynamic aspects of the environment. Once the dynamic features (e.g. feature codings) have been retrieved by the dynamic hash encoder 106, they can be provided to one or more MLPs of the model(s) 110 for machine learning.

[0023] The history hash encoder or flow hash encoder 108 can contain one or more components configured to capture correspondences between dynamic objects and to link time-shifted features (e.g., dynamic features that occur over multiple time steps). In at least one embodiment, the history hash encoder 108 can be queried to retrieve one or more history vectors (e.g., history or flow) of a history field that transform a point specified by the provided query into its position in the next time step. In at least one embodiment, the history hash encoder 108 is configured to generate forward-facing and / or backward-facing history vectors. In at least one embodiment, one or more history vectors generated by the history hash encoder 108 can be used to determine one or more dynamic features (e.g.,to aggregate the data generated by the dynamic hash encoder 106. Once the history vectors have been retrieved by the history hash encoder 108, they can be fed to one or more MLPs of the model(s) 110 for machine learning.

[0024] The RGB mesh 130 can contain one or more components designed to generate one or more color values ​​associated with the environment. For example, the RGB mesh 130 is designed to generate one or more static color values ​​associated with static features of the environment and / or one or more dynamic color values ​​associated with dynamic features of the environment. The RGB mesh 130 can use one or more static geometric features, one or more dynamic geometric features, and / or one or more viewing directions to generate one or more static color values ​​and / or one or more dynamic color values. The color values ​​generated by the RGB mesh 130 can be used to render one or more images (e.g., with the rendering module 120). The RGB mesh 130 can contain a static RGB 132 and a dynamic RGB 134.Static RGB 132 can contain one or more components designed to access one or more static geometric features and / or one or more viewing directions to generate one or more static color values ​​associated with one or more static features of the environment, which can be used to generate a rendering of the environment. Dynamic RGB 134 can contain one or more components designed to access one or more dynamic geometric features and / or one or more viewing directions to generate one or more dynamic color values ​​associated with one or more dynamic features of the environment, which can be used to generate a rendering of the environment.

[0025] The gaze direction module 112 can contain one or more components configured to determine one or more gaze directions (e.g., viewing directions) that can be provided to the RGB mesh 130. In at least one embodiment, a gaze direction can represent a direction from which points in a NeRF are viewed. For example, for a NeRF representing a scene in which an autonomous vehicle travels along a roadway, a gaze direction can correspond to a direction that corresponds to the viewing angle or position of the autonomous vehicle. The gaze direction module 112 can determine the gaze direction, which is represented as a vector. In some examples, the gaze direction is based on the position of an object. For example, the position of an autonomous machine can be used to calculate the gaze direction on the environment corresponding to the autonomous machine.

[0026] The rendering module 120 can contain one or more components designed to render one or more images of the environment. The rendering module 120 can generate one or more images of the environment using one or more color values ​​and / or one or more density values ​​associated with one or more points in the environment. In at least one embodiment, the rendering module 120 can use static density values, static color values, dynamic density values, and / or dynamic color values ​​to generate one or more images of the environment.For example, the rendering module 120 can receive one or more static color values ​​from the static RGB 132, one or more static density values ​​from the machine learning model(s) 110, one or more dynamic color values ​​from the dynamic RGB 134, and / or one or more dynamic density values ​​from the machine learning model(s) 110 to render one or more images that can be output for display by one or more devices, such as the display 122. In at least one embodiment, the rendering module 120 uses one or more density-based weights to combine values ​​from the static and dynamic fields. c=δsσs+σd⋅(1−ρ)⋅cs+σdσs+σd⋅cd. When rendering a pixel, the rendering module can take 120 K discrete samples {x1, ..., x K Use along its ray to estimate an integral of the color. The output values ​​can be given by: C^=∑i=1KTiαici+(1−∑i=1KTiαi)csky, where Ti=∏j=1i−1(1−αj) the accumulated transmission is and α i = 1 - exp (-σ i (x i+1 - x i ) the piecewise opacity. In at least one embodiment, the rendering module 120 can regulate the dynamic density by adjusting the expected dynamic density σ. d minimizes what the dynamic field can cause to generate density values ​​as needed: Lσd=E(σd).

[0027] Fig. Figure 2 is an example of a scene decomposition 200 according to at least one embodiment. In at least one embodiment, the scene decomposition 200 comprises one or more NeRFs 206 representing an environment. The NeRFs 206 may contain one or more representations of the environment, including one or more color, density, and / or radiance values ​​for one or more viewing directions from one or more points in the NeRFs 206 representing points and / or objects of the environment. Using one or more components of the system 100 of Fig. For example, the environment of a processor 140, a machine learning model 110, and / or an RGB mesh 130 can be decomposed into a static component 204 and / or a dynamic component 202. The static component 204 can contain one or more static (e.g., non-moving) sections of the environment represented by the NeRFs 206. For example, the static component 204 can be an image showing non-moving sections of the environment represented by the NeRFs 206. The dynamic component 202 can contain one or more dynamic (e.g., moving) sections of the environment represented by the NeRFs 206. For example, the dynamic component 202 can be an image showing moving sections of the environment represented by the NeRFs 206.

[0028] Fig. Figure 3 is an example of an image generation device 300 in accordance with at least one embodiment. The image generation device 300 can use one or more components which, in conjunction with Fig. 1 are described to generate one or more images, e.g., a predicted composite RGB image 304. The image generation 300 can access one or more machine learning models, such as the machine learning model(s) 110 of Fig. 1, to decompose a NeRF into static components and / or dynamic components. For example, the decomposed static scene 306 represents static features (e.g., trees, roadway, walls, structures, etc.) of a NeRF that are associated with one or more captured images, such as the ground-truth RGB image 302. As another example, the decomposed dynamic scene 308 represents dynamic features (e.g., moving vehicles) of the NeRF that are associated with the one or more captured images, such as the ground-truth RGB image 302. In at least one embodiment, the decomposed static scene 306 and the decomposed dynamic scene 308 can be mixed or otherwise combined to generate a predicted composite RGB image 304.

[0029] Fig. Figure 4 is an example of generating a hybrid scene 400 in accordance with at least one embodiment. In at least one embodiment, Fig. 4 in conjunction with the system 100 of Fig. 1 described. One or more components of Fig. 1, such as processor 140, can be used to perform the generation 400 of a hybrid scene. In at least one embodiment, one or more 3D coordinates 402 of an environment are sent as a query to the hash encoder 404 (e.g., the static hash encoder 104 of Fig. 1) transmitted and used to retrieve one or more feature encodings 406 associated with static features of a NeRF. In some examples, the encodings 406 can be provided to the MLP 408, which is configured to use the encodings 406 to predict a static density 412 and / or one or more static features 410 corresponding to the encoding 406. In some embodiments, the static features 410 can be provided to the static RGB mesh 414 (e.g., the static RGB 132 of Fig. 1) be provided which is designed to use the static features 410 and one or more viewing directions 418 to generate one or more static color values ​​416 that are assigned to the environment (e.g. a scene).

[0030] In at least one embodiment, one or more 4D parameters 422 of the environment are sent as a query to a hash encoder 424 (e.g., the dynamic hash encoder 106 of Fig. 1) transmitted and used to retrieve one or more feature encodings 426 associated with dynamic features represented in the NeRF. In some examples, the encodings 426 can be provided to the MLP 428, which is configured to use the encodings 426 to predict a dynamic density 432 and / or one or more dynamic features 430 corresponding to the encoding 426. In some embodiments, the dynamic features 430 can be provided to the dynamic RGB mesh 434 (e.g., the dynamic RGB 134 of Fig. 1) be provided which is designed to use the dynamic features 430 and one or more viewing directions 418 to generate one or more dynamic color values ​​436 associated with the environment (e.g., a scene). In at least one embodiment, a renderer 420 (e.g., the rendering module 120 of) uses Fig. 1) the static density 412, the static color values ​​416, the dynamic density 432 and / or the dynamic color values ​​436 to generate a composite image of the environment. In at least one embodiment, the renderer 420 is configured to generate a composite RGB image, such as the predicted composite RGB image 304 from Fig. 4.

[0031] Fig. Figure 5 is an example of a composition 500 of a static and a dynamic scene in accordance with at least one embodiment. In at least one embodiment, Fig. 5 in conjunction with the system 100 of Fig. 1 described. One or more components of Fig. 1, such as processor 140, can be used to perform the composition 500 of a static and a dynamic scene. In at least one embodiment, one or more 3D coordinates 502 of an environment are sent as a query to a hash encoder 504 (e.g., the static hash encoder 104 of Fig. 1) transmitted and used to retrieve one or more feature encodings 506 associated with static features of a NeRF. In some examples, the encodings 506 can be provided to an MLP 508 configured to use the encodings 506 to predict a static density 512 and / or one or more static features 510 corresponding to the encoding 506. In some embodiments, the static features 510 can be provided to an RGB mesh 534 (e.g., the RGB mesh 130 of Fig. 1) supplied, which is designed to provide the static features 510 and one or more viewing directions 518 (e.g. from the viewing direction module 112 of Fig. 1) to use to create one or more color values ​​536 associated with the environment (e.g., a scene).

[0032] In at least one embodiment, one or more 4D parameters 522 of the environment are sent as a query to a hash encoder 524 (e.g., the dynamic hash encoder 106 of Fig. 1) transmitted and used to retrieve one or more feature encodings 526 associated with dynamic features represented in a NeRF. In some examples, the encodings 526 can be provided to the MLP 528, which is configured to use the encodings 526 to predict a dynamic density 532 and / or one or more dynamic features 530 corresponding to the encoding 526. In some embodiments, the dynamic features 530 can be assigned to an RGB mesh 534 (e.g., the RGB mesh 130 of Fig. 1) be provided which is designed to use the dynamic features 530 and one or more viewing directions 518 to generate one or more color values ​​536 that are associated with the environment (e.g., a scene). In at least one embodiment, the renderer 520 (e.g., the rendering module 120 of Fig. 1) configured to use the static density 512, the dynamic density 532 and / or the color values ​​536 to generate a composite image of the environment. In at least one embodiment, the renderer 520 is configured to generate a composite RGB image, such as the predicted composite RGB image 304 from Fig. 4, to generate.

[0033] Fig. Figure 6 is an example of a decomposition 600 of a scene into a static and a dynamic part in accordance with at least one embodiment. In at least one embodiment, the decomposition 600 of a scene into a static and a dynamic part is performed in conjunction with the system 100 of Fig. 1 described. In at least one embodiment, a specific temporal query 602, which is associated with a 3D scene, is input into a static field 604, a dynamic field 606, and / or a history field 608. In some examples, the query 602 can contain one or more coordinates (e.g., x, y, z) and / or one or more time steps (e.g., t). In at least one embodiment, the static field 604 is configured to (e.g., using the static hash encoder 104 of Fig. 1) To generate one or more static features 610 that represent one or more static features within a scene or environment. In at least one example, the static field 604 is configured to generate a static density 630. The static features 610 can be assigned to a color head 620 (e.g., one or more MLPs and / or an RGB mesh 130). Fig. 1) be supplied.

[0034] In at least one embodiment, the history field 608 is configured to receive the query 602 and generate one or more histories 614. In at least one embodiment, the history field 608 is configured to use a hash encoder to generate a forward-facing and / or a backward-facing history. The one or more histories 614 generated by the history field 608 can be fed to the dynamic field 606. In at least one embodiment, the dynamic field 606 is configured to receive the query 602 and / or the histories 614 as input and to (e.g., using the dynamic hash encoder 106) Fig. 1) to generate one or more dynamic features 612. The dynamic features 612 can be one or more closely related temporal features (e.g., gdt−1, gdt, gdt+1 The dynamic features 612 can be provided to an aggregator 616, which is configured to generate temporally aggregated features 618. The aggregated features 618, the static features, and / or the viewing direction 622 can be provided to a color head 620, which is configured to generate a static color 632 and / or a dynamic color 634. In at least one embodiment, the aggregated features 618 are used to generate one or more dynamic density values ​​638.

[0035] In at least one embodiment, a sky head 624 is configured to receive the viewing direction 622 as input and to generate a sky color value 628. In at least one embodiment, the aggregated features 618 are fed to a shadow head 626, which is configured to generate a shadow value 636. In at least one embodiment, the sky color 628, the static density 630, the static color 632, the dynamic color 634, the shadow value 636, and / or the dynamic density 638 can be used to render a reconstructed scene (e.g., using the rendering module 120 of Fig. 1) to render.

[0036] In at least one embodiment, each block of the method 700 described herein comprises a computational procedure that can be performed using any combination of hardware, firmware, and / or software. For example, in at least one embodiment, various functions can be performed by a processor executing instructions stored in memory. In at least one embodiment, the method 700 can also be executed in the form of computer-usable instructions stored on computer storage media. In at least one embodiment, the method 700 can be provided by a standalone application, a service, a hosted service (standalone or in combination with another hosted service), or a plug-in for another product, to name just a few examples. In at least one embodiment, the method 700 is also described by way of example with respect to the system 100 of Fig. 1 described. In at least one embodiment, these methods can additionally or alternatively be performed by any system or any combination of systems, including, but not limited to, the systems described herein.

[0037] Fig. Figure 7 is a flowchart showing a method 700 for generating an image according to at least one embodiment. Block 702 of the method 700 involves accessing a 3D representation of an environment. For example, a NeRF of model(s) 110 can be used for machine learning of Fig. 1. Represent an environment that includes one or more objects.

[0038] In at least one embodiment, method 700 in block 704 includes determining one or more static features and one or more dynamic features of the 3D representation. For example, the static hash encoder 104 of Fig. 1 can be used to retrieve one or more static features, and the dynamic hash encoder 106 of Fig. 1 can be used to retrieve one or more dynamic features.

[0039] In at least one embodiment, the method 700 in block 706 includes determining one or more static density values ​​using the static features determined in block 704. For example, the machine learning model(s) 110 can use the static features and one or more MLPs to predict a static density value.

[0040] In at least one embodiment, the method 700 in block 708 includes determining one or more dynamic density values ​​using the dynamic features determined in block 704. For example, the machine learning model(s) 110 can use the dynamic features and one or more MLPs to predict a dynamic density value.

[0041] In at least one embodiment, the method 700 in block 710 includes a prediction of one or more color values. For example, the RGB network 130 can use the dynamic features and the static features to predict the one or more color values.

[0042] In at least one embodiment, the method 700 in block 712 comprises generating one or more images using the static density values, the dynamic density values, and the color values. For example, the rendering module 120 of Fig. 1. Use the color values ​​predicted by the RGB network 130 and the density values ​​determined by the machine learning model(s) 110 to generate an output image that can be displayed using the display 122. In at least one embodiment, the method 700 can be terminated according to block 712.

[0043] Fig. Figure 8 shows an example 800 of a processor according to at least one embodiment. In at least one embodiment, a processor 802 performs one or more methods as described with reference to the Fig. 1-7 are described to capture a three-dimensional (3D) representation of an environment; to determine one or more static features and one or more dynamic features of the 3D representation; to determine one or more static density values ​​using the one or more static features; to determine one or more dynamic density values ​​using the one or more dynamic features; and to generate one or more images based on the one or more static density values ​​and the one or more dynamic density values.In at least one embodiment, the processor 802 performs operations to acquire a three-dimensional (3D) representation of an environment; to determine one or more static features and one or more dynamic features of the 3D representation; to determine one or more static density values ​​using the one or more static features; to determine one or more dynamic density values ​​using the one or more dynamic features; and to generate one or more images based on the one or more static density values ​​and the one or more dynamic density values.

[0044] In at least one embodiment, the processor 802 comprises one or more processors such as those used in conjunction with the Fig. as described in Figures 18-30. In at least one embodiment, the processor 800 is any suitable processing unit or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, or PPUs. In at least one embodiment, the processor 802 comprises a static feature module 804, a dynamic feature module 806, and / or a rendering module 808. In at least one embodiment, the static feature module 804, the dynamic feature module 806, and / or the rendering module 808 are part of the processor 802, for example, as described in Figures 18-30. Fig. 8 shown, or part of one or more other processors. In at least one embodiment, the static feature module 804, the dynamic feature module 806, and / or the rendering module 808 are distributed across multiple processors that communicate via a bus, a network, by writing to shared memory, or any suitable communication method, such as those described in the Fig. 18-30 described.

[0045] In at least one embodiment, the static feature module 804 comprises circuits that cause one or more static features to be determined and used to predict one or more density and / or color values ​​associated with static objects represented in a 3D representation of an environment, e.g., as described in the Fig. 1-7 is shown.

[0046] In at least one embodiment, the module 806 for dynamic features comprises circuits that cause one or more dynamic features to be determined and used to predict one or more density and / or color values ​​associated with dynamic objects represented in a 3D representation of an environment, e.g., as described in the Fig. 1-7 is shown.

[0047] In at least one embodiment, the rendering module 808 comprises circuits that cause one or more images to be rendered using one or more color values ​​and / or density values, e.g., as described in the Fig. 1-7 is shown. LOGIC

[0048] Fig. Figure 9A illustrates the logic 915, which, as described herein, can be used in one or more settings to perform operations such as those discussed herein according to at least one embodiment. In at least one embodiment, the logic 915 is used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, the logic 915 is inference and / or training logic. Details of the logic 915 are given below in conjunction with the Fig. 9A and / or 9B specified. In at least one embodiment, logic refers to any combination of software logic, hardware logic and / or firmware logic to provide the functions or operations described herein, wherein the logic may be implemented collectively or individually as a circuit that is part of a larger system, for example, an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0049] In at least one embodiment, the logic 915 can, without limitation, comprise a code and / or data memory 901 for storing forward and / or output weights and / or input / output data and / or other parameters for configuring neurons or layers of a neural network that is trained in aspects of one or more embodiments and / or used for inference. In at least one embodiment, the logic 915 can comprise or be coupled to a code and / or data memory 901 for storing graph code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code, such as...Graph code, based on a neural network architecture to which the code corresponds, weights or other parameter information in processor ALUs. In at least one embodiment, the code and / or data memory 901 stores weight parameters and / or input / output data of each layer of a neural network that is trained during the forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments, or used in conjunction with one or more embodiments. In at least one embodiment, each part of the code and / or data memory 901 may be encompassed by another on-chip or off-chip data memory, including the L1, L2, or L3 cache of a processor or system memory.

[0050] In at least one embodiment, each part of the code and / or data memory 901 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or code and / or data memory 901 can be a cache memory, a dynamic randomly addressable memory (“DRAM”), a static randomly addressable memory (“SRAM”), a non-volatile memory (e.g., flash memory), or another type of memory.In at least one embodiment, the decision as to whether the code and / or code and / or data memory 901 is internal or external to a processor, or comprises DRAM, SRAM, Flash or another type of memory, may depend on whether memory is available on or off the chip, on the latency requirements of the training and / or inference functions being performed, on the size of the data stacks used in inferencing and / or training a neural network, or on a combination of these factors.

[0051] In at least one embodiment, the logic 915 may, without limitation, comprise a code and / or data memory 905 for storing backward and / or output weighting and / or input / output data corresponding to neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data memory 905 stores weighting parameters and / or input / output data of each layer of a neural network that is trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments.In at least one embodiment, the logic 915 may include or be coupled to a code and / or data memory 905 to store a graph code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0052] In at least one embodiment, a code, such as a graph code, based on a neural network architecture to which the code corresponds, causes weight or other parameter information to be loaded into processor ALUs. In at least one embodiment, any part of the code and / or data memory 905 may comprise another on-chip or off-chip data memory, including the L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any part of the code and / or data memory 905 may be contained internally or externally in one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data memory 905 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or data storage 905 is internal or external to a processor, or whether it comprises, for example, DRAM, SRAM, Flash or another type of memory, may depend on the available memory on or off the chip, on the latency requirements of the training and / or inference functions being performed, on the batch size of the data used in inferencing and / or training a neural network, or on a combination of these factors.

[0053] In at least one embodiment, the code and / or data memory 901 and the code and / or data memory 905 can be separate memory structures. In at least one embodiment, the code and / or data memory 901 and the code and / or data memory 905 can be a combined memory structure. In at least one embodiment, the code and / or data memory 901 and the code and / or data memory 905 can be partially combined and partially separate. In at least one embodiment, each part of the code and / or data memory 901 and the code and / or data memory 905 can be encompassed by another on-chip or off-chip data memory, including the L1, L2, or L3 cache of a processor or system memory.

[0054] In at least one embodiment, the logic 915 can, without limitation, comprise one or more arithmetic logic unit(s) (“ALU(s)”) 910, including integer and / or floating-point units, to perform logical and / or mathematical operations that can be performed at least partially on a training and / or inference code (e.g., graph code), the result of which can generate activations (e.g., output values ​​of layers or neurons within a neural network) stored in an activation memory 920, which are functions of input / output and / or weighting parameter data stored in code and / or data memory 901 and / or code and / or data memory 905.In at least one embodiment, activations stored in an activation memory 920 are generated according to linear algebraic and / or matrix-based mathematics, which are executed by ALU(s) 910 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data memory 905 and / or data memory 901 are used as operands together with other values, such as default values, gradient information, pulse values ​​or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 905 or code and / or data memory 901 or in another memory on or off the chip.

[0055] In at least one embodiment, ALU(s) 910 are contained within one or more processors or other hardware logic devices or circuits, while in another embodiment, ALU(s) 910 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, the ALU(s) 910 may be contained within the execution units of a processor or otherwise in a group of ALUs that the execution units of a processor can access, either within the same processor or distributed across different processors of different types (e.g., central processing units, graphics processing units, fixed functional units, etc.).In at least one embodiment, the code and / or data memory 901, the code and / or data memory 905, and the activation memory 920 can share a processor or other hardware logic device or circuit, while in another embodiment they can be located in different processors or other hardware logic devices or circuits, or in a combination of identical and different processors or other hardware logic devices or circuits. In at least one embodiment, any part of the activation memory 920 can be contained in another on-chip or off-chip data memory, including the L1, L2, or L3 cache memory or system memory of a processor.Furthermore, the code for inference and / or training can be stored together with other code that a processor or other hardware logic or circuitry can access and that is fetched and / or processed using the fetch, decode, scheduling, execution, elimination, and / or other logic circuitry of a processor.

[0056] In at least one embodiment, the activation memory 920 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or another type of memory. In at least one embodiment, the activation memory 920 can be located wholly or partially inside or outside one or more processors or other logic circuits. In at least one embodiment, the decision as to whether the activation memory 920 is located, for example, inside or outside a processor, or whether it comprises DRAM, SRAM, flash memory, or another type of memory, can depend on the available on-chip or off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferencing and / or training a neural network, or a combination of these factors.

[0057] In at least one embodiment, the in Fig. The logic 915 shown in Figure 9A can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as Google’s TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® processor (e.g., “Lake Crest”). In at least one embodiment, the logic shown in Figure 9A can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as Google’s TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® Processor (e.g., “Lake Crest”). Fig. 9A shows that the logic 915 can be used in conjunction with hardware of the central processing unit (“CPU”), the graphics processing unit (“GPU”) or other hardware, such as field-programmable gate arrays (“FPGAs”).

[0058] In at least one embodiment, at least one in Fig. 9A Component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 9A is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 9A selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0059] Fig. Figure 9B shows the logic 915 according to at least one embodiment. In at least one embodiment, the logic 915 is an inference and / or training logic. In at least one embodiment, the logic 915 can, without limitation, comprise hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the logic 915 can be further defined by the following: Fig. The logic 915 shown in Figure 9B can be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® processor (e.g., "Lake Crest"). In at least one embodiment, the logic shown in Figure 9B can be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® Processor ... Fig. The logic 915 shown in Figure 9B is used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, the logic 915 comprises, without limitation, a code and / or data memory 901 and a code and / or data memory 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including default values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, the logic 915 is further described in Figure 9B. Fig. As shown in Figure 9B, each code and / or data store 901 and each code and / or data store 905 is associated with a dedicated computing resource, such as computing hardware 902 and computing hardware 906, respectively. In at least one embodiment, each of the computing hardware 902 and computing hardware 906 comprises one or more ALUs that execute mathematical functions, such as linear algebraic functions, only on information stored in the code and / or data store 901 and in the code and / or data store 905, respectively, with the result being stored in the activation memory 920.

[0060] In at least one embodiment, each of the code and / or data stores 901 and 905 and the corresponding computing hardware 902 and 906, respectively, corresponds to different layers of a neural network, such that the resulting activation from a "memory / computing pair 901 / 902" consisting of code and / or data store 901 and computing hardware 902 is provided as input for a next "memory / computing pair 905 / 906" consisting of code and / or data store 905 and computing hardware 906, in order to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / computing pairs 901 / 902 and 905 / 906 can correspond to more than one layer of the neural network. In at least one embodiment, additional memory / computing pairs (not shown) can be included sequentially or in parallel with the memory / computing pairs 901 / 902 and 905 / 906 in the logic 915.

[0061] In at least one embodiment, at least one in Fig. 9B component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 9B is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 9B selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described. TRAINING AND USE OF A NEURAL NETWORK

[0062] Fig. Figure 10 shows, according to at least one embodiment, the training and use of a deep neural network. In at least one embodiment, the untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, the training framework 1004 is a PyTorch framework, while in other embodiments, the training framework 1004 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 1004 trains an untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008.In at least one embodiment, the weights can be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training can be supervised, partially supervised, or unsupervised.

[0063] In at least one embodiment, an untrained neural network 1006 is trained using supervised learning, wherein the training dataset 1002 comprises an input paired with a desired output for that input, or wherein the training dataset 1002 comprises an input paired with a known output, and an output of the neural network 1006 is manually evaluated. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner and processes inputs from the training dataset 1002 and compares the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the errors are then propagated back by the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts the weights that control the untrained neural network 1006.In at least one embodiment, the training framework 1004 includes tools to monitor how well the untrained neural network 1006 converges to a model, such as the trained neural network 1008, that is capable of generating correct answers based on input data, such as a new dataset 1012, as shown in the result 1014. In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine an output of the untrained neural network 1006 using a loss function and an adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 achieves a desired accuracy.In at least one embodiment, the trained neural network 1008 can then be used to implement any number of machine learning operations.

[0064] In at least one embodiment, the untrained neural network 1006 is trained using unsupervised learning, wherein the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised training dataset 1002 comprises input data without associated execution data or "ground truth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and determine how individual inputs relate to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 1008, which is capable of performing operations useful in reducing the dimensionality of a new dataset 1012.In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which makes it possible to identify data points in a new data set 1012 that deviate from normal patterns of the new data set 1012.

[0065] In at least one embodiment, semi-supervised learning can be used, which is a method in which the training dataset 1002 comprises a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, for example, by transferred learning methods. In at least one embodiment, the incremental learning enables a trained neural network 1008 to adapt to a new dataset 1012 without forgetting the knowledge imparted to the trained neural network during the initial training.

[0066] In at least one embodiment, the training framework 1004 is a framework processed in conjunction with a software development toolkit such as an OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation in Santa Clara, CA. In at least one embodiment, OpenVINO includes or uses Logic 915 to perform operations described herein. In at least one embodiment, a system-on-a-chip (SoC), integrated circuit, or processor uses OpenVINO to perform operations described herein.

[0067] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), feedback and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.

[0068] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object recognition, face recognition, speech recognition, pose estimation (e.g., of people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, coloring, and / or variations thereof.

[0069] In at least one embodiment, OpenVINO comprises one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, a model optimizer is a command-line tool that facilitates the transitions between training and deploying neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variants thereof. In at least one embodiment, a model optimizer creates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces the number of layers in a model.In at least one embodiment, a model optimizer removes the layers of a model that are used for training. In at least one embodiment, a model optimizer performs various operations on neural networks, such as changing the inputs to a model (e.g., changing the size of the inputs to a model), changing the size of the inputs to a model (e.g., changing the stack size of a model), changing a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0070] In at least one embodiment, OpenVINO comprises one or more software libraries for inferencing, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or another suitable library in a programming language. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes to derive input data and generate one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, specify input and / or output formats, and / or execute a model on one or more devices.

[0071] In at least one embodiment, OpenVINO offers various options for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that use one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute a program and / or sections of a program on different devices. In at least one embodiment, OpenVINO provides various software functions to, for example, execute a first section of the code on a CPU and a second section of the code on a GPU and / or FPGA.In at least one embodiment, OpenVINO provides various software functions to run one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0072] In at least one embodiment, OpenVINO exhibits various functionalities similar to those of a CUDA programming model, such as various model operations for neural networks associated with frameworks like TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0073] In at least one embodiment, at least one in Fig. 10. The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 10 is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 10 select at least one aspect relating to the model(s) 110 for machine learning, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described. DATA CENTER

[0074] Fig. Figure 11 shows an example of a data center 1100 in which at least one embodiment can be used. In at least one embodiment, the data center 1100 has a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0075] In at least one embodiment, as described in Fig. As shown in Figure 11, the data center infrastructure layer 1110 can include a resource orchestrator 1112, clustered compute resources 1114 and node compute resources (“node CRs”) 1116(1)-1116(N), where “N” is a positive integer (which may be a different positive integer “N” than the one used in other figures). In at least one embodiment, the node CRs 1116(1)-1116(N) can include any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processing units, etc.), storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid-state or hard disk drives), network input / output devices (“NW I / O”), network switches, virtual machines (“VMs”), power supply modules, and cooling modules, etc. In at least one embodiment, one or more node CRs can be among the node CRss 1116(1)-1116(N) refers to a server that has one or more of the computing resources mentioned above.

[0076] In at least one embodiment, the grouped compute resources 1114 can comprise separate groupings of node CRs housed in one or more racks (not shown), or many racks housed in data centers at different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within the grouped compute resources 1114 can comprise grouped compute, network, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs comprising CPUs or processors can be grouped in one or more racks to provide compute resources to support one or more workloads.In at least one embodiment, one or more racks can also include any number of power supply modules, cooling modules and network switches in any combination.

[0077] In at least one embodiment, the resource orchestrator 1112 can configure or otherwise control one or more nodes CRs 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, the resource orchestrator 1112 can include a software design infrastructure (“SDI”) management unit for the data center 1100. In at least one embodiment, the resource orchestrator can include hardware, software, or a combination thereof.

[0078] In at least one embodiment, as described in Fig. As shown in Figure 11, the framework layer 1120 includes a job scheduler 1122, a configuration manager 1134, a resource manager 1136, and a distributed file system 1138. In at least one embodiment, the framework layer 1120 can include a frame or framework to support the software 1132 of software layer 1130 and / or one or more applications 1142 of application layer 1140. In at least one embodiment, the software 1132 or the application(s) 1142 can each be web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be a type of free and open-source software web application framework such as Apache Spark™ (hereinafter referred to as "Spark"), which can use a distributed file system 1138 for processing large amounts of data (e.g., "Big Data").In at least one embodiment, the job scheduler 1122 can include a Spark driver to facilitate the scheduling of workloads supported by different layers of the data center 1100. In at least one embodiment, the configuration manager 1134 can be able to configure different layers, such as the software layer 1130 and the framework layer 1120, which includes Spark and the distributed file system 1138, to support the processing of large amounts of data. In at least one embodiment, the resource manager 1136 can be able to manage clustered or grouped computing resources allocated or assigned to support the distributed file system 1138 and the job scheduler 1122. In at least one embodiment, clustered or grouped computing resources 1114 can be located in the infrastructure layer 1110 of the data center.In at least one embodiment, the resource manager 1136 can be coordinated with the resource orchestrator 1112 to manage these allocated or assigned computer resources.

[0079] In at least one embodiment, the software 1130 contained in software layer 1132 may comprise software used by at least sections of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. In at least one embodiment, one or more types of software may, but are not limited to, internet search software, email virus scanning software, database software, and streaming video content software.

[0080] In at least one embodiment, the application(s) 1142 contained in the application layer 1140 may comprise one or more types of applications used by at least sections of the nodes CRs 1116(1)-1116(N), grouped compute resources 1114, and / or the distributed file system 1138 of the framework layer 1120. In at least one embodiment, one or more types of applications may comprise any number of genome applications, cognitive computations, and machine learning applications, including, but not limited to, training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0081] In at least one embodiment, each of the configuration manager 1134, resource manager 1136, and resource orchestrator 1112 can implement any number and type of self-modifying actions based on any set and type of data collected in any technically feasible way. In at least one embodiment, self-modifying actions can relieve a data center operator of data center 1100 of potentially making poor configuration decisions and potentially avoiding underutilized and / or poorly functioning sections of a data center.

[0082] In at least one embodiment, the data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or deriving information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computing resources described above in relation to the data center 1100.In at least one embodiment, trained machine learning models corresponding to one or more neural networks can be used to derive or predict information, utilizing the resources described above in relation to the data center 1100 by using weighting parameters calculated by one or more training techniques described here.

[0083] In at least one embodiment, the data center can use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using the resources described above. Furthermore, one or more of the software and / or hardware resources described above can be provided as a service to allow users to train information or perform inferencing, such as image recognition, speech recognition, or other artificial intelligence services.

[0084] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig. 9A and / or 9B described. In at least one embodiment, the logic 915 can be implemented in the system of Fig. 11 for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or neural network architectures or neural network use cases described herein.

[0085] In at least one embodiment, at least one in Fig. 11. The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 11 is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 11 selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described. AUTONOMOUS VEHICLE

[0086] Fig. Figure 12A shows an example of an autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1200 (here alternatively referred to as "vehicle 1200") can be, without restriction, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that carries one or more passengers. In at least one embodiment, the vehicle 1200 can be a semi-trailer truck used for transporting goods. In at least one embodiment, the vehicle 1200 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0087] Autonomous vehicles can be described in terms of automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) in the “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201809, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and earlier and future versions of this standard). In at least one embodiment, the Vehicle 1200 may be capable of performing functionality corresponding to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, the Vehicle 1200 may be capable of driving conditionally automated (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0088] In at least one embodiment, the vehicle 1200 can, without restriction, comprise components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, the vehicle 1200 can, without restriction, comprise a drive system 1250, such as an internal combustion engine, a hybrid-electric drive, a pure electric motor, and / or another type of drive system. In at least one embodiment, the drive system 1250 can be connected to a drivetrain of the vehicle 1200, which may include, among other things, a transmission to enable the propulsion of the vehicle 1200. In at least one embodiment, the drive system 1250 can be controlled in response to the reception of signals from a throttle valve / accelerator pedal (or multiple accelerator pedals) 1252.

[0089] In at least one embodiment, a steering system 1254, which may include a steering wheel without restriction, is used to steer the vehicle 1200 (e.g., along a desired path or route) when a drive system 1250 is in operation (e.g., when the vehicle is in motion). In at least one embodiment, the steering system 1254 can receive signals from one or more steering actuators 1256. In at least one embodiment, a steering wheel can optionally be used for full automation (Level 5). In at least one embodiment, a brake sensor system 1246 can be used to actuate the vehicle brakes in response to receiving signals from one or more brake actuators 1248 and / or brake sensors.

[0090] In at least one embodiment, the controller(s) 1236, which without restriction include one or more system-on-chips (“SoCs”) (in Fig. 12A not shown) and / or graphics processing units (“GPUs”), send signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1200. In at least one embodiment, the controller(s) 1236 may, for example, send signals to actuate the vehicle brakes via the brake actuator(s) 1248, to actuate the steering system 1254 via the steering actuator(s) 1256, and to actuate the drive system 1250 via a throttle valve / accelerator pedal(s) 1252. In at least one embodiment, the controller(s) 1236 may include one or more in-vehicle (e.g., integrated) computing units that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in operating the vehicle 1200.In at least one embodiment, the controller(s) 1236 may comprise a first controller 1236 for autonomous driving functions, a second controller 1236 for functional safety functions, a third controller 1236 for artificial intelligence functions (e.g., computer vision), a fourth controller 1236 for infotainment functions, a fifth controller 1236 for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller 1236 may perform two or more of the aforementioned functions, two or more controllers 1236 may perform a single function, and / or any combination thereof.

[0091] In at least one embodiment, the controller(s) 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g. sensor inputs). In at least one embodiment, sensor data can be obtained, for example, and without limitation, from a Global Navigation Satellite System (“GNSS”) sensor(s) 1258 (e.g., Global Positioning System sensor(s)), radar sensor(s) 1260, ultrasonic sensor(s) 1262, lidar sensor(s) 1264, inertial measurement unit (“IMU”) sensor(s) 1266 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or compasses, magnetometer, etc.), microphone(s) 1296, stereo camera(s) 1268, wide-angle camera(s) 1270 (e.g., fisheye cameras), infrared camera(s) 1272, surround camera(s) 1274 (e.g., 360-degree cameras), remote cameras (not in Fig. 12A shown), mid-range camera(s) (not shown in Fig. 12A shown), speed sensor(s) 1244 (e.g. to measure the speed of the vehicle 1200), vibration sensor(s) 1242, steering sensor(s) 1240, brake sensor(s) (e.g. as part of the brake sensor system 1246) and / or other sensor types are received.

[0092] In at least one embodiment, one or more of the controllers 1236 can receive inputs (e.g., in the form of input data) from an instrument cluster 1232 of the vehicle 1200 and provide outputs (e.g., in the form of output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, an acoustic alarm, a loudspeaker, and / or via other components of the vehicle 1200. In at least one embodiment, the outputs can include information such as vehicle speed, engine speed, time, map data (e.g., a high-resolution map (in Fig. 12A not shown)), position data (e.g., the position of vehicle 1200, as shown on a map), direction, position of other vehicles (e.g., an occupancy grid), information about objects and the status of objects as perceived by the controller(s) 1236, etc. In at least one embodiment, the HMI display 1234 can, for example, show information about the presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about driving maneuvers that the vehicle has performed, is currently performing, or will perform (e.g., lane change now, exit 34B in two miles, etc.).

[0093] In at least one embodiment, the vehicle 1200 further comprises a network interface 1224 which can use radio antenna(s) 1226 and / or modem(s) for communication via one or more networks. For example, in at least one embodiment, the network interface 1224 may be capable of communicating via Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, the radio antenna(s) 1226 can also enable communication between objects in the environment (e.g. vehicles, mobile equipment, etc.) using local network protocols such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low-power wide area networks (“LPWANs”) such as LoRaWAN, SigFox, etc.

[0094] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig. 12A and / or 12B described. In at least one embodiment, the logic 915 can be implemented in the system of Fig. 12A for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or neural network architectures or neural network use cases described herein.

[0095] In at least one embodiment, at least one in Fig. 12A The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 12A is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 12A selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0096] Fig. Figure 12B shows an example of camera positions and fields of view for the autonomous vehicle 1200. Fig. 12A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view represent an exemplary embodiment and are not to be considered limiting. For example, in at least one embodiment, additional and / or alternative cameras may be present and / or the cameras may be arranged at other locations on the vehicle 1200.

[0097] In at least one embodiment, the camera types may be digital cameras, which may be adapted for use with components and / or systems of the vehicle 1200, but are not limited to this. In at least one embodiment, the camera(s) may operate at Automotive Safety Integrity Level (ASIL) B and / or at another ASIL. In at least one embodiment, the camera types may achieve any frame rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the cameras may use a rolling shutter, a global shutter, another shutter type, or a combination thereof.In at least one embodiment, the color filter arrangement can comprise a red-clear-clear-clear color filter arrangement (“RCCC”), a red-clear-clear-blue color filter arrangement (“RCCB”), a red-blue-green clear color filter arrangement (“RBGC”), a Foveon X3 color filter arrangement, a Bayer sensor color filter arrangement (“RGGB”), a monochrome sensor color filter arrangement, and / or another type of color filter arrangement. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter arrangement, can be used to increase light sensitivity.

[0098] In at least one embodiment, one or more cameras can be used to implement advanced driver assistance systems (ADAS) (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed, providing functions such as lane keeping assist, traffic sign recognition, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0099] In at least one embodiment, one or more cameras can be mounted in a mounting arrangement, such as a custom-designed (three-dimensional ("3D") printed) arrangement, to eliminate stray light and reflections from the vehicle 1200 (e.g., reflections from the dashboard reflected in the windshield mirrors) that could impair the camera's ability to capture image data. In at least one embodiment, the assemblies for the exterior mirrors can be individually 3D printed, so that a camera mounting plate corresponds to the shape of an exterior mirror. In at least one embodiment, the camera(s) can be integrated into the exterior mirrors. In at least one embodiment, for side cameras, the camera(s) can also be integrated into four pillars at each corner of a passenger compartment.

[0100] In at least one embodiment, cameras with a field of view that includes sections of the environment in front of the vehicle 1200 (e.g., forward-facing cameras) can be used for all-around vision to assist in the detection of forward-facing paths and obstacles, and, with the aid of one or more controllers 1236 and / or control SoCs, to provide information that is crucial for generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, forward-facing cameras can be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”) and / or other functions such as traffic sign recognition.

[0101] In at least one embodiment, a plurality of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform comprising a CMOS color image sensor (complementary metal oxide semiconductor). In at least one embodiment, the wide-angle camera 1270 can be used to detect objects approaching from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. While only one wide-angle camera 1270 is shown in Figure 12B, other embodiments may include any number (including zero) of wide-angle cameras on the vehicle 1200. In at least one embodiment, any number of wide-angle camera(s) 1298 (e.g., a pair of wide-angle stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the wide-angle camera(s) 1298 may also be used for object detection and classification, as well as for basic object tracking.

[0102] In at least one embodiment, any number of stereo camera(s) 1268 can also be arranged in a forward-facing configuration. In at least one embodiment, one or more of the stereo camera(s) 1268 can have an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit can be used to create a 3D map of the vehicle 1200's surroundings, which includes a distance estimate for all points in the image.In at least one embodiment, one or more of the stereo camera(s) 1268 can, without limitation, include compact stereo vision sensor(s) which can, without limitation, contain two camera lenses (one each on the left and right side) and an image processing chip that can measure the distance between the vehicle 1200 and the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 can also be used in addition to or as an alternative to those described here.

[0103] In at least one embodiment, cameras with a field of view that includes sections of the environment to the sides of the vehicle 1200 (e.g., side cameras) can be used for the surround view and provide information that is used to create and update an occupancy grid and to generate side impact warnings. In at least one embodiment, the surround camera(s) 1274 (e.g., four surround cameras 1274, as described in Fig. (as shown in Figure 12B) is positioned on the vehicle 1200. In at least one embodiment, the surround camera(s) 1274 can comprise any number and combination of wide-angle camera(s), fisheye camera(s), 360-degree camera(s), and / or similar cameras without limitation. For example, in at least one embodiment, four fisheye cameras can be positioned at the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround camera(s) 1274 (e.g., left, right, and rear) and one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0104] In at least one embodiment, cameras with a field of view that includes sections of the environment behind the vehicle 1200 (e.g., reversing cameras) can be used for parking assistance, surround view, rear collision warnings, and the creation and updating of the occupancy grid. In at least one embodiment, a plurality of cameras can be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., wide-area cameras 1298 and / or mid-range cameras 1276, stereo cameras 1268, infrared cameras 1272, etc.), as described herein.

[0105] In at least one embodiment, at least one in Fig. The component shown or described in 12B is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 12B is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 12B selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0106] Fig. 12C is a block diagram showing an exemplary system architecture for the autonomous vehicle 1200. Fig. 12A according to at least one embodiment. In at least one embodiment, each component, feature and system of the vehicle 1200 is shown. Fig. 12C is shown as connected via a bus 1202. In at least one embodiment, the bus 1202 can have a CAN data interface (here alternatively referred to as a "CAN bus") without restriction. In at least one embodiment, a CAN can be a network within the vehicle 1200, used to support the control of various features and functions of the vehicle 1200, such as actuation of the brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, the bus 1202 can be configured to have dozens or even hundreds of nodes, each of which has its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1202 can be read to determine the steering wheel angle, vehicle speed, engine revolutions per minute ("RPMs"), button positions, and / or other vehicle status indicators.In at least one embodiment, the bus 1202 can be a CAN bus that is ASIL B compliant.

[0107] In at least one embodiment, FlexRay and / or Ethernet protocols can be used in addition to or as an alternative to CAN. In at least one embodiment, any number of buses can be used to form Bus 1202, which can, without restriction, include zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses with other protocols. In at least one embodiment, two or more Bus 1202s can be used to perform different functions and / or they can be used for redundancy. For example, a first bus can be used for collision avoidance functionality and a second bus for actuation control. In at least one embodiment, each Bus 1202 can communicate with any component of the vehicle 1200, and two or more Bus 1202s can communicate with corresponding components.In at least one embodiment, any number of system(s) on (one) chip(s) (“SoC(s)”) 1204 (such as SoC 1204(A) and SoC 1204(B)), any controller 1236 and / or any computer in the vehicle can have access to the same input data (e.g. inputs from sensors of the vehicle 1200) and be connected to a common bus, such as the CAN bus.

[0108] In at least one embodiment, the vehicle 1200 can have one or more control units 1236, as described here in relation to Fig. 12A is described. In at least one embodiment, the controller(s) 1236 can be used for a variety of functions. In at least one embodiment, the controller(s) 1236 can be coupled with various other components and systems of the vehicle 1200 and used for controlling the vehicle 1200, for the artificial intelligence of the vehicle 1200, for infotainment for the vehicle 1200, and / or other functions.

[0109] In at least one embodiment, the vehicle 1200 can have any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 can, without limitation, include central processing units (“CPU(s)”) 1206, graphics processing units (“GPU(s)”) 1208, processor(s) 1210, cache(s) 1212, accelerators 1214, data storage 1216, and / or other components and features not shown. In at least one embodiment, the SoC(s) 1204 can be used to control the vehicle 1200 in a variety of platforms and systems. In at least one embodiment, the SoC(s) 1204 can, for example, be combined in a system (e.g., the system of the vehicle 1200) with a high-definition (“HD”) card 1222, which is accessed via a network interface 1224 by one or more servers (in Fig. (12C not shown) may receive map refreshes and / or updates.

[0110] In at least one embodiment, the CPU(s) 1206 may comprise a CPU cluster or CPU complex (here alternatively referred to as "CCPLEX"). In at least one embodiment, the CPU(s) 1206 may comprise multiple cores and / or Level Two ("L2") caches. In at least one embodiment, the CPU(s) 1206 may, for example, comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1206 may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1206 (e.g., CCPLEX) may be configured to support concurrent cluster operations, so that any combination of clusters of the CPU(s) 1206 can be active at any given time.

[0111] In at least one embodiment, one or more of the CPU(s) 1206 can implement power management functions that, without limitation, have one or more of the following features: individual hardware blocks can be automatically clocked when idle to save dynamic power; each core can be clocked when the core is not actively executing instructions due to the execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core can be independently power-controlled; each core cluster can be independently clock-controlled when all cores are clock-controlled or power-controlled; and / or each core cluster can be independently power-controlled when all cores are power-controlled.In at least one embodiment, the CPU(s) 1206 can further implement an extended power state management algorithm in which permissible power states and expected wake-up times are defined, and the hardware / microcode determines the best power state to adopt for the core, cluster, and CCPLEX. In at least one embodiment, the processor cores can support simplified sequences for inputting the power state into software, with the work offloaded to the microcode.

[0112] In at least one embodiment, the GPU(s) 1208 may include an integrated GPU (here alternatively referred to as an "iGPU"). In at least one embodiment, the GPU(s) 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, the GPU(s) 1208 may use an extended Tensor instruction set. In at least one embodiment, the GPU(s) 1208 may include one or more streaming microprocessors, each streaming microprocessor having an L1 cache (e.g., an L1 cache with a memory capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In at least one embodiment, the GPU(s) 1208 may include at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 1208 can use one or more application programming interfaces (APIs) for computations. In at least one embodiment, the GPU(s) 1208 can use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0113] In at least one embodiment, one or more of the GPU(s) 1208 can be energy-optimized for best performance in automotive and embedded applications. In at least one embodiment, the GPU(s) 1208 can, for example, be manufactured using a Fin field-effect transistor (“FinFETs”) circuit. In at least one embodiment, each streaming microprocessor can contain a number of mixed-precision processing cores divided into multiple blocks. For example, 64 PF32 cores and 32 FP64 cores can be divided into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA mixed-precision Tensor cores for deep learning matrix arithmetic, a level zero instruction cache (“L0”), a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file.In at least one embodiment, streaming microprocessors can have independent parallel integer and floating-point data paths to enable efficient execution of workloads with a mix of computations and addressing calculations. In at least one embodiment, streaming microprocessors can have an independent thread scheduling function to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, streaming microprocessors can have a combined L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0114] In at least one embodiment, one or more of the GPU(s) 1208 may incorporate high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 1300 GB / second in some examples. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as type 5 synchronous graphics dual-data-rate random-access memory (“GDDR5”), may be used in addition to or as an alternative to the HBM memory.

[0115] In at least one embodiment, the GPU(s) 1208 can incorporate unified memory technology. In at least one embodiment, support for address translation services (“ATS”) can be used so that the GPU(s) 1208 can directly access the page tables of the CPU(s) 1206. In at least one embodiment, an address translation request can be sent to the CPU(s) 1206 when the memory management unit (“MMU”) of the GPU(s) 1208 detects an error. In response, two CPUs of the CPU(s) 1206 can search their page tables for a virtual-physical mapping of the address and, in at least one embodiment, transmit the translation back to the GPU(s) 1208.In at least one embodiment, the Unified Memory technology can enable a single, unified virtual address space for the memory of both the CPU(s) 1206 and the GPU(s) 1208, thereby simplifying the programming of the GPU(s) 1208 and the connection of applications to the GPU(s) 1208.

[0116] In at least one embodiment, the GPU(s) 1208 can have any number of access counters that can track the frequency of GPU(s) 1208 access to the memory of other processors. In at least one embodiment, access counters can help move memory pages into the physical memory of the processor that accesses pages most frequently, thereby improving the efficiency of memory areas shared by processors.

[0117] In at least one embodiment, one or more of the SoC(s) 1204 can have any number of cache(s) 1212, including those described herein. In at least one embodiment, the cache(s) 1212 can, for example, have a Level 3 cache (“L3”) available to both the CPU(s) 1206 and the GPU(s) 1208 (e.g., connected to both the CPU(s) 1206 and the GPU(s) 1208). In at least one embodiment, the cache(s) 1212 can have a write-back cache capable of tracking the states of the rows, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache can have 4 MB of memory or more, depending on the embodiment, although smaller cache sizes can also be used.

[0118] In at least one embodiment, one or more of the SoC(s) 1204 can include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1204 can include a hardware acceleration cluster, which may include optimized hardware accelerators and / or a large on-chip memory. In at least one embodiment, a large on-chip memory (e.g., 4 MB SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster can be used to complement the GPU(s) 1208 and to offload some tasks of the GPU(s) 1208 (e.g., to free up more GPU cycles for other tasks).In at least one embodiment, the accelerator(s) 1214 can be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), regenerative neural networks (“RNNs”), etc.) that are stable enough to be suitable for acceleration. In at least one embodiment, a CNN can include a region-based or regional convolutional neural network (“RCNNs”) and a fast RCNN (e.g., as used for object recognition) or another type of CNN.

[0119] In at least one embodiment, the accelerator(s) 1214 (e.g., hardware acceleration cluster) may include one or more deep learning accelerators (“DLA”). In at least one embodiment, a DLA may, without restriction, include one or more tensor processing units (“TPUs”), which may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, the TPUs may be accelerators designed and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA may also be optimized for a specific set of neural network types and floating-point operations, as well as for inferencing.In at least one embodiment, the design of the DLA(s) can provide more performance per millimeter than a typical general-purpose GPU and generally far surpasses the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function that supports, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions.In at least one embodiment, DLA(s) can quickly and efficiently execute neural networks, in particular CNNs, on processed or unprocessed data for a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for the detection and identification of emergency vehicles and recognition using data from microphones; a CNN for facial recognition and the identification of vehicle owners using data from camera sensors; and / or a CNN for safety-related and / or security-related events.

[0120] In at least one embodiment, the DLA(s) can perform any function of the GPU(s) 1208, and by using an inference accelerator, a developer can, for example, allocate either the DLA(s) or the GPU(s) 1208 to any given function. In at least one embodiment, a developer can, for example, concentrate the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 1208 and / or the accelerator(s) 1214.

[0121] In at least one embodiment, the accelerator(s) 1214 may comprise the programmable image processing accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA(s) may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA(s) may offer a balance between performance and flexibility. In at least one embodiment, each PVA may, for example, without limitation, comprise any number of reduced instruction set compute cores (“RISC”), direct memory access (“DMA”), and / or any number of vector processors.

[0122] In at least one embodiment, the RISC cores can interact with image sensors (e.g., image sensors of one of the cameras described herein), image signal processors, etc. In at least one embodiment, each RISC core can have any amount of memory. In at least one embodiment, the RISC cores can use one of several protocols, depending on the embodiment. In at least one embodiment, RISC cores can run a real-time operating system (RTOS). In at least one embodiment, RISC cores can be implemented with one or more integrated circuit devices, application-specific integrated circuits (ASICs), and / or memory devices. In at least one embodiment, RISC cores can, for example, include an instruction cache and / or tightly coupled RAM.

[0123] In at least one embodiment, a DMA can enable components of the PVA(s) to access system memory independently of the CPU(s) 1206. In at least one embodiment, a DMA can support any number of features used to optimize a PVA, including, but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, a DMA can support up to six or more dimensions of addressing, which can, without limitation, include block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0124] In at least one embodiment, vector processors can be programmable processors designed for efficient and flexible execution of computer vision algorithm programming and providing signal processing capabilities. In at least one embodiment, a PVA can comprise a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core can comprise a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem can function as a primary processing unit of a PVA and comprise a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core can comprise a digital signal processor, such as…A digital signal processor with multiple data points per instruction (“SIMD”) and very long instruction words (“VLIW”). In at least one embodiment, a combination of SIMD and VLIW can increase throughput and speed.

[0125] In at least one embodiment, each vector processor can have an instruction cache and be connected to dedicated memory. Consequently, in at least one embodiment, each vector processor can be configured to operate independently of other vector processors. In at least one embodiment, vector processors contained in a given PVA can be configured to use data parallelism. For example, in at least one embodiment, multiple vector processors contained in a single PVA can execute a general computer vision algorithm, but for different image regions. In at least one embodiment, vector processors contained in a given PVA can simultaneously execute different image processing algorithms for a single image, or even different algorithms for successive images or sections of an image.In at least one embodiment, an arbitrary number of PVAs can be present in a hardware acceleration cluster, and an arbitrary number of vector processors can be present in each PVA. In at least one embodiment, the PVA(s) can include an additional error correction code (ECC) memory to increase overall system safety.

[0126] In at least one embodiment, the accelerator(s) 1214 may include an on-chip computer vision network and static random-access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator(s). In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an extended peripheral bus interface (“APB”), configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any desired memory type may be used.In at least one embodiment, a PVA and a DLA can access the memory via a backbone, enabling high-speed access to the memory for both the PVA and the DLA. In at least one embodiment, the backbone can include an on-chip computer vision network that connects the PVA and the DLA to the memory (e.g., using an APB).

[0127] In at least one embodiment, a computer vision network on the chip can have an interface that, prior to the transmission of control signals / addresses / data, determines that both a PVA and a DLA are providing available and valid signals. In at least one embodiment, an interface can provide separate phases and separate channels for the transmission of control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface can conform to the standards of the International Organization for Standardization (ISO) 21262 or the International Electrotechnical Commission (IEC) 57508, although other standards and protocols can also be used.

[0128] In at least one embodiment, one or more of the SoC(s) 1204 can include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator can be used to quickly and efficiently determine the positions and dimensions of objects (e.g., within a world model), to generate real-time visualization simulations, for radar signal interpretation, for sound propagation synthesis and / or analysis, for the simulation of SONAR systems, for general wave propagation simulation, for comparison with lidar data for localization purposes, and / or for other functions and / or purposes.

[0129] In at least one embodiment, the accelerator(s) 1214 can have a wide range of applications for autonomous driving. In at least one embodiment, a PVA can be used for key processing steps in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are well suited for algorithmic domains that require predictable processing with low power consumption and low latency. In other words, a PVA is well suited for semi-dense or dense regular computations, even with small datasets, that require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in the vehicle 1200, PVAs can be designed to execute classical computer vision algorithms, as they can efficiently perform object recognition and integer mathematical procedures.

[0130] For example, in at least one embodiment of a technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not intended as a limitation. In at least one embodiment, motion estimation / stereo matching is used in-motion applications for Level 3-5 autonomous driving (e.g., structure of motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA can perform computer stereo vision functions on input from two monocular cameras.

[0131] In at least one embodiment, a PVA can be used to perform a dense optical flow. For example, in at least one embodiment, a PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to deliver processed RADAR data. In at least one embodiment, a PVA is used for time-of-flight depth processing by processing raw time-of-flight data to, for example, provide processed time-of-flight data.

[0132] In at least one embodiment, a DLA can be used to operate any type of network to improve control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as a relative "weighting" of each detection compared to other detections. In at least one embodiment, a confidence measure further enables the system to make decisions about which detections should be considered true positives and which should be considered false positives. In at least one embodiment, a system can set a confidence threshold and consider only detections that exceed the threshold as true positives.In an embodiment where an automatic emergency braking system (“AEB”) is used, false positive detections would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly reliable detections can be considered triggers for AEB. In at least one embodiment, a DLA can employ a neural network for regression of the confidence level. In at least one embodiment, the neural network can take as input at least a subset of parameters, such as the dimensions of the boundary frame, the estimated base area (obtained, for example, from another subsystem), the output of the IMU sensor(s) 1266, which correlates with the orientation of the vehicle 1200, the distance, the estimates of the 3D position of the object obtained from the neural network and / or other sensors (e.g., LIDAR sensor(s) 1264 or RADAR sensor(s) 1260), and others.

[0133] In at least one embodiment, one or more SoC(s) 1204 can include one or more data memories 1216 (e.g., a memory). In at least one embodiment, the data memory 1216 can be on-chip memory of the SoC(s) 1204 that can store neural networks to be executed on GPU(s) 1208 and / or a DLA. In at least one embodiment, the capacity of the data memory 1216 can be large enough to store multiple instances of neural networks for redundancy and security. In at least one embodiment, the data memory 1216 can include L2 or L3 cache(s).

[0134] In at least one embodiment, one or more of the SoC(s) 1204 can include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, the processor(s) 1210 can include a boot and power management processor, which can be a dedicated processor and a dedicated subsystem for handling the boot power and management functions and the associated security enforcement. In at least one embodiment, the boot and power management processor can be part of the boot sequence of the SoC(s) 1204 and provide runtime power management services.In at least one embodiment, a processor can provide clock and voltage programming, low-power system transition support, SoC(s) 1204 temperature and sensor management, and / or SoC(s) 1204 power supply state management for boot power supply and management. In at least one embodiment, each temperature sensor can be implemented as a ring oscillator whose output frequency is proportional to the temperature, and the SoC(s) 1204 can use ring oscillators to sense temperatures of the CPU(s) 1206, GPU(s) 1208, and / or accelerator(s) 1214.In at least one embodiment, when it is detected that the temperatures exceed a threshold, a boot and power management processor can enter a temperature fault routine and put the SoC(s) 1204 into a lower power state and / or put the vehicle 1200 into a chauffeur-assured-stop mode (e.g., bring the vehicle 1200 to a safe stop).

[0135] In at least one embodiment, the processor(s) 1210 may further comprise a set of embedded processors that can serve as an audio processing machine, which may be an audio subsystem that enables full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing machine is a dedicated processor core with a digital signal processor and dedicated RAM.

[0136] In at least one embodiment, the processor(s) 1210 may further comprise an "always on" processor machine that can provide the necessary hardware functions to support low-power sensor management and wake-up use cases. In at least one embodiment, an "always on" processor machine may, without restriction, comprise a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0137] In at least one embodiment, the processor(s) 1210 can further comprise a safety cluster machine which, without limitation, includes a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, a safety cluster machine can, without limitation, comprise two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt control, etc.), and / or routing logic. In a safety mode, in at least one embodiment, two or more cores can operate in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations.In at least one embodiment, the processor(s) 1210 may further comprise a real-time camera machine, which may, without limitation, include a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1210 may further comprise a high dynamic range signal processor, which may, without limitation, include an image signal processor that is a hardware machine that is part of a camera processing pipeline.

[0138] In at least one embodiment, the processor(s) 1210 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on the wide-angle camera(s) 1270, the surround camera(s) 1274, and / or on the sensor(s) of the surveillance camera(s) in the cabin. In at least one embodiment, the sensor(s) of the surveillance camera(s) in the cabin are preferably monitored by a neural network running on a separate instance of the SoC 1204 and configured to detect events in the cabin and react accordingly.In at least one embodiment, a system inside the vehicle can perform lip-reading without restriction to activate the mobile phone service and make a call, dictate emails, change the destination, activate or change the infotainment system and vehicle settings, or enable voice-controlled internet browsing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in autonomous mode and are otherwise deactivated.

[0139] In at least one embodiment, the video image compositor can feature improved temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in a video, the noise reduction appropriately weights the spatial information and reduces the weight of information provided by adjacent frames. In at least one embodiment where a frame or a portion of a frame does not exhibit motion, the temporal noise reduction performed by the video image compositor can use information from a previous frame to reduce the noise in the current frame.

[0140] In at least one embodiment, a video image compositor can also be configured to perform stereo rectification on input stereo lens frames. Furthermore, in at least one embodiment, a video image compositor can be used for user interface design when the operating system desktop is in use and the GPU(s) 1208 are not required for continuously rendering new surfaces. In at least one embodiment, when the GPU(s) 1208 are powered on and actively performing 3D rendering, a video image compositor can be used to offload the GPU(s) 1208 to improve performance and responsiveness.

[0141] In at least one embodiment, one or more of the SoC(s) 1204 may additionally include a serial (Mobile Industry Processor Interface ("MIPI") camera interface for receiving video and camera inputs, a high-speed interface, and / or a video input block that can be used for a camera and related pixel input functions. In at least one embodiment, one or more of the SoC(s) 1204 may additionally include one or more software-controlled input / output controllers that can be used to receive I / O signals that are not assigned to a specific role.

[0142] In at least one embodiment, one or more of the SoC(s) 1204 can also have a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, the SoC(s) 1204 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LiDAR sensor(s) 1264, radar sensor(s) 1260, etc., which can be connected via Ethernet channels), data from bus 1202 (e.g., vehicle speed 1200, steering wheel position, etc.), data from GNSS sensor(s) 1258 (e.g., connected via an Ethernet bus or a CAN bus), etc.In at least one embodiment, one or more of the SoC(s) 1204 may also have dedicated high-performance mass storage controllers, which may have their own DMA machines and which may be used to relieve the CPU(s) 1206 of routine data management tasks.

[0143] In at least one embodiment, the SoC(s) 1204 can be an end-to-end platform with a flexible architecture that encompasses automation levels 3 to 5, thereby providing a comprehensive functional safety architecture that utilizes computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 1204 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 1214, in combination with the CPU(s) 1206, the GPU(s) 1208, and the data storage(s) 1216, can form a fast, efficient platform for autonomous vehicles of levels 3-5.

[0144] In at least one embodiment, computer vision algorithms can be executed on CPUs, which may be designed using high-level programming languages ​​such as C to perform a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many image processing applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object recognition algorithms in real time, as used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0145] Embodiments such as those described here enable the simultaneous and / or sequential execution of multiple neural networks and the combination of the results to enable Level 3-5 autonomous driving functions. For example, in at least one embodiment, a CNN running on a DLA or a discrete GPU (e.g., GPU(s) 1220) can include text and word recognition that enables the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, a DLA can also include a neural network capable of identifying, interpreting, and semantically understanding a traffic sign and passing this semantic understanding to the path planning modules running on a CPU complex.

[0146] In at least one embodiment, multiple neural networks can be executed simultaneously, as in Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icing" can be interpreted independently or jointly by multiple neural networks, along with an electric light. In at least one embodiment, such a warning sign itself can be identified as a traffic sign by a first neural network (e.g., a trained neural network), and the text "Flashing lights indicate black ice" can be interpreted by a second neural network, which informs the vehicle's path planning software (preferably running on a CPU complex) that black ice is present when flashing lights are detected.In at least one embodiment, the flashing light can be identified by operating a third neural network across multiple images, which informs the vehicle's path planning software about the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example, within a DLA and / or on GPU(s) 1208.

[0147] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processing machine can be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and, in security mode, to disable the vehicle when the owner leaves the vehicle. In this way, the SoC(s) 1204 provide security against theft and / or carjacking.

[0148] In at least one embodiment, a CNN for the detection and identification of emergency vehicles can use data from microphones 1296 to detect and identify the sirens of emergency vehicles. In at least one embodiment, the SoC(s) 1204 use a CNN for classifying environmental and urban noise as well as for classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to detect the relative approach speed of emergency vehicles (e.g., using the Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is traveling, as identified by GNSS sensor(s) 1258.In at least one embodiment, a CNN will attempt to detect European sirens when deployed in Europe, and a CNN will attempt to identify only North American sirens when deployed in North America. In at least one embodiment, once an emergency vehicle is detected, a control program can be used to execute an emergency vehicle safety routine, slowing the vehicle down, pulling over to the side of the road, parking the vehicle, and / or letting the vehicle idle, using the ultrasonic sensor(s) 1262, until the emergency vehicle(s) pass by.

[0149] In at least one embodiment, the vehicle 1200 may have one or more CPU(s) 1218 (e.g., discrete CPU(s) or dCPU(s)) which may be connected to the SoC(s) 1204 via a high-speed connection (e.g., PCIe). In at least one embodiment, the CPU(s) 1218 may, for example, be an x86 processor. A CPU(s) 1218 may be used to perform a variety of functions, including mediating potentially inconsistent results between ADAS sensors and the SoC(s) 1204 and / or monitoring the status and state of the controller(s) 1236 and / or an infotainment system on a single chip (“infotainment SoC”) 1230, for example. In at least one embodiment, the SoC(s) 1204 has (have) one or more connections, wherein one connection may be a Peripheral Component Interconnect Express (PCIe).

[0150] In at least one embodiment, the vehicle 1200 can have GPU(s) 1220 (e.g., discrete GPU(s) or dGPU(s)) that can be coupled to the SoC(s) 1204 via a high-speed connection (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU(s) 1220 can provide additional artificial intelligence functionality, for example, by running redundant and / or different neural networks, and can be used to train and / or update neural networks, based at least partially on inputs (e.g., sensor data) from sensors of the vehicle 1200.

[0151] In at least one embodiment, the vehicle 1200 can also have a network interface 1224, which can, without restriction, include one or more radio antennas 1226 (e.g., one or more radio antennas 1226 for different communication protocols, such as a mobile communication antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1224 can be used to enable a wireless connection to internet cloud services (e.g., with one or more servers and / or other network equipment), with other vehicles, and / or with computing equipment (e.g., passenger client devices). In at least one embodiment, a direct connection between the vehicle 80 and another vehicle and / or an indirect connection (e.g., via networks and the internet) can be established for communication with other vehicles.In at least one embodiment, direct connections can be established via a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link can provide the vehicle 1200 with information about vehicles in its vicinity (e.g., vehicles in front of, beside, and / or behind the vehicle 1200). In at least one embodiment, the aforementioned functionality can be part of a cooperative adaptive cruise control function of the vehicle 1200.

[0152] In at least one embodiment, the network interface 1224 can include a SoC that provides modulation and demodulation functions and enables the controller(s) 1236 to communicate via wireless networks. In at least one embodiment, the network interface 1224 can include a high-frequency front end for up-conversion from a baseband to a high frequency and down-conversion from a high frequency to a baseband. In at least one embodiment, the frequency conversions can be performed in any technically feasible way. For example, frequency conversions can be performed by known methods and / or using superheterodyne methods. In at least one embodiment, the high-frequency front-end functionality can be provided by a separate chip.In at least one embodiment, the network interfaces can have wireless functionality for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN and / or other wireless protocols.

[0153] In at least one embodiment, the vehicle 1200 may furthermore include one or more data storage devices 1228, which may, without restriction, include off-chip memory (e.g., off-SoC(s) 1204). In at least one embodiment, the data storage device(s) 1228 may, without restriction, include one or more memory elements, including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices capable of storing at least one bit of data.

[0154] In at least one embodiment, the vehicle 1200 may additionally include GNSS sensor(s) 1258 (e.g., GPS and / or GPS-enabled sensors) to assist in mapping, perception, grid generation, and / or path planning. In at least one embodiment, any number of GNSS sensor(s) 1258 may be used, including, for example, and without limitation, a GPS unit that uses a USB port with an Ethernet-to-serial bridge (e.g., RS-232).

[0155] In at least one embodiment, the vehicle 1200 may also include RADAR sensor(s) 1260. In at least one embodiment, the RADAR sensor(s) 1260 of a vehicle 1200 may be used for vehicle detection over long distances, even in darkness and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety levels may be ASIL B. In at least one embodiment, the RADAR sensor(s) 1260 may use a CAN bus and / or the bus 1202 (e.g., for transmitting the data generated by the RADAR sensor(s) 1260) for control and access to object tracking data, with some examples providing access to raw data via Ethernet channels. In at least one embodiment, a wide range of RADAR sensor types may be used.For example, and without limitation, RADAR sensor(s) 1260 can be suitable for use with front, rear, and side radar. In at least one embodiment, one or more of the RADAR sensors 1260 are pulse-Doppler radar sensors.

[0156] In at least one embodiment, the RADAR sensor(s) 1260 can have different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, side coverage with short-range, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control. In at least one embodiment, long-range RADAR systems can provide a wide field of view, which is achieved by two or more independent scans, for example, within a range of 250 m (meters). In at least one embodiment, the RADAR sensor(s) 1260 can help to distinguish between stationary and moving objects and can be used by the ADAS system 1238 for emergency braking assistance and forward collision warning.In at least one embodiment, the sensor(s) 1260, which is / are included in a long-range radar system, can, without restriction, comprise a monostatic multimodal radar with multiple (e.g., six or more) fixed radar antennas and a high-speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center can generate a focused beam pattern for detecting the vehicle's surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the other two antennas can extend the field of view so that vehicles entering or leaving a lane of the vehicle 1200 can be detected quickly.

[0157] In at least one embodiment, medium-range RADAR systems can, for example, have a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems can, without limitation, include any number of RADAR sensors 1260, which can be installed at both ends of the rear bumper. In at least one embodiment, a RADAR sensor system, when installed at both ends of the rear bumper, can generate two beams that continuously monitor the blind spots in the direction behind and beside the vehicle. In at least one embodiment, short-range RADAR systems can be used in the ADAS system 1238 for blind spot detection and / or lane-change assistance.

[0158] In at least one embodiment, the vehicle 1200 may also have ultrasonic sensor(s) 1262. In at least one embodiment, the ultrasonic sensor(s) 1262, which may be arranged on the front, rear, and / or sides of the vehicle 1200, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a plurality of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1262 may operate at functional safety levels of ASIL B.

[0159] In at least one embodiment, the vehicle can have 1200 LIDAR sensor(s) 1264. In at least one embodiment, the LIDAR sensor(s) 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1264 can operate at functional safety level ASIL B. In at least one embodiment, the vehicle can have multiple LIDAR sensors 1264 (e.g., two, four, six, etc.) that can use an Ethernet channel (e.g., to deliver data to a Gigabit Ethernet switch).

[0160] In at least one embodiment, the LIDAR sensor(s) 1264 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 1264 may have a displayed range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1264 may have a small device that can be embedded in the front, rear, a side, and / or a corner area of ​​the vehicle 1200.In at least one embodiment, the LIDAR sensor(s) 1264 can provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m, even for objects with low reflectivity. In at least one embodiment, the front-mounted LIDAR sensor(s) 1264 can be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0161] In at least one embodiment, LIDAR technologies, such as 3D Flash LIDAR, can also be used. In at least one embodiment, a 3D Flash LIDAR uses a laser pulse as a transmission source to illuminate the area around the vehicle 1200 up to a distance of approximately 200 m. In at least one embodiment, a Flash LIDAR unit without limitation includes a receptor that records the time of flight of the laser pulse and the reflected light on each pixel, which in turn corresponds to the distance of the vehicle 1200 to objects. In at least one embodiment, the Flash LIDAR can enable the generation of highly accurate and distortion-free images of the surroundings with each laser pulse. In at least one embodiment, four Flash LIDAR sensors can be used, one on each side of the vehicle 1200.In at least one embodiment, 3D flash LIDAR systems without restriction include a solid-state 3D star array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per image and capture the reflected laser light as a 3D distance point cloud and co-registered intensity data.

[0162] In at least one embodiment, the vehicle may also have one or more IMU sensors 1266. In at least one embodiment, the IMU sensor(s) 1266 may be located in the center of the rear axle of the vehicle 1200. In at least one embodiment, the IMU sensor(s) 1266 may, for example, without limitation, include one or more accelerometers, magnetometers, gyroscopes, a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1266 may, without limitation, include accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1266 may, without limitation, include accelerometers, gyroscopes, and magnetometers.

[0163] In at least one embodiment, the IMU sensor(s) 1266 can be implemented as a miniaturized, high-performance GPS-based inertial navigation system (“GPS / INS”) that combines microelectromechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, speed, and orientation. In at least one embodiment, the IMU sensor(s) 1266 can enable the vehicle 1200 to estimate its course without requiring input from a magnetic sensor by directly observing and correlating changes in speed from the GPS with the IMU sensor(s) 1266. In at least one embodiment, the IMU sensor(s) 1266 and GNSS sensor(s) 1258 can be combined in a single integrated unit.

[0164] In at least one embodiment, the vehicle 1200 can have one or more microphones 1296 arranged in and / or around the vehicle 1200. In at least one embodiment, the microphone(s) 1296 can be used, among other things, for the detection and identification of emergency vehicles.

[0165] In at least one embodiment, the vehicle 1200 can also have any number of camera types, including stereo camera(s) 1268, wide-angle camera(s) 1270, infrared camera(s) 1272, surround camera(s) 1274, wide-area camera(s) 1298, medium-area camera(s) 1276, and / or other camera types. In at least one embodiment, cameras can be used to capture image data around the entire perimeter of the vehicle 1200. In at least one embodiment, the types of cameras used depend on the vehicle 1200. In at least one embodiment, any combination of camera types can be used to ensure the required coverage around the vehicle 1200. In at least one embodiment, the number of cameras can vary depending on the embodiment.In at least one embodiment, the vehicle 1200 can, for example, have six, seven, ten, twelve, or any other number of cameras. In at least one embodiment, the cameras can, for example, and without limitation, support Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communication. In at least one embodiment, each camera can be one of those previously described here with reference to… Fig. 12A and Fig. 12B is described in more detail.

[0166] In at least one embodiment, the vehicle 1200 may also have one or more vibration sensors 1242. In at least one embodiment, the vibration sensor(s) 1242 may measure vibrations of components of the vehicle 1200, such as the axle(s). For example, in at least one embodiment, changes in the vibrations may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, differences between the vibrations may be used to determine the friction or slip of the road surface (e.g., when the difference in vibrations is between a driven axle and a freely rotating axle).

[0167] In at least one embodiment, the vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may, in some examples without restriction, include a system of control (SoC). In at least one embodiment, the ADAS system 1238 may, without restriction, include any number and combination of an autonomous / adaptive / automatic cruise control system (“ACC”), a cooperative adaptive cruise control system (“CACC”), a forward collision warning system (“FCW”), an automatic emergency braking system (“AEB”), a lane departure warning system (“LDW”), a lane keeping assist system (“LKA”), a blind spot warning system (“BSW”), a rear cross traffic warning system (“RCTW”), a collision warning system (“CW”), a lane centering system (“LC”), and / or other systems, features, and / or functions.

[0168] In at least one embodiment, the ACC system can use radar sensor(s) 1260, lidar sensor(s) 1264, and / or any number of cameras. In at least one embodiment, the ACC system can include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from vehicles ahead. In at least one embodiment, the lateral ACC system maintains the distance and advises the vehicle 1200 to change lanes if necessary. In at least one embodiment, the lateral ACC system is connected to other ADAS applications such as LC and CW.

[0169] In at least one embodiment, the CACC system uses information from other vehicles that can be received via the network interface 1224 and / or the radio antenna(s) 1226 from other vehicles via a wireless connection or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, direct connections can be provided by a vehicle-to-vehicle communication link (“V2V”), while indirect connections can be provided by an infrastructure-to-vehicle communication link (“I2V”). In general, V2V communication provides information about vehicles immediately ahead (e.g., vehicles that are directly in front of and in the same lane as vehicle 1200), while I2V communication provides information about traffic further ahead.In at least one embodiment, a CACC system can have either one or both I2V and V2V information sources. In at least one embodiment, a CACC system can be more reliable given the information about vehicles ahead of vehicle 1200 and has the potential to improve traffic flow and reduce congestion on the road.

[0170] In at least one embodiment, an FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or radar sensor(s) 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to the driver, e.g., via a display, a speaker, and / or a vibrating component. In at least one embodiment, an FCW system can provide a warning, e.g., in the form of a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0171] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or object and can automatically apply the brakes if the driver does not take corrective action within a specific time or distance parameter. In at least one embodiment, the AEB system can use forward-facing camera(s) and / or radar sensor(s) 1260 coupled with a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver so that they can take corrective action to avoid a collision. If the driver does not take corrective action, the AEB system can automatically apply the brakes to prevent or at least mitigate the effects of the predicted collision.In at least one embodiment, the AEB system may incorporate techniques such as dynamic brake support and / or crash imminent braking or braking in the event of an impending collision.

[0172] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver if the vehicle crosses the lane markings. In at least one embodiment, the LDW system is not activated if the driver indicates an intentional lane departure, for example, by using a turn signal. In at least one embodiment, the LDW system can use forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to the driver, for example, via a display, a speaker, and / or a vibrating component. In at least one embodiment, an LKA system is a variant of an LDW system.In at least one embodiment, an LKA system provides steering intervention or braking to correct vehicle 1200 when vehicle 1200 begins to leave its lane.

[0173] In at least one embodiment, a BSW system detects and warns the driver of vehicles in the vehicle's blind spot. In at least one embodiment, a BSW system can issue a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system can issue an additional warning when the driver activates a turn signal. In at least one embodiment, the BSW system can use a rear-facing camera and / or radar sensor 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, a speaker, and / or a vibrating component.

[0174] In at least one embodiment, an RCTW system can provide a visual, audible, and / or tactile notification when an object is detected outside the range of the reversing camera while the vehicle is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing radar sensors coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to the driver, such as a display, a speaker, and / or a vibrating component.

[0175] In at least one embodiment, conventional ADAS systems can be prone to false positives, which can be annoying and distracting for the driver, but are typically not catastrophic because conventional ADAS systems warn the driver and give them the opportunity to decide whether a safety condition actually exists and to act accordingly. In at least one embodiment, the vehicle 1200 itself decides, in the event of conflicting results, whether to follow the result of a primary computer or a secondary computer (e.g., a first controller 1236 or a second controller of the controllers 1236). In at least one embodiment, the ADAS system 1238 can, for example, be a backup and / or secondary computer that provides perceptual information to a rationality module of the backup computer.In at least one embodiment, a rationality monitor of the backup computer can execute redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, the outputs of the ADAS system 1238 can be forwarded to a higher-level MCU. In at least one embodiment, a monitoring MCU determines how conflicts can be resolved between outputs from a primary computer and outputs from a secondary computer to ensure safe operation.

[0176] In at least one embodiment, a primary computer can be configured to provide the higher-level MCU with a confidence value indicating the primary computer's confidence in the selected result. In at least one embodiment, the supervising MCU can follow the primary computer's instruction if the confidence value exceeds a threshold, regardless of whether the secondary computer delivers a contradictory or inconsistent result. In at least one embodiment where the confidence value does not reach the threshold and the primary and secondary computers display different results (e.g., a conflict), the supervising MCU can mediate between the computers to determine the appropriate result.

[0177] In at least one embodiment, the monitoring MCU can be configured to execute a neural network or networks that are trained and configured to determine, at least partially, based on outputs from a primary computer and outputs from a secondary computer, the conditions under which the secondary computer triggers false alarms. In at least one embodiment, the neural network(s) in the monitoring MCU can learn when the output of the secondary computer can be trusted and when it cannot. For example, in at least one embodiment, if the secondary computer is a radar-based FCW system, a neural network in the monitoring MCU can learn when the FCW system identifies metallic objects that are not actually hazards, such as a drain grate or a manhole cover, triggering an alarm.In at least one embodiment, where the secondary computer is a camera-based LDW system, a neural network in the monitoring MCU can learn to override the LDW system when cyclists or pedestrians are present and leaving the lane is indeed the safest maneuver. In at least one embodiment, a monitoring MCU can include a DLA or a GPU suitable for running neural networks with associated memory. In at least one embodiment, the monitoring MCU can include and / or be contained within a component of the SoC(s) 1204.

[0178] In at least one embodiment, the ADAS system 1238 can include a secondary computer that executes the ADAS functionality using conventional computer vision rules. In at least one embodiment, the secondary computer can use classic computer vision rules (if-then), and the presence of a neural network (or neural networks) in the higher-level MCU can improve reliability, safety, and performance. In at least one embodiment, the overall system becomes more fault-tolerant due to the different implementation and intentional non-identity, particularly with respect to errors caused by software functions (or software-hardware interfaces).For example, in at least one embodiment, if there is a software bug or error in the software running on the primary computer, and if non-identical software code running on the secondary computer produces a consistent overall result, then the monitoring MCU can have greater confidence that an overall result is correct and that a bug in the software or hardware on the primary computer is not causing a material error.

[0179] In at least one embodiment, an output from the ADAS system 1238 can be fed into the perception block and / or the dynamic driving task block of the primary computer. For example, if, in at least one embodiment, the ADAS system 1238 displays a forward crash warning due to an object immediately ahead, the perception block can use this information in object identification. In at least one embodiment, the secondary computer can have its own trained neural network, thus reducing the risk of false alarms, as described herein.

[0180] In at least one embodiment, the vehicle 1200 may additionally include an infotainment SoC 1230 (e.g., an onboard infotainment system (IVI)). Although depicted and described as an SoC, in at least one embodiment the infotainment SoC 1230 may not be an SoC and may, without limitation, comprise two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may, without limitation, comprise a combination of hardware and software that can be used to provide audio (e.g., music, a personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g.,Navigation systems, rear parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fluid level, oil level, door open / close status, air filter information, etc.) for the vehicle 1200. The infotainment SoC 1230 can, for example, include radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-car entertainment, WiFi, audio controls on the steering wheel, a hands-free system, a heads-up display (“HUD”), an HMI display 1234, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, functions, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1230 can also be used to provide information (e.g., visual and / or audible) to the user(s) of the vehicle 1200, such as...Information from the ADAS system 1238, information on autonomous driving, such as planned vehicle maneuvers, trajectories, environmental information (e.g. intersection information, vehicle information, road information, etc.), and / or other information.

[0181] In at least one embodiment, the infotainment SoC 1230 can have any quantity and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 can communicate with other devices, systems, and / or components of the vehicle 1200 via bus 1202. In at least one embodiment, the infotainment SoC 1230 can be coupled with a monitoring MCU so that a GPU of the infotainment system can perform some self-driving functions if the primary controller(s) 1236 (e.g., the primary and / or backup computer of the vehicle 1200) fails. In at least one embodiment, the infotainment SoC 1230 can put the vehicle 1200 into a chauffeur-to-safe-stop mode, as described herein.

[0182] In at least one embodiment, the vehicle 1200 may also include a combination instrument 1232 (e.g., a digital dashboard, an electronic combination instrument, a digital instrument panel, etc.). In at least one embodiment, the combination instrument 1232 may, without limitation, include a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the combination instrument 1232 may, without limitation, include any number and combination of instruments, such as a speedometer, fuel level indicator, oil pressure indicator, tachometer, odometer, turn signals, gear position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), information about additional restraint systems (e.g., airbags), lighting controls, safety system controls, navigation information, etc.In some examples, the information can be displayed and / or shared between the infotainment SoC 1230 and the instrument cluster 1232. In at least one embodiment, the instrument cluster 1232 can incorporate part of the infotainment SoC 1230, or vice versa.

[0183] In at least one embodiment, at least one in Fig. The component shown or described in 12C is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 12C is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 12C selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0184] Fig. 12D is a diagram of a system 1276 for communication between the cloud-based server(s) and the autonomous vehicle 1200. Fig. 12A, according to at least one embodiment. In at least one embodiment, the system can, without limitation, comprise the server(s) 1278, the network(s) 1290, and any number and type of vehicles, including the vehicle 1200. In at least one embodiment, the server(s) 1278 can, without limitation, comprise a plurality of GPUs 1284(A)-1284(H) (hereinafter collectively referred to as GPUs 1284), PCIe switches 1282(A)-1282(H) (hereinafter collectively referred to as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (hereinafter collectively referred to as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280 and PCIe switches 1282 can be interconnected via high-speed connections, such as, and without limitation, the NVLink interfaces 1288 and / or PCIe connections 1286 developed by NVIDIA.In at least one embodiment, the GPUs 1284 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe links. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not to be understood as a limitation. In at least one embodiment, each of the servers 1278 can, without limitation, have any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, the server(s) 1278 can each have eight, sixteen, thirty-two, and / or more GPUs 1284.

[0185] In at least one embodiment, the server(s) 1278 can receive image data from vehicles via the network(s) 1290. This data is representative of images showing unexpected or altered road conditions, such as recently commenced roadworks. In at least one embodiment, the server(s) 1278 can transmit neural networks 1292, updated neural networks 1292, and / or map information 1294 to vehicles via the network(s) 1290. This map information includes, without limitation, information about traffic and road conditions. In at least one embodiment, the map information updates 1294 can include, without limitation, updates to the HD map 1222, such as information about construction sites, potholes, detours, floods, and / or other obstacles.In at least one embodiment, neural networks 1292 and / or map information 1294 can result from new training and / or experience represented in data received from any number of vehicles in the environment, and / or be based at least partially on training performed in a data center (e.g. using server(s) 1278 and / or other servers).

[0186] In at least one embodiment, the server(s) 1278 can be used to train machine learning models (e.g., neural networks) at least partially based on training data. In at least one embodiment, the training data can be generated from vehicles and / or in a simulation (e.g., using a game machine). In at least one embodiment, any amount of training data is tagged (e.g., if the associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any amount of training data is not tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, vehicle machine learning models can be used (e.g.,Transmission to vehicles via network(s) 1290, and / or machine learning models can be used by server(s) 1278 for remote monitoring of vehicles.

[0187] In at least one embodiment, the server(s) 1278 can receive data from vehicles and apply that data to current real-time neural networks for intelligent inferencing in real time. In at least one embodiment, the server(s) 1278 can include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server(s) 1278 can include a deep learning infrastructure that uses CPU-powered data centers.

[0188] In at least one embodiment, the deep learning infrastructure of server(s) 1278 can be capable of fast, real-time inference and use this capability to evaluate and verify the state of processors, software, and / or associated hardware in the vehicle 1200. In at least one embodiment, the deep learning infrastructure can, for example, receive periodic updates from the vehicle 1200, such as an image sequence and / or objects that the vehicle 1200 has located in this image sequence (e.g., via computer vision and / or other machine object classification techniques).In at least one embodiment, the deep learning infrastructure can run its own neural network to identify objects and compare them with the objects identified by the vehicle 1200, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1200 is malfunctioning, the server(s) 1278 can send a signal to the vehicle 1200 instructing a fail-safe computer of the vehicle 1200 to take over control, notify the passengers and perform a safe parking maneuver.

[0189] In at least one embodiment, the server(s) can have 1278 GPU(s) and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responsiveness. In at least one embodiment, e.g., when performance is less critical, servers with CPUs, FPGAs, and other processors can also be used for inferencing. In at least one embodiment, the hardware structure(s) 1115 is / are used to implement one or more embodiments. Details about the hardware structure(s) 1115 are provided in conjunction with the Fig. 12A and / or 12B described.

[0190] In at least one embodiment, at least one in Fig. The component shown or described in 12D is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 12D is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 12D selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described. COMPUTER SYSTEMS

[0191] Fig. Figure 13 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected facilities and components, a system-on-a-chip (SoC), or a combination thereof, 1300, which, according to at least one embodiment, includes a processor containing execution units for executing an instruction. In at least one embodiment, the computer system 1300 may, without limitation, include a component, such as a processor 1302, to employ execution units, including logic, for performing algorithms for processing data according to the present disclosure, as in the embodiment described herein. In at least one embodiment, the computer system 1300 may include processors, such as...The PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation in Santa Clara, California, although other systems (including PCs with other microprocessors, technical workstations, set-top boxes, and the like) may also be used. In at least one embodiment, the Computer System 1300 may run a version of the WINDOWS operating system available from Microsoft Corporation in Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0192] These embodiments can also be used in other devices, such as handheld devices and embedded applications. Some examples of portable devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, network computers (NetPCs), set-top boxes, network hubs, wide-area network switches (WANs), or any other system capable of executing one or more instructions according to at least one embodiment.

[0193] In at least one embodiment, the computer system 1300 can, without limitation, comprise a processor 1302, which can, without limitation, include one or more execution units 1308 for training a machine learning and / or inferencing model according to the techniques described herein. In at least one embodiment, the computer system 1300 is a single-processor desktop or server system, but in another embodiment, the computer system 1300 can be a multiprocessor system. In at least one embodiment, the processor 1302 can, without limitation, comprise a CISC (Complex Instruction Set Computer) microprocessor, a RISC (Reduced Instruction Set Computing) microprocessor, a VLIW (Very Long Instruction Word) microprocessor, a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor.In at least one embodiment, the processor 1302 can be connected to a processor bus 1310, which can transmit data signals between the processor 1302 and other components in the computer system 1300.

[0194] In at least one embodiment, the processor 1302 can, without limitation, include an internal Level 1 ("L1") cache memory ("cache") 1304. In at least one embodiment, the processor 1302 can have a single internal cache or multiple levels of an internal cache. In at least one embodiment, the cache memory can be located outside the processor 1302. Other embodiments can also include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, the register file 1306 can store different data types in different registers, including, without limitation, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0195] In at least one embodiment, the execution unit 1308, which includes unrestricted logic for performing integer and floating-point operations, is also located in the processor 1302. In at least one embodiment, the processor 1302 may also include a read-only memory ("ROM") for microcode ("ucode") that stores microcode for specific macro instructions. In at least one embodiment, the execution unit 1308 may include logic for handling a packed instruction set 1309. In at least one embodiment, by including a packed instruction set 1309 in the instruction set of a general-purpose processor 1302 together with associated instruction execution circuitry, the operations used by many multimedia applications using packed data can be performed in a general-purpose processor 1302.In at least one embodiment, many multimedia applications can be accelerated and run more efficiently by utilizing the full width of a processor's data bus to perform operations on packed data, thereby eliminating the need to transfer smaller data units across the processor's data bus to perform one or more operations on one data element at a time.

[0196] In at least one embodiment, the execution unit 1308 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, the computer system 1300 can, without restriction, include a memory 1320. In at least one embodiment, the memory 1320 can be a dynamic random-access memory (“DRAM”) device, a static random-access memory (“SRAM”) device, a flash memory device, or another type of memory device. In at least one embodiment, the memory 1320 can store instructions 1319 and / or data 1321, represented by data signals that can be executed by the processor 1302.

[0197] In at least one embodiment, the system logic chip can be connected to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip can, without restriction, include a memory control hub (“MCH”) 1316, and the processor 1302 can communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 can provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storing graphics instructions, data, and textures. In at least one embodiment, the MCH 1316 can route data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and a system I / O interface 1322.In at least one embodiment, the system logic chip can provide a graphics port for connection to a graphics controller. In at least one embodiment, the MCH 1316 can be coupled to the memory 1320 via a high-bandwidth memory path 1318, and the graphics / video card 1312 can be coupled to the MCH 1316 via an AGP connection 1314.

[0198] In at least one embodiment, the computer system 1300 can use the system I / O interface 1322 as a proprietary hub interface bus to couple the MCH 1316 to an I / O controller hub (“ICH”) 1330. In at least one embodiment, the ICH 1330 can provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can, without restriction, include a high-speed I / O bus for connecting peripheral devices to the memory 1320, the chipset, and the processor 1302. Examples include an audio controller 1329, a firmware hub (“Flash BIOS”) 1328, a wireless transceiver 1326, a data storage device 1324, a legacy I / O controller 1323 with user input and keyboard interfaces, a serial expansion port 1327, such as a Universal Serial Bus (“USB”) port, and a network controller 1334.In at least one embodiment, the data storage device 1324 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device or another mass storage device.

[0199] In at least one embodiment, it shows Fig. 13 a system that has interconnected hardware devices or “chips”, whereas in other designs Fig. 13 can show an exemplary SoC. In at least one embodiment, the in Fig. The 13 illustrated devices are interconnected via proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of the 1300 computer system are interconnected via Compute Express Link (CXL) connections.

[0200] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig. 9A and / or 9B described. In at least one embodiment, the logic 915 in the computer system 1300 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0201] In at least one embodiment, at least one in Fig. 13. The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 13 is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 13 at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0202] Fig.Figure 14 is a block diagram showing an electronic device 1400 for using a method 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 can be, for example, and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a telephone, an embedded computer, or any other suitable electronic device.

[0203] In at least one embodiment, the electronic device 1400 can, without restriction, include a processor 1410 that is communicatively connected to any number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled via a bus or interface, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Fig. 14 a system that has interconnected hardware devices or “chips”, whereas in other designs Fig.14 can show an exemplary SoC. In at least one embodiment, the Fig. The devices shown in Figure 14 are interconnected via proprietary connections, standardized connections (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 14 are interconnected via Compute Express Link (CXL) connections.

[0204] In at least one embodiment, Fig.14 a display 1424, a touchscreen 1425, a touchpad 1430, a Near Field Communications (“NFC”) unit 1445, a sensor hub 1440, a thermal sensor 1446, an Express chipset (“EC”) 1435, a Trusted Platform Module (“TPM”) 1438, BIOS / Firmware / Flash memory (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 such as a solid state disk (“SSD”) or a hard disk drive (“HDD”), a wireless local area network (“WLAN”) unit 1450, a Bluetooth unit 1452, a wireless wide area network (“WWAN”) unit 1456, a global positioning system (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454, such as a USB 3.0 camera, and / or a low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1415, which is implemented, for example, in an LPDDR3 standard. These components can be implemented in any suitable way.

[0205] In at least one embodiment, other components can be communicatively connected to the processor 1410 via the components described herein. In at least one embodiment, an accelerometer 1441, an ambient light sensor (“ALS”) 1442, a compass 1443, and a gyroscope 1444 can be communicatively connected to the sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and a touchpad 1430 can be communicatively connected to the EC 1435. In at least one embodiment, loudspeakers 1463, headphones 1464, and a microphone (“mic”) 1465 can be communicatively coupled to an audio unit (“audio codec and class D amp”) 1462, which in turn can be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1462 can, for example and without restriction, include an audio encoder / decoder (“codec”) and a Class-D amplifier.In at least one embodiment, a SIM card (“SIM”) 1457 can be communicatively connected to the WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452, as well as the WWAN unit 1456, can be implemented in a Next Generation Form Factor (“NGFF”).

[0206] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are given here in conjunction with the Fig.9A and / or 9B described. In at least one embodiment, the logic 915 in the electronic device 1400 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0207] In at least one embodiment, at least one in Fig. 14. The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.14 is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 14 select at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0208] Fig. Figure 15 shows a computer system 1500 in at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement various processes and procedures described in this disclosure.

[0209] In at least one embodiment, the computer system 1500 comprises, without limitation, at least one central processing unit (“CPU”) 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or another bus or point-to-point communication protocol. In at least one embodiment, the computer system 1500 comprises, without limitation, main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and the data is stored in the main memory 1504, which may be in the form of random-access memory (“RAM”).In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks to receive data with the computer system 1500 and to transmit data to other systems.

[0210] In at least one embodiment, the computer system 1500 comprises, without limitation, input devices 1508, a parallel processing system 1512, and display devices 1506, which may be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light-emitting diode (“LED”), a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1508, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be arranged on a single semiconductor platform to form a processing system.

[0211] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig.9A and / or 9B described. In at least one embodiment, the logic 915 in the computer system 1500 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0212] In at least one embodiment, at least one in Fig. 15. The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.15 is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 15 at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0213] Fig.Figure 16 illustrates a computer system 1600 according to at least one embodiment. In at least one embodiment, the computer system 1600 comprises, without limitation, a computer 1610 and a USB stick 1620. In at least one embodiment, the computer 1610 can comprise, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1610 comprises, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0214] In at least one embodiment, the USB stick 1620 comprises, without limitation, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 can be any instruction execution system, device, or facility capable of executing instructions. In at least one embodiment, the processing unit 1630 can comprise, without limitation, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 comprises an application-specific integrated circuit (“ASIC”) optimized for performing any number and type of machine learning operations.In at least one embodiment, the processing unit 1630 is, for example, a Tensor Processing Unit (“TPC”) optimized for performing inference operations within the context of machine learning. In at least one embodiment, the processing unit 1630 is an image processing unit (“VPU”) optimized for performing machine image processing and machine learning operations.

[0215] In at least one embodiment, the USB interface 1640 can be any type of USB plug or USB socket. In at least one embodiment, for example, the USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1650 can comprise any amount and type of logic that enables the processing unit 1630 to communicate with devices (e.g., the computer 1610) via the USB port 1640.

[0216] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig.9A and / or 9B described. In at least one embodiment, the logic 915 in the computer system 1600 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0217] In at least one embodiment, at least one in Fig. 16. The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.16 is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 16 at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0218] Fig.Figure 17A shows an exemplary architecture in which a plurality of GPUs 1710(1) - 1710(N) are communicatively coupled to a plurality of multi-core processors 1705(1) - 1705(M) via high-speed links 1740(1) - 1740(N) (e.g., buses, point-to-point links, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various link protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, which may differ from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1710(1)-1710(N) have one or more graphics cores (also simply referred to as "cores") 2000, as described in the Fig. 20A and Fig. 20B is disclosed. In at least one embodiment, one or more graphics cores 2000 can be designated as streaming multiprocessors (“SMs”), stream processors (“SPs”), stream processing units (“SPUs”), compute units (“CUs”), execution units (“EUs”) and / or slices, wherein a slice in this context can refer to a section of the processing resources in a processing unit (e.g. 16 cores, a ray tracing unit, a thread director or scheduler).

[0219] Additionally, and in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed links 1729(1)-1729(2), which may be implemented with similar or different protocols / links than those used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 may be interconnected via a high-speed link 1728, which may be a symmetric multiprocessor bus (SMP) operating at 20 GB / s, 30 GB / s, 120 GB / s or more. Alternatively, all communication between the various in Fig. System components shown in 17A are connected via similar protocols / lines (e.g., via a common connection structure).

[0220] In at least one embodiment, each multi-core processor 1705 is communicatively connected to a processor memory 1701(1) - 1701(M) via memory links 1726(1) - 1726(M), and each GPU 1710(1) - 1710(N) is communicatively connected to the GPU memory 1720(1) - 1720(N) via GPU memory links 1750(1) - 1750(N). In at least one embodiment, the memory links 1726 and 1750 can use similar or different memory access technologies. For example, the processor memories 1701(1) - 1701(M) and the GPU memories 1720 can be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or non-volatile memories such as 3D XPoint or Nano-RAM. In at least one embodiment, one section of the processor memories 1701 can be volatile memory and another section can be non-volatile memory (e.g.,using a two-level memory hierarchy (2LM).

[0221] As described here, different multi-core processors 1705 and GPUs 1710 can be physically connected to specific memory 1701 and 1720, respectively, and / or a unified memory architecture can be implemented where a virtual system address space (also called "effective address space") is distributed across different physical memory locations. For example, the processor memory locations 1701(1) - 1701(M) can each comprise 64 GB of system address space, and the GPU memory locations 1720(1) - 1720(N) can each comprise 32 GB of system address space, resulting in a total addressable memory of 256 GB in this example if M=2 and N=4. Other values ​​for N and M are possible.

[0222] In at least one embodiment, at least one in Fig.17A component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 17A is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig.17A selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0223] Fig.Figure 17B shows additional details for a connection between a multi-core processor 1707 and a graphics acceleration module 1746 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 can comprise one or more GPU chips integrated on a line card connected to the processor 1707 via a high-speed connection 1740 (e.g., a PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1746 can be integrated on a package or chip with the processor 1707.

[0224] In at least one embodiment, the processor 1707 comprises a plurality of cores 1760A-1760D (which may be referred to as "execution units"), each with a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components for instruction execution and data processing, which are not shown. In at least one embodiment, the caches 1762A-1762D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1756 may be present within the caches 1762A-1762D, which are shared by groups of cores 1760A-1760D. For example, one embodiment of the 1707 processor has 24 cores, each with its own L1 cache, twelve shared L2 caches and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to the system memory 1714, which shares the processor memories 1701(1) - 1701(M) of . Fig. can exhibit 17A.

[0225] In at least one embodiment, the coherence of data and instructions stored in various caches 1762A-1762D, 1756, and system memory 1714 is maintained by communication between the cores via a coherence bus 1764. In at least one embodiment, for example, each cache can have cache coherence logic / circuitry connected to it to communicate via the coherence bus 1764 in response to detected read or write operations in specific cache rows. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1764 to monitor cache accesses.

[0226] In at least one embodiment, a proxy circuit 1725 communicatively couples the graphics acceleration module 1746 to the coherence bus 1764, so that the graphics acceleration module 1746 can participate in a cache coherence protocol as a peer of the cores 1760A-1760D. In at least one embodiment, an interface 1735 provides connectivity with the proxy circuit 1725 via the high-speed connection 1740, and an interface 1737 connects the graphics acceleration module 1746 to the high-speed connection 1740.

[0227] In at least one embodiment, an accelerator integration circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing machines 1731(1) to 1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing machines 1731(1) to 1731(N) can each comprise a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing machines 1731(1) to 1731(N) of the graphics acceleration module 1746 can comprise one or more graphics cores 2000, as described in the following sections: Fig. 20A and Fig.20B is discussed. In at least one embodiment, the graphics processing machines 1731(1) - 1731(N) can alternatively comprise different types of graphics processing machines within a graphics processor, such as graphics execution units, media processing machines (e.g., video encoders / decoders), samplers, and blith modules. In at least one embodiment, the graphics acceleration module 1746 can be a GPU with a plurality of graphics processing units 1731(1) - 1731(N), or the graphics processing units 1731(1) - 1731(N) can be individual GPUs integrated in a common package, line card, or chip.

[0228] In one embodiment, the accelerator integration circuit 1736 includes a memory management unit (MMU) 1739 to perform various memory management functions, such as translations from virtual to physical memory (also referred to as translations from effective to real memory) and memory access protocols for accessing the system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) to cache translations from virtual / effective to physical / real addresses. In at least one embodiment, instructions and data may be stored in a cache 1738 for efficient access by the graphics processors 1731(1) - 1731(N).In at least one embodiment, the data stored in the cache 1738 and in the graphics memories 1733(1) - 1733(M) are kept coherent with the core caches 1762A-1762D, 1756 and the system memory 1714, possibly employing a retrieval unit 1744. As already mentioned, this can be accomplished via a proxy circuit 1725 on behalf of the cache 1738 and the memories 1733(1) - 1733(M) (e.g., sending updates to the cache 1738 in connection with changes / accesses to cache lines in the processor caches 1762A-1762D, 1756 and receiving updates from the cache 1738).

[0229] In at least one embodiment, a set of registers 1745 stores context data for threads executed by graphics processing machines 1731(1) - 1731N, and a context management circuit 1748 manages thread contexts. For example, the context management circuit 1748 can perform save and restore operations to save and restore the contexts of different threads during context switching (e.g., when a first thread is saved and a second thread is saved so that a second thread can be executed by a graphics processing machine). During a context switch, the context management circuit 1748 can, for example, store current register values ​​in a specific area in memory (e.g., identified by a context pointer). The register values ​​can then be restored upon returning to a context.In at least one embodiment, an interrupt management circuit 1747 receives and processes interruptions received by system devices.

[0230] In at least one embodiment, virtual / effective addresses from a graphics processing unit 1731 are translated by the MMU 1739 into real / physical addresses in system memory 1714. In at least one embodiment, the accelerator integration circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1746 can be dedicated to a single application running on the processor 1707, or it can be shared by multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processors 1731(1) - 1731(N) are shared by multiple applications or virtual machines (VMs).In at least one embodiment, the resources can be divided into “slices” that are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0231] In at least one embodiment, an accelerator integration circuit 1736 acts as a bridge to a system for the graphics acceleration module 1746 and provides address translation and system memory cache services. Furthermore, in at least one embodiment, the accelerator integration circuit 1736 can provide virtualization functions for a host processor to manage the virtualization of the graphics processing modules 1731(1) - 1731(N), interrupts, and memory management.

[0232] Since, in at least one embodiment, the hardware resources of the graphics processors 1731(1) - 1731(N) are explicitly mapped to a real address space seen by the host processor 1707, each host processor can directly address these resources with an effective address value. In at least one embodiment, a function of the accelerator integration circuit 1736 is the physical separation of the graphics processing machines 1731(1) - 1731(N), so that they appear to a system as independent units.

[0233] In at least one embodiment, one or more graphics memories 1733(1) - 1733(M) are connected to each of the graphics processing machines 1731(1) - 1731(N), and N=M. In at least one embodiment, the graphics memories 1733(1) - 1733(M) store instructions and data that are processed by each of the graphics processing machines 1731(1) - 1731N. In at least one embodiment, the graphics memories 1733(1) - 1733(M) can be volatile memory such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or Nano-RAM.

[0234] In at least one embodiment, allocation or biasing methods can be used to reduce data traffic over the high-speed connection 1740 by ensuring that the data stored in the graphics memories 1733(1) - 1733(M) is data most frequently used by the graphics processing units 1731(1) - 1731(N) and preferably not (or at least not frequently) used by the cores 1760A-1760D. Similarly, in at least one embodiment, an allocation or biasing mechanism attempts to keep data required by cores (and preferably not by the graphics processing units 1731(1) - 1731(N)) in the caches 1762A-1762D, 1756, and in system memory 1714.

[0235] In at least one embodiment, at least one in Fig.The component shown or described in 17B is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 17B is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig.17B selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0236] Fig.Figure 17C shows another exemplary embodiment in which the accelerator integration circuit 1736 is integrated into the processor 1707. In this embodiment, the graphics processors 1731(1) - 1731(N) communicate directly with the accelerator integration circuit 1736 via the high-speed link 1740, through interface 1737 and interface 1735 (which in turn can use any type of bus or interface protocol). In at least one embodiment, the accelerator integration circuit 1736 can perform operations similar to those described in Figure 17C. Fig.17B, ​​but possibly with a higher throughput, since it is located in close proximity to the coherence bus 1764 and the caches 1762A-1762D, 1756. In at least one embodiment, the accelerator integration circuit supports various programming models, including a programming model for dedicated processes (without virtualization of the graphics acceleration module) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1736 and programming models controlled by the graphics acceleration module 1746.

[0237] In at least one embodiment, the graphics processing machines 1731(1) - 1731(N) are intended for a single application or a single process under a single operating system. In at least one embodiment, a single application can forward other application requests to the graphics processing machines 1731(1)-1731(N), thereby enabling virtualization within a VM / partition.

[0238] In at least one embodiment, the graphics processing machines 1731(1) - 1731(N) can be shared by multiple VM / application partitions. In at least one embodiment, shared models can use a system hypervisor to virtualize the graphics processing machines 1731(1) - 1731(N) and allow access by any operating system. In single-partition systems without a hypervisor, the graphics processors 1731(1) - 1731(N) belong to an operating system. In at least one embodiment, an operating system can virtualize the graphics processing machines 1731(1) - 1731(N) to grant access to any process or application.

[0239] In at least one embodiment, the graphics acceleration module 1746 or a single graphics processing machine 1731(1) - 1731(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1714 and are addressable using an effective address-to-real address translation technique, as described herein. In at least one embodiment, a process handle can be an implementation-specific value provided to a host process when it registers its context with the graphics processing machine 1731(1) - 1731(N) (i.e., when it calls the system software to add a process element to a linked process element list). In at least one embodiment, the lower 16 bits of a process handle can be an offset of a process element within a linked process element list.

[0240] In at least one embodiment, at least one in Fig. The component shown or described in 17C is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 17C is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig.17C selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0241] Fig.Figure 17D shows an exemplary accelerator integration slice 1790. In at least one embodiment, a "slice" comprises a specific portion of the processing resources of the accelerator integration circuit 1736. In at least one embodiment, an application is an effective application address space 1782 in system memory 1714 that stores process elements 1783. In at least one embodiment, the process elements 1783 are stored in response to GPU calls 1781 from applications 1780 running on the processor 1707. In at least one embodiment, a process element 1783 contains the process state for the corresponding application 1780. In at least one embodiment, a work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by an application or a pointer to a queue of jobs.In at least one embodiment, the WD 1784 is a pointer to a job request queue in the effective address space 1782 of an application.

[0242] In at least one embodiment, the graphics acceleration module 1746 and / or the individual graphics processing machines 1731(1)-1731(N) can be shared by all or a subset of the processes in a system. In at least one embodiment, an infrastructure for setting the process states and sending a WD 1784 to a graphics acceleration module 1746 to start a job in a virtualized environment can be provided.

[0243] In at least one embodiment, a programming model for dedicated processes is implementation-specific. In at least one embodiment, a single process in this model owns the graphics acceleration module 1746 or a single graphics processing machine 1731. When the graphics acceleration module 1746 is owned by a single process in at least one embodiment, a hypervisor initializes the accelerator integration circuit 1736 for an owning partition, and an operating system initializes the accelerator integration circuit 1736 for an owning process when the graphics acceleration module 1746 is allocated.

[0244] In operation, a WD retrieval unit 1791 in the accelerator integration slice 1790 retrieves the nearest WD 1784 in at least one embodiment. This WD contains information about the work to be performed by one or more graphics processing units of the graphics acceleration module 1746. In at least one embodiment, the data from the WD 1784 can be stored in registers 1745 and used by the MMU 1739, the interrupt management circuit 1747, and / or the context management circuit 1748, as shown. For example, one embodiment of the MMU 1739 includes a segment / page scrolling circuit for accessing segment / page tables 1786 in the virtual address space 1785 of the operating system. In at least one embodiment, the interrupt management circuit 1747 can process interrupt events 1792 received from the graphics acceleration module 1746.In at least one embodiment, when performing graphics operations, an effective address 1793, generated by a graphics processing machine 1731-1731, N, is translated into a real address by the MMU 1739.

[0245] In at least one embodiment, for each graphics processing machine 1731(1) - 1731(N) and / or each graphics acceleration module 1746, the same set of registers 1745 is duplicated and can be initialized by a hypervisor or operating system. Each of these duplicated registers can be present in an accelerator integration slice 1790 in at least one embodiment. Exemplary registers that can be initialized by a hypervisor are listed in Table 2. Table 1 - Registers initialized by the hypervisor Register # Description 1 Slice control register 2 Real Address (RA) Area indicator of planned processes 3 Authority Mask Override Register 4 Break vector table entry offset 5 Break vector table entry boundary 6 Status register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Usage Record Pointer 9 Memory description register

[0246] Examples of registers that can be initialized by an operating system are listed in Table 2. Table 2 - Initialized registers of the operating system Register # Description 1 Process and thread identification 2 Effective Address (EA) Context Memory / Recovery Pointer 3 Virtual Address (VA) Accelerator Usage Record Pointer 4 Virtual Address (VA) Pointer to the memory segment table 5 Authority mask 6 Work descriptor

[0247] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or the graphics processing machines 1731(1) - 1731(N). In at least one embodiment, it contains all the information required by a graphics processing machine 1731(1) - 1731(N) to perform work, or it can be a pointer to a memory location where an application has established a queue of commands to be executed.

[0248] In at least one embodiment, at least one in Fig. The component shown or described in Figure 17D is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.17D is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 17D selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0249] Fig.Figure 17E illustrates additional details for an exemplary embodiment of a common model. This embodiment has a real hypervisor address space 1798 in which a process element list 1799 is stored. In at least one embodiment, the real hypervisor address space 1798 can be accessed via a hypervisor 1796, which virtualizes graphics acceleration module machines for the operating system 1795.

[0250] In at least one embodiment, shared programming models allow all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1746. In at least one embodiment, there are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions: namely, time-shared and graphically directed sharing.

[0251] In this model, in at least one embodiment, the SystemHypervisor 1796 owns the Graphics Acceleration Module 1746 and makes its functionality available to all Operating Systems 1795. For a Graphics Acceleration Module 1746 to support virtualization by the SystemHypervisor 1796, in at least one embodiment, the Graphics Acceleration Module 1746 may meet certain conditions, such as: 1) An application job request must be autonomous (i.e., the state does not need to be maintained between jobs), or the Graphics Acceleration Module 1746 must provide a context saving and recovery mechanism.2) A graphics acceleration module 1746 guarantees that the job request of an application will be completed within a certain time period, including any translation errors, or the graphics acceleration module 1746 provides the possibility to interrupt the processing of a job, and 3) the graphics acceleration module 1746 must be guaranteed fairness between processes when operating in a directed common programming model.

[0252] In at least one embodiment, the application 1780 must execute a system call of the operating system 1795 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a specific acceleration function for a system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can be in the form of a graphics acceleration module 1746 instruction, an effective address pointer to a user-defined structure, an effective address pointer to an instruction queue, or another data structure that describes the work to be performed by the graphics acceleration module 1746.

[0253] In one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. If the implementations of the accelerator integration circuit 1736 and the graphics acceleration module 1746 do not support a User Authority Mask Override Register (UAMOR) in at least one embodiment, an operating system can apply a current UAMOR value to an AMR value before an AMR is passed in a hypervisor call. The hypervisor 1796 can optionally apply a current AMR value before an AMR is placed in a process element 1783 in at least one embodiment.In at least one embodiment, CSRP is one of the registers 1745 that contain an effective address of a range in the effective address space 1782 of an application for the graphics acceleration module 1746 for storing and restoring context state. This pointer is optional in at least one embodiment if no state needs to be stored between jobs or if a job is prematurely terminated. In at least one embodiment, the context memory / restore area can be anchored in system memory.

[0254] Upon receiving a system call, the operating system 1795 can check whether the application 1780 is registered and has been granted permission to use the graphics acceleration module 1746. In at least one embodiment, the operating system 1795 then calls the hypervisor 1796 with the information shown in Table 3. Table 3 - Hypervisor call parameters from the operating system Parameter # Description 1 A working descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 An effective address (EA) Context Backup / Restore Area Pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) Accelerator Usage Record Pointer (AURP) 6 Virtual address of a memory segment table pointer (SSTP) 7 A Logical Interrupt Service Number (LISN)

[0255] Upon receiving a hypervisor call, in at least one embodiment, the hypervisor 1796 checks whether the operating system 1795 is registered and has been granted permission to use the graphics acceleration module 1746. In at least one embodiment, the hypervisor 1796 then adds the process element 1783 to a linked process element list for a corresponding graphics acceleration module type 1746. In at least one embodiment, a process element can contain the information shown in Table 4. Table 4 - Process element information Parameter # Description 1 A working descriptor (WD) 2 An Authority Mask Register (AMR) value (possibly masked) 3 An effective address (EA) Context Backup / Restore Area Pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) Accelerator Usage Record Pointer (AURP) 6 Virtual address of a memory segment table pointer (SSTP) 7 A Logical Interrupt Service Number (LISN) 8 Break vector table derived from hypervisor call parameters 9 A status register (SR) value 10 A logical partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Usage Record Pointer 12 Memory Description Registers (SDRs)

[0256] In at least one embodiment, the hypervisor initializes a plurality of registers 1745 for accelerator integration slices 1790.

[0257] In at least one embodiment, at least one in Fig. 17E component shown or described is used to implement procedures and / or functions related to the Fig.1-8 are described. In at least one embodiment, at least one component of Fig. 17E is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig.17E selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0258] As it is in Fig.As shown in Figure 17F, at least one embodiment uses a unified memory addressable via a common virtual memory address space, which is used for accessing physical processor memories 1701(1) - 1701(N) and GPU memories 1720(1) - 1720(N). In this implementation, operations performed on the GPUs 1710(1) - 1710(N) use the same virtual / effective memory address space for accessing the processor memories 1701(1) - 1701(N) and vice versa, simplifying programmability. In at least one embodiment, a first section of a virtual / effective address space is allocated to the processor memory 1701(1), a second section to the second processor memory 1701(N), a third section to the GPU memory 1720(1), and so on.In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes also referred to as effective address space) across each of the processor memory 1701 and GPU memory 1720, allowing each processor or GPU to access each physical memory with a virtual address assigned to that memory.

[0259] In at least one embodiment, the bias / coherence management circuit 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherence between the caches of one or more host processors (e.g., 1705) and GPUs 1710 and implements biasing procedures that specify in which physical memories certain data types should be stored. While in at least one embodiment multiple instances of the bias / coherence management circuit 1794A-1794E are located in Fig.As shown in Figure 17F, the bias / coherence circuit can be implemented within an MMU of one or more host processors 1705 and / or within the accelerator integration circuit 1736.

[0260] One embodiment allows GPU memory 1720 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1720 as system memory without the cumbersome cache coherence overhead provides an advantageous operating environment for GPU offloading. This arrangement allows the host processor 1705 software, in at least one embodiment, to set operands and access computational results without the overhead of conventional I / O DMA data copies. Such conventional copies, in at least one embodiment, involve driver calls, interrupts, and memory-mapping I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses.In at least one embodiment, the ability to access GPU memory 1720 without cache coherence overhead can be critical for the execution time of an offloaded computation. In cases with significant streaming write memory traffic, the cache coherence overhead can, for example, significantly reduce the effective write bandwidth of a GPU 1710 in at least one embodiment. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can all play a role in determining the effectiveness of GPU offloading.

[0261] In at least one embodiment, the selection of a GPU bias and a host processor bias is controlled by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (i.e., controlled by the granularity of a memory page) having 1 or 2 bits per GPU-connected memory page. In at least one embodiment, a bias table can be implemented in a stolen memory area of ​​one or more GPU 1720 memories, with or without a bias cache in a GPU 1710 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table can be managed in a single GPU.

[0262] In at least one embodiment, before the actual access to a GPU memory, a bias table entry associated with each access to GPU memory 1720-1723 is accessed, which performs the following operations. First, in at least one embodiment, local requests from GPU 1710 that find their page in the GPU bias are forwarded directly to a corresponding GPU memory 1720. In at least one embodiment, local requests from a GPU that find their page in the host bias are forwarded to processor 1705 (e.g., via a high-speed connection). In at least one embodiment, requests from processor 1705 that find a requested page in the host processor bias are completed like a normal memory read access. Alternatively, requests directed to a GPU-biased or GPU-bound page can be forwarded to GPU 1710.In at least one embodiment, a GPU can transition a page into a host processor bias when it is not currently using that page. In at least one embodiment, the bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited number of cases, a purely hardware-based mechanism.

[0263] In at least one embodiment, a mechanism for changing the bias state uses an API call (e.g., OpenCL) that in turn calls a GPU setup driver, which then sends a message to a GPU (or queues a command descriptor) to instruct it to change a bias state and, for some transitions, to perform a cache flushing operation on a host. In at least one embodiment, the cache flushing operation is used for a transition from the bias of the host processor 1705 to the bias of the GPU, but not for a reverse transition.

[0264] In one embodiment, cache coherence is maintained by temporarily rendering GPU-bound pages that cannot be cached by the host processor 1705. To access these pages in at least one embodiment, the processor 1705 may request access from the GPU 1710, which may not grant access immediately. Therefore, to reduce communication between the processor 1705 and the GPU 1710 in at least one embodiment, it is advantageous to ensure that GPU-bound pages are those required by a GPU but not by the host processor 1705, and vice versa.

[0265] Hardware structure(s) 1115 are used to implement one or more embodiments. Details of the hardware structure(s) 1115 can be found here in conjunction with the Fig. 9A and / or 9B must be specified.

[0266] Fig.Figure 18 shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to the circuits shown, at least one embodiment may include further logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0267] In at least one embodiment, at least one in Fig. The component shown or described in section 17F is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.17F is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 17F selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0268] Fig.Figure 18 is a block diagram illustrating an exemplary integrated circuit 1800 with a system-on-a-chip, which can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 comprises one or more application processor(s) 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 comprises peripheral or bus logic, including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I 2 2S / I 22C controller 1840. In at least one embodiment, the integrated circuit 1800 may include a display device 1845 connected to one or more HDMI (High-Definition Multimedia Interface) controllers 1850 and a MIPI (Mobile Industry Processor Interface) display interface 1855. In at least one embodiment, the memory may be provided by a flash memory subsystem 1860 comprising flash memory and a flash memory controller. In at least one embodiment, the memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security machine 1870.

[0269] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig. 9A and / or 9B described. In at least one embodiment, the logic 915 in the integrated circuit 1500 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0270] In at least one embodiment, at least one is incorporated into the Fig. The component shown or described in 18A-B is used to implement procedures and / or functions related to the Fig.1-8 are described. In at least one embodiment, at least one component is removed from the Fig. 18A-B is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of the Fig.18A-B selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0271] Fig. 19A and Fig.Figure 19B shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments as described herein. In addition to the circuits shown, at least one embodiment may include further logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0272] Fig. 19A and Fig. Section 19B contains block diagrams showing exemplary graphics processors for use in a SoC according to the embodiments described herein. Fig. Figure 19A shows an exemplary graphics processor 1910 of an integrated circuit with a system on a chip, which according to at least one embodiment can be manufactured by means of one or more IP cores. Fig.19B represents an additional exemplary graphics processor 1940 of an integrated circuit with a system-on-a-chip, which can be manufactured according to at least one embodiment using one or more IP cores. In at least one embodiment, the graphics processor 1910 is of Fig. 19A is a power-saving graphics processor core. In at least one embodiment, the graphics processor is 1940. Fig. 19B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1910 and 1940 can be a variant of the graphics processor 1810. Fig. Be 18.

[0273] In at least one embodiment, the graphics processor 1910 comprises a vertex processor 1905 and one or more fragment processor(s) 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized for executing operations for vertex shader programs, while one or more fragment processor(s) 1915A-1915N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the Vertex Processor 1905 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, the fragment processors 1915A-1915N use the primitive and vertex data generated by the vertex processor 1905 to create an image buffer that is displayed on a display device. In at least one embodiment, the fragment processor(s) 1915A-1915N is / are optimized for executing fragment shader programs as provided in an OpenGL API, which can be used to perform operations similar to those of a pixel shader program as provided in a Direct3D API.

[0274] In at least one embodiment, the graphics processor 1910 additionally comprises one or more memory management units (MMUs) 1920A-1920B, one or more caches 1925A-1925B, and one or more interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide the mapping of virtual to physical addresses for the graphics processor 1910, including for the vertex processor 1905 and / or the fragment processor(s) 1915A-1915N, which, in addition to the vertex or image / texture data stored in one or more caches 1925A-1925B, can refer to vertex or image / texture data stored in memory.In at least one embodiment, one or more MMU(s) 1920A-1920B can be synchronized with other MMUs within the system, including one or more MMUs connected to one or more application processors 1805, image processors 1815 and / or video processors 1820. Fig. 18 are assigned, so that each processor 1805-1820 can participate in a common or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable the graphics processor 1910 to connect to other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0275] In at least one embodiment, the graphics processor 1940 has one or more shader core(s) 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N-1 and 1955N), as described in Fig.Figure 22B illustrates a unified shader core architecture where a single core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945, which acts as a thread dispatcher to distribute execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space to, for example, exploit local spatial coherence within a scene or optimize the use of internal caches.

[0276] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig. 9A and / or 9B described. In at least one embodiment, the logic 915 in the graphics processor 1910 and / or 1940 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0277] In at least one embodiment, at least one is incorporated into the Fig. The component shown or described in 19A-B is used to implement procedures and / or functions related to the Fig.1-8 are described. In at least one embodiment, at least one component is removed from the Fig. 19A-B is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of the Fig.19A-B selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0278] Fig. 20A and Fig.Figure 20B illustrates an additional exemplary graphics processor logic according to the embodiments described herein. In at least one embodiment, the logic described in the Fig. The components shown and described in 20A-20B are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or another type of processor. Fig. 20A shows a graphics core 2000, which in at least one embodiment is in the graphics processor 1810. Fig. 18 may be present and in at least one embodiment a uniform shader core 1955A-1955N as in Fig. It could be 19B. Fig.Figure 20B illustrates a highly parallel, general-purpose graphics processing unit (“GPGPU,” which may be referred to as a “graphics processing unit”) 2030, which in at least one embodiment is suitable for use on a multi-chip module. In at least one embodiment, the graphics processing unit 2030 is a GPGPU comprising a graphics processor. In at least one embodiment, the integrated circuit 1800 comprises the graphics core 2000, for example, to form an integrated circuit and / or a system-on-a-chip (SoC), wherein such an integrated circuit and / or SoC performs the operations described herein.

[0279] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020 (which may include, for example, an L1, an L2, an L3, a last-level cache, or other caches) that are common to the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may have multiple slices 2001A-2001N or partitions for each core, and a graphics processor may have multiple instances of the graphics core 2000. In at least one embodiment, each slice 2001A-2001N relates to the graphics core 2000. In at least one embodiment, the slices 2001A-2001N have sub-slices that are part of a slice 2001A-2001N. In at least one embodiment, the slices 2001A-2001N are independent of other slices or dependent on other slices.The slices 2001A-2001N can, in at least one embodiment, include support logic comprising a local instruction cache 2004A-2004N, a thread scheduler (sequencer) 2006A-2006N, a thread dispatcher 2008A-2008N and a set of registers 2010A-2010N. In at least one embodiment, the slices 2001A-2001N can include a set of additional functional units (AFUs 2012A-2012N), floating-point units (FPUs 2014A-2014N), integer arithmetic logic units (ALUs 2016-2016N), address calculation units (ACUs 2013A-2013N), double-precision floating-point units (DPFPUs 2015A-2015N), and matrix processing units (MPUs 2017A-2017N). In at least one embodiment, the MPUs 2017A-2017N are referred to as matrix machines.

[0280] In at least one embodiment, each slice 2001A-2001N includes one or more machines or engines for floating-point and integer vector operations, as well as one or more machines or engines for accelerating convolution and matrix operations in AI, machine learning, or large datasets. In at least one embodiment, one or more slices 2001A-2001N include one or more vector engines for calculating a vector (e.g., for calculating mathematical operations on vectors). In at least one embodiment, a vector engine can calculate a vector operation in 16-bit floating-point (also referred to as "FP16"), 32-bit floating-point (also referred to as "FP32"), or 64-bit floating-point (also referred to as "FP64").In at least one embodiment, one or more slices 2001A-2001N comprise 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, the vector engines and math units being accessible via matrix extensions. In at least one embodiment, a slice comprises a specific portion of the processing resources of a processing unit, e.g., 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 2000 comprises one or more matrix engines for computational matrix operations, e.g., in the computation of tensor operations.

[0281] In at least one embodiment, one or more slices 2001A-2001N have one or more ray tracing units to compute ray tracing operations (e.g., 16 ray tracing units per slice 2001A-2001N). In at least one embodiment, a ray tracing unit computes ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0282] In at least one embodiment, one or more slices 2001A-2001N include a media slice that encodes, decodes and / or transcodes data, scales and / or formats data and / or performs operations to improve video quality on video data.

[0283] In at least one embodiment, one or more slices 2001A-2001N are connected to an L2 cache and memory structure, interconnects, HBM memory stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 2001A-2001N have multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) coupled to each core. In at least one embodiment, one or more slices 2001A-2001N have one or more L1 caches. In at least one embodiment, one or more slices 2001A-2001N have one or more vector machines, one or more instruction caches for storing instructions, one or more L1 caches for storing data, one or more shared local storage (SLMs) for storing data, etc.B, which correspond to commands; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in vector graphics format (e.g., in a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that together form an image represented by shapes when displayed); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 2001A-2001N includes a memory structure, e.g., an L2 cache.

[0284] In at least one embodiment, the FPUs 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2015A-2015N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2016A-2016N can perform variable-precision integer operations at 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2017A-2017N can also be configured for mixed-precision matrix operations, including floating-point and 8-bit half-precision integer operations. In at least one embodiment, the MPUs 2017-2017N can perform a variety of matrix operations to accelerate machine learning application frameworks, including support for accelerated general matrix-matrix multiplication (GEMM).In at least one embodiment, the AFUs 2012A-2012N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0285] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig. 9A and / or 9B described. In at least one embodiment, the logic 915 in the graphics kernel 2000 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0286] In at least one embodiment, the Graphics Core 2000 comprises an intermediate layer and a link fabric sublayer connected to a switch and a GPU-to-GPU bridge, enabling multiple Graphics Processors 2000 (e.g., 8) to be interconnected without adhesive bonding to load / store units (LSUs), data transfer units, and synchronization semantics across multiple Graphics Processors 2000. In at least one embodiment, the connections utilize standardized interfaces (e.g., PCIe) or a combination thereof.

[0287] In at least one embodiment, the Graphics Core 2000 comprises multiple tiles. In at least one embodiment, a tile is a single chip or one or more chips, wherein individual chips may be connected by a link (e.g., an Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, the Graphics Core 2000 comprises a compute tile, a memory tile (e.g., if a memory tile can be accessed exclusively by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, wherein all tiles are housed together in the Graphics Core 2000 as part of a GPU. In at least one embodiment, the Graphics Core 2000 may comprise multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile can have 8 Graphics Cores 2000, an L1 cache, and a base tile with a host interface including PCIe 5.0, HBM2e, MDFI, and EMIB, as well as a link tile with 8 links, 8 ports, and an embedded switch. In at least one embodiment, the tiles are connected via face-to-face (F2F) chip-on-chip bonding using finely graduated 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the Graphics Core 2000 has a memory structure containing memory and is a tile that multiple tiles can access. In at least one embodiment, the graphics core 2000 stores, accesses, or loads its own hardware contexts in memory, wherein a hardware context is a set of data that is loaded from registers before a process continues, and wherein a hardware context can specify a state of the hardware (e.g., the state of a GPU).

[0288] In at least one embodiment, the 2000 graphics core includes a serialization / deserialization circuit (SERDES) that converts a serial data stream into a parallel data stream or converts a parallel data stream into a serial data stream.

[0289] In at least one embodiment, the Graphics Core 2000 features a coherent high-speed unified fabric (GPU to GPU), load / store units, mass data transfer and sync semantics, and GPUs connected via an embedded switch, wherein a GPU-GPU bridge is controlled by a controller.

[0290] In at least one embodiment, the Graphics Core 2000 executes an API, wherein the API abstracts the hardware of the Graphics Core 2000 and accesses libraries containing instructions for performing mathematical operations (e.g., Mathematics Kernel Library), deep neural network operations (e.g., Deep Neural Network Library), vector operations, collective communication, thread building blocks, video processing, data analysis library, and / or ray tracing operations.

[0291] In at least one embodiment, at least one in Fig. 20A component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.20A is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 20A selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0292] Fig.Figure 20B illustrates a GPGPU 2030, which in at least one embodiment can be configured to perform highly parallel computational operations through an array of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly connected to other instances of the GPGPU 2030 to form a multi-GPU cluster and improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 has a host interface 2032 to enable communication with a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 can be a vendor-specific communication interface or communication structure.In at least one embodiment, the GPGPU 2030 receives instructions from a host processor and uses a global scheduler 2034 (which can be described as a thread sequencer and / or an asynchronous computation machine) to distribute the execution threads associated with these instructions across a set of compute clusters 2036A-2036H. In at least one embodiment, the compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, the cache memory 2038 can serve as a higher-level cache for cache memories within the compute clusters 2036A-2036H.

[0293] In at least one embodiment, the GPGPU 2030 comprises a memory 2044A-2044B coupled to compute clusters 2036A-2036H via a series of memory controllers 2042A-2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, the memory 2044A-2044B can comprise various types of memory devices, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including graphics dual-rate memory (GDDR).

[0294] In at least one embodiment, the 2036A-2036H compute clusters each have a set of graphics cores, such as the 2000 graphics core from Fig.20A, which can have several types of integer and floating-point logic units capable of performing arithmetic operations with a range of accuracies suitable for machine learning computations. For example, in at least one embodiment, at least one subset of floating-point units in each of the compute clusters 2036A-2036H can be configured to perform 16-bit or 32-bit floating-point operations, while another subset of floating-point units can be configured to perform 64-bit floating-point operations.

[0295] In at least one embodiment, multiple instances of the GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, the communication used by the compute clusters 2036A-2036H for synchronization and data exchange varies between the embodiments. In at least one embodiment, multiple instances of the GPGPU 2030 communicate via the host interface 2032. In at least one embodiment, the GPGPU 2030 has an I / O hub 2039 that couples the GPGPU 2030 to a GPU link 2040, enabling a direct connection to other instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 2030.In at least one embodiment, the GPU link 2040 is coupled to a high-speed connection for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 2030 are located in separate data processing systems and communicate via a network device accessible through the host interface 2032. In at least one embodiment, the GPU link 2040 can be configured to provide a connection to a host processor in addition to, or as an alternative to, the host interface 2032.

[0296] In at least one embodiment, the GPGPU 2030 can be configured to train neural networks. In at least one embodiment, the GPGPU 2030 can be used within an inferencing platform. In at least one embodiment where the GPGPU 2030 is used for inferencing, the GPGPU can have fewer compute clusters 2036A-2036H than when the GPGPU is used for training a neural network. In at least one embodiment, the memory technology associated with the memory 2044A-2044B can differ between inferencing and training configurations, with higher-bandwidth memory technologies being assigned to the training configurations. In at least one embodiment, the inferencing configuration of the GPGPU 2030 can support inferencing-specific instructions.For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions that can be used during inferencing operations for deployed neural networks.

[0297] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig. 9A and / or 9B described. In at least one embodiment, the logic 915 in the GPGPU 2030 can be used for inferencing or prediction operations that are based at least partially on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0298] In at least one embodiment, at least one in Fig. The component shown or described in 20B is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 20B is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig.20B selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0299] Fig.Figure 21 is a block diagram showing a computing system 2100 according to at least one embodiment. In at least one embodiment, the computing system 2100 comprises a processing subsystem 2101 with one or more processors 2102 and a system memory 2104, which communicate via a connection path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or be integrated into one or more processors 2102. In at least one embodiment, the memory hub 2105 is connected to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107, which enables the computing system 2100 to receive input from one or more input devices 2108.In at least one embodiment, the I / O hub 2107 enables a display controller, which may be contained in one or more processor(s) 2102, to provide outputs to one or more display device(s) 2110A. In at least one embodiment, one or more display device(s) 2110A coupled to the I / O hub 2107 may comprise a local, internal, or embedded display device.

[0300] In at least one embodiment, the processing subsystem 2101 comprises one or more parallel processor(s) 2112 connected to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 may be, but is not limited to, any number of standards-based communication link technologies or protocols, such as PCI Express, or a vendor-specific communication interface or communication structure. In at least one embodiment, some or all of the parallel processors 2112 form a computationally focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor.In at least one embodiment, one or more parallel processor(s) 2112 form a graphics processing subsystem that can output pixels to one or more display devices 2110A coupled via the I / O hub 2107. In at least one embodiment, one or more parallel processor(s) 2112 can also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 2110B. In at least one embodiment, the parallel processor(s) 2112 has one or more cores, such as the graphics cores 2000 discussed here.

[0301] In at least one embodiment, a system storage unit 2114 can be connected to the I / O hub 2107 to provide a storage mechanism for the computer system 2100. In at least one embodiment, an I / O switch 2116 can be used to provide an interface mechanism to enable connections between the I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119, which may be integrated into the platform, and various other devices that may be added via one or more add-in devices 2120. In at least one embodiment, the network adapter 2118 can be an Ethernet adapter or another wired network adapter.In at least one embodiment, the wireless network adapter 2119 may include one or more Wi-Fi, Bluetooth, Near Field Communication (NFC) or other networking devices, which include one or more wireless radio devices.

[0302] In at least one embodiment, the computing system 2100 may include other components not explicitly shown, including USB or other ports, optical storage drives, video recording devices, and the like, which may also be connected to the I / O hub 2107. In at least one embodiment, communication paths connecting various components in Fig.21 interconnect, be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect)-based protocols (e.g. PCI-Express) or other bus or point-to-point communication interfaces and / or protocols, such as NV-Link High-Speed ​​Interconnect or Interconnect protocols.

[0303] In at least one embodiment, one or more parallel processor(s) 2112 comprise a circuit optimized for graphics and video processing, which, for example, includes a video output circuit and represents a graphics processing unit (GPU). For example, the parallel processor(s) 2112 comprise the graphics core 2000. In at least one embodiment, one or more parallel processor(s) 2112 include circuits optimized for general-purpose processing. In at least one embodiment, components of the computing system 2100 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s) 2112, a memory hub 2105, a processor(s) 2102, and an I / O hub 2107 can be integrated in an integrated circuit with a system-on-a-chip (SoC).In at least one embodiment, the components of the 2100 computer system can be integrated into a single enclosure to form a system-in-package (SIP) configuration. In at least one embodiment, at least one section of the components of the 2100 computer system can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computer system.

[0304] Logic 915 is used to perform inferencing and / or training operations in conjunction with one or more embodiments. Details of Logic 915 are provided here in conjunction with the Fig.12A and / or 12B described. In at least one embodiment, the logic 915 in the computing system 2100 can be used for inferencing or prediction operations that are at least partially based on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0305] In at least one embodiment, at least one in Fig. 21. The component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.21 is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 21 at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described. PROCESSORS

[0306] Fig.Figure 22A illustrates a parallel processor 2200 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2200 can be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the parallel processor 2200 shown is a variant of one or more parallel processors 2112, which are implemented in Fig. Figure 21 shows an exemplary embodiment. In at least one embodiment, the parallel processor 2200 has one or more graphics cores 2000.

[0307] In at least one embodiment, the parallel processor 2200 comprises a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 comprises an I / O unit 2204, which enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 can be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices via a hub or switch interface, such as the memory hub 2105. In at least one embodiment, the connections between the memory hub 2105 and the I / O unit 2204 form a communication link 2113.In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory interface 2216, wherein the host interface 2206 receives commands for performing processing operations and the memory interface 2216 receives commands for performing storage operations.

[0308] In at least one embodiment, when the host interface 2206 receives an instruction buffer via the I / O unit 2204, the host interface 2206 can direct work operations to a front end 2208 for the execution of these instructions. In at least one embodiment, the front end 2208 is coupled to a scheduler 2210 (which can be referred to as a sequencer) configured to distribute instructions or other work items to a processing cluster arrangement 2212. In at least one embodiment, the scheduler 2210 ensures that the processing cluster arrangement 2212 is properly configured and in a valid state before tasks are distributed to the cluster of the processing cluster arrangement 2212. In at least one embodiment, the scheduler 2210 is implemented via firmware logic running on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2210 is configured to perform complex sequence control and work distribution operations with coarse and fine granularity, enabling fast interruption and context switching of threads running on the processing cluster 2212. In at least one embodiment, the host software can detect workloads for scheduling on the processing cluster 2212 via one of several graphics processing paths. In at least one embodiment, the workloads can then be automatically distributed on the processing cluster 2212 by the logic of the scheduler 2210 within a microcontroller that incorporates the scheduler 2210.

[0309] In at least one embodiment, the processing cluster arrangement 2212 can have up to "N" processing clusters (e.g., cluster 2214A, cluster 2214B, up to cluster 2214N), where "N" is a positive integer (which may be a different positive integer "N" than the one used in the other figures). In at least one embodiment, each cluster 2214A-2214N of the processing cluster arrangement 2212 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 can allocate work to the clusters 2214A-2214N of the processing cluster arrangement 2212 by using various flow control and / or work distribution algorithms that can vary depending on the workload generated by each type of program or computation.In at least one embodiment, scheduling can be performed dynamically by the scheduler 2210 or partially supported by compiler logic during the compilation of the program logic, which is configured for execution by the processing cluster arrangement 2212. In at least one embodiment, different clusters 2214A-2214N of the processing cluster arrangement 2212 can be assigned for processing different types of programs or for performing different types of calculations.

[0310] In at least one embodiment, the processing cluster arrangement 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster arrangement 2212 is configured to perform parallel general-purpose computing operations. For example, in at least one embodiment, the processing cluster arrangement 2212 can include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0311] In at least one embodiment, the processing cluster arrangement 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster arrangement 2212 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster arrangement 2212 may be configured to execute graphics processing-related shader programs, such as vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from system memory via the I / O unit 2204 for processing.In at least one embodiment, the transmitted data can be stored in on-chip memory (e.g., in the parallel processor memory 2222) during processing and then written back to system memory.

[0312] In at least one embodiment, when the parallel processing unit 2202 is used to perform graphics processing, the scheduler 2210 can be configured to divide a processing load into approximately equal tasks to enable better distribution of graphics processing operations across multiple clusters 2214A-2214N of the processing cluster arrangement 2212. In at least one embodiment, sections of the processing cluster arrangement 2212 can be configured to perform different types of processing.For example, in at least one embodiment, a first section can be configured to perform vertex shading and topology generation, a second section can be configured to perform tessellation and geometry shading, and a third section can be configured to perform pixel shading or other screenspace operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more clusters 2214A-2214N can be stored in buffers so that intermediate data can be transferred between clusters 2214A-2214N for further processing.

[0313] In at least one embodiment, the processing cluster arrangement 2212 can receive processing tasks to be executed via the scheduler 2210, which receives instructions for defining processing tasks from the frontend 2208. In at least one embodiment, the processing tasks can have indices of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and instructions that define how the data is to be processed (e.g., which program is to be executed). In at least one embodiment, the scheduler 2210 can be configured to retrieve indices corresponding to the tasks or to receive indices from the frontend 2208. In at least one embodiment, the frontend 2208 can be configured to ensure that the processing cluster arrangement 2212 is configured in a valid state before an incoming instruction buffer (e.g.,Batch buffer, push buffer, etc.) specified workload is initiated.

[0314] In at least one embodiment, each instance of the parallel processing unit 2202 can be coupled to the parallel processor memory 2222. In at least one embodiment, the parallel processor memory 2222 can be accessed via the memory coupling field 2216, which can receive memory requests from the processing cluster arrangement 2212 and the I / O unit 2204. In at least one embodiment, the memory coupling field 2216 can access the parallel processor memory 2222 via a memory interface 2218. In at least one embodiment, the memory interface 2218 can have several partition units (e.g., partition unit 2220A, partition unit 2220B to partition unit 2220N), each of which can be coupled to a section (e.g., a memory unit) of the parallel processor memory 2222.In at least one embodiment, the number of partition units 2220A-2220N is configured to correspond to the number of storage units, such that a first partition unit 2220A has a corresponding first storage unit 2224A, a second partition unit 2220B has a corresponding storage unit 2224B, and an Nth partition unit 2220N has a corresponding Nth storage unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N cannot be equal to the number of storage units.

[0315] In at least one embodiment, the memory units 2224A-2224N can have different types of memory facilities, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including graphics dual-rate memory (GDDR). In at least one embodiment, the memory units 2224A-2224N can also have 3D stacked memory, including, but not limited to, high-bandwidth memory (HBM, HBM2, or HDM3). In at least one embodiment, rendering targets, such as frame buffers or texture maps, can be stored across the memory units 2224A-2224N, so that the partition units 2220A-2220N can write sections of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2222.In at least one embodiment, a local instance of the parallel processor memory 2222 can be excluded in favor of a unified memory design that uses the system memory in conjunction with the local cache memory.

[0316] In at least one embodiment, each of the clusters 2214A-2214N of the processing cluster arrangement 2212 can process data written to each of the storage units 2224A-2224N in the parallel processor memory 2222. In at least one embodiment, the memory interface 2216 can be configured to transmit an output from each cluster 2214A-2214N to any partition unit 2220A-2220N or to another cluster 2214A-2214N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 via the memory interface 2216 to read from or write to various external devices.In at least one embodiment, the memory interconnect 2216 has a connection to the memory interface 2218 for communication with the I / O unit 2204, as well as a connection to a local instance of the parallel processor memory 2222, so that the processing units in the various processing clusters 2214A-2214N can communicate with the system memory or other memory that is not local to the parallel processing unit 2202. In at least one embodiment, the memory interconnect 2216 can use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0317] In at least one embodiment, multiple instances of the 2202 parallel processing unit can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the 2202 parallel processing unit can be configured to cooperate even if the different instances have a different number of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the 2202 parallel processing unit can have higher-precision floating-point units compared to other embodiments.In at least one embodiment, systems containing one or more instances of the Parallel Processing Unit 2202 or the Parallel Processor 2200 can be implemented in a variety of embodiments and form factors, including, but not limited to, desktop, laptop or handheld personal computers, servers, workstations, game consoles and / or embedded systems.

[0318] In at least one embodiment, at least one in Fig. 22A component shown or described is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig.22A is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig. 22A selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig.2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dynamic decomposition 600 of Fig. 6, the procedure 700 of Fig. 7 and / or the 800 processor from Fig. 8 is described.

[0319] Fig. Figure 22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, the partition unit 2220 is an instance of one of the partition units 2220A-2220N. Fig.22A. In at least one embodiment, the partition unit 2220 comprises an L2 cache 2221, a single-frame buffer interface 2225, and a ROP 2226 (raster operation unit). In at least one embodiment, the L2 cache 2221 is a read / write cache configured to perform load and store operations received from the memory coupling array 2216 and the ROP 2226. In at least one embodiment, read errors and urgent write-back requests are output from the L2 cache 2221 to the single-frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to a single-frame buffer for processing via the single-frame buffer interface 2225. In at least one embodiment, the single-frame buffer interface 2225 is connected to one of the storage units in the parallel processor memory, such as the storage units 2224A-2224N of Fig.22A (e.g., within the parallel processor memory 2222).

[0320] In at least one embodiment, the ROP 2226 is a processing unit that performs raster operations such as stenciling, Z-testing, blending, etc. In at least one embodiment, the ROP 2226 then outputs processed graphics data, which is stored in graphics memory. In at least one embodiment, the ROP 2226 has compression logic to compress depth or color data written to memory and to decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that uses one or more of several compression algorithms. In at least one embodiment, the type of compression performed by the ROP 2226 can vary based on statistical characteristics of the data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0321] In at least one embodiment, the ROP 2226 is in each processing cluster (e.g., clusters 2214A-2214N of Fig. 22) and is not present in the partition unit 2220. In at least one embodiment, read and write requests for pixel data are transmitted via the memory coupling field 2216 instead of pixel fragment data. In at least one embodiment, processed graphics data can be displayed on a display device, such as one of one or more display devices 2110. Fig. 21, for further processing by processor(s) 2102 or for further processing by one of the processing units within the parallel processor 2200 of Fig. 22A will be forwarded.

[0322] In at least one embodiment, at least one in Fig. The component shown or described in Figure 22B is used to implement procedures and / or functions related to the Fig. 1-8 are described. In at least one embodiment, at least one component of Fig. 22B is used to cause access to a three-dimensional (3D) representation of an environment, the determination of one or more static features and one or more dynamic features of the 3D representation, the determination of one or more static density values, the determination of one or more dynamic density values, and / or the generation of one or more images based on the one or more static density values ​​and the one or more dynamic density values. In at least one embodiment, at least one component of Fig.22B selects at least one aspect relating to the machine learning model(s) 110, the static hash encoder 104, the dynamic hash encoder 106, the flow hash encoder 108, the RGB mesh 130, the rendering module 120, the gaze direction module 112 and / or the processor 140 of Fig. 1, the scene breakdown 200 of Fig. 2, the image generation 300 of Fig. 3, the hash encoder 404, the hash encoder 424, the MLP 408, the MLP 428, the static RGB net 414, the dynamic RGB net 434 and / or the renderer 420 of Fig. 4, the hash encoder 504, the hash encoder 524, the MLP 508, the MLP 528, the RGB net 534 and / or the renderer 520 of Fig. 5, the static and dy...

Claims

[1] A method for generating one or more images, comprising: Accessing a three-dimensional representation or 3D representation of an environment; Determining one or more static features and one or more dynamic features of the 3D representation; Determining, using the one or more static features, one or more static density values; Determining, using the one or more dynamic features, one or more dynamic density values; and Generating the one or more images based on the one or more static density values and the one or more dynamic density values. [2] The method of claim 1, further comprising generating one or more color values based on the one or more static features and the one or more dynamic features; and generating the one or more images using the one or more color values. [3] The method of claim 1 or 2, wherein the 3D representation of the environment is a neural radiation field (NeRF). [4] The method of any preceding claim, further comprising determining a gaze direction associated with an autonomous machine; and using the gaze direction to generate the one or more images. [5] A method according to any one of the preceding claims, wherein the one or more static features associated with a position within the environment are determined using a feature encoder. [6] A method according to any one of the preceding claims, wherein the one or more dynamic features are determined using a feature encoder associated with a position and a time indication associated with the 3D representation of the environment. [7] The method according to any one of the preceding claims further comprises using one or more neural networks to generate the one or more images. [8] Non-transitory computer-readable storage medium on which executable instructions are stored which, as a result of execution by one or more processors of a computer system, cause the computer system to: to access a three-dimensional representation or 3D representation of an environment; to determine one or more static features and one or more dynamic features of the 3D representation; using the one or more static features, to determine one or more static density values; using the one or more dynamic features, to determine one or more dynamic density values; and generate one or more images based on the one or more static density values and the one or more dynamic density values. [9] The non-transitory computer-readable storage medium of claim 8, further causing the computer system to generate one or more color values based on the one or more static features and the one or more dynamic features; and generate the one or more images using the one or more color values. [10] A non-transitory computer-readable storage medium according to claim 8 or 9, wherein the 3D representation of the environment is a neural radiation field (NeRF). [11] The non-transitory computer-readable storage medium of any one of claims 8 to 10, further causing the computer system to determine a viewing direction associated with an autonomous machine; and to use the viewing direction to create the one or more images. [12] The non-transitory computer-readable storage medium of any of claims 8 to 10, wherein the one or more static features associated with a position within the environment are determined using a feature encoder. [13] The non-transitory computer-readable storage medium of any of claims 8 to 12, wherein the one or more dynamic features are determined using a feature encoder associated with a position and a time indication associated with the 3D representation of the environment. [14] The non-transitory computer-readable storage medium of any of claims 8 to 13, wherein one or more neural networks are used to generate the one or more images. [15] System comprising: one or more processors to: Accessing a three-dimensional representation or 3D representation of an environment; Determining one or more static features and one or more dynamic features of the 3D representation; Determining, using the one or more static features, one or more static density values; Determining, using the one or more dynamic features, one or more dynamic density values; and Generating one or more images based on the one or more static density values and the one or more dynamic density values. [16] The system of claim 15, wherein the one or more processors are further configured to generate one or more color values based on the one or more static features and the one or more dynamic features; and to generate the one or more images using the one or more color values. [17] The system of claim 15 or 16, wherein the 3D representation of the environment is a neural radiation field (NeRF). [18] The system of any of claims 15 to 17, wherein the one or more processors are further configured to determine a gaze direction associated with an autonomous machine; and to use the gaze direction to generate the one or more images. [19] The system of any of claims 15 to 18, wherein the one or more dynamic features are determined using a feature encoder associated with a position and a time indication associated with the 3D representation of the environment. [20] A system according to any one of claims 15 to 19, wherein the system comprises at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a first system for performing simulation operations; a second system for performing deep learning operations; a third system implemented using an edge device; a fourth system implemented using a robot; a fifth system containing one or more virtual machines, VMs; a sixth system that is at least partially implemented in a data center; a seventh system for performing operations on a digital twin; an eighth system for performing light transport simulations; a ninth system for conducting collaborative content creation for 3D assets; a tenth system for performing artificial intelligence operations in dialogue; an eleventh system for generating synthetic data; a twelfth system for implementing a web-hosted service for detecting inefficiencies in program utilization; an application as an application programming interface, API; a thirteenth system implemented at least in part using cloud computing resources; a fourteenth system for displaying virtual reality content, augmented reality content, and / or mixed reality content; or a fifteenth system that implements one or more large language models (LLMs).

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