On-Chip Kryostat

Abstract

On-chip cryostat and method, in particular for providing one or more quantum elements, comprising a substrate; a layer structure arranged on the substrate, wherein a sample, in particular a quantum element, can be arranged on a sample surface on the side of the layer structure opposite the substrate, and a vacuum housing surrounding the layer structure; wherein the layer structure comprises more than one ADR layer.

Description

[0001] The present invention relates to an on-chip cryostat, in particular for providing one or more cryogenic areas on the chip for the arrangement and operation of one or more quantum elements or low-temperature physical technologies (superconductivity, quantum states, qubits, etc.). The present invention further relates to a method for operating such an on-chip cryostat.

[0002] Cryostat technology plays a crucial role in various scientific and technological applications, particularly in low-temperature physics and high-performance electronics. A cryostat is a device used to cool samples or instruments to extremely low temperatures, often close to absolute zero (-273.15 °C or 0 K).

[0003] Superconducting circuits and quantum computers are examples of applications that require extremely low temperatures to ensure optimal operating conditions. For this reason, cryostat technology is a crucial enabling technology for modern applications of quantum physics in quantum computers, quantum sensors, and other advanced technologies. The most promising of these technologies require temperatures below 4 K (the temperature of liquid helium), making cost-effective cooling with liquid nitrogen impractical. Therefore, cooling with liquid helium (LHe) is typically necessary. Helium becomes liquid at low temperatures, usually below 4 K. This type of cooling is required for applications that demand extremely low temperatures, such as in superconductor research.However, helium is more expensive than nitrogen and, due to supply constraints in some regions, only available in limited quantities. Cryostats can also use closed cooling circuits in which LHe circulates and removes heat from the sample or instrument. This method requires a compression chiller to compress and liquefy the refrigerant. Because of the necessary recirculation process, expensive, large compressors are required, which also consume a significant amount of energy. This results in a substantial technological overhead that severely limits the use of quantum technologies.

[0004] Cooling to 4K with current technologies is very complex. Due to the limited amount of helium and the fact that helium escapes from the Earth's atmosphere, cooling with LHe is very expensive and unsustainable. Other cryostat technologies with closed cooling circuits, however, have a huge technological overhead, making them very large, energy-intensive, and expensive. Because of the need for sub-4K cooling for quantum computers, quantum sensors, or other low-temperature technologies, these techniques can primarily be used in university research or large-scale applications. Using these technologies in mobile devices or for end users is not possible with the current state of technology.

[0005] Another problem with the macroscopic cooling of low-temperature technologies is that classical CMOS electronics cannot be used at extreme temperatures below 4K. For this reason, the classical control electronics required for quantum sensing or quantum computing are placed outside the cooled area of ​​the cryostat. This necessitates numerous cables running into the cooled area of ​​the cryostat between the cold and hot sections. This results in a significant heat load for the cold section, while simultaneously increasing susceptibility to interference due to the large number of required cables. This problem hinders the further scaling of superconducting or quantum dot quantum computers.

[0006] Most quantum technologies that require cooling below 4K are microscopically small. For example, the two-dimensional extent of silicon quantum dots used for quantum computing is less than 200 nm. 2 To utilize the quantum state, it is only necessary to cool this microscopically small area to the required temperature below 4K, while the surrounding environment can be kept at higher temperatures. However, current technology only allows macroscopic cooling, necessitating the use of large devices that cool not only the sample but also a large area of ​​the surroundings. This results in high energy and space requirements, which precludes its use in mobile devices.

[0007] WO 2013 / 177678 A1 describes a solid-state cooling system for semiconductor materials, including but not limited to silicon. Advantageous active electronic devices can be monolithically integrated with solid-state semiconductor coolers that provide magnetic cooling across the entire substrate or predetermined areas of the substrate. Alternatively, active devices can be formed with integrated semiconductor layers that provide magnetic cooling.

[0008] BRADLEY, DI, et al. On-chip magnetic cooling of a nanoelectronic device. Scientific reports, 2017, Vol. 7, No. 1, p. 45566 describes an on-chip magnetic cooling of a nanoelectronic device.

[0009] The object of the present invention is to provide an on-chip cryostat that is compact and enables efficient cooling.

[0010] The problem is solved by an on-chip cryostat according to claim 1 and a method for operating an on-chip cryostat according to claim 20.

[0011] The on-chip cryostat according to the invention, particularly for providing one or more cryogenic areas on the chip, comprises a substrate. A layered structure with a plurality of layers is arranged on the substrate, wherein the layered structure forms a sample area on one side opposite the substrate, on which a sample, in particular a quantum dot, superconductor, or the like, can be arranged. The layers of the layered structure are arranged one above the other, in particular parallel to a surface of the substrate. Naturally, the present invention is not limited to a specific sample, so that, in addition to quantum dots, other samples requiring cooling and having small dimensions can also be arranged, allowing them to be integrated into the on-chip cryostat of the present invention.Furthermore, the on-chip cryostat according to the present invention comprises a vacuum housing surrounding, and in particular completely surrounding, the layer structure. The vacuum housing can be vacuum-tightly connected to the substrate, such that the layer structure is arranged in a vacuum chamber formed by the vacuum housing. To generate the vacuum, the vacuum housing can, for example, be connected to a vacuum pump. Alternatively, a vacuum is created once within the vacuum housing, and the vacuum housing is subsequently sealed, so that the vacuum is maintained within the vacuum housing. Alternatively or additionally, the vacuum housing can be connected to an active vacuum pump or a passive vacuum pump, such as a non-evaporable getter pump (NEG pump).This makes it possible to maintain the vacuum inside the vacuum housing for a long period of time and to ensure constant operation of the on-chip cryostat.

[0012] According to the invention, the layer structure comprises more than one ADR (adiabatic demagnetization refrigerator) layer. The ADR layer is, in particular, a paramagnetic material. Cooling using ADR in bulk ADR material is known, as the cooling capacity is proportional to the volume of the ADR material. However, the ADR material is typically actively cooled using LHe cooling to achieve temperatures in the mK range. For ADR cooling, a magnetic field is first applied so that the magnetic moments of the ADR material are coherently aligned. This reduces the magnetic entropy of the ADR material. The heat generated in the bulk material is then dissipated. In conventional ADR applications, this is achieved using LHe. Subsequently, the magnetic field is switched off, and adiabatic demagnetization begins, thus reducing the temperature.This process is known as magnetic cooling or cooling by adiabatic demagnetization. This makes it possible to achieve the required temperature at the sample surface. In the present invention, the ADR material is formed as a layer. In the on-chip cryostat of the present invention, all necessary elements can thus be integrated into the chip by nanofabrication. Cooling the sample surface to below 4K is limited to specific areas of the on-chip cryostat, so less energy is required for cooling the surrounding environment. In particular, LHe cooling can be omitted, and cooling with liquid nitrogen is sufficient due to the small size of the volume to be cooled. It is also necessary to use only layers of the ADR material, since the volume of these layers already provides sufficient cooling capacity for the reduced volume to be cooled in the on-chip cryostat.This makes it possible to develop compact applications of quantum computers, quantum sensors, or the like.

[0013] Preferably, the substrate and / or the vacuum housing has a temperature between 20 K and 100 K. Therefore, it is not necessary to cool the substrate or the vacuum housing to a temperature of 4 K or less, for example, using LHe. The cooling effort required for the substrate and / or the vacuum housing can be significantly reduced. In particular, active cooling of the substrate or the vacuum housing can be achieved by circulating a suitable coolant through the substrate or around the substrate and / or the vacuum housing. Specifically, the substrate and / or the vacuum housing is cooled with liquid nitrogen. Expensive and sometimes difficult-to-obtain liquid helium is thus not required for cooling the substrate and / or the vacuum housing.The heat generated during the magnetization of the ADR layer material can thus be efficiently dissipated by cooling the substrate and / or the vacuum housing.

[0014] Preferably, the on-chip cryostat includes a magnetization device that at least partially surrounds the layer structure for aligning the magnetic moments of the at least one ADR layer. The magnetization device can comprise one or more permanent magnets or electromagnets, with the alignment of the magnetic moments of the at least one ADR layer being achieved by applying a current when using an electromagnet. When using permanent magnets as the magnetization device, the alignment of the magnetic moments of the at least one ADR layer can be achieved, for example, by changing the distance and orientation of the permanent magnets relative to the ADR layer. The magnetic field of the magnetization device can, in particular, have a direction perpendicular to a surface of the substrate or perpendicular to the at least one ADR layer. Other orientations of the magnetic field are also possible.In particular, the magnetizing device is arranged outside the vacuum housing or at least partially surrounds the vacuum housing. Alternatively, the magnetizing device can be arranged inside the vacuum housing and preferably be at least partially integrated into the layer structure and / or the substrate.

[0015] According to the invention, the layer structure comprises more than one ADR layer. By providing multiple ADR layers, the temperature can be gradually reduced from the temperature of the substrate or the vacuum housing to the required temperature, in particular to 4 K or less. Thus, the required cooling capacity is not provided by a single ADR layer alone. Rather, the multiple ADR layers work together so that even when the substrate and / or the vacuum housing is cooled to only 20 K to 100 K, the multiple ADR layers together achieve a suitably low temperature at the sample surface of the layer structure. The individual ADR layers interact in such a way that the heat from one ADR layer is dissipated by another / further ADR layer when the magnetic moments align, and so on. Thus, the individual ADR layers work together.In particular, the multiple ADR layers can create a preferred direction for heat flow, from the sample surface towards the substrate, so that the required low temperature is achieved at the sample surface.

[0016] Preferably, a thermal switching layer is provided between at least two successive ADR layers. This thermal switching layer can be configured as a superconductor, enabling heat conduction between the two successive ADR layers when the thermal switching layer is in a conducting state and preventing heat conduction when the thermal switching layer is in a blocking state. Thus, the heat transfer from one ADR layer to a subsequent ADR layer can be controlled by means of the thermal switching layer. The thermal switching layer ensures that heat is directed towards the substrate. In particular, the thermal switching layer enforces a preferred direction of heat flow by appropriately switching the thermal switching layer from the sample surface to the substrate.This heat is either absorbed by the ADR layer from the environment or an adjacent ADR layer oriented towards the sample area, or it is the heat generated during the magnetization of the corresponding ADR layer. Due to the thermal switching layer, this heat is not conducted towards the sample area, but rather towards the substrate of the on-chip cryostat, where it can be dissipated by cooling the substrate, particularly with liquid nitrogen. Thus, the thermal switching layers enable controlled transfer of the heat generated within the layer structure towards the substrate. These thermal switching layers can be implemented as superconducting heat switches, thermal rectifiers, or using other established technologies. In particular, the thermally conductive layers can also be integrated into the layer structure using nanofabrication.

[0017] Preferably, at least two ADR layers are directly adjacent to one another. Thus, a first ADR layer borders directly on a second ADR layer, so that they share a common interface. This allows a multitude of ADR layers to be arranged in a stack within the layer structure. This enables a cascade-like or stepwise cooling of the temperature from the substrate temperature down to the temperature at the sample surface.

[0018] Preferably, the ADR layers exhibit a higher thermal conductivity towards the substrate than those towards the sample surface. Due to this higher thermal conductivity, efficient heat dissipation occurs in the direction of the substrate. This results in a preferred direction for heat flow towards the substrate, allowing heat generated or absorbed by the ADR layers—whether from the environment, an immediately adjacent ADR layer, or during magnetization—to be dissipated towards the substrate. Therefore, the layer structure does not require thermal switching layers, as the controlled thermal conductivity of the individual ADR layers ensures heat transport away from the sample surface towards the substrate.

[0019] Preferably, the layer structure has at least two ADR layers separated by a thermal switching layer and at least two ADR layers directly adjacent to each other, so that in this embodiment the variants shown above are combined.

[0020] The ADR layers towards the substrate have a greater thickness and / or material-related demagnetization entropy, thus enabling improved cooling performance. The cooling performance at the surface can be adjusted by the thickness and material of the top layer, whereby the increased heat generation during magnetization in thicker top layers (towards the sample) necessitates that the underlying layers also exhibit higher cooling performance.

[0021] Preferably, the temperature is lower at each ADR layer, starting from the substrate. As described above, a stepwise or cascade-like reduction of the temperature from the substrate towards the sample surface through the individual ADR layers is possible.

[0022] Preferably, the on-chip cryostat has a thermal shield, wherein the thermal shield surrounds at least one ADR layer and is arranged within the vacuum housing. Thus, individual ADR layers can prevent or block heat input by thermal radiation through a thermal shield, which is of a particularly suitable design. Here, at least one thermal shield can serve as an inner vacuum housing, so that a greater vacuum (lower pressure) prevails within the thermal shield than, for example, between the thermal shield and the vacuum housing. Thus, a gradual reduction of the pressure can also be achieved through the at least one thermal shield, thereby reducing the leakage rate between the individual vacuum chambers formed by the thermal shields and the vacuum housing.In particular, multiple heat shields are provided so that individual temperature levels of the layer structure are separated from one another, preventing heat transfer by thermal radiation. Specifically, each heat shield surrounds exactly one ADR layer. Preferably, each temperature level is separated from the adjacent temperature levels, generated by the individual ADR layers, by exactly one heat shield. Alternatively, more than one ADR layer / temperature level can be combined and separated from adjacent temperature levels by a respective heat shield, so that the number of existing heat shields is less than the number of ADR layers in the layer structure.Since each ADR layer reduces the temperature, individual areas with different temperatures can be effectively separated from each other by the heat shields, thereby reducing or preventing heat transfer through thermal radiation.

[0023] Preferably, the temperature at the sample surface is less than 10 K and preferably less than 4 K. Thus, suitable low temperatures for corresponding applications, in particular quantum sensing or quantum computing, can be easily achieved by the on-chip cryostat of the present invention without the use of helium as a coolant.

[0024] Preferably, electrical components, particularly those based on CMOS technology, are arranged on the substrate outside the vacuum housing. These components can be connected to a sample or the sample surface via vias. Since conventional semiconductors do not function at low temperatures, the design of the on-chip cryostat of the present invention allows for separation, enabling the electrical components to be arranged on the substrate outside the vacuum housing. A vacuum-tight connection through the substrate and the layer structure can be achieved conventionally using simple conductor tracks or vias. Complex and expensive vacuum feedthroughs, as required in conventional low-temperature vacuum technologies, are therefore unnecessary.At the same time, conventional CMOS or semiconductor technology can be used, and adapting the electrical components to the low temperature inside the cryostat is not necessary.

[0025] Preferably, the substrate is connected to a cooling element. This cooling element can, for example, have a cooling channel through which a coolant such as liquid nitrogen flows to cool the substrate. Preferably, a thermal break layer is arranged between the substrate and the cooling element. This allows for thermal separation between the cooling element and the substrate. Heat input into the layer structure from the cooling element is prevented by appropriate switching of the thermal break layer.

[0026] Preferably one or more of the ADR layers comprises erbium (Er), gadolinium (Gd), holmium (Ho), europium (Eu), dysprosium (Dy), therbium (Tb), thulium (Tm) or lanthanum (La) or an alloy thereof.

[0027] Preferably, two ADR layers of the layered structure comprise different materials. In particular, each ADR layer of the layered structure comprises a different material. The cooling capacity at different temperatures of the individual ADR layers can be controlled by selecting the appropriate material, thus enabling heat conduction from the sample surface to the substrate. For example, a first layer can consist of LiGdF4, a second layer of GdNi2, and a third layer of GdPd, thereby achieving a gradual cooling or temperature reduction from the substrate to the sample surface.

[0028] Preferably, more than one layer structure is arranged within the vacuum housing. Thus, multiple structures, and therefore multiple samples, can be arranged within a single vacuum housing. The layer structures can be identical or different. In particular, the layer structures can be maintained at different temperatures, so that the sample surfaces of the individual layer structures have different temperatures. Specifically, the layer structures within the vacuum housing can be separated by one or more thermal shields to prevent heat transfer by thermal radiation from one layer structure to another. Furthermore, the number of ADR layers, the material of the individual ADR layers, the formation of thermal break layers between individual ADR layers, etc., of the intended layer structures can be the same or different.

[0029] Preferably, the vacuum housing has a volume of between 100 µm³ 3 and 10cm 3 , especially between 100µm 3 and 1cm 3 and especially preferably between 100µm 3 and 100mm 3 .

[0030] Preferably, the area of ​​the ADR layers, and in particular the area of ​​the layer structure or the sample area, has an area of ​​less than 1 cm². 2 and preferably less than 10mm 2 .

[0031] Preferably, the thickness of one or more of the ADR layers is less than 200 µm, particularly less than 150 µm. In particular, the ADR layers can all have the same thickness, or at least two ADR layers can have different thicknesses.

[0032] Preferably the height of the layer structure is less than 1mm, in particular less than 500µm and preferably less than 250µm.

[0033] In a further aspect of the present invention, a method for operating an on-chip cryostat is provided. The on-chip cryostat is configured in particular as described above. The on-chip cryostat has a layered structure and a vacuum housing surrounding the layered structure. The layered structure comprises more than one ADR layer. The method comprises the following steps: Applying a magnetic field to the ADR layer to coherently align the magnetic moments of the ADR layer; Cooling the ADR layer; Switching off the magnetic field; Dephasing the magnetic moments of the ADR layer, thereby reducing the temperature of the ADR layer.

[0034] In another embodiment, the method comprises the following steps: Applying a magnetic field to the ADR layer leads to coherent alignment of the magnetic moments within the ADR layer. This results in magnetization and heat generation within the ADR layer. Dissipating heat into the cooling element or layer in the direction of the substrate; Open the heat switch towards the substrate to thermally decouple the ADR layer and the cooling element from each other; Switching off the magnetic field. This leads to a demagnetization of the ADR layer, which reduces the temperature of the ADR layer; Thermal switches close opposite to the substrate to thermally couple the ADR layer and the next layer or sample; Cooling of the sample or nearest layer opposite the substrate; Open the heat switch opposite the substrate; Close the heat switch in the direction of the substrate;

[0035] In particular, the steps of the process are repeated cyclically to achieve a constant cooling performance on a sample area of ​​the layer structure.

[0036] According to the invention, the layer structure comprises more than one ADR layer, with a thermal switching layer preferably arranged between each pair of successive ADR layers. In a first cycle, the thermal switching layer is thermally conductive, and in an immediately subsequent cycle, the thermal switching layer is non-thermally conductive, or vice versa. This can be done differently or staggered for successive thermal switching layers, so that a thermal switching layer is thermally conductive in one cycle and non-thermally conductive in an immediately subsequent thermal switching layer (separated by the corresponding ADR layer) in the same cycle, or vice versa.

[0037] According to the invention, the layer structure comprises more than one ADR layer, with a thermal switching layer preferably arranged between two successive ADR layers. During the application of the magnetic field and cooling of the ADR layer, the thermal switching layer is thermally conductive, and during the dephasing of the magnetic elements, the thermal switching layer is not thermally conductive, or vice versa. Thus, the processes in which cooling and heat dissipation generated in the respective ADR layer are separated by aligning the magnetic moments of the ADR layer can be achieved through the thermal switching layer and suitable control of the heat flow towards the substrate.

[0038] Of course, with successive thermal switching layers (separated by a corresponding ADR layer), this can be exactly the opposite, so that when the magnetic field is applied and the ADR layer is cooled, a thermal switching layer immediately adjacent to the ADR layer is thermally conductive and a second thermal switching layer immediately adjacent to the same ADR layer is not thermally conductive, whereby during the dephasing of the magnetic moments, the first thermal switching layer is not thermally conductive and the second thermal switching layer is thermally conductive, or vice versa.

[0039] The invention will now be explained in more detail with reference to preferred embodiments and the accompanying figures.

[0040] The figures show: Fig. 1 a first embodiment of the on-chip cryostat according to the present invention, Fig. 2 another embodiment of the on-chip cryostat according to the present invention, Fig. 3A and Fig. 3B a detailed representation of the layer structure, Fig. 4 another embodiment of the on-chip cryostat according to the present invention, Fig. 5 a further embodiment of the on-chip cryostat according to the present invention and Fig. 6 another embodiment of the on-chip cryostat according to the present invention.

[0041] The on-chip cryostat 10 according to the invention is shown in the Fig. The device 1 comprises a substrate 12. A vacuum housing 14 is connected to the substrate 12. The vacuum housing 14 creates a vacuum chamber 16. A layered structure 18 is arranged on the substrate 12 within the vacuum chamber 16. The layered structure 18 can comprise a plurality of layers. The layered structure 18 includes more than one ADR layer, as described below. A sample area 19 is formed on the side of the layered structure 18 opposite the substrate 12. A sample 24 can be arranged on the sample area 19. This sample could be, for example, a quantum dot, a superconducting nanowire single photodetector (SNSPD), a superconducting quantum interference device (SQID), or the like. However, the present invention is not limited to a specific sample or use.Rather, the on-chip cryostat 10 of the present invention provides the possibility of arranging a sample 24 in a vacuum at low temperatures, particularly of less than 10 K and preferably less than 4 K. The small dimensions of the layer structure 18 and the vacuum housing 14 significantly reduce the volume to be cooled, thereby limiting the cooling power and enabling miniaturization. For example, the substrate 12 or the vacuum housing 14 is actively cooled, particularly by means of liquid nitrogen. Liquid nitrogen has a temperature of 77 K. For this purpose, the substrate 12 can, for example, be equipped with a cooling element 22 as indicated in the figure. Fig. 1. The cooling element 22 can have cooling channels through which liquid nitrogen flows. Thus, for example, the end of the layer structure 18 opposite the sample surface 19 is connected to a substrate 12 cooled to 77 K. Further temperature reduction is achieved by the at least one ADR layer within the layer structure 18, so that the required temperature for the sample 24 is reached at the sample surface.

[0042] A magnetizing device 13 is schematically depicted, arranged as an example on the vacuum housing 14. This device can, for example, be an electromagnet that generates a magnetic field at the location of the ADR layer for magnetizing or aligning the magnetic moments within the respective ADR layer. Other embodiments are also possible; for example, the magnetizing device 13 need not be directly connected to the vacuum housing 14 and / or can be designed as a permanent magnet. In particular, the magnetizing device 13 can be arranged below the on-chip cryostat, i.e., on the substrate 12 side. Furthermore, the magnetizing device 13 can also be arranged within the vacuum housing 14 or even be part of the layer structure.

[0043] In the following, identical or similar components are identified using the same reference symbols.

[0044] The following refers to the Fig. 2. Here, the layer structure 18 has a multitude of layers. Thus, the layer structure 18 of the Fig. Two ADR layers 26, 26', 26" are arranged, alternating with thermal switching layers 28, 28', 28". For example, the first ADR layer 26 can be formed by GdPd, the second ADR layer 26' by GdNi2, and the third ADR layer 26" by LiGdF4. This allows the temperature of the substrate 12 to be gradually reduced so that a suitable low temperature, particularly lower than 10 K and preferably less than 4 K, can be achieved at the location of the sample 24. While the substrate 12 is at a temperature of, for example, 77 K, a gradual reduction can be achieved by the individual ADR layers 26, 26', 26". For example, a temperature of 39K can be achieved through the first ADR layer 26', a temperature of 19K through the second ADR layer 26' and a temperature of 4K through the third ADR layer 26".In this arrangement, areas of different temperatures are separated from each other by heat shields 15, 15', 15" so that heat transfer between the individual areas is prevented. For example, thermal radiation from the vacuum housing 14 cannot be transferred to areas with a lower temperature. The heat shields 15, 15', 15" at least partially surround one of the respective ADR layers. A first heat shield 15, which is located directly inside the vacuum housing 14, can, for example, be connected to and at least partially surround the first ADR layer 26. Further heat shields 15', 15" can then be arranged within the first heat shield 15.

[0045] Electronic components 30 can be arranged outside the vacuum housing 14 and on the substrate 12. These components are thus cooled to only 77 K. Semiconductor components continue to function as usual. The electronic components 30 can be connected to the sample 24 via internal conductors and / or vias. Vacuum feedthroughs through the vacuum housing 14 are not required due to the use of the shared substrate. This significantly simplifies the design of the vacuum housing and eliminates the need to adapt the electronic components 30 to low temperatures.

[0046] The following refers to the Fig. 3A and Fig. Figure 3B schematically represents the state of the thermal switching layers 28, 28' and 28". In a first state, the first thermal switching layer 28 can thermally connect the first ADR layer to the substrate 12, which is indicated by the open thermal switch of the Fig. 3A is shown schematically. A second thermally conductive layer 28' can thermally connect the first ADR layer 26 with the second ADR layer 26', which is facilitated by the closed thermal switch of the Fig. Figure 3A shows the second ADR layer 26' being thermally non-conductively connected to the third ADR layer 26" via the third thermal break layer 28". Heat generated in the second ADR layer 26' in this state cannot be transferred to the third ADR layer 26" due to the thermal separation provided by the third thermal break layer 28". The heat generated in the second ADR layer 26' can be transferred to the first ADR layer 26 due to the state of the second thermal break layer 28' and absorbed there, for example, by the cooling capacity of the first ADR layer 26. A second state is shown in the Fig. 3B is the second thermal switching layer 28', which is thermally conductive and thus thermally connects the second ADR layer 26' to the third ADR layer 26". Heat generated in the third ADR layer 26" can therefore be transferred to the second ADR layer 26' via the third thermal switching layer 28". In this process, the Fig. 3A and Fig. The states shown in 3B occur in different cycles. Each cycle has the following steps: Applying a magnetic field; Cooling the ADR layer; Switching off the magnetic field; and Dephasing the magnetic moments of the ADR layer, thereby reducing the temperature of the ADR layer.

[0047] In another embodiment, the method comprises the following steps: Applying a magnetic field to the ADR layer leads to coherent alignment of the magnetic moments within the ADR layer. This results in magnetization and heat generation within the ADR layer. Dissipating heat into the cooling element or layer in the direction of the substrate; Open the heat switch towards the substrate to thermally decouple the ADR layer and the cooling element from each other; Switching off the magnetic field. This leads to a demagnetization of the ADR layer, which reduces the temperature of the ADR layer; Thermal switches close opposite to the substrate to thermally couple the ADR layer and the next layer or sample; Cooling of the sample or nearest layer opposite the substrate; Open the heat switch opposite the substrate; Close the heat switch in the direction of the substrate;

[0048] Alternatively, the states can be shown in Fig. 3A and Fig. 3B occur at different times within a single cycle, so that, for example, the application of a magnetic field to the ADR layers and cooling of the ADR layer takes place in the state shown in the Fig. 3A and the switching off of the magnetic field and dephasing of the magnetic moments of the ADR layer is carried out according to the Fig. 3B.

[0049] The following refers to the Fig. 4. Here, the layer structure 32 comprises four directly consecutive ADR layers 34, 34', 34'', and 34'''. In particular, no thermal break layer is provided between the ADR layers 34, 34', 34'', and 34''', as in the preceding embodiments. The different ADR layers 34, 34', 34'', and 34''' generate different cooling capacities at different temperatures, resulting in gradual cooling. Preferably, the first ADR layer 34 has a higher thermal conductivity than the second ADR layer 34', and so on. Thus, heat generated in the second ADR layer 34' can be dissipated into the cooled substrate.

[0050] In particular, the ADR layers 34, 34', 34'' and / or 34''' can be formed by one or more of erbium (Er), holmium (Ho), lanthanum (La), gadolinium (Gd), europium (Eu), dysprosium (Dy), therbium (Tb), thulium (Tm), or an alloy thereof. For example, a temperature of 45 K can be achieved by the first ADR layer 34, a temperature of 30 K by the second ADR layer 34', a temperature of 13 K by the third ADR layer 34'', and a temperature of 6 K by the fourth ADR layer 34'''. The ADR layers 34, ..., 34'' can be formed by ErNi₂, ErAl₂, HoNi₂, and / or HoN. These are, of course, only examples, and other material compositions are also conceivable.

[0051] The aforementioned temperature levels of the individual ADR layers are merely examples, so that a stepwise reduction of the substrate temperature to the temperature of the sample surfaces 19 takes place.

[0052] In the same way as, for example, in the Fig. As shown in 2, layers of different temperatures can also be separated from each other by suitable heat shields.

[0053] It is also possible that the layered structure consists of layers separated by corresponding thermal switching layers, as well as ADR layers that follow directly one another, thus, for example, separating the layers in the Fig. 2 and Fig. 3 illustrated embodiments of the layer structure 18 with the embodiments of the layer structure 32 of the Fig. 4 and Fig. 5 to combine.

[0054] The following refers to the Fig. 5. Here, a thermal break layer 36 is arranged between the substrate 12 and the cooling element 22, so that thermal separation of the substrate 12 from the cooling element 22 is possible. Although the thermal break layer 36 is shown between the substrate 12 and the cooling element 22, in conjunction with the embodiment of the Fig. 4, can of course also be implemented analogously in the embodiment of the Fig. 1 and Fig. 2 such a thermal switching layer 36 is provided between the substrate 12 and the cooling element 22.

[0055] The following refers to the Fig.6. Here, more than one layer structure 18, 32 is arranged within the vacuum chamber 16 formed by the vacuum housing 14. Several samples 24, 24', 24'' are arranged on the respective layer structures. The layer structures 18, 32, 18', 32', and 18'', 32'' can be identical or different. Naturally, the number of layer structures is not limited to the number shown in the figures, so more than one layer structure, or fewer or more than three layer structures, can be provided.

Claims

[1] On-chip cryostat, especially for providing one or more cryogenic areas on the chip, with a substrate; a layered structure arranged on the substrate with a plurality of layers, wherein a sample, in particular a quantum dot, superconductor or other samples from quantum technology, can be arranged on a sample surface on the side of the layered structure opposite the substrate and a vacuum housing surrounding the layered structure; characterized by , that the layer structure has more than one ADR layer. [2] On-chip cryostat according to claim 1, characterized by that the substrate and / or the vacuum housing has a temperature between 20K and 100K. [3] On-chip cryostat according to claim 1 or 2, characterized by that the substrate and / or the vacuum housing are actively cooled, in particular with liquid nitrogen. [4] On-chip cryostat according to any one of claims 1 to 3, characterized by , that a magnetization device is provided which at least partially surrounds the layer structure for aligning the magnetic moments of the at least one ADR layer. [5] On-chip cryostat according to any one of claims 1 to 4, characterized by that a thermal switching layer is provided between at least two successive ADR layers, wherein the thermal switching layer is in particular designed as a superconductor. [6] On-chip cryostat according to any one of claims 1 to 5, characterized by that at least two ADR layers follow each other immediately. [7] On-chip cryostat according to any one of claims 1 to 6, characterized by that the ADR layer has a higher thermal conductivity in the direction of the substrate. [8] On-chip cryostat according to any one of claims 1 to 7, characterized by , that the temperature is lower at each ADR layer, starting from the substrate. [9] On-chip cryostat according to any one of claims 1 to 8, characterized by , that at least one heat shield, wherein the heat shield at least partially surrounds at least one ADR layer and is arranged within the vacuum housing. [10] On-chip cryostat according to any one of claims 1 to 9, characterized by that the temperature at the sample surface is less than 10K and preferably less than 4K. [11] On-chip cryostat according to any one of claims 1 to 10, characterized by , that electrical components, particularly those based on CMOS, are arranged on the substrate outside the vacuum housing, wherein the electrical components are connected to the sample by means of vias or electrical feedthroughs. [12] On-chip cryostat according to any one of claims 1 to 11, characterized by that the substrate is connected to a cooling element, wherein in particular a thermal switching layer is arranged between the substrate and the cooling element. [13] On-chip cryostat according to any one of claims 1 to 12, characterized by that the ADR layers contain Er, Gd, Ho, La, Eu, Dy, Tb, Tm or are an alloy of one or more of these elements. [14] On-chip cryostat according to any one of claims 1 to 13, characterized by that at least two ADR layers are made of different materials and, in particular, that each ADR layer is made of a different material. [15] On-chip cryostat according to any one of claims 1 to 14, characterized by that more than one layer structure is arranged within the vacuum housing. [16] On-chip cryostat according to any one of claims 1 to 15, characterized by , that the volume of the vacuum housing is between 100µm 3 and 10cm 3 lies... [17] On-chip cryostat according to any one of claims 1 to 16, characterized by that the area of ​​the ADR layer is less than 1 cm 2 and preferably less than 10mm 2 amounts. [18] On-chip cryostat according to any one of claims 1 to 17, characterized by that the thickness of one or more of the ADR layers is less than 200µm. [19] Method for operating an on-chip cryostat, in particular according to one of claims 1 to 18, with a layer structure and a vacuum housing surrounding the layer structure, wherein the layer structure has more than one ADR layer, wherein the method comprises the steps: Applying a magnetic field to the ADR layer to coherently align the magnetic moments of the ADR layer; Cooling the ADR layer; Switching off the magnetic field; Dephasing the magnetic moments of the ADR layer, thereby reducing the temperature of the ADR layer. [20] Method according to claim 19, wherein the steps of the method are repeated cyclically. [21] Method according to claim 20, wherein a thermal switching layer is arranged between each two successive ADR layers, wherein in a first cycle the thermal switching layer is thermally conductive or non-thermally conductive and during an immediately following cycle the thermal switching layer is accordingly non-thermally conductive or thermally conductive. [22] Method according to claim 19 or 20, wherein a thermal switching layer is arranged between each two successive ADR layers, wherein the thermal switching layer is thermally conductive or non-thermally conductive during the application of the magnetic field and cooling of the ADR layer and is correspondingly non-thermally conductive or thermally conductive during the dephasing of the magnetic moments.

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